1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_DPM_H__ 24 #define __AMDGPU_DPM_H__ 25 26 /* Argument for PPSMC_MSG_GpuChangeState */ 27 enum gfx_change_state { 28 sGpuChangeState_D0Entry = 1, 29 sGpuChangeState_D3Entry, 30 }; 31 32 enum amdgpu_int_thermal_type { 33 THERMAL_TYPE_NONE, 34 THERMAL_TYPE_EXTERNAL, 35 THERMAL_TYPE_EXTERNAL_GPIO, 36 THERMAL_TYPE_RV6XX, 37 THERMAL_TYPE_RV770, 38 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 39 THERMAL_TYPE_EVERGREEN, 40 THERMAL_TYPE_SUMO, 41 THERMAL_TYPE_NI, 42 THERMAL_TYPE_SI, 43 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 44 THERMAL_TYPE_CI, 45 THERMAL_TYPE_KV, 46 }; 47 48 struct amdgpu_ps { 49 u32 caps; /* vbios flags */ 50 u32 class; /* vbios flags */ 51 u32 class2; /* vbios flags */ 52 /* UVD clocks */ 53 u32 vclk; 54 u32 dclk; 55 /* VCE clocks */ 56 u32 evclk; 57 u32 ecclk; 58 bool vce_active; 59 enum amd_vce_level vce_level; 60 /* asic priv */ 61 void *ps_priv; 62 }; 63 64 struct amdgpu_dpm_thermal { 65 /* thermal interrupt work */ 66 struct work_struct work; 67 /* low temperature threshold */ 68 int min_temp; 69 /* high temperature threshold */ 70 int max_temp; 71 /* edge max emergency(shutdown) temp */ 72 int max_edge_emergency_temp; 73 /* hotspot low temperature threshold */ 74 int min_hotspot_temp; 75 /* hotspot high temperature critical threshold */ 76 int max_hotspot_crit_temp; 77 /* hotspot max emergency(shutdown) temp */ 78 int max_hotspot_emergency_temp; 79 /* memory low temperature threshold */ 80 int min_mem_temp; 81 /* memory high temperature critical threshold */ 82 int max_mem_crit_temp; 83 /* memory max emergency(shutdown) temp */ 84 int max_mem_emergency_temp; 85 /* was last interrupt low to high or high to low */ 86 bool high_to_low; 87 /* interrupt source */ 88 struct amdgpu_irq_src irq; 89 }; 90 91 struct amdgpu_clock_and_voltage_limits { 92 u32 sclk; 93 u32 mclk; 94 u16 vddc; 95 u16 vddci; 96 }; 97 98 struct amdgpu_clock_array { 99 u32 count; 100 u32 *values; 101 }; 102 103 struct amdgpu_clock_voltage_dependency_entry { 104 u32 clk; 105 u16 v; 106 }; 107 108 struct amdgpu_clock_voltage_dependency_table { 109 u32 count; 110 struct amdgpu_clock_voltage_dependency_entry *entries; 111 }; 112 113 union amdgpu_cac_leakage_entry { 114 struct { 115 u16 vddc; 116 u32 leakage; 117 }; 118 struct { 119 u16 vddc1; 120 u16 vddc2; 121 u16 vddc3; 122 }; 123 }; 124 125 struct amdgpu_cac_leakage_table { 126 u32 count; 127 union amdgpu_cac_leakage_entry *entries; 128 }; 129 130 struct amdgpu_phase_shedding_limits_entry { 131 u16 voltage; 132 u32 sclk; 133 u32 mclk; 134 }; 135 136 struct amdgpu_phase_shedding_limits_table { 137 u32 count; 138 struct amdgpu_phase_shedding_limits_entry *entries; 139 }; 140 141 struct amdgpu_uvd_clock_voltage_dependency_entry { 142 u32 vclk; 143 u32 dclk; 144 u16 v; 145 }; 146 147 struct amdgpu_uvd_clock_voltage_dependency_table { 148 u8 count; 149 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 150 }; 151 152 struct amdgpu_vce_clock_voltage_dependency_entry { 153 u32 ecclk; 154 u32 evclk; 155 u16 v; 156 }; 157 158 struct amdgpu_vce_clock_voltage_dependency_table { 159 u8 count; 160 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 161 }; 162 163 struct amdgpu_ppm_table { 164 u8 ppm_design; 165 u16 cpu_core_number; 166 u32 platform_tdp; 167 u32 small_ac_platform_tdp; 168 u32 platform_tdc; 169 u32 small_ac_platform_tdc; 170 u32 apu_tdp; 171 u32 dgpu_tdp; 172 u32 dgpu_ulv_power; 173 u32 tj_max; 174 }; 175 176 struct amdgpu_cac_tdp_table { 177 u16 tdp; 178 u16 configurable_tdp; 179 u16 tdc; 180 u16 battery_power_limit; 181 u16 small_power_limit; 182 u16 low_cac_leakage; 183 u16 high_cac_leakage; 184 u16 maximum_power_delivery_limit; 185 }; 186 187 struct amdgpu_dpm_dynamic_state { 188 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 189 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 190 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 191 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 192 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 193 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 194 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 195 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 196 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 197 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 198 struct amdgpu_clock_array valid_sclk_values; 199 struct amdgpu_clock_array valid_mclk_values; 200 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 201 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 202 u32 mclk_sclk_ratio; 203 u32 sclk_mclk_delta; 204 u16 vddc_vddci_delta; 205 u16 min_vddc_for_pcie_gen2; 206 struct amdgpu_cac_leakage_table cac_leakage_table; 207 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 208 struct amdgpu_ppm_table *ppm_table; 209 struct amdgpu_cac_tdp_table *cac_tdp_table; 210 }; 211 212 struct amdgpu_dpm_fan { 213 u16 t_min; 214 u16 t_med; 215 u16 t_high; 216 u16 pwm_min; 217 u16 pwm_med; 218 u16 pwm_high; 219 u8 t_hyst; 220 u32 cycle_delay; 221 u16 t_max; 222 u8 control_mode; 223 u16 default_max_fan_pwm; 224 u16 default_fan_output_sensitivity; 225 u16 fan_output_sensitivity; 226 bool ucode_fan_control; 227 }; 228 229 struct amdgpu_dpm { 230 struct amdgpu_ps *ps; 231 /* number of valid power states */ 232 int num_ps; 233 /* current power state that is active */ 234 struct amdgpu_ps *current_ps; 235 /* requested power state */ 236 struct amdgpu_ps *requested_ps; 237 /* boot up power state */ 238 struct amdgpu_ps *boot_ps; 239 /* default uvd power state */ 240 struct amdgpu_ps *uvd_ps; 241 /* vce requirements */ 242 u32 num_of_vce_states; 243 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 244 enum amd_vce_level vce_level; 245 enum amd_pm_state_type state; 246 enum amd_pm_state_type user_state; 247 enum amd_pm_state_type last_state; 248 enum amd_pm_state_type last_user_state; 249 u32 platform_caps; 250 u32 voltage_response_time; 251 u32 backbias_response_time; 252 void *priv; 253 u32 new_active_crtcs; 254 int new_active_crtc_count; 255 u32 current_active_crtcs; 256 int current_active_crtc_count; 257 struct amdgpu_dpm_dynamic_state dyn_state; 258 struct amdgpu_dpm_fan fan; 259 u32 tdp_limit; 260 u32 near_tdp_limit; 261 u32 near_tdp_limit_adjusted; 262 u32 sq_ramping_threshold; 263 u32 cac_leakage; 264 u16 tdp_od_limit; 265 u32 tdp_adjustment; 266 u16 load_line_slope; 267 bool power_control; 268 /* special states active */ 269 bool thermal_active; 270 bool uvd_active; 271 bool vce_active; 272 /* thermal handling */ 273 struct amdgpu_dpm_thermal thermal; 274 /* forced levels */ 275 enum amd_dpm_forced_level forced_level; 276 }; 277 278 enum ip_power_state { 279 POWER_STATE_UNKNOWN, 280 POWER_STATE_ON, 281 POWER_STATE_OFF, 282 }; 283 284 /* Used to mask smu debug modes */ 285 #define SMU_DEBUG_HALT_ON_ERROR 0x1 286 287 #define MAX_SMU_I2C_BUSES 2 288 289 struct amdgpu_smu_i2c_bus { 290 struct i2c_adapter adapter; 291 struct amdgpu_device *adev; 292 int port; 293 struct mutex mutex; 294 }; 295 296 struct amdgpu_pm { 297 struct mutex mutex; 298 u32 current_sclk; 299 u32 current_mclk; 300 u32 default_sclk; 301 u32 default_mclk; 302 struct amdgpu_i2c_chan *i2c_bus; 303 bool bus_locked; 304 /* internal thermal controller on rv6xx+ */ 305 enum amdgpu_int_thermal_type int_thermal_type; 306 struct device *int_hwmon_dev; 307 /* fan control parameters */ 308 bool no_fan; 309 u8 fan_pulses_per_revolution; 310 u8 fan_min_rpm; 311 u8 fan_max_rpm; 312 /* dpm */ 313 bool dpm_enabled; 314 bool sysfs_initialized; 315 struct amdgpu_dpm dpm; 316 const struct firmware *fw; /* SMC firmware */ 317 uint32_t fw_version; 318 uint32_t pcie_gen_mask; 319 uint32_t pcie_mlw_mask; 320 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ 321 uint32_t smu_prv_buffer_size; 322 struct amdgpu_bo *smu_prv_buffer; 323 bool ac_power; 324 /* powerplay feature */ 325 uint32_t pp_feature; 326 327 /* Used for I2C access to various EEPROMs on relevant ASICs */ 328 struct amdgpu_smu_i2c_bus smu_i2c[MAX_SMU_I2C_BUSES]; 329 struct i2c_adapter *ras_eeprom_i2c_bus; 330 struct i2c_adapter *fru_eeprom_i2c_bus; 331 struct list_head pm_attr_list; 332 333 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM]; 334 335 /* 336 * 0 = disabled (default), otherwise enable corresponding debug mode 337 */ 338 uint32_t smu_debug_mask; 339 340 bool pp_force_state_enabled; 341 342 struct mutex stable_pstate_ctx_lock; 343 struct amdgpu_ctx *stable_pstate_ctx; 344 }; 345 346 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); 347 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 348 void *data, uint32_t *size); 349 350 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, 351 uint32_t block_type, bool gate); 352 353 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); 354 355 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low); 356 357 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 358 uint32_t pstate); 359 360 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 361 enum PP_SMC_POWER_PROFILE type, 362 bool en); 363 364 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev); 365 366 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev); 367 368 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev); 369 370 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev); 371 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); 372 373 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 374 enum pp_mp1_state mp1_state); 375 376 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); 377 378 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); 379 380 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 381 uint32_t cstate); 382 383 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en); 384 385 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev); 386 387 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 388 uint32_t msg_id); 389 390 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 391 bool acquire); 392 393 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); 394 395 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev); 396 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); 397 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable); 398 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable); 399 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version); 400 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable); 401 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size); 402 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 403 enum pp_clock_type type, 404 uint32_t *min, 405 uint32_t *max); 406 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 407 enum pp_clock_type type, 408 uint32_t min, 409 uint32_t max); 410 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev); 411 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 412 uint64_t event_arg); 413 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); 414 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev); 415 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 416 enum gfx_change_state state); 417 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 418 void *umc_ecc); 419 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 420 uint32_t idx); 421 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state); 422 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 423 enum amd_pm_state_type state); 424 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev); 425 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 426 enum amd_dpm_forced_level level); 427 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 428 struct pp_states_info *states); 429 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 430 enum amd_pp_task task_id, 431 enum amd_pm_state_type *user_state); 432 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table); 433 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 434 uint32_t type, 435 long *input, 436 uint32_t size); 437 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 438 uint32_t type, 439 long *input, 440 uint32_t size); 441 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 442 enum pp_clock_type type, 443 char *buf); 444 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 445 uint64_t ppfeature_masks); 446 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf); 447 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 448 enum pp_clock_type type, 449 uint32_t mask); 450 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev); 451 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value); 452 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev); 453 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value); 454 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 455 char *buf); 456 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 457 long *input, uint32_t size); 458 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table); 459 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 460 uint32_t *fan_mode); 461 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 462 uint32_t speed); 463 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 464 uint32_t *speed); 465 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 466 uint32_t *speed); 467 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 468 uint32_t speed); 469 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 470 uint32_t mode); 471 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 472 uint32_t *limit, 473 enum pp_power_limit_level pp_limit_level, 474 enum pp_power_type power_type); 475 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 476 uint32_t limit); 477 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev); 478 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 479 struct seq_file *m); 480 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 481 void **addr, 482 size_t *size); 483 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev); 484 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 485 const char *buf, 486 size_t size); 487 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev); 488 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev); 489 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 490 const struct amd_pp_display_configuration *input); 491 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 492 enum amd_pp_clock_type type, 493 struct amd_pp_clocks *clocks); 494 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 495 struct amd_pp_simple_clock_info *clocks); 496 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 497 enum amd_pp_clock_type type, 498 struct pp_clock_levels_with_latency *clocks); 499 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 500 enum amd_pp_clock_type type, 501 struct pp_clock_levels_with_voltage *clocks); 502 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 503 void *clock_ranges); 504 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 505 struct pp_display_clock_request *clock); 506 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 507 struct amd_pp_clock_info *clocks); 508 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev); 509 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 510 uint32_t count); 511 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 512 uint32_t clock); 513 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 514 uint32_t clock); 515 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 516 uint32_t clock); 517 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 518 bool disable_memory_clock_switch); 519 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 520 struct pp_smu_nv_clock_table *max_clocks); 521 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 522 unsigned int *clock_values_in_khz, 523 unsigned int *num_states); 524 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 525 struct dpm_clocks *clock_table); 526 #endif 527