1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 29 struct amd_vce_state { 30 /* vce clocks */ 31 u32 evclk; 32 u32 ecclk; 33 /* gpu clocks */ 34 u32 sclk; 35 u32 mclk; 36 u8 clk_idx; 37 u8 pstate; 38 }; 39 40 41 enum amd_dpm_forced_level { 42 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 43 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 44 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 45 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 46 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 47 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 49 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 50 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 51 }; 52 53 enum amd_pm_state_type { 54 /* not used for dpm */ 55 POWER_STATE_TYPE_DEFAULT, 56 POWER_STATE_TYPE_POWERSAVE, 57 /* user selectable states */ 58 POWER_STATE_TYPE_BATTERY, 59 POWER_STATE_TYPE_BALANCED, 60 POWER_STATE_TYPE_PERFORMANCE, 61 /* internal states */ 62 POWER_STATE_TYPE_INTERNAL_UVD, 63 POWER_STATE_TYPE_INTERNAL_UVD_SD, 64 POWER_STATE_TYPE_INTERNAL_UVD_HD, 65 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 66 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 67 POWER_STATE_TYPE_INTERNAL_BOOT, 68 POWER_STATE_TYPE_INTERNAL_THERMAL, 69 POWER_STATE_TYPE_INTERNAL_ACPI, 70 POWER_STATE_TYPE_INTERNAL_ULV, 71 POWER_STATE_TYPE_INTERNAL_3DPERF, 72 }; 73 74 #define AMD_MAX_VCE_LEVELS 6 75 76 enum amd_vce_level { 77 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 78 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 79 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 80 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 81 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 82 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 83 }; 84 85 enum amd_fan_ctrl_mode { 86 AMD_FAN_CTRL_NONE = 0, 87 AMD_FAN_CTRL_MANUAL = 1, 88 AMD_FAN_CTRL_AUTO = 2, 89 }; 90 91 enum pp_clock_type { 92 PP_SCLK, 93 PP_MCLK, 94 PP_PCIE, 95 OD_SCLK, 96 OD_MCLK, 97 }; 98 99 enum amd_pp_sensors { 100 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 101 AMDGPU_PP_SENSOR_VDDNB, 102 AMDGPU_PP_SENSOR_VDDGFX, 103 AMDGPU_PP_SENSOR_UVD_VCLK, 104 AMDGPU_PP_SENSOR_UVD_DCLK, 105 AMDGPU_PP_SENSOR_VCE_ECCLK, 106 AMDGPU_PP_SENSOR_GPU_LOAD, 107 AMDGPU_PP_SENSOR_GFX_MCLK, 108 AMDGPU_PP_SENSOR_GPU_TEMP, 109 AMDGPU_PP_SENSOR_VCE_POWER, 110 AMDGPU_PP_SENSOR_UVD_POWER, 111 AMDGPU_PP_SENSOR_GPU_POWER, 112 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 113 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 114 }; 115 116 enum amd_pp_task { 117 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 118 AMD_PP_TASK_ENABLE_USER_STATE, 119 AMD_PP_TASK_READJUST_POWER_STATE, 120 AMD_PP_TASK_COMPLETE_INIT, 121 AMD_PP_TASK_MAX 122 }; 123 124 enum PP_SMC_POWER_PROFILE { 125 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x0, 126 PP_SMC_POWER_PROFILE_POWERSAVING = 0x1, 127 PP_SMC_POWER_PROFILE_VIDEO = 0x2, 128 PP_SMC_POWER_PROFILE_VR = 0x3, 129 PP_SMC_POWER_PROFILE_COMPUTE = 0x4, 130 PP_SMC_POWER_PROFILE_CUSTOM = 0x5, 131 }; 132 133 enum { 134 PP_GROUP_UNKNOWN = 0, 135 PP_GROUP_GFX = 1, 136 PP_GROUP_SYS, 137 PP_GROUP_MAX 138 }; 139 140 enum PP_OD_DPM_TABLE_COMMAND { 141 PP_OD_EDIT_SCLK_VDDC_TABLE, 142 PP_OD_EDIT_MCLK_VDDC_TABLE, 143 PP_OD_RESTORE_DEFAULT_TABLE, 144 PP_OD_COMMIT_DPM_TABLE 145 }; 146 147 struct pp_states_info { 148 uint32_t nums; 149 uint32_t states[16]; 150 }; 151 152 struct pp_gpu_power { 153 uint32_t vddc_power; 154 uint32_t vddci_power; 155 uint32_t max_gpu_power; 156 uint32_t average_gpu_power; 157 }; 158 159 #define PP_GROUP_MASK 0xF0000000 160 #define PP_GROUP_SHIFT 28 161 162 #define PP_BLOCK_MASK 0x0FFFFF00 163 #define PP_BLOCK_SHIFT 8 164 165 #define PP_BLOCK_GFX_CG 0x01 166 #define PP_BLOCK_GFX_MG 0x02 167 #define PP_BLOCK_GFX_3D 0x04 168 #define PP_BLOCK_GFX_RLC 0x08 169 #define PP_BLOCK_GFX_CP 0x10 170 #define PP_BLOCK_SYS_BIF 0x01 171 #define PP_BLOCK_SYS_MC 0x02 172 #define PP_BLOCK_SYS_ROM 0x04 173 #define PP_BLOCK_SYS_DRM 0x08 174 #define PP_BLOCK_SYS_HDP 0x10 175 #define PP_BLOCK_SYS_SDMA 0x20 176 177 #define PP_STATE_MASK 0x0000000F 178 #define PP_STATE_SHIFT 0 179 #define PP_STATE_SUPPORT_MASK 0x000000F0 180 #define PP_STATE_SUPPORT_SHIFT 0 181 182 #define PP_STATE_CG 0x01 183 #define PP_STATE_LS 0x02 184 #define PP_STATE_DS 0x04 185 #define PP_STATE_SD 0x08 186 #define PP_STATE_SUPPORT_CG 0x10 187 #define PP_STATE_SUPPORT_LS 0x20 188 #define PP_STATE_SUPPORT_DS 0x40 189 #define PP_STATE_SUPPORT_SD 0x80 190 191 #define PP_CG_MSG_ID(group, block, support, state) \ 192 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 193 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 194 195 struct seq_file; 196 enum amd_pp_clock_type; 197 struct amd_pp_simple_clock_info; 198 struct amd_pp_display_configuration; 199 struct amd_pp_clock_info; 200 struct pp_display_clock_request; 201 struct pp_wm_sets_with_clock_ranges_soc15; 202 struct pp_clock_levels_with_voltage; 203 struct pp_clock_levels_with_latency; 204 struct amd_pp_clocks; 205 206 struct amd_pm_funcs { 207 /* export for dpm on ci and si */ 208 int (*pre_set_power_state)(void *handle); 209 int (*set_power_state)(void *handle); 210 void (*post_set_power_state)(void *handle); 211 void (*display_configuration_changed)(void *handle); 212 void (*print_power_state)(void *handle, void *ps); 213 bool (*vblank_too_short)(void *handle); 214 void (*enable_bapm)(void *handle, bool enable); 215 int (*check_state_equal)(void *handle, 216 void *cps, 217 void *rps, 218 bool *equal); 219 /* export for sysfs */ 220 void (*set_fan_control_mode)(void *handle, u32 mode); 221 u32 (*get_fan_control_mode)(void *handle); 222 int (*set_fan_speed_percent)(void *handle, u32 speed); 223 int (*get_fan_speed_percent)(void *handle, u32 *speed); 224 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 225 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 226 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 227 int (*get_sclk_od)(void *handle); 228 int (*set_sclk_od)(void *handle, uint32_t value); 229 int (*get_mclk_od)(void *handle); 230 int (*set_mclk_od)(void *handle, uint32_t value); 231 int (*read_sensor)(void *handle, int idx, void *value, int *size); 232 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 233 enum amd_pm_state_type (*get_current_power_state)(void *handle); 234 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 235 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 236 int (*get_pp_table)(void *handle, char **table); 237 int (*set_pp_table)(void *handle, const char *buf, size_t size); 238 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 239 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 240 /* export to amdgpu */ 241 void (*powergate_uvd)(void *handle, bool gate); 242 void (*powergate_vce)(void *handle, bool gate); 243 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 244 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 245 enum amd_pm_state_type *user_state); 246 int (*load_firmware)(void *handle); 247 int (*wait_for_fw_loading_complete)(void *handle); 248 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 249 int (*notify_smu_memory_info)(void *handle, uint32_t virtual_addr_low, 250 uint32_t virtual_addr_hi, 251 uint32_t mc_addr_low, 252 uint32_t mc_addr_hi, 253 uint32_t size); 254 int (*set_power_limit)(void *handle, uint32_t n); 255 int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit); 256 /* export to DC */ 257 u32 (*get_sclk)(void *handle, bool low); 258 u32 (*get_mclk)(void *handle, bool low); 259 int (*display_configuration_change)(void *handle, 260 const struct amd_pp_display_configuration *input); 261 int (*get_display_power_level)(void *handle, 262 struct amd_pp_simple_clock_info *output); 263 int (*get_current_clocks)(void *handle, 264 struct amd_pp_clock_info *clocks); 265 int (*get_clock_by_type)(void *handle, 266 enum amd_pp_clock_type type, 267 struct amd_pp_clocks *clocks); 268 int (*get_clock_by_type_with_latency)(void *handle, 269 enum amd_pp_clock_type type, 270 struct pp_clock_levels_with_latency *clocks); 271 int (*get_clock_by_type_with_voltage)(void *handle, 272 enum amd_pp_clock_type type, 273 struct pp_clock_levels_with_voltage *clocks); 274 int (*set_watermarks_for_clocks_ranges)(void *handle, 275 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); 276 int (*display_clock_voltage_request)(void *handle, 277 struct pp_display_clock_request *clock); 278 int (*get_display_mode_validation_clocks)(void *handle, 279 struct amd_pp_simple_clock_info *clocks); 280 int (*get_power_profile_mode)(void *handle, char *buf); 281 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 282 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size); 283 int (*set_mmhub_powergating_by_smu)(void *handle); 284 }; 285 286 #endif 287