1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 32 enum smu_event_type { 33 SMU_EVENT_RESET_COMPLETE = 0, 34 }; 35 36 struct amd_vce_state { 37 /* vce clocks */ 38 u32 evclk; 39 u32 ecclk; 40 /* gpu clocks */ 41 u32 sclk; 42 u32 mclk; 43 u8 clk_idx; 44 u8 pstate; 45 }; 46 47 48 enum amd_dpm_forced_level { 49 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 50 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 51 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 52 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 53 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 54 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 56 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 57 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 58 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 59 }; 60 61 enum amd_pm_state_type { 62 /* not used for dpm */ 63 POWER_STATE_TYPE_DEFAULT, 64 POWER_STATE_TYPE_POWERSAVE, 65 /* user selectable states */ 66 POWER_STATE_TYPE_BATTERY, 67 POWER_STATE_TYPE_BALANCED, 68 POWER_STATE_TYPE_PERFORMANCE, 69 /* internal states */ 70 POWER_STATE_TYPE_INTERNAL_UVD, 71 POWER_STATE_TYPE_INTERNAL_UVD_SD, 72 POWER_STATE_TYPE_INTERNAL_UVD_HD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 74 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 75 POWER_STATE_TYPE_INTERNAL_BOOT, 76 POWER_STATE_TYPE_INTERNAL_THERMAL, 77 POWER_STATE_TYPE_INTERNAL_ACPI, 78 POWER_STATE_TYPE_INTERNAL_ULV, 79 POWER_STATE_TYPE_INTERNAL_3DPERF, 80 }; 81 82 #define AMD_MAX_VCE_LEVELS 6 83 84 enum amd_vce_level { 85 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 86 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 87 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 88 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 89 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 90 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 91 }; 92 93 enum amd_fan_ctrl_mode { 94 AMD_FAN_CTRL_NONE = 0, 95 AMD_FAN_CTRL_MANUAL = 1, 96 AMD_FAN_CTRL_AUTO = 2, 97 }; 98 99 enum pp_clock_type { 100 PP_SCLK, 101 PP_MCLK, 102 PP_PCIE, 103 PP_SOCCLK, 104 PP_FCLK, 105 PP_DCEFCLK, 106 PP_VCLK, 107 PP_DCLK, 108 OD_SCLK, 109 OD_MCLK, 110 OD_VDDC_CURVE, 111 OD_RANGE, 112 OD_VDDGFX_OFFSET, 113 OD_CCLK, 114 }; 115 116 enum amd_pp_sensors { 117 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 118 AMDGPU_PP_SENSOR_CPU_CLK, 119 AMDGPU_PP_SENSOR_VDDNB, 120 AMDGPU_PP_SENSOR_VDDGFX, 121 AMDGPU_PP_SENSOR_UVD_VCLK, 122 AMDGPU_PP_SENSOR_UVD_DCLK, 123 AMDGPU_PP_SENSOR_VCE_ECCLK, 124 AMDGPU_PP_SENSOR_GPU_LOAD, 125 AMDGPU_PP_SENSOR_MEM_LOAD, 126 AMDGPU_PP_SENSOR_GFX_MCLK, 127 AMDGPU_PP_SENSOR_GPU_TEMP, 128 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 129 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 130 AMDGPU_PP_SENSOR_MEM_TEMP, 131 AMDGPU_PP_SENSOR_VCE_POWER, 132 AMDGPU_PP_SENSOR_UVD_POWER, 133 AMDGPU_PP_SENSOR_GPU_POWER, 134 AMDGPU_PP_SENSOR_SS_APU_SHARE, 135 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 136 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 137 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 138 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 139 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 140 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 141 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 142 }; 143 144 enum amd_pp_task { 145 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 146 AMD_PP_TASK_ENABLE_USER_STATE, 147 AMD_PP_TASK_READJUST_POWER_STATE, 148 AMD_PP_TASK_COMPLETE_INIT, 149 AMD_PP_TASK_MAX 150 }; 151 152 enum PP_SMC_POWER_PROFILE { 153 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 154 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 155 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 156 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 157 PP_SMC_POWER_PROFILE_VR = 0x4, 158 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 159 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 160 PP_SMC_POWER_PROFILE_COUNT, 161 }; 162 163 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 164 165 166 167 enum { 168 PP_GROUP_UNKNOWN = 0, 169 PP_GROUP_GFX = 1, 170 PP_GROUP_SYS, 171 PP_GROUP_MAX 172 }; 173 174 enum PP_OD_DPM_TABLE_COMMAND { 175 PP_OD_EDIT_SCLK_VDDC_TABLE, 176 PP_OD_EDIT_MCLK_VDDC_TABLE, 177 PP_OD_EDIT_CCLK_VDDC_TABLE, 178 PP_OD_EDIT_VDDC_CURVE, 179 PP_OD_RESTORE_DEFAULT_TABLE, 180 PP_OD_COMMIT_DPM_TABLE, 181 PP_OD_EDIT_VDDGFX_OFFSET 182 }; 183 184 struct pp_states_info { 185 uint32_t nums; 186 uint32_t states[16]; 187 }; 188 189 enum PP_HWMON_TEMP { 190 PP_TEMP_EDGE = 0, 191 PP_TEMP_JUNCTION, 192 PP_TEMP_MEM, 193 PP_TEMP_MAX 194 }; 195 196 enum pp_mp1_state { 197 PP_MP1_STATE_NONE, 198 PP_MP1_STATE_SHUTDOWN, 199 PP_MP1_STATE_UNLOAD, 200 PP_MP1_STATE_RESET, 201 }; 202 203 enum pp_df_cstate { 204 DF_CSTATE_DISALLOW = 0, 205 DF_CSTATE_ALLOW, 206 }; 207 208 /** 209 * DOC: amdgpu_pp_power 210 * 211 * APU power is managed to system-level requirements through the PPT 212 * (package power tracking) feature. PPT is intended to limit power to the 213 * requirements of the power source and could be dynamically updated to 214 * maximize APU performance within the system power budget. 215 * 216 * Two types of power measurement can be requested, where supported, with 217 * :c:type:`enum pp_power_type <pp_power_type>`. 218 */ 219 220 /** 221 * enum pp_power_limit_level - Used to query the power limits 222 * 223 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 224 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 225 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 226 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 227 */ 228 enum pp_power_limit_level 229 { 230 PP_PWR_LIMIT_MIN = -1, 231 PP_PWR_LIMIT_CURRENT, 232 PP_PWR_LIMIT_DEFAULT, 233 PP_PWR_LIMIT_MAX, 234 }; 235 236 /** 237 * enum pp_power_type - Used to specify the type of the requested power 238 * 239 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 240 * moving average of APU power (default ~5000 ms). 241 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 242 * where supported. 243 */ 244 enum pp_power_type 245 { 246 PP_PWR_TYPE_SUSTAINED, 247 PP_PWR_TYPE_FAST, 248 }; 249 250 #define PP_GROUP_MASK 0xF0000000 251 #define PP_GROUP_SHIFT 28 252 253 #define PP_BLOCK_MASK 0x0FFFFF00 254 #define PP_BLOCK_SHIFT 8 255 256 #define PP_BLOCK_GFX_CG 0x01 257 #define PP_BLOCK_GFX_MG 0x02 258 #define PP_BLOCK_GFX_3D 0x04 259 #define PP_BLOCK_GFX_RLC 0x08 260 #define PP_BLOCK_GFX_CP 0x10 261 #define PP_BLOCK_SYS_BIF 0x01 262 #define PP_BLOCK_SYS_MC 0x02 263 #define PP_BLOCK_SYS_ROM 0x04 264 #define PP_BLOCK_SYS_DRM 0x08 265 #define PP_BLOCK_SYS_HDP 0x10 266 #define PP_BLOCK_SYS_SDMA 0x20 267 268 #define PP_STATE_MASK 0x0000000F 269 #define PP_STATE_SHIFT 0 270 #define PP_STATE_SUPPORT_MASK 0x000000F0 271 #define PP_STATE_SUPPORT_SHIFT 0 272 273 #define PP_STATE_CG 0x01 274 #define PP_STATE_LS 0x02 275 #define PP_STATE_DS 0x04 276 #define PP_STATE_SD 0x08 277 #define PP_STATE_SUPPORT_CG 0x10 278 #define PP_STATE_SUPPORT_LS 0x20 279 #define PP_STATE_SUPPORT_DS 0x40 280 #define PP_STATE_SUPPORT_SD 0x80 281 282 #define PP_CG_MSG_ID(group, block, support, state) \ 283 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 284 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 285 286 #define XGMI_MODE_PSTATE_D3 0 287 #define XGMI_MODE_PSTATE_D0 1 288 289 #define NUM_HBM_INSTANCES 4 290 291 struct seq_file; 292 enum amd_pp_clock_type; 293 struct amd_pp_simple_clock_info; 294 struct amd_pp_display_configuration; 295 struct amd_pp_clock_info; 296 struct pp_display_clock_request; 297 struct pp_clock_levels_with_voltage; 298 struct pp_clock_levels_with_latency; 299 struct amd_pp_clocks; 300 struct pp_smu_wm_range_sets; 301 struct pp_smu_nv_clock_table; 302 struct dpm_clocks; 303 304 struct amd_pm_funcs { 305 /* export for dpm on ci and si */ 306 int (*pre_set_power_state)(void *handle); 307 int (*set_power_state)(void *handle); 308 void (*post_set_power_state)(void *handle); 309 void (*display_configuration_changed)(void *handle); 310 void (*print_power_state)(void *handle, void *ps); 311 bool (*vblank_too_short)(void *handle); 312 void (*enable_bapm)(void *handle, bool enable); 313 int (*check_state_equal)(void *handle, 314 void *cps, 315 void *rps, 316 bool *equal); 317 /* export for sysfs */ 318 int (*set_fan_control_mode)(void *handle, u32 mode); 319 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 320 int (*set_fan_speed_pwm)(void *handle, u32 speed); 321 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 322 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 323 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 324 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 325 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 326 int (*get_sclk_od)(void *handle); 327 int (*set_sclk_od)(void *handle, uint32_t value); 328 int (*get_mclk_od)(void *handle); 329 int (*set_mclk_od)(void *handle, uint32_t value); 330 int (*read_sensor)(void *handle, int idx, void *value, int *size); 331 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 332 enum amd_pm_state_type (*get_current_power_state)(void *handle); 333 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 334 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 335 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 336 int (*get_pp_table)(void *handle, char **table); 337 int (*set_pp_table)(void *handle, const char *buf, size_t size); 338 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 339 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 340 /* export to amdgpu */ 341 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 342 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 343 enum amd_pm_state_type *user_state); 344 int (*load_firmware)(void *handle); 345 int (*wait_for_fw_loading_complete)(void *handle); 346 int (*set_powergating_by_smu)(void *handle, 347 uint32_t block_type, bool gate); 348 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 349 int (*set_power_limit)(void *handle, uint32_t n); 350 int (*get_power_limit)(void *handle, uint32_t *limit, 351 enum pp_power_limit_level pp_limit_level, 352 enum pp_power_type power_type); 353 int (*get_power_profile_mode)(void *handle, char *buf); 354 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 355 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 356 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size); 357 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 358 int (*smu_i2c_bus_access)(void *handle, bool acquire); 359 int (*gfx_state_change_set)(void *handle, uint32_t state); 360 /* export to DC */ 361 u32 (*get_sclk)(void *handle, bool low); 362 u32 (*get_mclk)(void *handle, bool low); 363 int (*display_configuration_change)(void *handle, 364 const struct amd_pp_display_configuration *input); 365 int (*get_display_power_level)(void *handle, 366 struct amd_pp_simple_clock_info *output); 367 int (*get_current_clocks)(void *handle, 368 struct amd_pp_clock_info *clocks); 369 int (*get_clock_by_type)(void *handle, 370 enum amd_pp_clock_type type, 371 struct amd_pp_clocks *clocks); 372 int (*get_clock_by_type_with_latency)(void *handle, 373 enum amd_pp_clock_type type, 374 struct pp_clock_levels_with_latency *clocks); 375 int (*get_clock_by_type_with_voltage)(void *handle, 376 enum amd_pp_clock_type type, 377 struct pp_clock_levels_with_voltage *clocks); 378 int (*set_watermarks_for_clocks_ranges)(void *handle, 379 void *clock_ranges); 380 int (*display_clock_voltage_request)(void *handle, 381 struct pp_display_clock_request *clock); 382 int (*get_display_mode_validation_clocks)(void *handle, 383 struct amd_pp_simple_clock_info *clocks); 384 int (*notify_smu_enable_pwe)(void *handle); 385 int (*enable_mgpu_fan_boost)(void *handle); 386 int (*set_active_display_count)(void *handle, uint32_t count); 387 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 388 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 389 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 390 int (*get_asic_baco_capability)(void *handle, bool *cap); 391 int (*get_asic_baco_state)(void *handle, int *state); 392 int (*set_asic_baco_state)(void *handle, int state); 393 int (*get_ppfeature_status)(void *handle, char *buf); 394 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 395 int (*asic_reset_mode_2)(void *handle); 396 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 397 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 398 ssize_t (*get_gpu_metrics)(void *handle, void **table); 399 int (*set_watermarks_for_clock_ranges)(void *handle, 400 struct pp_smu_wm_range_sets *ranges); 401 int (*display_disable_memory_clock_switch)(void *handle, 402 bool disable_memory_clock_switch); 403 int (*get_max_sustainable_clocks_by_dc)(void *handle, 404 struct pp_smu_nv_clock_table *max_clocks); 405 int (*get_uclk_dpm_states)(void *handle, 406 unsigned int *clock_values_in_khz, 407 unsigned int *num_states); 408 int (*get_dpm_clock_table)(void *handle, 409 struct dpm_clocks *clock_table); 410 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 411 void (*pm_compute_clocks)(void *handle); 412 }; 413 414 struct metrics_table_header { 415 uint16_t structure_size; 416 uint8_t format_revision; 417 uint8_t content_revision; 418 }; 419 420 /* 421 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 422 * Use gpu_metrics_v1_1 or later instead. 423 */ 424 struct gpu_metrics_v1_0 { 425 struct metrics_table_header common_header; 426 427 /* Driver attached timestamp (in ns) */ 428 uint64_t system_clock_counter; 429 430 /* Temperature */ 431 uint16_t temperature_edge; 432 uint16_t temperature_hotspot; 433 uint16_t temperature_mem; 434 uint16_t temperature_vrgfx; 435 uint16_t temperature_vrsoc; 436 uint16_t temperature_vrmem; 437 438 /* Utilization */ 439 uint16_t average_gfx_activity; 440 uint16_t average_umc_activity; // memory controller 441 uint16_t average_mm_activity; // UVD or VCN 442 443 /* Power/Energy */ 444 uint16_t average_socket_power; 445 uint32_t energy_accumulator; 446 447 /* Average clocks */ 448 uint16_t average_gfxclk_frequency; 449 uint16_t average_socclk_frequency; 450 uint16_t average_uclk_frequency; 451 uint16_t average_vclk0_frequency; 452 uint16_t average_dclk0_frequency; 453 uint16_t average_vclk1_frequency; 454 uint16_t average_dclk1_frequency; 455 456 /* Current clocks */ 457 uint16_t current_gfxclk; 458 uint16_t current_socclk; 459 uint16_t current_uclk; 460 uint16_t current_vclk0; 461 uint16_t current_dclk0; 462 uint16_t current_vclk1; 463 uint16_t current_dclk1; 464 465 /* Throttle status */ 466 uint32_t throttle_status; 467 468 /* Fans */ 469 uint16_t current_fan_speed; 470 471 /* Link width/speed */ 472 uint8_t pcie_link_width; 473 uint8_t pcie_link_speed; // in 0.1 GT/s 474 }; 475 476 struct gpu_metrics_v1_1 { 477 struct metrics_table_header common_header; 478 479 /* Temperature */ 480 uint16_t temperature_edge; 481 uint16_t temperature_hotspot; 482 uint16_t temperature_mem; 483 uint16_t temperature_vrgfx; 484 uint16_t temperature_vrsoc; 485 uint16_t temperature_vrmem; 486 487 /* Utilization */ 488 uint16_t average_gfx_activity; 489 uint16_t average_umc_activity; // memory controller 490 uint16_t average_mm_activity; // UVD or VCN 491 492 /* Power/Energy */ 493 uint16_t average_socket_power; 494 uint64_t energy_accumulator; 495 496 /* Driver attached timestamp (in ns) */ 497 uint64_t system_clock_counter; 498 499 /* Average clocks */ 500 uint16_t average_gfxclk_frequency; 501 uint16_t average_socclk_frequency; 502 uint16_t average_uclk_frequency; 503 uint16_t average_vclk0_frequency; 504 uint16_t average_dclk0_frequency; 505 uint16_t average_vclk1_frequency; 506 uint16_t average_dclk1_frequency; 507 508 /* Current clocks */ 509 uint16_t current_gfxclk; 510 uint16_t current_socclk; 511 uint16_t current_uclk; 512 uint16_t current_vclk0; 513 uint16_t current_dclk0; 514 uint16_t current_vclk1; 515 uint16_t current_dclk1; 516 517 /* Throttle status */ 518 uint32_t throttle_status; 519 520 /* Fans */ 521 uint16_t current_fan_speed; 522 523 /* Link width/speed */ 524 uint16_t pcie_link_width; 525 uint16_t pcie_link_speed; // in 0.1 GT/s 526 527 uint16_t padding; 528 529 uint32_t gfx_activity_acc; 530 uint32_t mem_activity_acc; 531 532 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 533 }; 534 535 struct gpu_metrics_v1_2 { 536 struct metrics_table_header common_header; 537 538 /* Temperature */ 539 uint16_t temperature_edge; 540 uint16_t temperature_hotspot; 541 uint16_t temperature_mem; 542 uint16_t temperature_vrgfx; 543 uint16_t temperature_vrsoc; 544 uint16_t temperature_vrmem; 545 546 /* Utilization */ 547 uint16_t average_gfx_activity; 548 uint16_t average_umc_activity; // memory controller 549 uint16_t average_mm_activity; // UVD or VCN 550 551 /* Power/Energy */ 552 uint16_t average_socket_power; 553 uint64_t energy_accumulator; 554 555 /* Driver attached timestamp (in ns) */ 556 uint64_t system_clock_counter; 557 558 /* Average clocks */ 559 uint16_t average_gfxclk_frequency; 560 uint16_t average_socclk_frequency; 561 uint16_t average_uclk_frequency; 562 uint16_t average_vclk0_frequency; 563 uint16_t average_dclk0_frequency; 564 uint16_t average_vclk1_frequency; 565 uint16_t average_dclk1_frequency; 566 567 /* Current clocks */ 568 uint16_t current_gfxclk; 569 uint16_t current_socclk; 570 uint16_t current_uclk; 571 uint16_t current_vclk0; 572 uint16_t current_dclk0; 573 uint16_t current_vclk1; 574 uint16_t current_dclk1; 575 576 /* Throttle status (ASIC dependent) */ 577 uint32_t throttle_status; 578 579 /* Fans */ 580 uint16_t current_fan_speed; 581 582 /* Link width/speed */ 583 uint16_t pcie_link_width; 584 uint16_t pcie_link_speed; // in 0.1 GT/s 585 586 uint16_t padding; 587 588 uint32_t gfx_activity_acc; 589 uint32_t mem_activity_acc; 590 591 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 592 593 /* PMFW attached timestamp (10ns resolution) */ 594 uint64_t firmware_timestamp; 595 }; 596 597 struct gpu_metrics_v1_3 { 598 struct metrics_table_header common_header; 599 600 /* Temperature */ 601 uint16_t temperature_edge; 602 uint16_t temperature_hotspot; 603 uint16_t temperature_mem; 604 uint16_t temperature_vrgfx; 605 uint16_t temperature_vrsoc; 606 uint16_t temperature_vrmem; 607 608 /* Utilization */ 609 uint16_t average_gfx_activity; 610 uint16_t average_umc_activity; // memory controller 611 uint16_t average_mm_activity; // UVD or VCN 612 613 /* Power/Energy */ 614 uint16_t average_socket_power; 615 uint64_t energy_accumulator; 616 617 /* Driver attached timestamp (in ns) */ 618 uint64_t system_clock_counter; 619 620 /* Average clocks */ 621 uint16_t average_gfxclk_frequency; 622 uint16_t average_socclk_frequency; 623 uint16_t average_uclk_frequency; 624 uint16_t average_vclk0_frequency; 625 uint16_t average_dclk0_frequency; 626 uint16_t average_vclk1_frequency; 627 uint16_t average_dclk1_frequency; 628 629 /* Current clocks */ 630 uint16_t current_gfxclk; 631 uint16_t current_socclk; 632 uint16_t current_uclk; 633 uint16_t current_vclk0; 634 uint16_t current_dclk0; 635 uint16_t current_vclk1; 636 uint16_t current_dclk1; 637 638 /* Throttle status */ 639 uint32_t throttle_status; 640 641 /* Fans */ 642 uint16_t current_fan_speed; 643 644 /* Link width/speed */ 645 uint16_t pcie_link_width; 646 uint16_t pcie_link_speed; // in 0.1 GT/s 647 648 uint16_t padding; 649 650 uint32_t gfx_activity_acc; 651 uint32_t mem_activity_acc; 652 653 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 654 655 /* PMFW attached timestamp (10ns resolution) */ 656 uint64_t firmware_timestamp; 657 658 /* Voltage (mV) */ 659 uint16_t voltage_soc; 660 uint16_t voltage_gfx; 661 uint16_t voltage_mem; 662 663 uint16_t padding1; 664 665 /* Throttle status (ASIC independent) */ 666 uint64_t indep_throttle_status; 667 }; 668 669 /* 670 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 671 * Use gpu_metrics_v2_1 or later instead. 672 */ 673 struct gpu_metrics_v2_0 { 674 struct metrics_table_header common_header; 675 676 /* Driver attached timestamp (in ns) */ 677 uint64_t system_clock_counter; 678 679 /* Temperature */ 680 uint16_t temperature_gfx; // gfx temperature on APUs 681 uint16_t temperature_soc; // soc temperature on APUs 682 uint16_t temperature_core[8]; // CPU core temperature on APUs 683 uint16_t temperature_l3[2]; 684 685 /* Utilization */ 686 uint16_t average_gfx_activity; 687 uint16_t average_mm_activity; // UVD or VCN 688 689 /* Power/Energy */ 690 uint16_t average_socket_power; // dGPU + APU power on A + A platform 691 uint16_t average_cpu_power; 692 uint16_t average_soc_power; 693 uint16_t average_gfx_power; 694 uint16_t average_core_power[8]; // CPU core power on APUs 695 696 /* Average clocks */ 697 uint16_t average_gfxclk_frequency; 698 uint16_t average_socclk_frequency; 699 uint16_t average_uclk_frequency; 700 uint16_t average_fclk_frequency; 701 uint16_t average_vclk_frequency; 702 uint16_t average_dclk_frequency; 703 704 /* Current clocks */ 705 uint16_t current_gfxclk; 706 uint16_t current_socclk; 707 uint16_t current_uclk; 708 uint16_t current_fclk; 709 uint16_t current_vclk; 710 uint16_t current_dclk; 711 uint16_t current_coreclk[8]; // CPU core clocks 712 uint16_t current_l3clk[2]; 713 714 /* Throttle status */ 715 uint32_t throttle_status; 716 717 /* Fans */ 718 uint16_t fan_pwm; 719 720 uint16_t padding; 721 }; 722 723 struct gpu_metrics_v2_1 { 724 struct metrics_table_header common_header; 725 726 /* Temperature */ 727 uint16_t temperature_gfx; // gfx temperature on APUs 728 uint16_t temperature_soc; // soc temperature on APUs 729 uint16_t temperature_core[8]; // CPU core temperature on APUs 730 uint16_t temperature_l3[2]; 731 732 /* Utilization */ 733 uint16_t average_gfx_activity; 734 uint16_t average_mm_activity; // UVD or VCN 735 736 /* Driver attached timestamp (in ns) */ 737 uint64_t system_clock_counter; 738 739 /* Power/Energy */ 740 uint16_t average_socket_power; // dGPU + APU power on A + A platform 741 uint16_t average_cpu_power; 742 uint16_t average_soc_power; 743 uint16_t average_gfx_power; 744 uint16_t average_core_power[8]; // CPU core power on APUs 745 746 /* Average clocks */ 747 uint16_t average_gfxclk_frequency; 748 uint16_t average_socclk_frequency; 749 uint16_t average_uclk_frequency; 750 uint16_t average_fclk_frequency; 751 uint16_t average_vclk_frequency; 752 uint16_t average_dclk_frequency; 753 754 /* Current clocks */ 755 uint16_t current_gfxclk; 756 uint16_t current_socclk; 757 uint16_t current_uclk; 758 uint16_t current_fclk; 759 uint16_t current_vclk; 760 uint16_t current_dclk; 761 uint16_t current_coreclk[8]; // CPU core clocks 762 uint16_t current_l3clk[2]; 763 764 /* Throttle status */ 765 uint32_t throttle_status; 766 767 /* Fans */ 768 uint16_t fan_pwm; 769 770 uint16_t padding[3]; 771 }; 772 773 struct gpu_metrics_v2_2 { 774 struct metrics_table_header common_header; 775 776 /* Temperature */ 777 uint16_t temperature_gfx; // gfx temperature on APUs 778 uint16_t temperature_soc; // soc temperature on APUs 779 uint16_t temperature_core[8]; // CPU core temperature on APUs 780 uint16_t temperature_l3[2]; 781 782 /* Utilization */ 783 uint16_t average_gfx_activity; 784 uint16_t average_mm_activity; // UVD or VCN 785 786 /* Driver attached timestamp (in ns) */ 787 uint64_t system_clock_counter; 788 789 /* Power/Energy */ 790 uint16_t average_socket_power; // dGPU + APU power on A + A platform 791 uint16_t average_cpu_power; 792 uint16_t average_soc_power; 793 uint16_t average_gfx_power; 794 uint16_t average_core_power[8]; // CPU core power on APUs 795 796 /* Average clocks */ 797 uint16_t average_gfxclk_frequency; 798 uint16_t average_socclk_frequency; 799 uint16_t average_uclk_frequency; 800 uint16_t average_fclk_frequency; 801 uint16_t average_vclk_frequency; 802 uint16_t average_dclk_frequency; 803 804 /* Current clocks */ 805 uint16_t current_gfxclk; 806 uint16_t current_socclk; 807 uint16_t current_uclk; 808 uint16_t current_fclk; 809 uint16_t current_vclk; 810 uint16_t current_dclk; 811 uint16_t current_coreclk[8]; // CPU core clocks 812 uint16_t current_l3clk[2]; 813 814 /* Throttle status (ASIC dependent) */ 815 uint32_t throttle_status; 816 817 /* Fans */ 818 uint16_t fan_pwm; 819 820 uint16_t padding[3]; 821 822 /* Throttle status (ASIC independent) */ 823 uint64_t indep_throttle_status; 824 }; 825 826 #endif 827