1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 32 enum smu_event_type { 33 SMU_EVENT_RESET_COMPLETE = 0, 34 }; 35 36 struct amd_vce_state { 37 /* vce clocks */ 38 u32 evclk; 39 u32 ecclk; 40 /* gpu clocks */ 41 u32 sclk; 42 u32 mclk; 43 u8 clk_idx; 44 u8 pstate; 45 }; 46 47 48 enum amd_dpm_forced_level { 49 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 50 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 51 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 52 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 53 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 54 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 56 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 57 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 58 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 59 }; 60 61 enum amd_pm_state_type { 62 /* not used for dpm */ 63 POWER_STATE_TYPE_DEFAULT, 64 POWER_STATE_TYPE_POWERSAVE, 65 /* user selectable states */ 66 POWER_STATE_TYPE_BATTERY, 67 POWER_STATE_TYPE_BALANCED, 68 POWER_STATE_TYPE_PERFORMANCE, 69 /* internal states */ 70 POWER_STATE_TYPE_INTERNAL_UVD, 71 POWER_STATE_TYPE_INTERNAL_UVD_SD, 72 POWER_STATE_TYPE_INTERNAL_UVD_HD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 74 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 75 POWER_STATE_TYPE_INTERNAL_BOOT, 76 POWER_STATE_TYPE_INTERNAL_THERMAL, 77 POWER_STATE_TYPE_INTERNAL_ACPI, 78 POWER_STATE_TYPE_INTERNAL_ULV, 79 POWER_STATE_TYPE_INTERNAL_3DPERF, 80 }; 81 82 #define AMD_MAX_VCE_LEVELS 6 83 84 enum amd_vce_level { 85 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 86 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 87 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 88 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 89 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 90 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 91 }; 92 93 enum amd_fan_ctrl_mode { 94 AMD_FAN_CTRL_NONE = 0, 95 AMD_FAN_CTRL_MANUAL = 1, 96 AMD_FAN_CTRL_AUTO = 2, 97 }; 98 99 enum pp_clock_type { 100 PP_SCLK, 101 PP_MCLK, 102 PP_PCIE, 103 PP_SOCCLK, 104 PP_FCLK, 105 PP_DCEFCLK, 106 PP_VCLK, 107 PP_DCLK, 108 OD_SCLK, 109 OD_MCLK, 110 OD_VDDC_CURVE, 111 OD_RANGE, 112 OD_VDDGFX_OFFSET, 113 OD_CCLK, 114 }; 115 116 enum amd_pp_sensors { 117 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 118 AMDGPU_PP_SENSOR_CPU_CLK, 119 AMDGPU_PP_SENSOR_VDDNB, 120 AMDGPU_PP_SENSOR_VDDGFX, 121 AMDGPU_PP_SENSOR_UVD_VCLK, 122 AMDGPU_PP_SENSOR_UVD_DCLK, 123 AMDGPU_PP_SENSOR_VCE_ECCLK, 124 AMDGPU_PP_SENSOR_GPU_LOAD, 125 AMDGPU_PP_SENSOR_MEM_LOAD, 126 AMDGPU_PP_SENSOR_GFX_MCLK, 127 AMDGPU_PP_SENSOR_GPU_TEMP, 128 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 129 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 130 AMDGPU_PP_SENSOR_MEM_TEMP, 131 AMDGPU_PP_SENSOR_VCE_POWER, 132 AMDGPU_PP_SENSOR_UVD_POWER, 133 AMDGPU_PP_SENSOR_GPU_POWER, 134 AMDGPU_PP_SENSOR_SS_APU_SHARE, 135 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 136 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 137 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 138 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 139 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 140 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 141 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 142 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 143 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 144 }; 145 146 enum amd_pp_task { 147 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 148 AMD_PP_TASK_ENABLE_USER_STATE, 149 AMD_PP_TASK_READJUST_POWER_STATE, 150 AMD_PP_TASK_COMPLETE_INIT, 151 AMD_PP_TASK_MAX 152 }; 153 154 enum PP_SMC_POWER_PROFILE { 155 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 156 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 157 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 158 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 159 PP_SMC_POWER_PROFILE_VR = 0x4, 160 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 161 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 162 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 163 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 164 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 165 PP_SMC_POWER_PROFILE_COUNT, 166 }; 167 168 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 169 170 171 172 enum { 173 PP_GROUP_UNKNOWN = 0, 174 PP_GROUP_GFX = 1, 175 PP_GROUP_SYS, 176 PP_GROUP_MAX 177 }; 178 179 enum PP_OD_DPM_TABLE_COMMAND { 180 PP_OD_EDIT_SCLK_VDDC_TABLE, 181 PP_OD_EDIT_MCLK_VDDC_TABLE, 182 PP_OD_EDIT_CCLK_VDDC_TABLE, 183 PP_OD_EDIT_VDDC_CURVE, 184 PP_OD_RESTORE_DEFAULT_TABLE, 185 PP_OD_COMMIT_DPM_TABLE, 186 PP_OD_EDIT_VDDGFX_OFFSET 187 }; 188 189 struct pp_states_info { 190 uint32_t nums; 191 uint32_t states[16]; 192 }; 193 194 enum PP_HWMON_TEMP { 195 PP_TEMP_EDGE = 0, 196 PP_TEMP_JUNCTION, 197 PP_TEMP_MEM, 198 PP_TEMP_MAX 199 }; 200 201 enum pp_mp1_state { 202 PP_MP1_STATE_NONE, 203 PP_MP1_STATE_SHUTDOWN, 204 PP_MP1_STATE_UNLOAD, 205 PP_MP1_STATE_RESET, 206 }; 207 208 enum pp_df_cstate { 209 DF_CSTATE_DISALLOW = 0, 210 DF_CSTATE_ALLOW, 211 }; 212 213 /** 214 * DOC: amdgpu_pp_power 215 * 216 * APU power is managed to system-level requirements through the PPT 217 * (package power tracking) feature. PPT is intended to limit power to the 218 * requirements of the power source and could be dynamically updated to 219 * maximize APU performance within the system power budget. 220 * 221 * Two types of power measurement can be requested, where supported, with 222 * :c:type:`enum pp_power_type <pp_power_type>`. 223 */ 224 225 /** 226 * enum pp_power_limit_level - Used to query the power limits 227 * 228 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 229 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 230 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 231 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 232 */ 233 enum pp_power_limit_level 234 { 235 PP_PWR_LIMIT_MIN = -1, 236 PP_PWR_LIMIT_CURRENT, 237 PP_PWR_LIMIT_DEFAULT, 238 PP_PWR_LIMIT_MAX, 239 }; 240 241 /** 242 * enum pp_power_type - Used to specify the type of the requested power 243 * 244 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 245 * moving average of APU power (default ~5000 ms). 246 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 247 * where supported. 248 */ 249 enum pp_power_type 250 { 251 PP_PWR_TYPE_SUSTAINED, 252 PP_PWR_TYPE_FAST, 253 }; 254 255 #define PP_GROUP_MASK 0xF0000000 256 #define PP_GROUP_SHIFT 28 257 258 #define PP_BLOCK_MASK 0x0FFFFF00 259 #define PP_BLOCK_SHIFT 8 260 261 #define PP_BLOCK_GFX_CG 0x01 262 #define PP_BLOCK_GFX_MG 0x02 263 #define PP_BLOCK_GFX_3D 0x04 264 #define PP_BLOCK_GFX_RLC 0x08 265 #define PP_BLOCK_GFX_CP 0x10 266 #define PP_BLOCK_SYS_BIF 0x01 267 #define PP_BLOCK_SYS_MC 0x02 268 #define PP_BLOCK_SYS_ROM 0x04 269 #define PP_BLOCK_SYS_DRM 0x08 270 #define PP_BLOCK_SYS_HDP 0x10 271 #define PP_BLOCK_SYS_SDMA 0x20 272 273 #define PP_STATE_MASK 0x0000000F 274 #define PP_STATE_SHIFT 0 275 #define PP_STATE_SUPPORT_MASK 0x000000F0 276 #define PP_STATE_SUPPORT_SHIFT 0 277 278 #define PP_STATE_CG 0x01 279 #define PP_STATE_LS 0x02 280 #define PP_STATE_DS 0x04 281 #define PP_STATE_SD 0x08 282 #define PP_STATE_SUPPORT_CG 0x10 283 #define PP_STATE_SUPPORT_LS 0x20 284 #define PP_STATE_SUPPORT_DS 0x40 285 #define PP_STATE_SUPPORT_SD 0x80 286 287 #define PP_CG_MSG_ID(group, block, support, state) \ 288 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 289 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 290 291 #define XGMI_MODE_PSTATE_D3 0 292 #define XGMI_MODE_PSTATE_D0 1 293 294 #define NUM_HBM_INSTANCES 4 295 296 struct seq_file; 297 enum amd_pp_clock_type; 298 struct amd_pp_simple_clock_info; 299 struct amd_pp_display_configuration; 300 struct amd_pp_clock_info; 301 struct pp_display_clock_request; 302 struct pp_clock_levels_with_voltage; 303 struct pp_clock_levels_with_latency; 304 struct amd_pp_clocks; 305 struct pp_smu_wm_range_sets; 306 struct pp_smu_nv_clock_table; 307 struct dpm_clocks; 308 309 struct amd_pm_funcs { 310 /* export for dpm on ci and si */ 311 int (*pre_set_power_state)(void *handle); 312 int (*set_power_state)(void *handle); 313 void (*post_set_power_state)(void *handle); 314 void (*display_configuration_changed)(void *handle); 315 void (*print_power_state)(void *handle, void *ps); 316 bool (*vblank_too_short)(void *handle); 317 void (*enable_bapm)(void *handle, bool enable); 318 int (*check_state_equal)(void *handle, 319 void *cps, 320 void *rps, 321 bool *equal); 322 /* export for sysfs */ 323 int (*set_fan_control_mode)(void *handle, u32 mode); 324 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 325 int (*set_fan_speed_pwm)(void *handle, u32 speed); 326 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 327 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 328 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 329 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 330 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 331 int (*get_sclk_od)(void *handle); 332 int (*set_sclk_od)(void *handle, uint32_t value); 333 int (*get_mclk_od)(void *handle); 334 int (*set_mclk_od)(void *handle, uint32_t value); 335 int (*read_sensor)(void *handle, int idx, void *value, int *size); 336 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 337 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 338 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 339 enum amd_pm_state_type (*get_current_power_state)(void *handle); 340 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 341 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 342 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 343 int (*get_pp_table)(void *handle, char **table); 344 int (*set_pp_table)(void *handle, const char *buf, size_t size); 345 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 346 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 347 /* export to amdgpu */ 348 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 349 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 350 enum amd_pm_state_type *user_state); 351 int (*load_firmware)(void *handle); 352 int (*wait_for_fw_loading_complete)(void *handle); 353 int (*set_powergating_by_smu)(void *handle, 354 uint32_t block_type, bool gate); 355 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 356 int (*set_power_limit)(void *handle, uint32_t n); 357 int (*get_power_limit)(void *handle, uint32_t *limit, 358 enum pp_power_limit_level pp_limit_level, 359 enum pp_power_type power_type); 360 int (*get_power_profile_mode)(void *handle, char *buf); 361 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 362 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 363 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 364 long *input, uint32_t size); 365 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 366 int (*smu_i2c_bus_access)(void *handle, bool acquire); 367 int (*gfx_state_change_set)(void *handle, uint32_t state); 368 /* export to DC */ 369 u32 (*get_sclk)(void *handle, bool low); 370 u32 (*get_mclk)(void *handle, bool low); 371 int (*display_configuration_change)(void *handle, 372 const struct amd_pp_display_configuration *input); 373 int (*get_display_power_level)(void *handle, 374 struct amd_pp_simple_clock_info *output); 375 int (*get_current_clocks)(void *handle, 376 struct amd_pp_clock_info *clocks); 377 int (*get_clock_by_type)(void *handle, 378 enum amd_pp_clock_type type, 379 struct amd_pp_clocks *clocks); 380 int (*get_clock_by_type_with_latency)(void *handle, 381 enum amd_pp_clock_type type, 382 struct pp_clock_levels_with_latency *clocks); 383 int (*get_clock_by_type_with_voltage)(void *handle, 384 enum amd_pp_clock_type type, 385 struct pp_clock_levels_with_voltage *clocks); 386 int (*set_watermarks_for_clocks_ranges)(void *handle, 387 void *clock_ranges); 388 int (*display_clock_voltage_request)(void *handle, 389 struct pp_display_clock_request *clock); 390 int (*get_display_mode_validation_clocks)(void *handle, 391 struct amd_pp_simple_clock_info *clocks); 392 int (*notify_smu_enable_pwe)(void *handle); 393 int (*enable_mgpu_fan_boost)(void *handle); 394 int (*set_active_display_count)(void *handle, uint32_t count); 395 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 396 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 397 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 398 int (*get_asic_baco_capability)(void *handle, bool *cap); 399 int (*get_asic_baco_state)(void *handle, int *state); 400 int (*set_asic_baco_state)(void *handle, int state); 401 int (*get_ppfeature_status)(void *handle, char *buf); 402 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 403 int (*asic_reset_mode_2)(void *handle); 404 int (*asic_reset_enable_gfx_features)(void *handle); 405 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 406 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 407 ssize_t (*get_gpu_metrics)(void *handle, void **table); 408 int (*set_watermarks_for_clock_ranges)(void *handle, 409 struct pp_smu_wm_range_sets *ranges); 410 int (*display_disable_memory_clock_switch)(void *handle, 411 bool disable_memory_clock_switch); 412 int (*get_max_sustainable_clocks_by_dc)(void *handle, 413 struct pp_smu_nv_clock_table *max_clocks); 414 int (*get_uclk_dpm_states)(void *handle, 415 unsigned int *clock_values_in_khz, 416 unsigned int *num_states); 417 int (*get_dpm_clock_table)(void *handle, 418 struct dpm_clocks *clock_table); 419 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 420 void (*pm_compute_clocks)(void *handle); 421 }; 422 423 struct metrics_table_header { 424 uint16_t structure_size; 425 uint8_t format_revision; 426 uint8_t content_revision; 427 }; 428 429 /* 430 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 431 * Use gpu_metrics_v1_1 or later instead. 432 */ 433 struct gpu_metrics_v1_0 { 434 struct metrics_table_header common_header; 435 436 /* Driver attached timestamp (in ns) */ 437 uint64_t system_clock_counter; 438 439 /* Temperature */ 440 uint16_t temperature_edge; 441 uint16_t temperature_hotspot; 442 uint16_t temperature_mem; 443 uint16_t temperature_vrgfx; 444 uint16_t temperature_vrsoc; 445 uint16_t temperature_vrmem; 446 447 /* Utilization */ 448 uint16_t average_gfx_activity; 449 uint16_t average_umc_activity; // memory controller 450 uint16_t average_mm_activity; // UVD or VCN 451 452 /* Power/Energy */ 453 uint16_t average_socket_power; 454 uint32_t energy_accumulator; 455 456 /* Average clocks */ 457 uint16_t average_gfxclk_frequency; 458 uint16_t average_socclk_frequency; 459 uint16_t average_uclk_frequency; 460 uint16_t average_vclk0_frequency; 461 uint16_t average_dclk0_frequency; 462 uint16_t average_vclk1_frequency; 463 uint16_t average_dclk1_frequency; 464 465 /* Current clocks */ 466 uint16_t current_gfxclk; 467 uint16_t current_socclk; 468 uint16_t current_uclk; 469 uint16_t current_vclk0; 470 uint16_t current_dclk0; 471 uint16_t current_vclk1; 472 uint16_t current_dclk1; 473 474 /* Throttle status */ 475 uint32_t throttle_status; 476 477 /* Fans */ 478 uint16_t current_fan_speed; 479 480 /* Link width/speed */ 481 uint8_t pcie_link_width; 482 uint8_t pcie_link_speed; // in 0.1 GT/s 483 }; 484 485 struct gpu_metrics_v1_1 { 486 struct metrics_table_header common_header; 487 488 /* Temperature */ 489 uint16_t temperature_edge; 490 uint16_t temperature_hotspot; 491 uint16_t temperature_mem; 492 uint16_t temperature_vrgfx; 493 uint16_t temperature_vrsoc; 494 uint16_t temperature_vrmem; 495 496 /* Utilization */ 497 uint16_t average_gfx_activity; 498 uint16_t average_umc_activity; // memory controller 499 uint16_t average_mm_activity; // UVD or VCN 500 501 /* Power/Energy */ 502 uint16_t average_socket_power; 503 uint64_t energy_accumulator; 504 505 /* Driver attached timestamp (in ns) */ 506 uint64_t system_clock_counter; 507 508 /* Average clocks */ 509 uint16_t average_gfxclk_frequency; 510 uint16_t average_socclk_frequency; 511 uint16_t average_uclk_frequency; 512 uint16_t average_vclk0_frequency; 513 uint16_t average_dclk0_frequency; 514 uint16_t average_vclk1_frequency; 515 uint16_t average_dclk1_frequency; 516 517 /* Current clocks */ 518 uint16_t current_gfxclk; 519 uint16_t current_socclk; 520 uint16_t current_uclk; 521 uint16_t current_vclk0; 522 uint16_t current_dclk0; 523 uint16_t current_vclk1; 524 uint16_t current_dclk1; 525 526 /* Throttle status */ 527 uint32_t throttle_status; 528 529 /* Fans */ 530 uint16_t current_fan_speed; 531 532 /* Link width/speed */ 533 uint16_t pcie_link_width; 534 uint16_t pcie_link_speed; // in 0.1 GT/s 535 536 uint16_t padding; 537 538 uint32_t gfx_activity_acc; 539 uint32_t mem_activity_acc; 540 541 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 542 }; 543 544 struct gpu_metrics_v1_2 { 545 struct metrics_table_header common_header; 546 547 /* Temperature */ 548 uint16_t temperature_edge; 549 uint16_t temperature_hotspot; 550 uint16_t temperature_mem; 551 uint16_t temperature_vrgfx; 552 uint16_t temperature_vrsoc; 553 uint16_t temperature_vrmem; 554 555 /* Utilization */ 556 uint16_t average_gfx_activity; 557 uint16_t average_umc_activity; // memory controller 558 uint16_t average_mm_activity; // UVD or VCN 559 560 /* Power/Energy */ 561 uint16_t average_socket_power; 562 uint64_t energy_accumulator; 563 564 /* Driver attached timestamp (in ns) */ 565 uint64_t system_clock_counter; 566 567 /* Average clocks */ 568 uint16_t average_gfxclk_frequency; 569 uint16_t average_socclk_frequency; 570 uint16_t average_uclk_frequency; 571 uint16_t average_vclk0_frequency; 572 uint16_t average_dclk0_frequency; 573 uint16_t average_vclk1_frequency; 574 uint16_t average_dclk1_frequency; 575 576 /* Current clocks */ 577 uint16_t current_gfxclk; 578 uint16_t current_socclk; 579 uint16_t current_uclk; 580 uint16_t current_vclk0; 581 uint16_t current_dclk0; 582 uint16_t current_vclk1; 583 uint16_t current_dclk1; 584 585 /* Throttle status (ASIC dependent) */ 586 uint32_t throttle_status; 587 588 /* Fans */ 589 uint16_t current_fan_speed; 590 591 /* Link width/speed */ 592 uint16_t pcie_link_width; 593 uint16_t pcie_link_speed; // in 0.1 GT/s 594 595 uint16_t padding; 596 597 uint32_t gfx_activity_acc; 598 uint32_t mem_activity_acc; 599 600 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 601 602 /* PMFW attached timestamp (10ns resolution) */ 603 uint64_t firmware_timestamp; 604 }; 605 606 struct gpu_metrics_v1_3 { 607 struct metrics_table_header common_header; 608 609 /* Temperature */ 610 uint16_t temperature_edge; 611 uint16_t temperature_hotspot; 612 uint16_t temperature_mem; 613 uint16_t temperature_vrgfx; 614 uint16_t temperature_vrsoc; 615 uint16_t temperature_vrmem; 616 617 /* Utilization */ 618 uint16_t average_gfx_activity; 619 uint16_t average_umc_activity; // memory controller 620 uint16_t average_mm_activity; // UVD or VCN 621 622 /* Power/Energy */ 623 uint16_t average_socket_power; 624 uint64_t energy_accumulator; 625 626 /* Driver attached timestamp (in ns) */ 627 uint64_t system_clock_counter; 628 629 /* Average clocks */ 630 uint16_t average_gfxclk_frequency; 631 uint16_t average_socclk_frequency; 632 uint16_t average_uclk_frequency; 633 uint16_t average_vclk0_frequency; 634 uint16_t average_dclk0_frequency; 635 uint16_t average_vclk1_frequency; 636 uint16_t average_dclk1_frequency; 637 638 /* Current clocks */ 639 uint16_t current_gfxclk; 640 uint16_t current_socclk; 641 uint16_t current_uclk; 642 uint16_t current_vclk0; 643 uint16_t current_dclk0; 644 uint16_t current_vclk1; 645 uint16_t current_dclk1; 646 647 /* Throttle status */ 648 uint32_t throttle_status; 649 650 /* Fans */ 651 uint16_t current_fan_speed; 652 653 /* Link width/speed */ 654 uint16_t pcie_link_width; 655 uint16_t pcie_link_speed; // in 0.1 GT/s 656 657 uint16_t padding; 658 659 uint32_t gfx_activity_acc; 660 uint32_t mem_activity_acc; 661 662 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 663 664 /* PMFW attached timestamp (10ns resolution) */ 665 uint64_t firmware_timestamp; 666 667 /* Voltage (mV) */ 668 uint16_t voltage_soc; 669 uint16_t voltage_gfx; 670 uint16_t voltage_mem; 671 672 uint16_t padding1; 673 674 /* Throttle status (ASIC independent) */ 675 uint64_t indep_throttle_status; 676 }; 677 678 /* 679 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 680 * Use gpu_metrics_v2_1 or later instead. 681 */ 682 struct gpu_metrics_v2_0 { 683 struct metrics_table_header common_header; 684 685 /* Driver attached timestamp (in ns) */ 686 uint64_t system_clock_counter; 687 688 /* Temperature */ 689 uint16_t temperature_gfx; // gfx temperature on APUs 690 uint16_t temperature_soc; // soc temperature on APUs 691 uint16_t temperature_core[8]; // CPU core temperature on APUs 692 uint16_t temperature_l3[2]; 693 694 /* Utilization */ 695 uint16_t average_gfx_activity; 696 uint16_t average_mm_activity; // UVD or VCN 697 698 /* Power/Energy */ 699 uint16_t average_socket_power; // dGPU + APU power on A + A platform 700 uint16_t average_cpu_power; 701 uint16_t average_soc_power; 702 uint16_t average_gfx_power; 703 uint16_t average_core_power[8]; // CPU core power on APUs 704 705 /* Average clocks */ 706 uint16_t average_gfxclk_frequency; 707 uint16_t average_socclk_frequency; 708 uint16_t average_uclk_frequency; 709 uint16_t average_fclk_frequency; 710 uint16_t average_vclk_frequency; 711 uint16_t average_dclk_frequency; 712 713 /* Current clocks */ 714 uint16_t current_gfxclk; 715 uint16_t current_socclk; 716 uint16_t current_uclk; 717 uint16_t current_fclk; 718 uint16_t current_vclk; 719 uint16_t current_dclk; 720 uint16_t current_coreclk[8]; // CPU core clocks 721 uint16_t current_l3clk[2]; 722 723 /* Throttle status */ 724 uint32_t throttle_status; 725 726 /* Fans */ 727 uint16_t fan_pwm; 728 729 uint16_t padding; 730 }; 731 732 struct gpu_metrics_v2_1 { 733 struct metrics_table_header common_header; 734 735 /* Temperature */ 736 uint16_t temperature_gfx; // gfx temperature on APUs 737 uint16_t temperature_soc; // soc temperature on APUs 738 uint16_t temperature_core[8]; // CPU core temperature on APUs 739 uint16_t temperature_l3[2]; 740 741 /* Utilization */ 742 uint16_t average_gfx_activity; 743 uint16_t average_mm_activity; // UVD or VCN 744 745 /* Driver attached timestamp (in ns) */ 746 uint64_t system_clock_counter; 747 748 /* Power/Energy */ 749 uint16_t average_socket_power; // dGPU + APU power on A + A platform 750 uint16_t average_cpu_power; 751 uint16_t average_soc_power; 752 uint16_t average_gfx_power; 753 uint16_t average_core_power[8]; // CPU core power on APUs 754 755 /* Average clocks */ 756 uint16_t average_gfxclk_frequency; 757 uint16_t average_socclk_frequency; 758 uint16_t average_uclk_frequency; 759 uint16_t average_fclk_frequency; 760 uint16_t average_vclk_frequency; 761 uint16_t average_dclk_frequency; 762 763 /* Current clocks */ 764 uint16_t current_gfxclk; 765 uint16_t current_socclk; 766 uint16_t current_uclk; 767 uint16_t current_fclk; 768 uint16_t current_vclk; 769 uint16_t current_dclk; 770 uint16_t current_coreclk[8]; // CPU core clocks 771 uint16_t current_l3clk[2]; 772 773 /* Throttle status */ 774 uint32_t throttle_status; 775 776 /* Fans */ 777 uint16_t fan_pwm; 778 779 uint16_t padding[3]; 780 }; 781 782 struct gpu_metrics_v2_2 { 783 struct metrics_table_header common_header; 784 785 /* Temperature */ 786 uint16_t temperature_gfx; // gfx temperature on APUs 787 uint16_t temperature_soc; // soc temperature on APUs 788 uint16_t temperature_core[8]; // CPU core temperature on APUs 789 uint16_t temperature_l3[2]; 790 791 /* Utilization */ 792 uint16_t average_gfx_activity; 793 uint16_t average_mm_activity; // UVD or VCN 794 795 /* Driver attached timestamp (in ns) */ 796 uint64_t system_clock_counter; 797 798 /* Power/Energy */ 799 uint16_t average_socket_power; // dGPU + APU power on A + A platform 800 uint16_t average_cpu_power; 801 uint16_t average_soc_power; 802 uint16_t average_gfx_power; 803 uint16_t average_core_power[8]; // CPU core power on APUs 804 805 /* Average clocks */ 806 uint16_t average_gfxclk_frequency; 807 uint16_t average_socclk_frequency; 808 uint16_t average_uclk_frequency; 809 uint16_t average_fclk_frequency; 810 uint16_t average_vclk_frequency; 811 uint16_t average_dclk_frequency; 812 813 /* Current clocks */ 814 uint16_t current_gfxclk; 815 uint16_t current_socclk; 816 uint16_t current_uclk; 817 uint16_t current_fclk; 818 uint16_t current_vclk; 819 uint16_t current_dclk; 820 uint16_t current_coreclk[8]; // CPU core clocks 821 uint16_t current_l3clk[2]; 822 823 /* Throttle status (ASIC dependent) */ 824 uint32_t throttle_status; 825 826 /* Fans */ 827 uint16_t fan_pwm; 828 829 uint16_t padding[3]; 830 831 /* Throttle status (ASIC independent) */ 832 uint64_t indep_throttle_status; 833 }; 834 835 struct gpu_metrics_v2_3 { 836 struct metrics_table_header common_header; 837 838 /* Temperature */ 839 uint16_t temperature_gfx; // gfx temperature on APUs 840 uint16_t temperature_soc; // soc temperature on APUs 841 uint16_t temperature_core[8]; // CPU core temperature on APUs 842 uint16_t temperature_l3[2]; 843 844 /* Utilization */ 845 uint16_t average_gfx_activity; 846 uint16_t average_mm_activity; // UVD or VCN 847 848 /* Driver attached timestamp (in ns) */ 849 uint64_t system_clock_counter; 850 851 /* Power/Energy */ 852 uint16_t average_socket_power; // dGPU + APU power on A + A platform 853 uint16_t average_cpu_power; 854 uint16_t average_soc_power; 855 uint16_t average_gfx_power; 856 uint16_t average_core_power[8]; // CPU core power on APUs 857 858 /* Average clocks */ 859 uint16_t average_gfxclk_frequency; 860 uint16_t average_socclk_frequency; 861 uint16_t average_uclk_frequency; 862 uint16_t average_fclk_frequency; 863 uint16_t average_vclk_frequency; 864 uint16_t average_dclk_frequency; 865 866 /* Current clocks */ 867 uint16_t current_gfxclk; 868 uint16_t current_socclk; 869 uint16_t current_uclk; 870 uint16_t current_fclk; 871 uint16_t current_vclk; 872 uint16_t current_dclk; 873 uint16_t current_coreclk[8]; // CPU core clocks 874 uint16_t current_l3clk[2]; 875 876 /* Throttle status (ASIC dependent) */ 877 uint32_t throttle_status; 878 879 /* Fans */ 880 uint16_t fan_pwm; 881 882 uint16_t padding[3]; 883 884 /* Throttle status (ASIC independent) */ 885 uint64_t indep_throttle_status; 886 887 /* Average Temperature */ 888 uint16_t average_temperature_gfx; // average gfx temperature on APUs 889 uint16_t average_temperature_soc; // average soc temperature on APUs 890 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 891 uint16_t average_temperature_l3[2]; 892 }; 893 #endif 894