1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amd_ip_funcs pp_ip_funcs; 28 extern const struct amd_pm_funcs pp_dpm_funcs; 29 30 struct amd_vce_state { 31 /* vce clocks */ 32 u32 evclk; 33 u32 ecclk; 34 /* gpu clocks */ 35 u32 sclk; 36 u32 mclk; 37 u8 clk_idx; 38 u8 pstate; 39 }; 40 41 42 enum amd_dpm_forced_level { 43 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 44 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 45 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 46 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 47 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 49 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 50 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 51 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 52 }; 53 54 enum amd_pm_state_type { 55 /* not used for dpm */ 56 POWER_STATE_TYPE_DEFAULT, 57 POWER_STATE_TYPE_POWERSAVE, 58 /* user selectable states */ 59 POWER_STATE_TYPE_BATTERY, 60 POWER_STATE_TYPE_BALANCED, 61 POWER_STATE_TYPE_PERFORMANCE, 62 /* internal states */ 63 POWER_STATE_TYPE_INTERNAL_UVD, 64 POWER_STATE_TYPE_INTERNAL_UVD_SD, 65 POWER_STATE_TYPE_INTERNAL_UVD_HD, 66 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 67 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 68 POWER_STATE_TYPE_INTERNAL_BOOT, 69 POWER_STATE_TYPE_INTERNAL_THERMAL, 70 POWER_STATE_TYPE_INTERNAL_ACPI, 71 POWER_STATE_TYPE_INTERNAL_ULV, 72 POWER_STATE_TYPE_INTERNAL_3DPERF, 73 }; 74 75 #define AMD_MAX_VCE_LEVELS 6 76 77 enum amd_vce_level { 78 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 79 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 80 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 81 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 82 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 83 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 84 }; 85 86 enum amd_pp_profile_type { 87 AMD_PP_GFX_PROFILE, 88 AMD_PP_COMPUTE_PROFILE, 89 }; 90 91 struct amd_pp_profile { 92 enum amd_pp_profile_type type; 93 uint32_t min_sclk; 94 uint32_t min_mclk; 95 uint16_t activity_threshold; 96 uint8_t up_hyst; 97 uint8_t down_hyst; 98 }; 99 100 enum amd_fan_ctrl_mode { 101 AMD_FAN_CTRL_NONE = 0, 102 AMD_FAN_CTRL_MANUAL = 1, 103 AMD_FAN_CTRL_AUTO = 2, 104 }; 105 106 enum pp_clock_type { 107 PP_SCLK, 108 PP_MCLK, 109 PP_PCIE, 110 OD_SCLK, 111 OD_MCLK, 112 }; 113 114 enum amd_pp_sensors { 115 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 116 AMDGPU_PP_SENSOR_VDDNB, 117 AMDGPU_PP_SENSOR_VDDGFX, 118 AMDGPU_PP_SENSOR_UVD_VCLK, 119 AMDGPU_PP_SENSOR_UVD_DCLK, 120 AMDGPU_PP_SENSOR_VCE_ECCLK, 121 AMDGPU_PP_SENSOR_GPU_LOAD, 122 AMDGPU_PP_SENSOR_GFX_MCLK, 123 AMDGPU_PP_SENSOR_GPU_TEMP, 124 AMDGPU_PP_SENSOR_VCE_POWER, 125 AMDGPU_PP_SENSOR_UVD_POWER, 126 AMDGPU_PP_SENSOR_GPU_POWER, 127 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 128 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 129 }; 130 131 enum amd_pp_task { 132 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 133 AMD_PP_TASK_ENABLE_USER_STATE, 134 AMD_PP_TASK_READJUST_POWER_STATE, 135 AMD_PP_TASK_COMPLETE_INIT, 136 AMD_PP_TASK_MAX 137 }; 138 139 struct amd_pp_init { 140 struct cgs_device *device; 141 uint32_t chip_family; 142 uint32_t chip_id; 143 bool pm_en; 144 uint32_t feature_mask; 145 }; 146 147 enum PP_SMC_POWER_PROFILE { 148 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x0, 149 PP_SMC_POWER_PROFILE_POWERSAVING = 0x1, 150 PP_SMC_POWER_PROFILE_VIDEO = 0x2, 151 PP_SMC_POWER_PROFILE_VR = 0x3, 152 PP_SMC_POWER_PROFILE_COMPUTE = 0x4, 153 PP_SMC_POWER_PROFILE_CUSTOM = 0x5, 154 PP_SMC_POWER_PROFILE_AUTO = 0x6, 155 }; 156 157 enum { 158 PP_GROUP_UNKNOWN = 0, 159 PP_GROUP_GFX = 1, 160 PP_GROUP_SYS, 161 PP_GROUP_MAX 162 }; 163 164 struct pp_states_info { 165 uint32_t nums; 166 uint32_t states[16]; 167 }; 168 169 struct pp_gpu_power { 170 uint32_t vddc_power; 171 uint32_t vddci_power; 172 uint32_t max_gpu_power; 173 uint32_t average_gpu_power; 174 }; 175 176 #define PP_GROUP_MASK 0xF0000000 177 #define PP_GROUP_SHIFT 28 178 179 #define PP_BLOCK_MASK 0x0FFFFF00 180 #define PP_BLOCK_SHIFT 8 181 182 #define PP_BLOCK_GFX_CG 0x01 183 #define PP_BLOCK_GFX_MG 0x02 184 #define PP_BLOCK_GFX_3D 0x04 185 #define PP_BLOCK_GFX_RLC 0x08 186 #define PP_BLOCK_GFX_CP 0x10 187 #define PP_BLOCK_SYS_BIF 0x01 188 #define PP_BLOCK_SYS_MC 0x02 189 #define PP_BLOCK_SYS_ROM 0x04 190 #define PP_BLOCK_SYS_DRM 0x08 191 #define PP_BLOCK_SYS_HDP 0x10 192 #define PP_BLOCK_SYS_SDMA 0x20 193 194 #define PP_STATE_MASK 0x0000000F 195 #define PP_STATE_SHIFT 0 196 #define PP_STATE_SUPPORT_MASK 0x000000F0 197 #define PP_STATE_SUPPORT_SHIFT 0 198 199 #define PP_STATE_CG 0x01 200 #define PP_STATE_LS 0x02 201 #define PP_STATE_DS 0x04 202 #define PP_STATE_SD 0x08 203 #define PP_STATE_SUPPORT_CG 0x10 204 #define PP_STATE_SUPPORT_LS 0x20 205 #define PP_STATE_SUPPORT_DS 0x40 206 #define PP_STATE_SUPPORT_SD 0x80 207 208 #define PP_CG_MSG_ID(group, block, support, state) \ 209 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 210 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 211 212 struct seq_file; 213 enum amd_pp_clock_type; 214 struct amd_pp_simple_clock_info; 215 struct amd_pp_display_configuration; 216 struct amd_pp_clock_info; 217 struct pp_display_clock_request; 218 struct pp_wm_sets_with_clock_ranges_soc15; 219 struct pp_clock_levels_with_voltage; 220 struct pp_clock_levels_with_latency; 221 struct amd_pp_clocks; 222 223 struct amd_pm_funcs { 224 /* export for dpm on ci and si */ 225 int (*pre_set_power_state)(void *handle); 226 int (*set_power_state)(void *handle); 227 void (*post_set_power_state)(void *handle); 228 void (*display_configuration_changed)(void *handle); 229 void (*print_power_state)(void *handle, void *ps); 230 bool (*vblank_too_short)(void *handle); 231 void (*enable_bapm)(void *handle, bool enable); 232 int (*check_state_equal)(void *handle, 233 void *cps, 234 void *rps, 235 bool *equal); 236 /* export for sysfs */ 237 int (*get_temperature)(void *handle); 238 void (*set_fan_control_mode)(void *handle, u32 mode); 239 u32 (*get_fan_control_mode)(void *handle); 240 int (*set_fan_speed_percent)(void *handle, u32 speed); 241 int (*get_fan_speed_percent)(void *handle, u32 *speed); 242 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 243 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 244 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 245 int (*get_sclk_od)(void *handle); 246 int (*set_sclk_od)(void *handle, uint32_t value); 247 int (*get_mclk_od)(void *handle); 248 int (*set_mclk_od)(void *handle, uint32_t value); 249 int (*read_sensor)(void *handle, int idx, void *value, int *size); 250 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 251 enum amd_pm_state_type (*get_current_power_state)(void *handle); 252 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 253 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 254 int (*get_pp_table)(void *handle, char **table); 255 int (*set_pp_table)(void *handle, const char *buf, size_t size); 256 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 257 258 int (*reset_power_profile_state)(void *handle, 259 struct amd_pp_profile *request); 260 int (*get_power_profile_state)(void *handle, 261 struct amd_pp_profile *query); 262 int (*set_power_profile_state)(void *handle, 263 struct amd_pp_profile *request); 264 int (*switch_power_profile)(void *handle, 265 enum amd_pp_profile_type type); 266 /* export to amdgpu */ 267 void (*powergate_uvd)(void *handle, bool gate); 268 void (*powergate_vce)(void *handle, bool gate); 269 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 270 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 271 enum amd_pm_state_type *user_state); 272 int (*load_firmware)(void *handle); 273 int (*wait_for_fw_loading_complete)(void *handle); 274 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 275 int (*notify_smu_memory_info)(void *handle, uint32_t virtual_addr_low, 276 uint32_t virtual_addr_hi, 277 uint32_t mc_addr_low, 278 uint32_t mc_addr_hi, 279 uint32_t size); 280 /* export to DC */ 281 u32 (*get_sclk)(void *handle, bool low); 282 u32 (*get_mclk)(void *handle, bool low); 283 int (*display_configuration_change)(void *handle, 284 const struct amd_pp_display_configuration *input); 285 int (*get_display_power_level)(void *handle, 286 struct amd_pp_simple_clock_info *output); 287 int (*get_current_clocks)(void *handle, 288 struct amd_pp_clock_info *clocks); 289 int (*get_clock_by_type)(void *handle, 290 enum amd_pp_clock_type type, 291 struct amd_pp_clocks *clocks); 292 int (*get_clock_by_type_with_latency)(void *handle, 293 enum amd_pp_clock_type type, 294 struct pp_clock_levels_with_latency *clocks); 295 int (*get_clock_by_type_with_voltage)(void *handle, 296 enum amd_pp_clock_type type, 297 struct pp_clock_levels_with_voltage *clocks); 298 int (*set_watermarks_for_clocks_ranges)(void *handle, 299 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); 300 int (*display_clock_voltage_request)(void *handle, 301 struct pp_display_clock_request *clock); 302 int (*get_display_mode_validation_clocks)(void *handle, 303 struct amd_pp_simple_clock_info *clocks); 304 int (*get_power_profile_mode)(void *handle, char *buf); 305 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 306 }; 307 308 #endif 309