1c79563a3SRex Zhu /* 2c79563a3SRex Zhu * Copyright 2017 Advanced Micro Devices, Inc. 3c79563a3SRex Zhu * 4c79563a3SRex Zhu * Permission is hereby granted, free of charge, to any person obtaining a 5c79563a3SRex Zhu * copy of this software and associated documentation files (the "Software"), 6c79563a3SRex Zhu * to deal in the Software without restriction, including without limitation 7c79563a3SRex Zhu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c79563a3SRex Zhu * and/or sell copies of the Software, and to permit persons to whom the 9c79563a3SRex Zhu * Software is furnished to do so, subject to the following conditions: 10c79563a3SRex Zhu * 11c79563a3SRex Zhu * The above copyright notice and this permission notice shall be included in 12c79563a3SRex Zhu * all copies or substantial portions of the Software. 13c79563a3SRex Zhu * 14c79563a3SRex Zhu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c79563a3SRex Zhu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c79563a3SRex Zhu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c79563a3SRex Zhu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c79563a3SRex Zhu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c79563a3SRex Zhu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c79563a3SRex Zhu * OTHER DEALINGS IN THE SOFTWARE. 21c79563a3SRex Zhu * 22c79563a3SRex Zhu */ 23c79563a3SRex Zhu 24c79563a3SRex Zhu #ifndef __KGD_PP_INTERFACE_H__ 25c79563a3SRex Zhu #define __KGD_PP_INTERFACE_H__ 26c79563a3SRex Zhu 27b905090dSRex Zhu extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28ebfc2533SEvan Quan extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29ebfc2533SEvan Quan extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30ebfc2533SEvan Quan extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31c79563a3SRex Zhu 32bc143d8bSEvan Quan enum smu_event_type { 33bc143d8bSEvan Quan SMU_EVENT_RESET_COMPLETE = 0, 34bc143d8bSEvan Quan }; 35bc143d8bSEvan Quan 36c79563a3SRex Zhu struct amd_vce_state { 37c79563a3SRex Zhu /* vce clocks */ 38c79563a3SRex Zhu u32 evclk; 39c79563a3SRex Zhu u32 ecclk; 40c79563a3SRex Zhu /* gpu clocks */ 41c79563a3SRex Zhu u32 sclk; 42c79563a3SRex Zhu u32 mclk; 43c79563a3SRex Zhu u8 clk_idx; 44c79563a3SRex Zhu u8 pstate; 45c79563a3SRex Zhu }; 46c79563a3SRex Zhu 47c79563a3SRex Zhu 48c79563a3SRex Zhu enum amd_dpm_forced_level { 49c79563a3SRex Zhu AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 50c79563a3SRex Zhu AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 51c79563a3SRex Zhu AMD_DPM_FORCED_LEVEL_LOW = 0x4, 52c79563a3SRex Zhu AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 53c79563a3SRex Zhu AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 54c79563a3SRex Zhu AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 55c79563a3SRex Zhu AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 56c79563a3SRex Zhu AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 57c79563a3SRex Zhu AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 586be64246SLijo Lazar AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 59c79563a3SRex Zhu }; 60c79563a3SRex Zhu 61c79563a3SRex Zhu enum amd_pm_state_type { 62c79563a3SRex Zhu /* not used for dpm */ 63c79563a3SRex Zhu POWER_STATE_TYPE_DEFAULT, 64c79563a3SRex Zhu POWER_STATE_TYPE_POWERSAVE, 65c79563a3SRex Zhu /* user selectable states */ 66c79563a3SRex Zhu POWER_STATE_TYPE_BATTERY, 67c79563a3SRex Zhu POWER_STATE_TYPE_BALANCED, 68c79563a3SRex Zhu POWER_STATE_TYPE_PERFORMANCE, 69c79563a3SRex Zhu /* internal states */ 70c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_UVD, 71c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_UVD_SD, 72c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_UVD_HD, 73c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_UVD_HD2, 74c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_UVD_MVC, 75c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_BOOT, 76c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_THERMAL, 77c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_ACPI, 78c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_ULV, 79c79563a3SRex Zhu POWER_STATE_TYPE_INTERNAL_3DPERF, 80c79563a3SRex Zhu }; 81c79563a3SRex Zhu 82c79563a3SRex Zhu #define AMD_MAX_VCE_LEVELS 6 83c79563a3SRex Zhu 84c79563a3SRex Zhu enum amd_vce_level { 85c79563a3SRex Zhu AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 86c79563a3SRex Zhu AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 87c79563a3SRex Zhu AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 88c79563a3SRex Zhu AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 89c79563a3SRex Zhu AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 90c79563a3SRex Zhu AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 91c79563a3SRex Zhu }; 92c79563a3SRex Zhu 93c79563a3SRex Zhu enum amd_fan_ctrl_mode { 94c79563a3SRex Zhu AMD_FAN_CTRL_NONE = 0, 95c79563a3SRex Zhu AMD_FAN_CTRL_MANUAL = 1, 96c79563a3SRex Zhu AMD_FAN_CTRL_AUTO = 2, 97c79563a3SRex Zhu }; 98c79563a3SRex Zhu 99c79563a3SRex Zhu enum pp_clock_type { 100c79563a3SRex Zhu PP_SCLK, 101c79563a3SRex Zhu PP_MCLK, 102c79563a3SRex Zhu PP_PCIE, 103d7337ca2SEvan Quan PP_SOCCLK, 104828e37efSEvan Quan PP_FCLK, 105d7e28e2dSEvan Quan PP_DCEFCLK, 1062ea092e5SDarren Powell PP_VCLK, 107d7001e72STong Liu01 PP_VCLK1, 1082ea092e5SDarren Powell PP_DCLK, 109d7001e72STong Liu01 PP_DCLK1, 1106df21b77SRex Zhu OD_SCLK, 1116df21b77SRex Zhu OD_MCLK, 112d5bf2653SEvan Quan OD_VDDC_CURVE, 113a3c991f9SRex Zhu OD_RANGE, 1142ea092e5SDarren Powell OD_VDDGFX_OFFSET, 1152ea092e5SDarren Powell OD_CCLK, 116c79563a3SRex Zhu }; 117c79563a3SRex Zhu 118c79563a3SRex Zhu enum amd_pp_sensors { 119c79563a3SRex Zhu AMDGPU_PP_SENSOR_GFX_SCLK = 0, 120517cb957SHuang Rui AMDGPU_PP_SENSOR_CPU_CLK, 121c79563a3SRex Zhu AMDGPU_PP_SENSOR_VDDNB, 122c79563a3SRex Zhu AMDGPU_PP_SENSOR_VDDGFX, 123c79563a3SRex Zhu AMDGPU_PP_SENSOR_UVD_VCLK, 124c79563a3SRex Zhu AMDGPU_PP_SENSOR_UVD_DCLK, 125c79563a3SRex Zhu AMDGPU_PP_SENSOR_VCE_ECCLK, 126c79563a3SRex Zhu AMDGPU_PP_SENSOR_GPU_LOAD, 1271846e3f9SEvan Quan AMDGPU_PP_SENSOR_MEM_LOAD, 128c79563a3SRex Zhu AMDGPU_PP_SENSOR_GFX_MCLK, 129c79563a3SRex Zhu AMDGPU_PP_SENSOR_GPU_TEMP, 130a34d1166SEvan Quan AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 131a34d1166SEvan Quan AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 132a34d1166SEvan Quan AMDGPU_PP_SENSOR_MEM_TEMP, 133c79563a3SRex Zhu AMDGPU_PP_SENSOR_VCE_POWER, 134c79563a3SRex Zhu AMDGPU_PP_SENSOR_UVD_POWER, 135*9366c2e8SMario Limonciello AMDGPU_PP_SENSOR_GPU_AVG_POWER, 13647f1724dSMario Limonciello AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 137a7673a1cSSathishkumar S AMDGPU_PP_SENSOR_SS_APU_SHARE, 138a7673a1cSSathishkumar S AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 1395ed8d656SRex Zhu AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1405ed8d656SRex Zhu AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 141e0c3d047SAlex Deucher AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 142862cd980SRex Zhu AMDGPU_PP_SENSOR_MIN_FAN_RPM, 143862cd980SRex Zhu AMDGPU_PP_SENSOR_MAX_FAN_RPM, 1449829e3d8SEvan Quan AMDGPU_PP_SENSOR_VCN_POWER_STATE, 145975b4b1dSEvan Quan AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 146975b4b1dSEvan Quan AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 147c79563a3SRex Zhu }; 148c79563a3SRex Zhu 149c79563a3SRex Zhu enum amd_pp_task { 150c79563a3SRex Zhu AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 151c79563a3SRex Zhu AMD_PP_TASK_ENABLE_USER_STATE, 152c79563a3SRex Zhu AMD_PP_TASK_READJUST_POWER_STATE, 153c79563a3SRex Zhu AMD_PP_TASK_COMPLETE_INIT, 154c79563a3SRex Zhu AMD_PP_TASK_MAX 155c79563a3SRex Zhu }; 156c79563a3SRex Zhu 15737c5c4dbSRex Zhu enum PP_SMC_POWER_PROFILE { 158c27c9778SEvan Quan PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 159c27c9778SEvan Quan PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 160c27c9778SEvan Quan PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 161c27c9778SEvan Quan PP_SMC_POWER_PROFILE_VIDEO = 0x3, 162c27c9778SEvan Quan PP_SMC_POWER_PROFILE_VR = 0x4, 163c27c9778SEvan Quan PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 164c27c9778SEvan Quan PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 165334682aeSKenneth Feng PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 16631865e96SPerry Yuan PP_SMC_POWER_PROFILE_CAPPED = 0x8, 16731865e96SPerry Yuan PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 1687e01a2ecSEvan Quan PP_SMC_POWER_PROFILE_COUNT, 16937c5c4dbSRex Zhu }; 170c79563a3SRex Zhu 1713867e370SDarren Powell extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 1723867e370SDarren Powell 1733867e370SDarren Powell 1743867e370SDarren Powell 175c79563a3SRex Zhu enum { 176c79563a3SRex Zhu PP_GROUP_UNKNOWN = 0, 177c79563a3SRex Zhu PP_GROUP_GFX = 1, 178c79563a3SRex Zhu PP_GROUP_SYS, 179c79563a3SRex Zhu PP_GROUP_MAX 180c79563a3SRex Zhu }; 181c79563a3SRex Zhu 182897e1bbeSRex Zhu enum PP_OD_DPM_TABLE_COMMAND { 183897e1bbeSRex Zhu PP_OD_EDIT_SCLK_VDDC_TABLE, 184897e1bbeSRex Zhu PP_OD_EDIT_MCLK_VDDC_TABLE, 1850d90d0ddSHuang Rui PP_OD_EDIT_CCLK_VDDC_TABLE, 186d5bf2653SEvan Quan PP_OD_EDIT_VDDC_CURVE, 187897e1bbeSRex Zhu PP_OD_RESTORE_DEFAULT_TABLE, 188a2b6df4fSEvan Quan PP_OD_COMMIT_DPM_TABLE, 189a2b6df4fSEvan Quan PP_OD_EDIT_VDDGFX_OFFSET 190897e1bbeSRex Zhu }; 191897e1bbeSRex Zhu 192c79563a3SRex Zhu struct pp_states_info { 193c79563a3SRex Zhu uint32_t nums; 194c79563a3SRex Zhu uint32_t states[16]; 195c79563a3SRex Zhu }; 196c79563a3SRex Zhu 1972adc1156SEvan Quan enum PP_HWMON_TEMP { 1982adc1156SEvan Quan PP_TEMP_EDGE = 0, 1992adc1156SEvan Quan PP_TEMP_JUNCTION, 2002adc1156SEvan Quan PP_TEMP_MEM, 2012adc1156SEvan Quan PP_TEMP_MAX 2022adc1156SEvan Quan }; 2032adc1156SEvan Quan 204a2c28e34SAlex Deucher enum pp_mp1_state { 205a2c28e34SAlex Deucher PP_MP1_STATE_NONE, 206a2c28e34SAlex Deucher PP_MP1_STATE_SHUTDOWN, 207a2c28e34SAlex Deucher PP_MP1_STATE_UNLOAD, 208a2c28e34SAlex Deucher PP_MP1_STATE_RESET, 209a2c28e34SAlex Deucher }; 210a2c28e34SAlex Deucher 21106615f9aSEvan Quan enum pp_df_cstate { 21206615f9aSEvan Quan DF_CSTATE_DISALLOW = 0, 21306615f9aSEvan Quan DF_CSTATE_ALLOW, 21406615f9aSEvan Quan }; 21506615f9aSEvan Quan 21690a681c5SDarren Powell /** 21790a681c5SDarren Powell * DOC: amdgpu_pp_power 21890a681c5SDarren Powell * 21990a681c5SDarren Powell * APU power is managed to system-level requirements through the PPT 22090a681c5SDarren Powell * (package power tracking) feature. PPT is intended to limit power to the 22190a681c5SDarren Powell * requirements of the power source and could be dynamically updated to 22290a681c5SDarren Powell * maximize APU performance within the system power budget. 22390a681c5SDarren Powell * 22490a681c5SDarren Powell * Two types of power measurement can be requested, where supported, with 22590a681c5SDarren Powell * :c:type:`enum pp_power_type <pp_power_type>`. 22690a681c5SDarren Powell */ 22790a681c5SDarren Powell 22890a681c5SDarren Powell /** 22990a681c5SDarren Powell * enum pp_power_limit_level - Used to query the power limits 23090a681c5SDarren Powell * 23190a681c5SDarren Powell * @PP_PWR_LIMIT_MIN: Minimum Power Limit 23290a681c5SDarren Powell * @PP_PWR_LIMIT_CURRENT: Current Power Limit 23390a681c5SDarren Powell * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 23490a681c5SDarren Powell * @PP_PWR_LIMIT_MAX: Maximum Power Limit 23590a681c5SDarren Powell */ 236a40a020dSDarren Powell enum pp_power_limit_level 237a40a020dSDarren Powell { 238a40a020dSDarren Powell PP_PWR_LIMIT_MIN = -1, 239a40a020dSDarren Powell PP_PWR_LIMIT_CURRENT, 240a40a020dSDarren Powell PP_PWR_LIMIT_DEFAULT, 241a40a020dSDarren Powell PP_PWR_LIMIT_MAX, 242a40a020dSDarren Powell }; 243a40a020dSDarren Powell 24490a681c5SDarren Powell /** 24590a681c5SDarren Powell * enum pp_power_type - Used to specify the type of the requested power 24690a681c5SDarren Powell * 24790a681c5SDarren Powell * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 24890a681c5SDarren Powell * moving average of APU power (default ~5000 ms). 24990a681c5SDarren Powell * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 25090a681c5SDarren Powell * where supported. 25190a681c5SDarren Powell */ 252a40a020dSDarren Powell enum pp_power_type 253a40a020dSDarren Powell { 254a40a020dSDarren Powell PP_PWR_TYPE_SUSTAINED, 255a40a020dSDarren Powell PP_PWR_TYPE_FAST, 256a40a020dSDarren Powell }; 257a40a020dSDarren Powell 258c79563a3SRex Zhu #define PP_GROUP_MASK 0xF0000000 259c79563a3SRex Zhu #define PP_GROUP_SHIFT 28 260c79563a3SRex Zhu 261c79563a3SRex Zhu #define PP_BLOCK_MASK 0x0FFFFF00 262c79563a3SRex Zhu #define PP_BLOCK_SHIFT 8 263c79563a3SRex Zhu 264c79563a3SRex Zhu #define PP_BLOCK_GFX_CG 0x01 265c79563a3SRex Zhu #define PP_BLOCK_GFX_MG 0x02 266c79563a3SRex Zhu #define PP_BLOCK_GFX_3D 0x04 267c79563a3SRex Zhu #define PP_BLOCK_GFX_RLC 0x08 268c79563a3SRex Zhu #define PP_BLOCK_GFX_CP 0x10 269c79563a3SRex Zhu #define PP_BLOCK_SYS_BIF 0x01 270c79563a3SRex Zhu #define PP_BLOCK_SYS_MC 0x02 271c79563a3SRex Zhu #define PP_BLOCK_SYS_ROM 0x04 272c79563a3SRex Zhu #define PP_BLOCK_SYS_DRM 0x08 273c79563a3SRex Zhu #define PP_BLOCK_SYS_HDP 0x10 274c79563a3SRex Zhu #define PP_BLOCK_SYS_SDMA 0x20 275c79563a3SRex Zhu 276c79563a3SRex Zhu #define PP_STATE_MASK 0x0000000F 277c79563a3SRex Zhu #define PP_STATE_SHIFT 0 278c79563a3SRex Zhu #define PP_STATE_SUPPORT_MASK 0x000000F0 279c79563a3SRex Zhu #define PP_STATE_SUPPORT_SHIFT 0 280c79563a3SRex Zhu 281c79563a3SRex Zhu #define PP_STATE_CG 0x01 282c79563a3SRex Zhu #define PP_STATE_LS 0x02 283c79563a3SRex Zhu #define PP_STATE_DS 0x04 284c79563a3SRex Zhu #define PP_STATE_SD 0x08 285c79563a3SRex Zhu #define PP_STATE_SUPPORT_CG 0x10 286c79563a3SRex Zhu #define PP_STATE_SUPPORT_LS 0x20 287c79563a3SRex Zhu #define PP_STATE_SUPPORT_DS 0x40 288c79563a3SRex Zhu #define PP_STATE_SUPPORT_SD 0x80 289c79563a3SRex Zhu 290c79563a3SRex Zhu #define PP_CG_MSG_ID(group, block, support, state) \ 291c79563a3SRex Zhu ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 292c79563a3SRex Zhu (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 293c79563a3SRex Zhu 2943e454860SEvan Quan #define XGMI_MODE_PSTATE_D3 0 2953e454860SEvan Quan #define XGMI_MODE_PSTATE_D0 1 2963e454860SEvan Quan 297bea9cd3fSKenneth Feng #define NUM_HBM_INSTANCES 4 298bea9cd3fSKenneth Feng 299c79563a3SRex Zhu struct seq_file; 300c79563a3SRex Zhu enum amd_pp_clock_type; 301c79563a3SRex Zhu struct amd_pp_simple_clock_info; 302c79563a3SRex Zhu struct amd_pp_display_configuration; 303c79563a3SRex Zhu struct amd_pp_clock_info; 304c79563a3SRex Zhu struct pp_display_clock_request; 305c79563a3SRex Zhu struct pp_clock_levels_with_voltage; 306c79563a3SRex Zhu struct pp_clock_levels_with_latency; 307c79563a3SRex Zhu struct amd_pp_clocks; 3085f400639SEvan Quan struct pp_smu_wm_range_sets; 3095f400639SEvan Quan struct pp_smu_nv_clock_table; 3105f400639SEvan Quan struct dpm_clocks; 311c79563a3SRex Zhu 312c79563a3SRex Zhu struct amd_pm_funcs { 313c79563a3SRex Zhu /* export for dpm on ci and si */ 314c79563a3SRex Zhu int (*pre_set_power_state)(void *handle); 315c79563a3SRex Zhu int (*set_power_state)(void *handle); 316c79563a3SRex Zhu void (*post_set_power_state)(void *handle); 317c79563a3SRex Zhu void (*display_configuration_changed)(void *handle); 318c79563a3SRex Zhu void (*print_power_state)(void *handle, void *ps); 319c79563a3SRex Zhu bool (*vblank_too_short)(void *handle); 320c79563a3SRex Zhu void (*enable_bapm)(void *handle, bool enable); 321c79563a3SRex Zhu int (*check_state_equal)(void *handle, 322c79563a3SRex Zhu void *cps, 323c79563a3SRex Zhu void *rps, 324c79563a3SRex Zhu bool *equal); 325c79563a3SRex Zhu /* export for sysfs */ 326685fae24SEvan Quan int (*set_fan_control_mode)(void *handle, u32 mode); 327685fae24SEvan Quan int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 3280d8318e1SEvan Quan int (*set_fan_speed_pwm)(void *handle, u32 speed); 3290d8318e1SEvan Quan int (*get_fan_speed_pwm)(void *handle, u32 *speed); 330c79563a3SRex Zhu int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 331c79563a3SRex Zhu int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 3325d64f9bbSDarren Powell int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 333c79563a3SRex Zhu int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 334c79563a3SRex Zhu int (*get_sclk_od)(void *handle); 335c79563a3SRex Zhu int (*set_sclk_od)(void *handle, uint32_t value); 336c79563a3SRex Zhu int (*get_mclk_od)(void *handle); 337c79563a3SRex Zhu int (*set_mclk_od)(void *handle, uint32_t value); 338c79563a3SRex Zhu int (*read_sensor)(void *handle, int idx, void *value, int *size); 339c3ed0e72SKun Liu int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 340c3ed0e72SKun Liu int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 341c79563a3SRex Zhu enum amd_dpm_forced_level (*get_performance_level)(void *handle); 342c79563a3SRex Zhu enum amd_pm_state_type (*get_current_power_state)(void *handle); 343c79563a3SRex Zhu int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 344c2870527SRex Zhu int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 345c79563a3SRex Zhu int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 346c79563a3SRex Zhu int (*get_pp_table)(void *handle, char **table); 347c79563a3SRex Zhu int (*set_pp_table)(void *handle, const char *buf, size_t size); 348c79563a3SRex Zhu void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 349052fe96dSRex Zhu int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 350c79563a3SRex Zhu /* export to amdgpu */ 351c79563a3SRex Zhu struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 352c79563a3SRex Zhu int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 35339199b80SEvan Quan enum amd_pm_state_type *user_state); 354c79563a3SRex Zhu int (*load_firmware)(void *handle); 355c79563a3SRex Zhu int (*wait_for_fw_loading_complete)(void *handle); 356b92c6287SRex Zhu int (*set_powergating_by_smu)(void *handle, 357b92c6287SRex Zhu uint32_t block_type, bool gate); 358c79563a3SRex Zhu int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 3596ab8555eSRex Zhu int (*set_power_limit)(void *handle, uint32_t n); 36004bec521SDarren Powell int (*get_power_limit)(void *handle, uint32_t *limit, 36104bec521SDarren Powell enum pp_power_limit_level pp_limit_level, 36204bec521SDarren Powell enum pp_power_type power_type); 363ea870e44SRex Zhu int (*get_power_profile_mode)(void *handle, char *buf); 364ea870e44SRex Zhu int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 36512a6727dSXiaojian Du int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 366e4d0ef75SNathan Chancellor int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 367e4d0ef75SNathan Chancellor long *input, uint32_t size); 368a2c28e34SAlex Deucher int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 3696acaa6afSAndrey Grodzovsky int (*smu_i2c_bus_access)(void *handle, bool acquire); 370d90a53d6SPrike Liang int (*gfx_state_change_set)(void *handle, uint32_t state); 371c79563a3SRex Zhu /* export to DC */ 372c79563a3SRex Zhu u32 (*get_sclk)(void *handle, bool low); 373c79563a3SRex Zhu u32 (*get_mclk)(void *handle, bool low); 374c79563a3SRex Zhu int (*display_configuration_change)(void *handle, 375c79563a3SRex Zhu const struct amd_pp_display_configuration *input); 376c79563a3SRex Zhu int (*get_display_power_level)(void *handle, 377c79563a3SRex Zhu struct amd_pp_simple_clock_info *output); 378c79563a3SRex Zhu int (*get_current_clocks)(void *handle, 379c79563a3SRex Zhu struct amd_pp_clock_info *clocks); 380c79563a3SRex Zhu int (*get_clock_by_type)(void *handle, 381c79563a3SRex Zhu enum amd_pp_clock_type type, 382c79563a3SRex Zhu struct amd_pp_clocks *clocks); 383c79563a3SRex Zhu int (*get_clock_by_type_with_latency)(void *handle, 384c79563a3SRex Zhu enum amd_pp_clock_type type, 385c79563a3SRex Zhu struct pp_clock_levels_with_latency *clocks); 386c79563a3SRex Zhu int (*get_clock_by_type_with_voltage)(void *handle, 387c79563a3SRex Zhu enum amd_pp_clock_type type, 388c79563a3SRex Zhu struct pp_clock_levels_with_voltage *clocks); 389c79563a3SRex Zhu int (*set_watermarks_for_clocks_ranges)(void *handle, 39099c5e27dSRex Zhu void *clock_ranges); 391c79563a3SRex Zhu int (*display_clock_voltage_request)(void *handle, 392c79563a3SRex Zhu struct pp_display_clock_request *clock); 393c79563a3SRex Zhu int (*get_display_mode_validation_clocks)(void *handle, 394c79563a3SRex Zhu struct amd_pp_simple_clock_info *clocks); 395ea870e44SRex Zhu int (*notify_smu_enable_pwe)(void *handle); 396b55c9e7aSEvan Quan int (*enable_mgpu_fan_boost)(void *handle); 3979ed9203cShersen wu int (*set_active_display_count)(void *handle, uint32_t count); 3989ed9203cShersen wu int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 3999ed9203cShersen wu int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 4009ed9203cShersen wu int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 4017451ca88SJim Qu int (*get_asic_baco_capability)(void *handle, bool *cap); 4027451ca88SJim Qu int (*get_asic_baco_state)(void *handle, int *state); 4037451ca88SJim Qu int (*set_asic_baco_state)(void *handle, int state); 4047ca881a8SEvan Quan int (*get_ppfeature_status)(void *handle, char *buf); 4057ca881a8SEvan Quan int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 406e97204eaSAndrey Grodzovsky int (*asic_reset_mode_2)(void *handle); 407230dd6bbSKenneth Feng int (*asic_reset_enable_gfx_features)(void *handle); 40806615f9aSEvan Quan int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 4093e454860SEvan Quan int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 41025c933b1SEvan Quan ssize_t (*get_gpu_metrics)(void *handle, void **table); 4115f400639SEvan Quan int (*set_watermarks_for_clock_ranges)(void *handle, 4125f400639SEvan Quan struct pp_smu_wm_range_sets *ranges); 4135f400639SEvan Quan int (*display_disable_memory_clock_switch)(void *handle, 4145f400639SEvan Quan bool disable_memory_clock_switch); 4155f400639SEvan Quan int (*get_max_sustainable_clocks_by_dc)(void *handle, 4165f400639SEvan Quan struct pp_smu_nv_clock_table *max_clocks); 4175f400639SEvan Quan int (*get_uclk_dpm_states)(void *handle, 4185f400639SEvan Quan unsigned int *clock_values_in_khz, 4195f400639SEvan Quan unsigned int *num_states); 4205f400639SEvan Quan int (*get_dpm_clock_table)(void *handle, 4215f400639SEvan Quan struct dpm_clocks *clock_table); 422b8c78bdbSLijo Lazar int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 4236ddbd37fSEvan Quan void (*pm_compute_clocks)(void *handle); 424c79563a3SRex Zhu }; 425c79563a3SRex Zhu 42639c5a1ceSEvan Quan struct metrics_table_header { 42739c5a1ceSEvan Quan uint16_t structure_size; 42839c5a1ceSEvan Quan uint8_t format_revision; 42939c5a1ceSEvan Quan uint8_t content_revision; 43039c5a1ceSEvan Quan }; 43139c5a1ceSEvan Quan 4322ce13b01SEvan Quan /* 4332ce13b01SEvan Quan * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 4342ce13b01SEvan Quan * Use gpu_metrics_v1_1 or later instead. 4352ce13b01SEvan Quan */ 43639c5a1ceSEvan Quan struct gpu_metrics_v1_0 { 43739c5a1ceSEvan Quan struct metrics_table_header common_header; 43839c5a1ceSEvan Quan 43939c5a1ceSEvan Quan /* Driver attached timestamp (in ns) */ 44039c5a1ceSEvan Quan uint64_t system_clock_counter; 44139c5a1ceSEvan Quan 44239c5a1ceSEvan Quan /* Temperature */ 44339c5a1ceSEvan Quan uint16_t temperature_edge; 44439c5a1ceSEvan Quan uint16_t temperature_hotspot; 44539c5a1ceSEvan Quan uint16_t temperature_mem; 44639c5a1ceSEvan Quan uint16_t temperature_vrgfx; 44739c5a1ceSEvan Quan uint16_t temperature_vrsoc; 44839c5a1ceSEvan Quan uint16_t temperature_vrmem; 44939c5a1ceSEvan Quan 45039c5a1ceSEvan Quan /* Utilization */ 45139c5a1ceSEvan Quan uint16_t average_gfx_activity; 45239c5a1ceSEvan Quan uint16_t average_umc_activity; // memory controller 45339c5a1ceSEvan Quan uint16_t average_mm_activity; // UVD or VCN 45439c5a1ceSEvan Quan 45539c5a1ceSEvan Quan /* Power/Energy */ 45639c5a1ceSEvan Quan uint16_t average_socket_power; 45739c5a1ceSEvan Quan uint32_t energy_accumulator; 45839c5a1ceSEvan Quan 45939c5a1ceSEvan Quan /* Average clocks */ 46039c5a1ceSEvan Quan uint16_t average_gfxclk_frequency; 46139c5a1ceSEvan Quan uint16_t average_socclk_frequency; 46239c5a1ceSEvan Quan uint16_t average_uclk_frequency; 46339c5a1ceSEvan Quan uint16_t average_vclk0_frequency; 46439c5a1ceSEvan Quan uint16_t average_dclk0_frequency; 46539c5a1ceSEvan Quan uint16_t average_vclk1_frequency; 46639c5a1ceSEvan Quan uint16_t average_dclk1_frequency; 46739c5a1ceSEvan Quan 46839c5a1ceSEvan Quan /* Current clocks */ 46939c5a1ceSEvan Quan uint16_t current_gfxclk; 47039c5a1ceSEvan Quan uint16_t current_socclk; 47139c5a1ceSEvan Quan uint16_t current_uclk; 47239c5a1ceSEvan Quan uint16_t current_vclk0; 47339c5a1ceSEvan Quan uint16_t current_dclk0; 47439c5a1ceSEvan Quan uint16_t current_vclk1; 47539c5a1ceSEvan Quan uint16_t current_dclk1; 47639c5a1ceSEvan Quan 47739c5a1ceSEvan Quan /* Throttle status */ 47839c5a1ceSEvan Quan uint32_t throttle_status; 47939c5a1ceSEvan Quan 48039c5a1ceSEvan Quan /* Fans */ 48139c5a1ceSEvan Quan uint16_t current_fan_speed; 48239c5a1ceSEvan Quan 48339c5a1ceSEvan Quan /* Link width/speed */ 48439c5a1ceSEvan Quan uint8_t pcie_link_width; 48539c5a1ceSEvan Quan uint8_t pcie_link_speed; // in 0.1 GT/s 48639c5a1ceSEvan Quan }; 48739c5a1ceSEvan Quan 4882ce13b01SEvan Quan struct gpu_metrics_v1_1 { 4892ce13b01SEvan Quan struct metrics_table_header common_header; 4902ce13b01SEvan Quan 4912ce13b01SEvan Quan /* Temperature */ 4922ce13b01SEvan Quan uint16_t temperature_edge; 4932ce13b01SEvan Quan uint16_t temperature_hotspot; 4942ce13b01SEvan Quan uint16_t temperature_mem; 4952ce13b01SEvan Quan uint16_t temperature_vrgfx; 4962ce13b01SEvan Quan uint16_t temperature_vrsoc; 4972ce13b01SEvan Quan uint16_t temperature_vrmem; 4982ce13b01SEvan Quan 4992ce13b01SEvan Quan /* Utilization */ 5002ce13b01SEvan Quan uint16_t average_gfx_activity; 5012ce13b01SEvan Quan uint16_t average_umc_activity; // memory controller 5022ce13b01SEvan Quan uint16_t average_mm_activity; // UVD or VCN 5032ce13b01SEvan Quan 5042ce13b01SEvan Quan /* Power/Energy */ 5052ce13b01SEvan Quan uint16_t average_socket_power; 5062ce13b01SEvan Quan uint64_t energy_accumulator; 5072ce13b01SEvan Quan 5082ce13b01SEvan Quan /* Driver attached timestamp (in ns) */ 5092ce13b01SEvan Quan uint64_t system_clock_counter; 5102ce13b01SEvan Quan 5112ce13b01SEvan Quan /* Average clocks */ 5122ce13b01SEvan Quan uint16_t average_gfxclk_frequency; 5132ce13b01SEvan Quan uint16_t average_socclk_frequency; 5142ce13b01SEvan Quan uint16_t average_uclk_frequency; 5152ce13b01SEvan Quan uint16_t average_vclk0_frequency; 5162ce13b01SEvan Quan uint16_t average_dclk0_frequency; 5172ce13b01SEvan Quan uint16_t average_vclk1_frequency; 5182ce13b01SEvan Quan uint16_t average_dclk1_frequency; 5192ce13b01SEvan Quan 5202ce13b01SEvan Quan /* Current clocks */ 5212ce13b01SEvan Quan uint16_t current_gfxclk; 5222ce13b01SEvan Quan uint16_t current_socclk; 5232ce13b01SEvan Quan uint16_t current_uclk; 5242ce13b01SEvan Quan uint16_t current_vclk0; 5252ce13b01SEvan Quan uint16_t current_dclk0; 5262ce13b01SEvan Quan uint16_t current_vclk1; 5272ce13b01SEvan Quan uint16_t current_dclk1; 5282ce13b01SEvan Quan 5292ce13b01SEvan Quan /* Throttle status */ 5302ce13b01SEvan Quan uint32_t throttle_status; 5312ce13b01SEvan Quan 5322ce13b01SEvan Quan /* Fans */ 5332ce13b01SEvan Quan uint16_t current_fan_speed; 5342ce13b01SEvan Quan 5352ce13b01SEvan Quan /* Link width/speed */ 5362ce13b01SEvan Quan uint16_t pcie_link_width; 5372ce13b01SEvan Quan uint16_t pcie_link_speed; // in 0.1 GT/s 5382ce13b01SEvan Quan 5392ce13b01SEvan Quan uint16_t padding; 540bea9cd3fSKenneth Feng 541bea9cd3fSKenneth Feng uint32_t gfx_activity_acc; 542bea9cd3fSKenneth Feng uint32_t mem_activity_acc; 543bea9cd3fSKenneth Feng 544bea9cd3fSKenneth Feng uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 5452ce13b01SEvan Quan }; 5462ce13b01SEvan Quan 547403c9674SEvan Quan struct gpu_metrics_v1_2 { 548403c9674SEvan Quan struct metrics_table_header common_header; 549403c9674SEvan Quan 550403c9674SEvan Quan /* Temperature */ 551403c9674SEvan Quan uint16_t temperature_edge; 552403c9674SEvan Quan uint16_t temperature_hotspot; 553403c9674SEvan Quan uint16_t temperature_mem; 554403c9674SEvan Quan uint16_t temperature_vrgfx; 555403c9674SEvan Quan uint16_t temperature_vrsoc; 556403c9674SEvan Quan uint16_t temperature_vrmem; 557403c9674SEvan Quan 558403c9674SEvan Quan /* Utilization */ 559403c9674SEvan Quan uint16_t average_gfx_activity; 560403c9674SEvan Quan uint16_t average_umc_activity; // memory controller 561403c9674SEvan Quan uint16_t average_mm_activity; // UVD or VCN 562403c9674SEvan Quan 563403c9674SEvan Quan /* Power/Energy */ 564403c9674SEvan Quan uint16_t average_socket_power; 565403c9674SEvan Quan uint64_t energy_accumulator; 566403c9674SEvan Quan 567403c9674SEvan Quan /* Driver attached timestamp (in ns) */ 568403c9674SEvan Quan uint64_t system_clock_counter; 569403c9674SEvan Quan 570403c9674SEvan Quan /* Average clocks */ 571403c9674SEvan Quan uint16_t average_gfxclk_frequency; 572403c9674SEvan Quan uint16_t average_socclk_frequency; 573403c9674SEvan Quan uint16_t average_uclk_frequency; 574403c9674SEvan Quan uint16_t average_vclk0_frequency; 575403c9674SEvan Quan uint16_t average_dclk0_frequency; 576403c9674SEvan Quan uint16_t average_vclk1_frequency; 577403c9674SEvan Quan uint16_t average_dclk1_frequency; 578403c9674SEvan Quan 579403c9674SEvan Quan /* Current clocks */ 580403c9674SEvan Quan uint16_t current_gfxclk; 581403c9674SEvan Quan uint16_t current_socclk; 582403c9674SEvan Quan uint16_t current_uclk; 583403c9674SEvan Quan uint16_t current_vclk0; 584403c9674SEvan Quan uint16_t current_dclk0; 585403c9674SEvan Quan uint16_t current_vclk1; 586403c9674SEvan Quan uint16_t current_dclk1; 587403c9674SEvan Quan 58822a7dcf5SGraham Sider /* Throttle status (ASIC dependent) */ 589403c9674SEvan Quan uint32_t throttle_status; 590403c9674SEvan Quan 591403c9674SEvan Quan /* Fans */ 592403c9674SEvan Quan uint16_t current_fan_speed; 593403c9674SEvan Quan 594403c9674SEvan Quan /* Link width/speed */ 595403c9674SEvan Quan uint16_t pcie_link_width; 596403c9674SEvan Quan uint16_t pcie_link_speed; // in 0.1 GT/s 597403c9674SEvan Quan 598403c9674SEvan Quan uint16_t padding; 599403c9674SEvan Quan 600403c9674SEvan Quan uint32_t gfx_activity_acc; 601403c9674SEvan Quan uint32_t mem_activity_acc; 602403c9674SEvan Quan 603403c9674SEvan Quan uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 604403c9674SEvan Quan 605403c9674SEvan Quan /* PMFW attached timestamp (10ns resolution) */ 606403c9674SEvan Quan uint64_t firmware_timestamp; 607403c9674SEvan Quan }; 608403c9674SEvan Quan 6090b7db431SDavid M Nieto struct gpu_metrics_v1_3 { 6100b7db431SDavid M Nieto struct metrics_table_header common_header; 6110b7db431SDavid M Nieto 6120b7db431SDavid M Nieto /* Temperature */ 6130b7db431SDavid M Nieto uint16_t temperature_edge; 6140b7db431SDavid M Nieto uint16_t temperature_hotspot; 6150b7db431SDavid M Nieto uint16_t temperature_mem; 6160b7db431SDavid M Nieto uint16_t temperature_vrgfx; 6170b7db431SDavid M Nieto uint16_t temperature_vrsoc; 6180b7db431SDavid M Nieto uint16_t temperature_vrmem; 6190b7db431SDavid M Nieto 6200b7db431SDavid M Nieto /* Utilization */ 6210b7db431SDavid M Nieto uint16_t average_gfx_activity; 6220b7db431SDavid M Nieto uint16_t average_umc_activity; // memory controller 6230b7db431SDavid M Nieto uint16_t average_mm_activity; // UVD or VCN 6240b7db431SDavid M Nieto 6250b7db431SDavid M Nieto /* Power/Energy */ 6260b7db431SDavid M Nieto uint16_t average_socket_power; 6270b7db431SDavid M Nieto uint64_t energy_accumulator; 6280b7db431SDavid M Nieto 6290b7db431SDavid M Nieto /* Driver attached timestamp (in ns) */ 6300b7db431SDavid M Nieto uint64_t system_clock_counter; 6310b7db431SDavid M Nieto 6320b7db431SDavid M Nieto /* Average clocks */ 6330b7db431SDavid M Nieto uint16_t average_gfxclk_frequency; 6340b7db431SDavid M Nieto uint16_t average_socclk_frequency; 6350b7db431SDavid M Nieto uint16_t average_uclk_frequency; 6360b7db431SDavid M Nieto uint16_t average_vclk0_frequency; 6370b7db431SDavid M Nieto uint16_t average_dclk0_frequency; 6380b7db431SDavid M Nieto uint16_t average_vclk1_frequency; 6390b7db431SDavid M Nieto uint16_t average_dclk1_frequency; 6400b7db431SDavid M Nieto 6410b7db431SDavid M Nieto /* Current clocks */ 6420b7db431SDavid M Nieto uint16_t current_gfxclk; 6430b7db431SDavid M Nieto uint16_t current_socclk; 6440b7db431SDavid M Nieto uint16_t current_uclk; 6450b7db431SDavid M Nieto uint16_t current_vclk0; 6460b7db431SDavid M Nieto uint16_t current_dclk0; 6470b7db431SDavid M Nieto uint16_t current_vclk1; 6480b7db431SDavid M Nieto uint16_t current_dclk1; 6490b7db431SDavid M Nieto 6500b7db431SDavid M Nieto /* Throttle status */ 6510b7db431SDavid M Nieto uint32_t throttle_status; 6520b7db431SDavid M Nieto 6530b7db431SDavid M Nieto /* Fans */ 6540b7db431SDavid M Nieto uint16_t current_fan_speed; 6550b7db431SDavid M Nieto 6560b7db431SDavid M Nieto /* Link width/speed */ 6570b7db431SDavid M Nieto uint16_t pcie_link_width; 6580b7db431SDavid M Nieto uint16_t pcie_link_speed; // in 0.1 GT/s 6590b7db431SDavid M Nieto 6600b7db431SDavid M Nieto uint16_t padding; 6610b7db431SDavid M Nieto 6620b7db431SDavid M Nieto uint32_t gfx_activity_acc; 6630b7db431SDavid M Nieto uint32_t mem_activity_acc; 6640b7db431SDavid M Nieto 6650b7db431SDavid M Nieto uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 6660b7db431SDavid M Nieto 6670b7db431SDavid M Nieto /* PMFW attached timestamp (10ns resolution) */ 6680b7db431SDavid M Nieto uint64_t firmware_timestamp; 6690b7db431SDavid M Nieto 6700b7db431SDavid M Nieto /* Voltage (mV) */ 6710b7db431SDavid M Nieto uint16_t voltage_soc; 6720b7db431SDavid M Nieto uint16_t voltage_gfx; 6730b7db431SDavid M Nieto uint16_t voltage_mem; 6740b7db431SDavid M Nieto 6750b7db431SDavid M Nieto uint16_t padding1; 67622a7dcf5SGraham Sider 67722a7dcf5SGraham Sider /* Throttle status (ASIC independent) */ 67822a7dcf5SGraham Sider uint64_t indep_throttle_status; 6790b7db431SDavid M Nieto }; 6800b7db431SDavid M Nieto 6812ce13b01SEvan Quan /* 6822ce13b01SEvan Quan * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 6832ce13b01SEvan Quan * Use gpu_metrics_v2_1 or later instead. 6842ce13b01SEvan Quan */ 68539c5a1ceSEvan Quan struct gpu_metrics_v2_0 { 68639c5a1ceSEvan Quan struct metrics_table_header common_header; 68739c5a1ceSEvan Quan 68839c5a1ceSEvan Quan /* Driver attached timestamp (in ns) */ 68939c5a1ceSEvan Quan uint64_t system_clock_counter; 69039c5a1ceSEvan Quan 69139c5a1ceSEvan Quan /* Temperature */ 69239c5a1ceSEvan Quan uint16_t temperature_gfx; // gfx temperature on APUs 69339c5a1ceSEvan Quan uint16_t temperature_soc; // soc temperature on APUs 69439c5a1ceSEvan Quan uint16_t temperature_core[8]; // CPU core temperature on APUs 69539c5a1ceSEvan Quan uint16_t temperature_l3[2]; 69639c5a1ceSEvan Quan 69739c5a1ceSEvan Quan /* Utilization */ 69839c5a1ceSEvan Quan uint16_t average_gfx_activity; 69939c5a1ceSEvan Quan uint16_t average_mm_activity; // UVD or VCN 70039c5a1ceSEvan Quan 70139c5a1ceSEvan Quan /* Power/Energy */ 70239c5a1ceSEvan Quan uint16_t average_socket_power; // dGPU + APU power on A + A platform 70339c5a1ceSEvan Quan uint16_t average_cpu_power; 70439c5a1ceSEvan Quan uint16_t average_soc_power; 70539c5a1ceSEvan Quan uint16_t average_gfx_power; 70639c5a1ceSEvan Quan uint16_t average_core_power[8]; // CPU core power on APUs 70739c5a1ceSEvan Quan 70839c5a1ceSEvan Quan /* Average clocks */ 70939c5a1ceSEvan Quan uint16_t average_gfxclk_frequency; 71039c5a1ceSEvan Quan uint16_t average_socclk_frequency; 71139c5a1ceSEvan Quan uint16_t average_uclk_frequency; 71239c5a1ceSEvan Quan uint16_t average_fclk_frequency; 71339c5a1ceSEvan Quan uint16_t average_vclk_frequency; 71439c5a1ceSEvan Quan uint16_t average_dclk_frequency; 71539c5a1ceSEvan Quan 71639c5a1ceSEvan Quan /* Current clocks */ 71739c5a1ceSEvan Quan uint16_t current_gfxclk; 71839c5a1ceSEvan Quan uint16_t current_socclk; 71939c5a1ceSEvan Quan uint16_t current_uclk; 72039c5a1ceSEvan Quan uint16_t current_fclk; 72139c5a1ceSEvan Quan uint16_t current_vclk; 72239c5a1ceSEvan Quan uint16_t current_dclk; 72339c5a1ceSEvan Quan uint16_t current_coreclk[8]; // CPU core clocks 72439c5a1ceSEvan Quan uint16_t current_l3clk[2]; 72539c5a1ceSEvan Quan 72639c5a1ceSEvan Quan /* Throttle status */ 72739c5a1ceSEvan Quan uint32_t throttle_status; 72839c5a1ceSEvan Quan 72939c5a1ceSEvan Quan /* Fans */ 73039c5a1ceSEvan Quan uint16_t fan_pwm; 73139c5a1ceSEvan Quan 73239c5a1ceSEvan Quan uint16_t padding; 73339c5a1ceSEvan Quan }; 73439c5a1ceSEvan Quan 7352ce13b01SEvan Quan struct gpu_metrics_v2_1 { 7362ce13b01SEvan Quan struct metrics_table_header common_header; 7372ce13b01SEvan Quan 7382ce13b01SEvan Quan /* Temperature */ 7392ce13b01SEvan Quan uint16_t temperature_gfx; // gfx temperature on APUs 7402ce13b01SEvan Quan uint16_t temperature_soc; // soc temperature on APUs 7412ce13b01SEvan Quan uint16_t temperature_core[8]; // CPU core temperature on APUs 7422ce13b01SEvan Quan uint16_t temperature_l3[2]; 7432ce13b01SEvan Quan 7442ce13b01SEvan Quan /* Utilization */ 7452ce13b01SEvan Quan uint16_t average_gfx_activity; 7462ce13b01SEvan Quan uint16_t average_mm_activity; // UVD or VCN 7472ce13b01SEvan Quan 7482ce13b01SEvan Quan /* Driver attached timestamp (in ns) */ 7492ce13b01SEvan Quan uint64_t system_clock_counter; 7502ce13b01SEvan Quan 7512ce13b01SEvan Quan /* Power/Energy */ 7522ce13b01SEvan Quan uint16_t average_socket_power; // dGPU + APU power on A + A platform 7532ce13b01SEvan Quan uint16_t average_cpu_power; 7542ce13b01SEvan Quan uint16_t average_soc_power; 7552ce13b01SEvan Quan uint16_t average_gfx_power; 7562ce13b01SEvan Quan uint16_t average_core_power[8]; // CPU core power on APUs 7572ce13b01SEvan Quan 7582ce13b01SEvan Quan /* Average clocks */ 7592ce13b01SEvan Quan uint16_t average_gfxclk_frequency; 7602ce13b01SEvan Quan uint16_t average_socclk_frequency; 7612ce13b01SEvan Quan uint16_t average_uclk_frequency; 7622ce13b01SEvan Quan uint16_t average_fclk_frequency; 7632ce13b01SEvan Quan uint16_t average_vclk_frequency; 7642ce13b01SEvan Quan uint16_t average_dclk_frequency; 7652ce13b01SEvan Quan 7662ce13b01SEvan Quan /* Current clocks */ 7672ce13b01SEvan Quan uint16_t current_gfxclk; 7682ce13b01SEvan Quan uint16_t current_socclk; 7692ce13b01SEvan Quan uint16_t current_uclk; 7702ce13b01SEvan Quan uint16_t current_fclk; 7712ce13b01SEvan Quan uint16_t current_vclk; 7722ce13b01SEvan Quan uint16_t current_dclk; 7732ce13b01SEvan Quan uint16_t current_coreclk[8]; // CPU core clocks 7742ce13b01SEvan Quan uint16_t current_l3clk[2]; 7752ce13b01SEvan Quan 7762ce13b01SEvan Quan /* Throttle status */ 7772ce13b01SEvan Quan uint32_t throttle_status; 7782ce13b01SEvan Quan 7792ce13b01SEvan Quan /* Fans */ 7802ce13b01SEvan Quan uint16_t fan_pwm; 7812ce13b01SEvan Quan 7822ce13b01SEvan Quan uint16_t padding[3]; 7832ce13b01SEvan Quan }; 7842ce13b01SEvan Quan 78522a7dcf5SGraham Sider struct gpu_metrics_v2_2 { 78622a7dcf5SGraham Sider struct metrics_table_header common_header; 78722a7dcf5SGraham Sider 78822a7dcf5SGraham Sider /* Temperature */ 78922a7dcf5SGraham Sider uint16_t temperature_gfx; // gfx temperature on APUs 79022a7dcf5SGraham Sider uint16_t temperature_soc; // soc temperature on APUs 79122a7dcf5SGraham Sider uint16_t temperature_core[8]; // CPU core temperature on APUs 79222a7dcf5SGraham Sider uint16_t temperature_l3[2]; 79322a7dcf5SGraham Sider 79422a7dcf5SGraham Sider /* Utilization */ 79522a7dcf5SGraham Sider uint16_t average_gfx_activity; 79622a7dcf5SGraham Sider uint16_t average_mm_activity; // UVD or VCN 79722a7dcf5SGraham Sider 79822a7dcf5SGraham Sider /* Driver attached timestamp (in ns) */ 79922a7dcf5SGraham Sider uint64_t system_clock_counter; 80022a7dcf5SGraham Sider 80122a7dcf5SGraham Sider /* Power/Energy */ 80222a7dcf5SGraham Sider uint16_t average_socket_power; // dGPU + APU power on A + A platform 80322a7dcf5SGraham Sider uint16_t average_cpu_power; 80422a7dcf5SGraham Sider uint16_t average_soc_power; 80522a7dcf5SGraham Sider uint16_t average_gfx_power; 80622a7dcf5SGraham Sider uint16_t average_core_power[8]; // CPU core power on APUs 80722a7dcf5SGraham Sider 80822a7dcf5SGraham Sider /* Average clocks */ 80922a7dcf5SGraham Sider uint16_t average_gfxclk_frequency; 81022a7dcf5SGraham Sider uint16_t average_socclk_frequency; 81122a7dcf5SGraham Sider uint16_t average_uclk_frequency; 81222a7dcf5SGraham Sider uint16_t average_fclk_frequency; 81322a7dcf5SGraham Sider uint16_t average_vclk_frequency; 81422a7dcf5SGraham Sider uint16_t average_dclk_frequency; 81522a7dcf5SGraham Sider 81622a7dcf5SGraham Sider /* Current clocks */ 81722a7dcf5SGraham Sider uint16_t current_gfxclk; 81822a7dcf5SGraham Sider uint16_t current_socclk; 81922a7dcf5SGraham Sider uint16_t current_uclk; 82022a7dcf5SGraham Sider uint16_t current_fclk; 82122a7dcf5SGraham Sider uint16_t current_vclk; 82222a7dcf5SGraham Sider uint16_t current_dclk; 82322a7dcf5SGraham Sider uint16_t current_coreclk[8]; // CPU core clocks 82422a7dcf5SGraham Sider uint16_t current_l3clk[2]; 82522a7dcf5SGraham Sider 82622a7dcf5SGraham Sider /* Throttle status (ASIC dependent) */ 82722a7dcf5SGraham Sider uint32_t throttle_status; 82822a7dcf5SGraham Sider 82922a7dcf5SGraham Sider /* Fans */ 83022a7dcf5SGraham Sider uint16_t fan_pwm; 83122a7dcf5SGraham Sider 83222a7dcf5SGraham Sider uint16_t padding[3]; 83322a7dcf5SGraham Sider 83422a7dcf5SGraham Sider /* Throttle status (ASIC independent) */ 83522a7dcf5SGraham Sider uint64_t indep_throttle_status; 83622a7dcf5SGraham Sider }; 83722a7dcf5SGraham Sider 8380d6516efSLi Ma struct gpu_metrics_v2_3 { 8390d6516efSLi Ma struct metrics_table_header common_header; 8400d6516efSLi Ma 8410d6516efSLi Ma /* Temperature */ 8420d6516efSLi Ma uint16_t temperature_gfx; // gfx temperature on APUs 8430d6516efSLi Ma uint16_t temperature_soc; // soc temperature on APUs 8440d6516efSLi Ma uint16_t temperature_core[8]; // CPU core temperature on APUs 8450d6516efSLi Ma uint16_t temperature_l3[2]; 8460d6516efSLi Ma 8470d6516efSLi Ma /* Utilization */ 8480d6516efSLi Ma uint16_t average_gfx_activity; 8490d6516efSLi Ma uint16_t average_mm_activity; // UVD or VCN 8500d6516efSLi Ma 8510d6516efSLi Ma /* Driver attached timestamp (in ns) */ 8520d6516efSLi Ma uint64_t system_clock_counter; 8530d6516efSLi Ma 8540d6516efSLi Ma /* Power/Energy */ 8550d6516efSLi Ma uint16_t average_socket_power; // dGPU + APU power on A + A platform 8560d6516efSLi Ma uint16_t average_cpu_power; 8570d6516efSLi Ma uint16_t average_soc_power; 8580d6516efSLi Ma uint16_t average_gfx_power; 8590d6516efSLi Ma uint16_t average_core_power[8]; // CPU core power on APUs 8600d6516efSLi Ma 8610d6516efSLi Ma /* Average clocks */ 8620d6516efSLi Ma uint16_t average_gfxclk_frequency; 8630d6516efSLi Ma uint16_t average_socclk_frequency; 8640d6516efSLi Ma uint16_t average_uclk_frequency; 8650d6516efSLi Ma uint16_t average_fclk_frequency; 8660d6516efSLi Ma uint16_t average_vclk_frequency; 8670d6516efSLi Ma uint16_t average_dclk_frequency; 8680d6516efSLi Ma 8690d6516efSLi Ma /* Current clocks */ 8700d6516efSLi Ma uint16_t current_gfxclk; 8710d6516efSLi Ma uint16_t current_socclk; 8720d6516efSLi Ma uint16_t current_uclk; 8730d6516efSLi Ma uint16_t current_fclk; 8740d6516efSLi Ma uint16_t current_vclk; 8750d6516efSLi Ma uint16_t current_dclk; 8760d6516efSLi Ma uint16_t current_coreclk[8]; // CPU core clocks 8770d6516efSLi Ma uint16_t current_l3clk[2]; 8780d6516efSLi Ma 8790d6516efSLi Ma /* Throttle status (ASIC dependent) */ 8800d6516efSLi Ma uint32_t throttle_status; 8810d6516efSLi Ma 8820d6516efSLi Ma /* Fans */ 8830d6516efSLi Ma uint16_t fan_pwm; 8840d6516efSLi Ma 8850d6516efSLi Ma uint16_t padding[3]; 8860d6516efSLi Ma 8870d6516efSLi Ma /* Throttle status (ASIC independent) */ 8880d6516efSLi Ma uint64_t indep_throttle_status; 8890d6516efSLi Ma 8900d6516efSLi Ma /* Average Temperature */ 8910d6516efSLi Ma uint16_t average_temperature_gfx; // average gfx temperature on APUs 8920d6516efSLi Ma uint16_t average_temperature_soc; // average soc temperature on APUs 8930d6516efSLi Ma uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 8940d6516efSLi Ma uint16_t average_temperature_l3[2]; 8950d6516efSLi Ma }; 89641cec40bSWenyou Yang 89741cec40bSWenyou Yang struct gpu_metrics_v2_4 { 89841cec40bSWenyou Yang struct metrics_table_header common_header; 89941cec40bSWenyou Yang 90041cec40bSWenyou Yang /* Temperature (unit: centi-Celsius) */ 90141cec40bSWenyou Yang uint16_t temperature_gfx; 90241cec40bSWenyou Yang uint16_t temperature_soc; 90341cec40bSWenyou Yang uint16_t temperature_core[8]; 90441cec40bSWenyou Yang uint16_t temperature_l3[2]; 90541cec40bSWenyou Yang 90641cec40bSWenyou Yang /* Utilization (unit: centi) */ 90741cec40bSWenyou Yang uint16_t average_gfx_activity; 90841cec40bSWenyou Yang uint16_t average_mm_activity; 90941cec40bSWenyou Yang 91041cec40bSWenyou Yang /* Driver attached timestamp (in ns) */ 91141cec40bSWenyou Yang uint64_t system_clock_counter; 91241cec40bSWenyou Yang 91341cec40bSWenyou Yang /* Power/Energy (unit: mW) */ 91441cec40bSWenyou Yang uint16_t average_socket_power; 91541cec40bSWenyou Yang uint16_t average_cpu_power; 91641cec40bSWenyou Yang uint16_t average_soc_power; 91741cec40bSWenyou Yang uint16_t average_gfx_power; 91841cec40bSWenyou Yang uint16_t average_core_power[8]; 91941cec40bSWenyou Yang 92041cec40bSWenyou Yang /* Average clocks (unit: MHz) */ 92141cec40bSWenyou Yang uint16_t average_gfxclk_frequency; 92241cec40bSWenyou Yang uint16_t average_socclk_frequency; 92341cec40bSWenyou Yang uint16_t average_uclk_frequency; 92441cec40bSWenyou Yang uint16_t average_fclk_frequency; 92541cec40bSWenyou Yang uint16_t average_vclk_frequency; 92641cec40bSWenyou Yang uint16_t average_dclk_frequency; 92741cec40bSWenyou Yang 92841cec40bSWenyou Yang /* Current clocks (unit: MHz) */ 92941cec40bSWenyou Yang uint16_t current_gfxclk; 93041cec40bSWenyou Yang uint16_t current_socclk; 93141cec40bSWenyou Yang uint16_t current_uclk; 93241cec40bSWenyou Yang uint16_t current_fclk; 93341cec40bSWenyou Yang uint16_t current_vclk; 93441cec40bSWenyou Yang uint16_t current_dclk; 93541cec40bSWenyou Yang uint16_t current_coreclk[8]; 93641cec40bSWenyou Yang uint16_t current_l3clk[2]; 93741cec40bSWenyou Yang 93841cec40bSWenyou Yang /* Throttle status (ASIC dependent) */ 93941cec40bSWenyou Yang uint32_t throttle_status; 94041cec40bSWenyou Yang 94141cec40bSWenyou Yang /* Fans */ 94241cec40bSWenyou Yang uint16_t fan_pwm; 94341cec40bSWenyou Yang 94441cec40bSWenyou Yang uint16_t padding[3]; 94541cec40bSWenyou Yang 94641cec40bSWenyou Yang /* Throttle status (ASIC independent) */ 94741cec40bSWenyou Yang uint64_t indep_throttle_status; 94841cec40bSWenyou Yang 94941cec40bSWenyou Yang /* Average Temperature (unit: centi-Celsius) */ 95041cec40bSWenyou Yang uint16_t average_temperature_gfx; 95141cec40bSWenyou Yang uint16_t average_temperature_soc; 95241cec40bSWenyou Yang uint16_t average_temperature_core[8]; 95341cec40bSWenyou Yang uint16_t average_temperature_l3[2]; 95441cec40bSWenyou Yang 95541cec40bSWenyou Yang /* Power/Voltage (unit: mV) */ 95641cec40bSWenyou Yang uint16_t average_cpu_voltage; 95741cec40bSWenyou Yang uint16_t average_soc_voltage; 95841cec40bSWenyou Yang uint16_t average_gfx_voltage; 95941cec40bSWenyou Yang 96041cec40bSWenyou Yang /* Power/Current (unit: mA) */ 96141cec40bSWenyou Yang uint16_t average_cpu_current; 96241cec40bSWenyou Yang uint16_t average_soc_current; 96341cec40bSWenyou Yang uint16_t average_gfx_current; 96441cec40bSWenyou Yang }; 965c79563a3SRex Zhu #endif 966