1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _umc_6_7_0_OFFSET_HEADER 24 #define _umc_6_7_0_OFFSET_HEADER 25 26 27 28 // addressBlock: umc_w_phy_umc0_mca_ip_umc0_mca_map 29 // base address: 0x50f00 30 #define regMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2 31 #define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0 32 #define regMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4 33 #define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0 34 35 36 // addressBlock: umc_w_phy_umc0_umcch0_umcchdec 37 // base address: 0x50000 38 #define regUMCCH0_0_BaseAddrCS0 0x0000 39 #define regUMCCH0_0_BaseAddrCS0_BASE_IDX 0 40 #define regUMCCH0_0_AddrMaskCS01 0x0008 41 #define regUMCCH0_0_AddrMaskCS01_BASE_IDX 0 42 #define regUMCCH0_0_AddrSelCS01 0x0010 43 #define regUMCCH0_0_AddrSelCS01_BASE_IDX 0 44 #define regUMCCH0_0_AddrHashBank0 0x0032 45 #define regUMCCH0_0_AddrHashBank0_BASE_IDX 0 46 #define regUMCCH0_0_AddrHashBank1 0x0033 47 #define regUMCCH0_0_AddrHashBank1_BASE_IDX 0 48 #define regUMCCH0_0_AddrHashBank2 0x0034 49 #define regUMCCH0_0_AddrHashBank2_BASE_IDX 0 50 #define regUMCCH0_0_AddrHashBank3 0x0035 51 #define regUMCCH0_0_AddrHashBank3_BASE_IDX 0 52 #define regUMCCH0_0_AddrHashBank4 0x0036 53 #define regUMCCH0_0_AddrHashBank4_BASE_IDX 0 54 #define regUMCCH0_0_AddrHashBank5 0x0037 55 #define regUMCCH0_0_AddrHashBank5_BASE_IDX 0 56 #define regUMCCH0_0_UMC_CONFIG 0x0040 57 #define regUMCCH0_0_UMC_CONFIG_BASE_IDX 0 58 #define regUMCCH0_0_EccCtrl 0x0053 59 #define regUMCCH0_0_EccCtrl_BASE_IDX 0 60 #define regUMCCH0_0_UmcLocalCap 0x0306 61 #define regUMCCH0_0_UmcLocalCap_BASE_IDX 0 62 #define regUMCCH0_0_EccErrCntSel 0x0328 63 #define regUMCCH0_0_EccErrCntSel_BASE_IDX 0 64 #define regUMCCH0_0_EccErrCnt 0x0329 65 #define regUMCCH0_0_EccErrCnt_BASE_IDX 0 66 #define regUMCCH0_0_PerfMonCtlClk 0x0340 67 #define regUMCCH0_0_PerfMonCtlClk_BASE_IDX 0 68 #define regUMCCH0_0_PerfMonCtrClk_Lo 0x0341 69 #define regUMCCH0_0_PerfMonCtrClk_Lo_BASE_IDX 0 70 #define regUMCCH0_0_PerfMonCtrClk_Hi 0x0342 71 #define regUMCCH0_0_PerfMonCtrClk_Hi_BASE_IDX 0 72 #define regUMCCH0_0_PerfMonCtl1 0x0344 73 #define regUMCCH0_0_PerfMonCtl1_BASE_IDX 0 74 #define regUMCCH0_0_PerfMonCtr1_Lo 0x0345 75 #define regUMCCH0_0_PerfMonCtr1_Lo_BASE_IDX 0 76 #define regUMCCH0_0_PerfMonCtr1_Hi 0x0346 77 #define regUMCCH0_0_PerfMonCtr1_Hi_BASE_IDX 0 78 #define regUMCCH0_0_PerfMonCtl2 0x0347 79 #define regUMCCH0_0_PerfMonCtl2_BASE_IDX 0 80 #define regUMCCH0_0_PerfMonCtr2_Lo 0x0348 81 #define regUMCCH0_0_PerfMonCtr2_Lo_BASE_IDX 0 82 #define regUMCCH0_0_PerfMonCtr2_Hi 0x0349 83 #define regUMCCH0_0_PerfMonCtr2_Hi_BASE_IDX 0 84 #define regUMCCH0_0_PerfMonCtl3 0x034a 85 #define regUMCCH0_0_PerfMonCtl3_BASE_IDX 0 86 #define regUMCCH0_0_PerfMonCtr3_Lo 0x034b 87 #define regUMCCH0_0_PerfMonCtr3_Lo_BASE_IDX 0 88 #define regUMCCH0_0_PerfMonCtr3_Hi 0x034c 89 #define regUMCCH0_0_PerfMonCtr3_Hi_BASE_IDX 0 90 #define regUMCCH0_0_PerfMonCtl4 0x034d 91 #define regUMCCH0_0_PerfMonCtl4_BASE_IDX 0 92 #define regUMCCH0_0_PerfMonCtr4_Lo 0x034e 93 #define regUMCCH0_0_PerfMonCtr4_Lo_BASE_IDX 0 94 #define regUMCCH0_0_PerfMonCtr4_Hi 0x034f 95 #define regUMCCH0_0_PerfMonCtr4_Hi_BASE_IDX 0 96 #define regUMCCH0_0_PerfMonCtl5 0x0350 97 #define regUMCCH0_0_PerfMonCtl5_BASE_IDX 0 98 #define regUMCCH0_0_PerfMonCtr5_Lo 0x0351 99 #define regUMCCH0_0_PerfMonCtr5_Lo_BASE_IDX 0 100 #define regUMCCH0_0_PerfMonCtr5_Hi 0x0352 101 #define regUMCCH0_0_PerfMonCtr5_Hi_BASE_IDX 0 102 #define regUMCCH0_0_PerfMonCtl6 0x0353 103 #define regUMCCH0_0_PerfMonCtl6_BASE_IDX 0 104 #define regUMCCH0_0_PerfMonCtr6_Lo 0x0354 105 #define regUMCCH0_0_PerfMonCtr6_Lo_BASE_IDX 0 106 #define regUMCCH0_0_PerfMonCtr6_Hi 0x0355 107 #define regUMCCH0_0_PerfMonCtr6_Hi_BASE_IDX 0 108 #define regUMCCH0_0_PerfMonCtl7 0x0356 109 #define regUMCCH0_0_PerfMonCtl7_BASE_IDX 0 110 #define regUMCCH0_0_PerfMonCtr7_Lo 0x0357 111 #define regUMCCH0_0_PerfMonCtr7_Lo_BASE_IDX 0 112 #define regUMCCH0_0_PerfMonCtr7_Hi 0x0358 113 #define regUMCCH0_0_PerfMonCtr7_Hi_BASE_IDX 0 114 #define regUMCCH0_0_PerfMonCtl8 0x0359 115 #define regUMCCH0_0_PerfMonCtl8_BASE_IDX 0 116 #define regUMCCH0_0_PerfMonCtr8_Lo 0x035a 117 #define regUMCCH0_0_PerfMonCtr8_Lo_BASE_IDX 0 118 #define regUMCCH0_0_PerfMonCtr8_Hi 0x035b 119 #define regUMCCH0_0_PerfMonCtr8_Hi_BASE_IDX 0 120 121 122 // addressBlock: umc_w_phy_umc0_umcch1_umcchdec 123 // base address: 0x51000 124 #define regUMCCH1_0_BaseAddrCS0 0x0400 125 #define regUMCCH1_0_BaseAddrCS0_BASE_IDX 0 126 #define regUMCCH1_0_AddrMaskCS01 0x0408 127 #define regUMCCH1_0_AddrMaskCS01_BASE_IDX 0 128 #define regUMCCH1_0_AddrSelCS01 0x0410 129 #define regUMCCH1_0_AddrSelCS01_BASE_IDX 0 130 #define regUMCCH1_0_AddrHashBank0 0x0432 131 #define regUMCCH1_0_AddrHashBank0_BASE_IDX 0 132 #define regUMCCH1_0_AddrHashBank1 0x0433 133 #define regUMCCH1_0_AddrHashBank1_BASE_IDX 0 134 #define regUMCCH1_0_AddrHashBank2 0x0434 135 #define regUMCCH1_0_AddrHashBank2_BASE_IDX 0 136 #define regUMCCH1_0_AddrHashBank3 0x0435 137 #define regUMCCH1_0_AddrHashBank3_BASE_IDX 0 138 #define regUMCCH1_0_AddrHashBank4 0x0436 139 #define regUMCCH1_0_AddrHashBank4_BASE_IDX 0 140 #define regUMCCH1_0_AddrHashBank5 0x0437 141 #define regUMCCH1_0_AddrHashBank5_BASE_IDX 0 142 #define regUMCCH1_0_UMC_CONFIG 0x0440 143 #define regUMCCH1_0_UMC_CONFIG_BASE_IDX 0 144 #define regUMCCH1_0_EccCtrl 0x0453 145 #define regUMCCH1_0_EccCtrl_BASE_IDX 0 146 #define regUMCCH1_0_UmcLocalCap 0x0706 147 #define regUMCCH1_0_UmcLocalCap_BASE_IDX 0 148 #define regUMCCH1_0_EccErrCntSel 0x0728 149 #define regUMCCH1_0_EccErrCntSel_BASE_IDX 0 150 #define regUMCCH1_0_EccErrCnt 0x0729 151 #define regUMCCH1_0_EccErrCnt_BASE_IDX 0 152 #define regUMCCH1_0_PerfMonCtlClk 0x0740 153 #define regUMCCH1_0_PerfMonCtlClk_BASE_IDX 0 154 #define regUMCCH1_0_PerfMonCtrClk_Lo 0x0741 155 #define regUMCCH1_0_PerfMonCtrClk_Lo_BASE_IDX 0 156 #define regUMCCH1_0_PerfMonCtrClk_Hi 0x0742 157 #define regUMCCH1_0_PerfMonCtrClk_Hi_BASE_IDX 0 158 #define regUMCCH1_0_PerfMonCtl1 0x0744 159 #define regUMCCH1_0_PerfMonCtl1_BASE_IDX 0 160 #define regUMCCH1_0_PerfMonCtr1_Lo 0x0745 161 #define regUMCCH1_0_PerfMonCtr1_Lo_BASE_IDX 0 162 #define regUMCCH1_0_PerfMonCtr1_Hi 0x0746 163 #define regUMCCH1_0_PerfMonCtr1_Hi_BASE_IDX 0 164 #define regUMCCH1_0_PerfMonCtl2 0x0747 165 #define regUMCCH1_0_PerfMonCtl2_BASE_IDX 0 166 #define regUMCCH1_0_PerfMonCtr2_Lo 0x0748 167 #define regUMCCH1_0_PerfMonCtr2_Lo_BASE_IDX 0 168 #define regUMCCH1_0_PerfMonCtr2_Hi 0x0749 169 #define regUMCCH1_0_PerfMonCtr2_Hi_BASE_IDX 0 170 #define regUMCCH1_0_PerfMonCtl3 0x074a 171 #define regUMCCH1_0_PerfMonCtl3_BASE_IDX 0 172 #define regUMCCH1_0_PerfMonCtr3_Lo 0x074b 173 #define regUMCCH1_0_PerfMonCtr3_Lo_BASE_IDX 0 174 #define regUMCCH1_0_PerfMonCtr3_Hi 0x074c 175 #define regUMCCH1_0_PerfMonCtr3_Hi_BASE_IDX 0 176 #define regUMCCH1_0_PerfMonCtl4 0x074d 177 #define regUMCCH1_0_PerfMonCtl4_BASE_IDX 0 178 #define regUMCCH1_0_PerfMonCtr4_Lo 0x074e 179 #define regUMCCH1_0_PerfMonCtr4_Lo_BASE_IDX 0 180 #define regUMCCH1_0_PerfMonCtr4_Hi 0x074f 181 #define regUMCCH1_0_PerfMonCtr4_Hi_BASE_IDX 0 182 #define regUMCCH1_0_PerfMonCtl5 0x0750 183 #define regUMCCH1_0_PerfMonCtl5_BASE_IDX 0 184 #define regUMCCH1_0_PerfMonCtr5_Lo 0x0751 185 #define regUMCCH1_0_PerfMonCtr5_Lo_BASE_IDX 0 186 #define regUMCCH1_0_PerfMonCtr5_Hi 0x0752 187 #define regUMCCH1_0_PerfMonCtr5_Hi_BASE_IDX 0 188 #define regUMCCH1_0_PerfMonCtl6 0x0753 189 #define regUMCCH1_0_PerfMonCtl6_BASE_IDX 0 190 #define regUMCCH1_0_PerfMonCtr6_Lo 0x0754 191 #define regUMCCH1_0_PerfMonCtr6_Lo_BASE_IDX 0 192 #define regUMCCH1_0_PerfMonCtr6_Hi 0x0755 193 #define regUMCCH1_0_PerfMonCtr6_Hi_BASE_IDX 0 194 #define regUMCCH1_0_PerfMonCtl7 0x0756 195 #define regUMCCH1_0_PerfMonCtl7_BASE_IDX 0 196 #define regUMCCH1_0_PerfMonCtr7_Lo 0x0757 197 #define regUMCCH1_0_PerfMonCtr7_Lo_BASE_IDX 0 198 #define regUMCCH1_0_PerfMonCtr7_Hi 0x0758 199 #define regUMCCH1_0_PerfMonCtr7_Hi_BASE_IDX 0 200 #define regUMCCH1_0_PerfMonCtl8 0x0759 201 #define regUMCCH1_0_PerfMonCtl8_BASE_IDX 0 202 #define regUMCCH1_0_PerfMonCtr8_Lo 0x075a 203 #define regUMCCH1_0_PerfMonCtr8_Lo_BASE_IDX 0 204 #define regUMCCH1_0_PerfMonCtr8_Hi 0x075b 205 #define regUMCCH1_0_PerfMonCtr8_Hi_BASE_IDX 0 206 207 208 // addressBlock: umc_w_phy_umc0_umcch2_umcchdec 209 // base address: 0x52000 210 #define regUMCCH2_0_BaseAddrCS0 0x0800 211 #define regUMCCH2_0_BaseAddrCS0_BASE_IDX 0 212 #define regUMCCH2_0_AddrMaskCS01 0x0808 213 #define regUMCCH2_0_AddrMaskCS01_BASE_IDX 0 214 #define regUMCCH2_0_AddrSelCS01 0x0810 215 #define regUMCCH2_0_AddrSelCS01_BASE_IDX 0 216 #define regUMCCH2_0_AddrHashBank0 0x0832 217 #define regUMCCH2_0_AddrHashBank0_BASE_IDX 0 218 #define regUMCCH2_0_AddrHashBank1 0x0833 219 #define regUMCCH2_0_AddrHashBank1_BASE_IDX 0 220 #define regUMCCH2_0_AddrHashBank2 0x0834 221 #define regUMCCH2_0_AddrHashBank2_BASE_IDX 0 222 #define regUMCCH2_0_AddrHashBank3 0x0835 223 #define regUMCCH2_0_AddrHashBank3_BASE_IDX 0 224 #define regUMCCH2_0_AddrHashBank4 0x0836 225 #define regUMCCH2_0_AddrHashBank4_BASE_IDX 0 226 #define regUMCCH2_0_AddrHashBank5 0x0837 227 #define regUMCCH2_0_AddrHashBank5_BASE_IDX 0 228 #define regUMCCH2_0_UMC_CONFIG 0x0840 229 #define regUMCCH2_0_UMC_CONFIG_BASE_IDX 0 230 #define regUMCCH2_0_EccCtrl 0x0853 231 #define regUMCCH2_0_EccCtrl_BASE_IDX 0 232 #define regUMCCH2_0_UmcLocalCap 0x0b06 233 #define regUMCCH2_0_UmcLocalCap_BASE_IDX 0 234 #define regUMCCH2_0_EccErrCntSel 0x0b28 235 #define regUMCCH2_0_EccErrCntSel_BASE_IDX 0 236 #define regUMCCH2_0_EccErrCnt 0x0b29 237 #define regUMCCH2_0_EccErrCnt_BASE_IDX 0 238 #define regUMCCH2_0_PerfMonCtlClk 0x0b40 239 #define regUMCCH2_0_PerfMonCtlClk_BASE_IDX 0 240 #define regUMCCH2_0_PerfMonCtrClk_Lo 0x0b41 241 #define regUMCCH2_0_PerfMonCtrClk_Lo_BASE_IDX 0 242 #define regUMCCH2_0_PerfMonCtrClk_Hi 0x0b42 243 #define regUMCCH2_0_PerfMonCtrClk_Hi_BASE_IDX 0 244 #define regUMCCH2_0_PerfMonCtl1 0x0b44 245 #define regUMCCH2_0_PerfMonCtl1_BASE_IDX 0 246 #define regUMCCH2_0_PerfMonCtr1_Lo 0x0b45 247 #define regUMCCH2_0_PerfMonCtr1_Lo_BASE_IDX 0 248 #define regUMCCH2_0_PerfMonCtr1_Hi 0x0b46 249 #define regUMCCH2_0_PerfMonCtr1_Hi_BASE_IDX 0 250 #define regUMCCH2_0_PerfMonCtl2 0x0b47 251 #define regUMCCH2_0_PerfMonCtl2_BASE_IDX 0 252 #define regUMCCH2_0_PerfMonCtr2_Lo 0x0b48 253 #define regUMCCH2_0_PerfMonCtr2_Lo_BASE_IDX 0 254 #define regUMCCH2_0_PerfMonCtr2_Hi 0x0b49 255 #define regUMCCH2_0_PerfMonCtr2_Hi_BASE_IDX 0 256 #define regUMCCH2_0_PerfMonCtl3 0x0b4a 257 #define regUMCCH2_0_PerfMonCtl3_BASE_IDX 0 258 #define regUMCCH2_0_PerfMonCtr3_Lo 0x0b4b 259 #define regUMCCH2_0_PerfMonCtr3_Lo_BASE_IDX 0 260 #define regUMCCH2_0_PerfMonCtr3_Hi 0x0b4c 261 #define regUMCCH2_0_PerfMonCtr3_Hi_BASE_IDX 0 262 #define regUMCCH2_0_PerfMonCtl4 0x0b4d 263 #define regUMCCH2_0_PerfMonCtl4_BASE_IDX 0 264 #define regUMCCH2_0_PerfMonCtr4_Lo 0x0b4e 265 #define regUMCCH2_0_PerfMonCtr4_Lo_BASE_IDX 0 266 #define regUMCCH2_0_PerfMonCtr4_Hi 0x0b4f 267 #define regUMCCH2_0_PerfMonCtr4_Hi_BASE_IDX 0 268 #define regUMCCH2_0_PerfMonCtl5 0x0b50 269 #define regUMCCH2_0_PerfMonCtl5_BASE_IDX 0 270 #define regUMCCH2_0_PerfMonCtr5_Lo 0x0b51 271 #define regUMCCH2_0_PerfMonCtr5_Lo_BASE_IDX 0 272 #define regUMCCH2_0_PerfMonCtr5_Hi 0x0b52 273 #define regUMCCH2_0_PerfMonCtr5_Hi_BASE_IDX 0 274 #define regUMCCH2_0_PerfMonCtl6 0x0b53 275 #define regUMCCH2_0_PerfMonCtl6_BASE_IDX 0 276 #define regUMCCH2_0_PerfMonCtr6_Lo 0x0b54 277 #define regUMCCH2_0_PerfMonCtr6_Lo_BASE_IDX 0 278 #define regUMCCH2_0_PerfMonCtr6_Hi 0x0b55 279 #define regUMCCH2_0_PerfMonCtr6_Hi_BASE_IDX 0 280 #define regUMCCH2_0_PerfMonCtl7 0x0b56 281 #define regUMCCH2_0_PerfMonCtl7_BASE_IDX 0 282 #define regUMCCH2_0_PerfMonCtr7_Lo 0x0b57 283 #define regUMCCH2_0_PerfMonCtr7_Lo_BASE_IDX 0 284 #define regUMCCH2_0_PerfMonCtr7_Hi 0x0b58 285 #define regUMCCH2_0_PerfMonCtr7_Hi_BASE_IDX 0 286 #define regUMCCH2_0_PerfMonCtl8 0x0b59 287 #define regUMCCH2_0_PerfMonCtl8_BASE_IDX 0 288 #define regUMCCH2_0_PerfMonCtr8_Lo 0x0b5a 289 #define regUMCCH2_0_PerfMonCtr8_Lo_BASE_IDX 0 290 #define regUMCCH2_0_PerfMonCtr8_Hi 0x0b5b 291 #define regUMCCH2_0_PerfMonCtr8_Hi_BASE_IDX 0 292 293 294 // addressBlock: umc_w_phy_umc0_umcch3_umcchdec 295 // base address: 0x53000 296 #define regUMCCH3_0_BaseAddrCS0 0x0c00 297 #define regUMCCH3_0_BaseAddrCS0_BASE_IDX 0 298 #define regUMCCH3_0_AddrMaskCS01 0x0c08 299 #define regUMCCH3_0_AddrMaskCS01_BASE_IDX 0 300 #define regUMCCH3_0_AddrSelCS01 0x0c10 301 #define regUMCCH3_0_AddrSelCS01_BASE_IDX 0 302 #define regUMCCH3_0_AddrHashBank0 0x0c32 303 #define regUMCCH3_0_AddrHashBank0_BASE_IDX 0 304 #define regUMCCH3_0_AddrHashBank1 0x0c33 305 #define regUMCCH3_0_AddrHashBank1_BASE_IDX 0 306 #define regUMCCH3_0_AddrHashBank2 0x0c34 307 #define regUMCCH3_0_AddrHashBank2_BASE_IDX 0 308 #define regUMCCH3_0_AddrHashBank3 0x0c35 309 #define regUMCCH3_0_AddrHashBank3_BASE_IDX 0 310 #define regUMCCH3_0_AddrHashBank4 0x0c36 311 #define regUMCCH3_0_AddrHashBank4_BASE_IDX 0 312 #define regUMCCH3_0_AddrHashBank5 0x0c37 313 #define regUMCCH3_0_AddrHashBank5_BASE_IDX 0 314 #define regUMCCH3_0_UMC_CONFIG 0x0c40 315 #define regUMCCH3_0_UMC_CONFIG_BASE_IDX 0 316 #define regUMCCH3_0_EccCtrl 0x0c53 317 #define regUMCCH3_0_EccCtrl_BASE_IDX 0 318 #define regUMCCH3_0_UmcLocalCap 0x0f06 319 #define regUMCCH3_0_UmcLocalCap_BASE_IDX 0 320 #define regUMCCH3_0_EccErrCntSel 0x0f28 321 #define regUMCCH3_0_EccErrCntSel_BASE_IDX 0 322 #define regUMCCH3_0_EccErrCnt 0x0f29 323 #define regUMCCH3_0_EccErrCnt_BASE_IDX 0 324 #define regUMCCH3_0_PerfMonCtlClk 0x0f40 325 #define regUMCCH3_0_PerfMonCtlClk_BASE_IDX 0 326 #define regUMCCH3_0_PerfMonCtrClk_Lo 0x0f41 327 #define regUMCCH3_0_PerfMonCtrClk_Lo_BASE_IDX 0 328 #define regUMCCH3_0_PerfMonCtrClk_Hi 0x0f42 329 #define regUMCCH3_0_PerfMonCtrClk_Hi_BASE_IDX 0 330 #define regUMCCH3_0_PerfMonCtl1 0x0f44 331 #define regUMCCH3_0_PerfMonCtl1_BASE_IDX 0 332 #define regUMCCH3_0_PerfMonCtr1_Lo 0x0f45 333 #define regUMCCH3_0_PerfMonCtr1_Lo_BASE_IDX 0 334 #define regUMCCH3_0_PerfMonCtr1_Hi 0x0f46 335 #define regUMCCH3_0_PerfMonCtr1_Hi_BASE_IDX 0 336 #define regUMCCH3_0_PerfMonCtl2 0x0f47 337 #define regUMCCH3_0_PerfMonCtl2_BASE_IDX 0 338 #define regUMCCH3_0_PerfMonCtr2_Lo 0x0f48 339 #define regUMCCH3_0_PerfMonCtr2_Lo_BASE_IDX 0 340 #define regUMCCH3_0_PerfMonCtr2_Hi 0x0f49 341 #define regUMCCH3_0_PerfMonCtr2_Hi_BASE_IDX 0 342 #define regUMCCH3_0_PerfMonCtl3 0x0f4a 343 #define regUMCCH3_0_PerfMonCtl3_BASE_IDX 0 344 #define regUMCCH3_0_PerfMonCtr3_Lo 0x0f4b 345 #define regUMCCH3_0_PerfMonCtr3_Lo_BASE_IDX 0 346 #define regUMCCH3_0_PerfMonCtr3_Hi 0x0f4c 347 #define regUMCCH3_0_PerfMonCtr3_Hi_BASE_IDX 0 348 #define regUMCCH3_0_PerfMonCtl4 0x0f4d 349 #define regUMCCH3_0_PerfMonCtl4_BASE_IDX 0 350 #define regUMCCH3_0_PerfMonCtr4_Lo 0x0f4e 351 #define regUMCCH3_0_PerfMonCtr4_Lo_BASE_IDX 0 352 #define regUMCCH3_0_PerfMonCtr4_Hi 0x0f4f 353 #define regUMCCH3_0_PerfMonCtr4_Hi_BASE_IDX 0 354 #define regUMCCH3_0_PerfMonCtl5 0x0f50 355 #define regUMCCH3_0_PerfMonCtl5_BASE_IDX 0 356 #define regUMCCH3_0_PerfMonCtr5_Lo 0x0f51 357 #define regUMCCH3_0_PerfMonCtr5_Lo_BASE_IDX 0 358 #define regUMCCH3_0_PerfMonCtr5_Hi 0x0f52 359 #define regUMCCH3_0_PerfMonCtr5_Hi_BASE_IDX 0 360 #define regUMCCH3_0_PerfMonCtl6 0x0f53 361 #define regUMCCH3_0_PerfMonCtl6_BASE_IDX 0 362 #define regUMCCH3_0_PerfMonCtr6_Lo 0x0f54 363 #define regUMCCH3_0_PerfMonCtr6_Lo_BASE_IDX 0 364 #define regUMCCH3_0_PerfMonCtr6_Hi 0x0f55 365 #define regUMCCH3_0_PerfMonCtr6_Hi_BASE_IDX 0 366 #define regUMCCH3_0_PerfMonCtl7 0x0f56 367 #define regUMCCH3_0_PerfMonCtl7_BASE_IDX 0 368 #define regUMCCH3_0_PerfMonCtr7_Lo 0x0f57 369 #define regUMCCH3_0_PerfMonCtr7_Lo_BASE_IDX 0 370 #define regUMCCH3_0_PerfMonCtr7_Hi 0x0f58 371 #define regUMCCH3_0_PerfMonCtr7_Hi_BASE_IDX 0 372 #define regUMCCH3_0_PerfMonCtl8 0x0f59 373 #define regUMCCH3_0_PerfMonCtl8_BASE_IDX 0 374 #define regUMCCH3_0_PerfMonCtr8_Lo 0x0f5a 375 #define regUMCCH3_0_PerfMonCtr8_Lo_BASE_IDX 0 376 #define regUMCCH3_0_PerfMonCtr8_Hi 0x0f5b 377 #define regUMCCH3_0_PerfMonCtr8_Hi_BASE_IDX 0 378 379 380 // addressBlock: umc_w_phy_umc0_umcch4_umcchdec 381 // base address: 0x150000 382 #define regUMCCH4_0_BaseAddrCS0 0x0000 383 #define regUMCCH4_0_BaseAddrCS0_BASE_IDX 1 384 #define regUMCCH4_0_AddrMaskCS01 0x0008 385 #define regUMCCH4_0_AddrMaskCS01_BASE_IDX 1 386 #define regUMCCH4_0_AddrSelCS01 0x0010 387 #define regUMCCH4_0_AddrSelCS01_BASE_IDX 1 388 #define regUMCCH4_0_AddrHashBank0 0x0032 389 #define regUMCCH4_0_AddrHashBank0_BASE_IDX 1 390 #define regUMCCH4_0_AddrHashBank1 0x0033 391 #define regUMCCH4_0_AddrHashBank1_BASE_IDX 1 392 #define regUMCCH4_0_AddrHashBank2 0x0034 393 #define regUMCCH4_0_AddrHashBank2_BASE_IDX 1 394 #define regUMCCH4_0_AddrHashBank3 0x0035 395 #define regUMCCH4_0_AddrHashBank3_BASE_IDX 1 396 #define regUMCCH4_0_AddrHashBank4 0x0036 397 #define regUMCCH4_0_AddrHashBank4_BASE_IDX 1 398 #define regUMCCH4_0_AddrHashBank5 0x0037 399 #define regUMCCH4_0_AddrHashBank5_BASE_IDX 1 400 #define regUMCCH4_0_EccErrCntSel 0x0328 401 #define regUMCCH4_0_EccErrCntSel_BASE_IDX 1 402 #define regUMCCH4_0_EccErrCnt 0x0329 403 #define regUMCCH4_0_EccErrCnt_BASE_IDX 1 404 #define regUMCCH4_0_PerfMonCtlClk 0x0340 405 #define regUMCCH4_0_PerfMonCtlClk_BASE_IDX 1 406 #define regUMCCH4_0_PerfMonCtrClk_Lo 0x0341 407 #define regUMCCH4_0_PerfMonCtrClk_Lo_BASE_IDX 1 408 #define regUMCCH4_0_PerfMonCtrClk_Hi 0x0342 409 #define regUMCCH4_0_PerfMonCtrClk_Hi_BASE_IDX 1 410 #define regUMCCH4_0_PerfMonCtl1 0x0344 411 #define regUMCCH4_0_PerfMonCtl1_BASE_IDX 1 412 #define regUMCCH4_0_PerfMonCtr1_Lo 0x0345 413 #define regUMCCH4_0_PerfMonCtr1_Lo_BASE_IDX 1 414 #define regUMCCH4_0_PerfMonCtr1_Hi 0x0346 415 #define regUMCCH4_0_PerfMonCtr1_Hi_BASE_IDX 1 416 #define regUMCCH4_0_PerfMonCtl2 0x0347 417 #define regUMCCH4_0_PerfMonCtl2_BASE_IDX 1 418 #define regUMCCH4_0_PerfMonCtr2_Lo 0x0348 419 #define regUMCCH4_0_PerfMonCtr2_Lo_BASE_IDX 1 420 #define regUMCCH4_0_PerfMonCtr2_Hi 0x0349 421 #define regUMCCH4_0_PerfMonCtr2_Hi_BASE_IDX 1 422 #define regUMCCH4_0_PerfMonCtl3 0x034a 423 #define regUMCCH4_0_PerfMonCtl3_BASE_IDX 1 424 #define regUMCCH4_0_PerfMonCtr3_Lo 0x034b 425 #define regUMCCH4_0_PerfMonCtr3_Lo_BASE_IDX 1 426 #define regUMCCH4_0_PerfMonCtr3_Hi 0x034c 427 #define regUMCCH4_0_PerfMonCtr3_Hi_BASE_IDX 1 428 #define regUMCCH4_0_PerfMonCtl4 0x034d 429 #define regUMCCH4_0_PerfMonCtl4_BASE_IDX 1 430 #define regUMCCH4_0_PerfMonCtr4_Lo 0x034e 431 #define regUMCCH4_0_PerfMonCtr4_Lo_BASE_IDX 1 432 #define regUMCCH4_0_PerfMonCtr4_Hi 0x034f 433 #define regUMCCH4_0_PerfMonCtr4_Hi_BASE_IDX 1 434 #define regUMCCH4_0_PerfMonCtl5 0x0350 435 #define regUMCCH4_0_PerfMonCtl5_BASE_IDX 1 436 #define regUMCCH4_0_PerfMonCtr5_Lo 0x0351 437 #define regUMCCH4_0_PerfMonCtr5_Lo_BASE_IDX 1 438 #define regUMCCH4_0_PerfMonCtr5_Hi 0x0352 439 #define regUMCCH4_0_PerfMonCtr5_Hi_BASE_IDX 1 440 #define regUMCCH4_0_PerfMonCtl6 0x0353 441 #define regUMCCH4_0_PerfMonCtl6_BASE_IDX 1 442 #define regUMCCH4_0_PerfMonCtr6_Lo 0x0354 443 #define regUMCCH4_0_PerfMonCtr6_Lo_BASE_IDX 1 444 #define regUMCCH4_0_PerfMonCtr6_Hi 0x0355 445 #define regUMCCH4_0_PerfMonCtr6_Hi_BASE_IDX 1 446 #define regUMCCH4_0_PerfMonCtl7 0x0356 447 #define regUMCCH4_0_PerfMonCtl7_BASE_IDX 1 448 #define regUMCCH4_0_PerfMonCtr7_Lo 0x0357 449 #define regUMCCH4_0_PerfMonCtr7_Lo_BASE_IDX 1 450 #define regUMCCH4_0_PerfMonCtr7_Hi 0x0358 451 #define regUMCCH4_0_PerfMonCtr7_Hi_BASE_IDX 1 452 #define regUMCCH4_0_PerfMonCtl8 0x0359 453 #define regUMCCH4_0_PerfMonCtl8_BASE_IDX 1 454 #define regUMCCH4_0_PerfMonCtr8_Lo 0x035a 455 #define regUMCCH4_0_PerfMonCtr8_Lo_BASE_IDX 1 456 #define regUMCCH4_0_PerfMonCtr8_Hi 0x035b 457 #define regUMCCH4_0_PerfMonCtr8_Hi_BASE_IDX 1 458 459 460 // addressBlock: umc_w_phy_umc0_umcch5_umcchdec 461 // base address: 0x151000 462 #define regUMCCH5_0_BaseAddrCS0 0x0400 463 #define regUMCCH5_0_BaseAddrCS0_BASE_IDX 1 464 #define regUMCCH5_0_AddrMaskCS01 0x0408 465 #define regUMCCH5_0_AddrMaskCS01_BASE_IDX 1 466 #define regUMCCH5_0_AddrSelCS01 0x0410 467 #define regUMCCH5_0_AddrSelCS01_BASE_IDX 1 468 #define regUMCCH5_0_AddrHashBank0 0x0432 469 #define regUMCCH5_0_AddrHashBank0_BASE_IDX 1 470 #define regUMCCH5_0_AddrHashBank1 0x0433 471 #define regUMCCH5_0_AddrHashBank1_BASE_IDX 1 472 #define regUMCCH5_0_AddrHashBank2 0x0434 473 #define regUMCCH5_0_AddrHashBank2_BASE_IDX 1 474 #define regUMCCH5_0_AddrHashBank3 0x0435 475 #define regUMCCH5_0_AddrHashBank3_BASE_IDX 1 476 #define regUMCCH5_0_AddrHashBank4 0x0436 477 #define regUMCCH5_0_AddrHashBank4_BASE_IDX 1 478 #define regUMCCH5_0_AddrHashBank5 0x0437 479 #define regUMCCH5_0_AddrHashBank5_BASE_IDX 1 480 #define regUMCCH5_0_EccErrCntSel 0x0728 481 #define regUMCCH5_0_EccErrCntSel_BASE_IDX 1 482 #define regUMCCH5_0_EccErrCnt 0x0729 483 #define regUMCCH5_0_EccErrCnt_BASE_IDX 1 484 #define regUMCCH5_0_PerfMonCtlClk 0x0740 485 #define regUMCCH5_0_PerfMonCtlClk_BASE_IDX 1 486 #define regUMCCH5_0_PerfMonCtrClk_Lo 0x0741 487 #define regUMCCH5_0_PerfMonCtrClk_Lo_BASE_IDX 1 488 #define regUMCCH5_0_PerfMonCtrClk_Hi 0x0742 489 #define regUMCCH5_0_PerfMonCtrClk_Hi_BASE_IDX 1 490 #define regUMCCH5_0_PerfMonCtl1 0x0744 491 #define regUMCCH5_0_PerfMonCtl1_BASE_IDX 1 492 #define regUMCCH5_0_PerfMonCtr1_Lo 0x0745 493 #define regUMCCH5_0_PerfMonCtr1_Lo_BASE_IDX 1 494 #define regUMCCH5_0_PerfMonCtr1_Hi 0x0746 495 #define regUMCCH5_0_PerfMonCtr1_Hi_BASE_IDX 1 496 #define regUMCCH5_0_PerfMonCtl2 0x0747 497 #define regUMCCH5_0_PerfMonCtl2_BASE_IDX 1 498 #define regUMCCH5_0_PerfMonCtr2_Lo 0x0748 499 #define regUMCCH5_0_PerfMonCtr2_Lo_BASE_IDX 1 500 #define regUMCCH5_0_PerfMonCtr2_Hi 0x0749 501 #define regUMCCH5_0_PerfMonCtr2_Hi_BASE_IDX 1 502 #define regUMCCH5_0_PerfMonCtl3 0x074a 503 #define regUMCCH5_0_PerfMonCtl3_BASE_IDX 1 504 #define regUMCCH5_0_PerfMonCtr3_Lo 0x074b 505 #define regUMCCH5_0_PerfMonCtr3_Lo_BASE_IDX 1 506 #define regUMCCH5_0_PerfMonCtr3_Hi 0x074c 507 #define regUMCCH5_0_PerfMonCtr3_Hi_BASE_IDX 1 508 #define regUMCCH5_0_PerfMonCtl4 0x074d 509 #define regUMCCH5_0_PerfMonCtl4_BASE_IDX 1 510 #define regUMCCH5_0_PerfMonCtr4_Lo 0x074e 511 #define regUMCCH5_0_PerfMonCtr4_Lo_BASE_IDX 1 512 #define regUMCCH5_0_PerfMonCtr4_Hi 0x074f 513 #define regUMCCH5_0_PerfMonCtr4_Hi_BASE_IDX 1 514 #define regUMCCH5_0_PerfMonCtl5 0x0750 515 #define regUMCCH5_0_PerfMonCtl5_BASE_IDX 1 516 #define regUMCCH5_0_PerfMonCtr5_Lo 0x0751 517 #define regUMCCH5_0_PerfMonCtr5_Lo_BASE_IDX 1 518 #define regUMCCH5_0_PerfMonCtr5_Hi 0x0752 519 #define regUMCCH5_0_PerfMonCtr5_Hi_BASE_IDX 1 520 #define regUMCCH5_0_PerfMonCtl6 0x0753 521 #define regUMCCH5_0_PerfMonCtl6_BASE_IDX 1 522 #define regUMCCH5_0_PerfMonCtr6_Lo 0x0754 523 #define regUMCCH5_0_PerfMonCtr6_Lo_BASE_IDX 1 524 #define regUMCCH5_0_PerfMonCtr6_Hi 0x0755 525 #define regUMCCH5_0_PerfMonCtr6_Hi_BASE_IDX 1 526 #define regUMCCH5_0_PerfMonCtl7 0x0756 527 #define regUMCCH5_0_PerfMonCtl7_BASE_IDX 1 528 #define regUMCCH5_0_PerfMonCtr7_Lo 0x0757 529 #define regUMCCH5_0_PerfMonCtr7_Lo_BASE_IDX 1 530 #define regUMCCH5_0_PerfMonCtr7_Hi 0x0758 531 #define regUMCCH5_0_PerfMonCtr7_Hi_BASE_IDX 1 532 #define regUMCCH5_0_PerfMonCtl8 0x0759 533 #define regUMCCH5_0_PerfMonCtl8_BASE_IDX 1 534 #define regUMCCH5_0_PerfMonCtr8_Lo 0x075a 535 #define regUMCCH5_0_PerfMonCtr8_Lo_BASE_IDX 1 536 #define regUMCCH5_0_PerfMonCtr8_Hi 0x075b 537 #define regUMCCH5_0_PerfMonCtr8_Hi_BASE_IDX 1 538 539 540 // addressBlock: umc_w_phy_umc0_umcch6_umcchdec 541 // base address: 0x152000 542 #define regUMCCH6_0_BaseAddrCS0 0x0800 543 #define regUMCCH6_0_BaseAddrCS0_BASE_IDX 1 544 #define regUMCCH6_0_AddrMaskCS01 0x0808 545 #define regUMCCH6_0_AddrMaskCS01_BASE_IDX 1 546 #define regUMCCH6_0_AddrSelCS01 0x0810 547 #define regUMCCH6_0_AddrSelCS01_BASE_IDX 1 548 #define regUMCCH6_0_AddrHashBank0 0x0832 549 #define regUMCCH6_0_AddrHashBank0_BASE_IDX 1 550 #define regUMCCH6_0_AddrHashBank1 0x0833 551 #define regUMCCH6_0_AddrHashBank1_BASE_IDX 1 552 #define regUMCCH6_0_AddrHashBank2 0x0834 553 #define regUMCCH6_0_AddrHashBank2_BASE_IDX 1 554 #define regUMCCH6_0_AddrHashBank3 0x0835 555 #define regUMCCH6_0_AddrHashBank3_BASE_IDX 1 556 #define regUMCCH6_0_AddrHashBank4 0x0836 557 #define regUMCCH6_0_AddrHashBank4_BASE_IDX 1 558 #define regUMCCH6_0_AddrHashBank5 0x0837 559 #define regUMCCH6_0_AddrHashBank5_BASE_IDX 1 560 #define regUMCCH6_0_EccErrCntSel 0x0b28 561 #define regUMCCH6_0_EccErrCntSel_BASE_IDX 1 562 #define regUMCCH6_0_EccErrCnt 0x0b29 563 #define regUMCCH6_0_EccErrCnt_BASE_IDX 1 564 #define regUMCCH6_0_PerfMonCtlClk 0x0b40 565 #define regUMCCH6_0_PerfMonCtlClk_BASE_IDX 1 566 #define regUMCCH6_0_PerfMonCtrClk_Lo 0x0b41 567 #define regUMCCH6_0_PerfMonCtrClk_Lo_BASE_IDX 1 568 #define regUMCCH6_0_PerfMonCtrClk_Hi 0x0b42 569 #define regUMCCH6_0_PerfMonCtrClk_Hi_BASE_IDX 1 570 #define regUMCCH6_0_PerfMonCtl1 0x0b44 571 #define regUMCCH6_0_PerfMonCtl1_BASE_IDX 1 572 #define regUMCCH6_0_PerfMonCtr1_Lo 0x0b45 573 #define regUMCCH6_0_PerfMonCtr1_Lo_BASE_IDX 1 574 #define regUMCCH6_0_PerfMonCtr1_Hi 0x0b46 575 #define regUMCCH6_0_PerfMonCtr1_Hi_BASE_IDX 1 576 #define regUMCCH6_0_PerfMonCtl2 0x0b47 577 #define regUMCCH6_0_PerfMonCtl2_BASE_IDX 1 578 #define regUMCCH6_0_PerfMonCtr2_Lo 0x0b48 579 #define regUMCCH6_0_PerfMonCtr2_Lo_BASE_IDX 1 580 #define regUMCCH6_0_PerfMonCtr2_Hi 0x0b49 581 #define regUMCCH6_0_PerfMonCtr2_Hi_BASE_IDX 1 582 #define regUMCCH6_0_PerfMonCtl3 0x0b4a 583 #define regUMCCH6_0_PerfMonCtl3_BASE_IDX 1 584 #define regUMCCH6_0_PerfMonCtr3_Lo 0x0b4b 585 #define regUMCCH6_0_PerfMonCtr3_Lo_BASE_IDX 1 586 #define regUMCCH6_0_PerfMonCtr3_Hi 0x0b4c 587 #define regUMCCH6_0_PerfMonCtr3_Hi_BASE_IDX 1 588 #define regUMCCH6_0_PerfMonCtl4 0x0b4d 589 #define regUMCCH6_0_PerfMonCtl4_BASE_IDX 1 590 #define regUMCCH6_0_PerfMonCtr4_Lo 0x0b4e 591 #define regUMCCH6_0_PerfMonCtr4_Lo_BASE_IDX 1 592 #define regUMCCH6_0_PerfMonCtr4_Hi 0x0b4f 593 #define regUMCCH6_0_PerfMonCtr4_Hi_BASE_IDX 1 594 #define regUMCCH6_0_PerfMonCtl5 0x0b50 595 #define regUMCCH6_0_PerfMonCtl5_BASE_IDX 1 596 #define regUMCCH6_0_PerfMonCtr5_Lo 0x0b51 597 #define regUMCCH6_0_PerfMonCtr5_Lo_BASE_IDX 1 598 #define regUMCCH6_0_PerfMonCtr5_Hi 0x0b52 599 #define regUMCCH6_0_PerfMonCtr5_Hi_BASE_IDX 1 600 #define regUMCCH6_0_PerfMonCtl6 0x0b53 601 #define regUMCCH6_0_PerfMonCtl6_BASE_IDX 1 602 #define regUMCCH6_0_PerfMonCtr6_Lo 0x0b54 603 #define regUMCCH6_0_PerfMonCtr6_Lo_BASE_IDX 1 604 #define regUMCCH6_0_PerfMonCtr6_Hi 0x0b55 605 #define regUMCCH6_0_PerfMonCtr6_Hi_BASE_IDX 1 606 #define regUMCCH6_0_PerfMonCtl7 0x0b56 607 #define regUMCCH6_0_PerfMonCtl7_BASE_IDX 1 608 #define regUMCCH6_0_PerfMonCtr7_Lo 0x0b57 609 #define regUMCCH6_0_PerfMonCtr7_Lo_BASE_IDX 1 610 #define regUMCCH6_0_PerfMonCtr7_Hi 0x0b58 611 #define regUMCCH6_0_PerfMonCtr7_Hi_BASE_IDX 1 612 #define regUMCCH6_0_PerfMonCtl8 0x0b59 613 #define regUMCCH6_0_PerfMonCtl8_BASE_IDX 1 614 #define regUMCCH6_0_PerfMonCtr8_Lo 0x0b5a 615 #define regUMCCH6_0_PerfMonCtr8_Lo_BASE_IDX 1 616 #define regUMCCH6_0_PerfMonCtr8_Hi 0x0b5b 617 #define regUMCCH6_0_PerfMonCtr8_Hi_BASE_IDX 1 618 619 620 // addressBlock: umc_w_phy_umc0_umcch7_umcchdec 621 // base address: 0x153000 622 #define regUMCCH7_0_BaseAddrCS0 0x0c00 623 #define regUMCCH7_0_BaseAddrCS0_BASE_IDX 1 624 #define regUMCCH7_0_AddrMaskCS01 0x0c08 625 #define regUMCCH7_0_AddrMaskCS01_BASE_IDX 1 626 #define regUMCCH7_0_AddrSelCS01 0x0c10 627 #define regUMCCH7_0_AddrSelCS01_BASE_IDX 1 628 #define regUMCCH7_0_AddrHashBank0 0x0c32 629 #define regUMCCH7_0_AddrHashBank0_BASE_IDX 1 630 #define regUMCCH7_0_AddrHashBank1 0x0c33 631 #define regUMCCH7_0_AddrHashBank1_BASE_IDX 1 632 #define regUMCCH7_0_AddrHashBank2 0x0c34 633 #define regUMCCH7_0_AddrHashBank2_BASE_IDX 1 634 #define regUMCCH7_0_AddrHashBank3 0x0c35 635 #define regUMCCH7_0_AddrHashBank3_BASE_IDX 1 636 #define regUMCCH7_0_AddrHashBank4 0x0c36 637 #define regUMCCH7_0_AddrHashBank4_BASE_IDX 1 638 #define regUMCCH7_0_AddrHashBank5 0x0c37 639 #define regUMCCH7_0_AddrHashBank5_BASE_IDX 1 640 #define regUMCCH7_0_EccErrCntSel 0x0f28 641 #define regUMCCH7_0_EccErrCntSel_BASE_IDX 1 642 #define regUMCCH7_0_EccErrCnt 0x0f29 643 #define regUMCCH7_0_EccErrCnt_BASE_IDX 1 644 #define regUMCCH7_0_PerfMonCtlClk 0x0f40 645 #define regUMCCH7_0_PerfMonCtlClk_BASE_IDX 1 646 #define regUMCCH7_0_PerfMonCtrClk_Lo 0x0f41 647 #define regUMCCH7_0_PerfMonCtrClk_Lo_BASE_IDX 1 648 #define regUMCCH7_0_PerfMonCtrClk_Hi 0x0f42 649 #define regUMCCH7_0_PerfMonCtrClk_Hi_BASE_IDX 1 650 #define regUMCCH7_0_PerfMonCtl1 0x0f44 651 #define regUMCCH7_0_PerfMonCtl1_BASE_IDX 1 652 #define regUMCCH7_0_PerfMonCtr1_Lo 0x0f45 653 #define regUMCCH7_0_PerfMonCtr1_Lo_BASE_IDX 1 654 #define regUMCCH7_0_PerfMonCtr1_Hi 0x0f46 655 #define regUMCCH7_0_PerfMonCtr1_Hi_BASE_IDX 1 656 #define regUMCCH7_0_PerfMonCtl2 0x0f47 657 #define regUMCCH7_0_PerfMonCtl2_BASE_IDX 1 658 #define regUMCCH7_0_PerfMonCtr2_Lo 0x0f48 659 #define regUMCCH7_0_PerfMonCtr2_Lo_BASE_IDX 1 660 #define regUMCCH7_0_PerfMonCtr2_Hi 0x0f49 661 #define regUMCCH7_0_PerfMonCtr2_Hi_BASE_IDX 1 662 #define regUMCCH7_0_PerfMonCtl3 0x0f4a 663 #define regUMCCH7_0_PerfMonCtl3_BASE_IDX 1 664 #define regUMCCH7_0_PerfMonCtr3_Lo 0x0f4b 665 #define regUMCCH7_0_PerfMonCtr3_Lo_BASE_IDX 1 666 #define regUMCCH7_0_PerfMonCtr3_Hi 0x0f4c 667 #define regUMCCH7_0_PerfMonCtr3_Hi_BASE_IDX 1 668 #define regUMCCH7_0_PerfMonCtl4 0x0f4d 669 #define regUMCCH7_0_PerfMonCtl4_BASE_IDX 1 670 #define regUMCCH7_0_PerfMonCtr4_Lo 0x0f4e 671 #define regUMCCH7_0_PerfMonCtr4_Lo_BASE_IDX 1 672 #define regUMCCH7_0_PerfMonCtr4_Hi 0x0f4f 673 #define regUMCCH7_0_PerfMonCtr4_Hi_BASE_IDX 1 674 #define regUMCCH7_0_PerfMonCtl5 0x0f50 675 #define regUMCCH7_0_PerfMonCtl5_BASE_IDX 1 676 #define regUMCCH7_0_PerfMonCtr5_Lo 0x0f51 677 #define regUMCCH7_0_PerfMonCtr5_Lo_BASE_IDX 1 678 #define regUMCCH7_0_PerfMonCtr5_Hi 0x0f52 679 #define regUMCCH7_0_PerfMonCtr5_Hi_BASE_IDX 1 680 #define regUMCCH7_0_PerfMonCtl6 0x0f53 681 #define regUMCCH7_0_PerfMonCtl6_BASE_IDX 1 682 #define regUMCCH7_0_PerfMonCtr6_Lo 0x0f54 683 #define regUMCCH7_0_PerfMonCtr6_Lo_BASE_IDX 1 684 #define regUMCCH7_0_PerfMonCtr6_Hi 0x0f55 685 #define regUMCCH7_0_PerfMonCtr6_Hi_BASE_IDX 1 686 #define regUMCCH7_0_PerfMonCtl7 0x0f56 687 #define regUMCCH7_0_PerfMonCtl7_BASE_IDX 1 688 #define regUMCCH7_0_PerfMonCtr7_Lo 0x0f57 689 #define regUMCCH7_0_PerfMonCtr7_Lo_BASE_IDX 1 690 #define regUMCCH7_0_PerfMonCtr7_Hi 0x0f58 691 #define regUMCCH7_0_PerfMonCtr7_Hi_BASE_IDX 1 692 #define regUMCCH7_0_PerfMonCtl8 0x0f59 693 #define regUMCCH7_0_PerfMonCtl8_BASE_IDX 1 694 #define regUMCCH7_0_PerfMonCtr8_Lo 0x0f5a 695 #define regUMCCH7_0_PerfMonCtr8_Lo_BASE_IDX 1 696 #define regUMCCH7_0_PerfMonCtr8_Hi 0x0f5b 697 #define regUMCCH7_0_PerfMonCtr8_Hi_BASE_IDX 1 698 699 700 // addressBlock: umc_w_phy_umc1_umcch0_umcchdec 701 // base address: 0x250000 702 #define regUMCCH0_1_BaseAddrCS0 0x40000 703 #define regUMCCH0_1_BaseAddrCS0_BASE_IDX 1 704 #define regUMCCH0_1_AddrMaskCS01 0x40008 705 #define regUMCCH0_1_AddrMaskCS01_BASE_IDX 1 706 #define regUMCCH0_1_AddrSelCS01 0x40010 707 #define regUMCCH0_1_AddrSelCS01_BASE_IDX 1 708 #define regUMCCH0_1_AddrHashBank0 0x40032 709 #define regUMCCH0_1_AddrHashBank0_BASE_IDX 1 710 #define regUMCCH0_1_AddrHashBank1 0x40033 711 #define regUMCCH0_1_AddrHashBank1_BASE_IDX 1 712 #define regUMCCH0_1_AddrHashBank2 0x40034 713 #define regUMCCH0_1_AddrHashBank2_BASE_IDX 1 714 #define regUMCCH0_1_AddrHashBank3 0x40035 715 #define regUMCCH0_1_AddrHashBank3_BASE_IDX 1 716 #define regUMCCH0_1_AddrHashBank4 0x40036 717 #define regUMCCH0_1_AddrHashBank4_BASE_IDX 1 718 #define regUMCCH0_1_AddrHashBank5 0x40037 719 #define regUMCCH0_1_AddrHashBank5_BASE_IDX 1 720 #define regUMCCH0_1_EccErrCntSel 0x40328 721 #define regUMCCH0_1_EccErrCntSel_BASE_IDX 1 722 #define regUMCCH0_1_EccErrCnt 0x40329 723 #define regUMCCH0_1_EccErrCnt_BASE_IDX 1 724 #define regUMCCH0_1_PerfMonCtlClk 0x40340 725 #define regUMCCH0_1_PerfMonCtlClk_BASE_IDX 1 726 #define regUMCCH0_1_PerfMonCtrClk_Lo 0x40341 727 #define regUMCCH0_1_PerfMonCtrClk_Lo_BASE_IDX 1 728 #define regUMCCH0_1_PerfMonCtrClk_Hi 0x40342 729 #define regUMCCH0_1_PerfMonCtrClk_Hi_BASE_IDX 1 730 #define regUMCCH0_1_PerfMonCtl1 0x40344 731 #define regUMCCH0_1_PerfMonCtl1_BASE_IDX 1 732 #define regUMCCH0_1_PerfMonCtr1_Lo 0x40345 733 #define regUMCCH0_1_PerfMonCtr1_Lo_BASE_IDX 1 734 #define regUMCCH0_1_PerfMonCtr1_Hi 0x40346 735 #define regUMCCH0_1_PerfMonCtr1_Hi_BASE_IDX 1 736 #define regUMCCH0_1_PerfMonCtl2 0x40347 737 #define regUMCCH0_1_PerfMonCtl2_BASE_IDX 1 738 #define regUMCCH0_1_PerfMonCtr2_Lo 0x40348 739 #define regUMCCH0_1_PerfMonCtr2_Lo_BASE_IDX 1 740 #define regUMCCH0_1_PerfMonCtr2_Hi 0x40349 741 #define regUMCCH0_1_PerfMonCtr2_Hi_BASE_IDX 1 742 #define regUMCCH0_1_PerfMonCtl3 0x4034a 743 #define regUMCCH0_1_PerfMonCtl3_BASE_IDX 1 744 #define regUMCCH0_1_PerfMonCtr3_Lo 0x4034b 745 #define regUMCCH0_1_PerfMonCtr3_Lo_BASE_IDX 1 746 #define regUMCCH0_1_PerfMonCtr3_Hi 0x4034c 747 #define regUMCCH0_1_PerfMonCtr3_Hi_BASE_IDX 1 748 #define regUMCCH0_1_PerfMonCtl4 0x4034d 749 #define regUMCCH0_1_PerfMonCtl4_BASE_IDX 1 750 #define regUMCCH0_1_PerfMonCtr4_Lo 0x4034e 751 #define regUMCCH0_1_PerfMonCtr4_Lo_BASE_IDX 1 752 #define regUMCCH0_1_PerfMonCtr4_Hi 0x4034f 753 #define regUMCCH0_1_PerfMonCtr4_Hi_BASE_IDX 1 754 #define regUMCCH0_1_PerfMonCtl5 0x40350 755 #define regUMCCH0_1_PerfMonCtl5_BASE_IDX 1 756 #define regUMCCH0_1_PerfMonCtr5_Lo 0x40351 757 #define regUMCCH0_1_PerfMonCtr5_Lo_BASE_IDX 1 758 #define regUMCCH0_1_PerfMonCtr5_Hi 0x40352 759 #define regUMCCH0_1_PerfMonCtr5_Hi_BASE_IDX 1 760 #define regUMCCH0_1_PerfMonCtl6 0x40353 761 #define regUMCCH0_1_PerfMonCtl6_BASE_IDX 1 762 #define regUMCCH0_1_PerfMonCtr6_Lo 0x40354 763 #define regUMCCH0_1_PerfMonCtr6_Lo_BASE_IDX 1 764 #define regUMCCH0_1_PerfMonCtr6_Hi 0x40355 765 #define regUMCCH0_1_PerfMonCtr6_Hi_BASE_IDX 1 766 #define regUMCCH0_1_PerfMonCtl7 0x40356 767 #define regUMCCH0_1_PerfMonCtl7_BASE_IDX 1 768 #define regUMCCH0_1_PerfMonCtr7_Lo 0x40357 769 #define regUMCCH0_1_PerfMonCtr7_Lo_BASE_IDX 1 770 #define regUMCCH0_1_PerfMonCtr7_Hi 0x40358 771 #define regUMCCH0_1_PerfMonCtr7_Hi_BASE_IDX 1 772 #define regUMCCH0_1_PerfMonCtl8 0x40359 773 #define regUMCCH0_1_PerfMonCtl8_BASE_IDX 1 774 #define regUMCCH0_1_PerfMonCtr8_Lo 0x4035a 775 #define regUMCCH0_1_PerfMonCtr8_Lo_BASE_IDX 1 776 #define regUMCCH0_1_PerfMonCtr8_Hi 0x4035b 777 #define regUMCCH0_1_PerfMonCtr8_Hi_BASE_IDX 1 778 779 780 // addressBlock: umc_w_phy_umc1_umcch1_umcchdec 781 // base address: 0x251000 782 #define regUMCCH1_1_BaseAddrCS0 0x40400 783 #define regUMCCH1_1_BaseAddrCS0_BASE_IDX 1 784 #define regUMCCH1_1_AddrMaskCS01 0x40408 785 #define regUMCCH1_1_AddrMaskCS01_BASE_IDX 1 786 #define regUMCCH1_1_AddrSelCS01 0x40410 787 #define regUMCCH1_1_AddrSelCS01_BASE_IDX 1 788 #define regUMCCH1_1_AddrHashBank0 0x40432 789 #define regUMCCH1_1_AddrHashBank0_BASE_IDX 1 790 #define regUMCCH1_1_AddrHashBank1 0x40433 791 #define regUMCCH1_1_AddrHashBank1_BASE_IDX 1 792 #define regUMCCH1_1_AddrHashBank2 0x40434 793 #define regUMCCH1_1_AddrHashBank2_BASE_IDX 1 794 #define regUMCCH1_1_AddrHashBank3 0x40435 795 #define regUMCCH1_1_AddrHashBank3_BASE_IDX 1 796 #define regUMCCH1_1_AddrHashBank4 0x40436 797 #define regUMCCH1_1_AddrHashBank4_BASE_IDX 1 798 #define regUMCCH1_1_AddrHashBank5 0x40437 799 #define regUMCCH1_1_AddrHashBank5_BASE_IDX 1 800 #define regUMCCH1_1_EccErrCntSel 0x40728 801 #define regUMCCH1_1_EccErrCntSel_BASE_IDX 1 802 #define regUMCCH1_1_EccErrCnt 0x40729 803 #define regUMCCH1_1_EccErrCnt_BASE_IDX 1 804 #define regUMCCH1_1_PerfMonCtlClk 0x40740 805 #define regUMCCH1_1_PerfMonCtlClk_BASE_IDX 1 806 #define regUMCCH1_1_PerfMonCtrClk_Lo 0x40741 807 #define regUMCCH1_1_PerfMonCtrClk_Lo_BASE_IDX 1 808 #define regUMCCH1_1_PerfMonCtrClk_Hi 0x40742 809 #define regUMCCH1_1_PerfMonCtrClk_Hi_BASE_IDX 1 810 #define regUMCCH1_1_PerfMonCtl1 0x40744 811 #define regUMCCH1_1_PerfMonCtl1_BASE_IDX 1 812 #define regUMCCH1_1_PerfMonCtr1_Lo 0x40745 813 #define regUMCCH1_1_PerfMonCtr1_Lo_BASE_IDX 1 814 #define regUMCCH1_1_PerfMonCtr1_Hi 0x40746 815 #define regUMCCH1_1_PerfMonCtr1_Hi_BASE_IDX 1 816 #define regUMCCH1_1_PerfMonCtl2 0x40747 817 #define regUMCCH1_1_PerfMonCtl2_BASE_IDX 1 818 #define regUMCCH1_1_PerfMonCtr2_Lo 0x40748 819 #define regUMCCH1_1_PerfMonCtr2_Lo_BASE_IDX 1 820 #define regUMCCH1_1_PerfMonCtr2_Hi 0x40749 821 #define regUMCCH1_1_PerfMonCtr2_Hi_BASE_IDX 1 822 #define regUMCCH1_1_PerfMonCtl3 0x4074a 823 #define regUMCCH1_1_PerfMonCtl3_BASE_IDX 1 824 #define regUMCCH1_1_PerfMonCtr3_Lo 0x4074b 825 #define regUMCCH1_1_PerfMonCtr3_Lo_BASE_IDX 1 826 #define regUMCCH1_1_PerfMonCtr3_Hi 0x4074c 827 #define regUMCCH1_1_PerfMonCtr3_Hi_BASE_IDX 1 828 #define regUMCCH1_1_PerfMonCtl4 0x4074d 829 #define regUMCCH1_1_PerfMonCtl4_BASE_IDX 1 830 #define regUMCCH1_1_PerfMonCtr4_Lo 0x4074e 831 #define regUMCCH1_1_PerfMonCtr4_Lo_BASE_IDX 1 832 #define regUMCCH1_1_PerfMonCtr4_Hi 0x4074f 833 #define regUMCCH1_1_PerfMonCtr4_Hi_BASE_IDX 1 834 #define regUMCCH1_1_PerfMonCtl5 0x40750 835 #define regUMCCH1_1_PerfMonCtl5_BASE_IDX 1 836 #define regUMCCH1_1_PerfMonCtr5_Lo 0x40751 837 #define regUMCCH1_1_PerfMonCtr5_Lo_BASE_IDX 1 838 #define regUMCCH1_1_PerfMonCtr5_Hi 0x40752 839 #define regUMCCH1_1_PerfMonCtr5_Hi_BASE_IDX 1 840 #define regUMCCH1_1_PerfMonCtl6 0x40753 841 #define regUMCCH1_1_PerfMonCtl6_BASE_IDX 1 842 #define regUMCCH1_1_PerfMonCtr6_Lo 0x40754 843 #define regUMCCH1_1_PerfMonCtr6_Lo_BASE_IDX 1 844 #define regUMCCH1_1_PerfMonCtr6_Hi 0x40755 845 #define regUMCCH1_1_PerfMonCtr6_Hi_BASE_IDX 1 846 #define regUMCCH1_1_PerfMonCtl7 0x40756 847 #define regUMCCH1_1_PerfMonCtl7_BASE_IDX 1 848 #define regUMCCH1_1_PerfMonCtr7_Lo 0x40757 849 #define regUMCCH1_1_PerfMonCtr7_Lo_BASE_IDX 1 850 #define regUMCCH1_1_PerfMonCtr7_Hi 0x40758 851 #define regUMCCH1_1_PerfMonCtr7_Hi_BASE_IDX 1 852 #define regUMCCH1_1_PerfMonCtl8 0x40759 853 #define regUMCCH1_1_PerfMonCtl8_BASE_IDX 1 854 #define regUMCCH1_1_PerfMonCtr8_Lo 0x4075a 855 #define regUMCCH1_1_PerfMonCtr8_Lo_BASE_IDX 1 856 #define regUMCCH1_1_PerfMonCtr8_Hi 0x4075b 857 #define regUMCCH1_1_PerfMonCtr8_Hi_BASE_IDX 1 858 859 860 // addressBlock: umc_w_phy_umc1_umcch2_umcchdec 861 // base address: 0x252000 862 #define regUMCCH2_1_BaseAddrCS0 0x40800 863 #define regUMCCH2_1_BaseAddrCS0_BASE_IDX 1 864 #define regUMCCH2_1_AddrMaskCS01 0x40808 865 #define regUMCCH2_1_AddrMaskCS01_BASE_IDX 1 866 #define regUMCCH2_1_AddrSelCS01 0x40810 867 #define regUMCCH2_1_AddrSelCS01_BASE_IDX 1 868 #define regUMCCH2_1_AddrHashBank0 0x40832 869 #define regUMCCH2_1_AddrHashBank0_BASE_IDX 1 870 #define regUMCCH2_1_AddrHashBank1 0x40833 871 #define regUMCCH2_1_AddrHashBank1_BASE_IDX 1 872 #define regUMCCH2_1_AddrHashBank2 0x40834 873 #define regUMCCH2_1_AddrHashBank2_BASE_IDX 1 874 #define regUMCCH2_1_AddrHashBank3 0x40835 875 #define regUMCCH2_1_AddrHashBank3_BASE_IDX 1 876 #define regUMCCH2_1_AddrHashBank4 0x40836 877 #define regUMCCH2_1_AddrHashBank4_BASE_IDX 1 878 #define regUMCCH2_1_AddrHashBank5 0x40837 879 #define regUMCCH2_1_AddrHashBank5_BASE_IDX 1 880 #define regUMCCH2_1_EccErrCntSel 0x40b28 881 #define regUMCCH2_1_EccErrCntSel_BASE_IDX 1 882 #define regUMCCH2_1_EccErrCnt 0x40b29 883 #define regUMCCH2_1_EccErrCnt_BASE_IDX 1 884 #define regUMCCH2_1_PerfMonCtlClk 0x40b40 885 #define regUMCCH2_1_PerfMonCtlClk_BASE_IDX 1 886 #define regUMCCH2_1_PerfMonCtrClk_Lo 0x40b41 887 #define regUMCCH2_1_PerfMonCtrClk_Lo_BASE_IDX 1 888 #define regUMCCH2_1_PerfMonCtrClk_Hi 0x40b42 889 #define regUMCCH2_1_PerfMonCtrClk_Hi_BASE_IDX 1 890 #define regUMCCH2_1_PerfMonCtl1 0x40b44 891 #define regUMCCH2_1_PerfMonCtl1_BASE_IDX 1 892 #define regUMCCH2_1_PerfMonCtr1_Lo 0x40b45 893 #define regUMCCH2_1_PerfMonCtr1_Lo_BASE_IDX 1 894 #define regUMCCH2_1_PerfMonCtr1_Hi 0x40b46 895 #define regUMCCH2_1_PerfMonCtr1_Hi_BASE_IDX 1 896 #define regUMCCH2_1_PerfMonCtl2 0x40b47 897 #define regUMCCH2_1_PerfMonCtl2_BASE_IDX 1 898 #define regUMCCH2_1_PerfMonCtr2_Lo 0x40b48 899 #define regUMCCH2_1_PerfMonCtr2_Lo_BASE_IDX 1 900 #define regUMCCH2_1_PerfMonCtr2_Hi 0x40b49 901 #define regUMCCH2_1_PerfMonCtr2_Hi_BASE_IDX 1 902 #define regUMCCH2_1_PerfMonCtl3 0x40b4a 903 #define regUMCCH2_1_PerfMonCtl3_BASE_IDX 1 904 #define regUMCCH2_1_PerfMonCtr3_Lo 0x40b4b 905 #define regUMCCH2_1_PerfMonCtr3_Lo_BASE_IDX 1 906 #define regUMCCH2_1_PerfMonCtr3_Hi 0x40b4c 907 #define regUMCCH2_1_PerfMonCtr3_Hi_BASE_IDX 1 908 #define regUMCCH2_1_PerfMonCtl4 0x40b4d 909 #define regUMCCH2_1_PerfMonCtl4_BASE_IDX 1 910 #define regUMCCH2_1_PerfMonCtr4_Lo 0x40b4e 911 #define regUMCCH2_1_PerfMonCtr4_Lo_BASE_IDX 1 912 #define regUMCCH2_1_PerfMonCtr4_Hi 0x40b4f 913 #define regUMCCH2_1_PerfMonCtr4_Hi_BASE_IDX 1 914 #define regUMCCH2_1_PerfMonCtl5 0x40b50 915 #define regUMCCH2_1_PerfMonCtl5_BASE_IDX 1 916 #define regUMCCH2_1_PerfMonCtr5_Lo 0x40b51 917 #define regUMCCH2_1_PerfMonCtr5_Lo_BASE_IDX 1 918 #define regUMCCH2_1_PerfMonCtr5_Hi 0x40b52 919 #define regUMCCH2_1_PerfMonCtr5_Hi_BASE_IDX 1 920 #define regUMCCH2_1_PerfMonCtl6 0x40b53 921 #define regUMCCH2_1_PerfMonCtl6_BASE_IDX 1 922 #define regUMCCH2_1_PerfMonCtr6_Lo 0x40b54 923 #define regUMCCH2_1_PerfMonCtr6_Lo_BASE_IDX 1 924 #define regUMCCH2_1_PerfMonCtr6_Hi 0x40b55 925 #define regUMCCH2_1_PerfMonCtr6_Hi_BASE_IDX 1 926 #define regUMCCH2_1_PerfMonCtl7 0x40b56 927 #define regUMCCH2_1_PerfMonCtl7_BASE_IDX 1 928 #define regUMCCH2_1_PerfMonCtr7_Lo 0x40b57 929 #define regUMCCH2_1_PerfMonCtr7_Lo_BASE_IDX 1 930 #define regUMCCH2_1_PerfMonCtr7_Hi 0x40b58 931 #define regUMCCH2_1_PerfMonCtr7_Hi_BASE_IDX 1 932 #define regUMCCH2_1_PerfMonCtl8 0x40b59 933 #define regUMCCH2_1_PerfMonCtl8_BASE_IDX 1 934 #define regUMCCH2_1_PerfMonCtr8_Lo 0x40b5a 935 #define regUMCCH2_1_PerfMonCtr8_Lo_BASE_IDX 1 936 #define regUMCCH2_1_PerfMonCtr8_Hi 0x40b5b 937 #define regUMCCH2_1_PerfMonCtr8_Hi_BASE_IDX 1 938 939 940 // addressBlock: umc_w_phy_umc1_umcch3_umcchdec 941 // base address: 0x253000 942 #define regUMCCH3_1_BaseAddrCS0 0x40c00 943 #define regUMCCH3_1_BaseAddrCS0_BASE_IDX 1 944 #define regUMCCH3_1_AddrMaskCS01 0x40c08 945 #define regUMCCH3_1_AddrMaskCS01_BASE_IDX 1 946 #define regUMCCH3_1_AddrSelCS01 0x40c10 947 #define regUMCCH3_1_AddrSelCS01_BASE_IDX 1 948 #define regUMCCH3_1_AddrHashBank0 0x40c32 949 #define regUMCCH3_1_AddrHashBank0_BASE_IDX 1 950 #define regUMCCH3_1_AddrHashBank1 0x40c33 951 #define regUMCCH3_1_AddrHashBank1_BASE_IDX 1 952 #define regUMCCH3_1_AddrHashBank2 0x40c34 953 #define regUMCCH3_1_AddrHashBank2_BASE_IDX 1 954 #define regUMCCH3_1_AddrHashBank3 0x40c35 955 #define regUMCCH3_1_AddrHashBank3_BASE_IDX 1 956 #define regUMCCH3_1_AddrHashBank4 0x40c36 957 #define regUMCCH3_1_AddrHashBank4_BASE_IDX 1 958 #define regUMCCH3_1_AddrHashBank5 0x40c37 959 #define regUMCCH3_1_AddrHashBank5_BASE_IDX 1 960 #define regUMCCH3_1_EccErrCntSel 0x40f28 961 #define regUMCCH3_1_EccErrCntSel_BASE_IDX 1 962 #define regUMCCH3_1_EccErrCnt 0x40f29 963 #define regUMCCH3_1_EccErrCnt_BASE_IDX 1 964 #define regUMCCH3_1_PerfMonCtlClk 0x40f40 965 #define regUMCCH3_1_PerfMonCtlClk_BASE_IDX 1 966 #define regUMCCH3_1_PerfMonCtrClk_Lo 0x40f41 967 #define regUMCCH3_1_PerfMonCtrClk_Lo_BASE_IDX 1 968 #define regUMCCH3_1_PerfMonCtrClk_Hi 0x40f42 969 #define regUMCCH3_1_PerfMonCtrClk_Hi_BASE_IDX 1 970 #define regUMCCH3_1_PerfMonCtl1 0x40f44 971 #define regUMCCH3_1_PerfMonCtl1_BASE_IDX 1 972 #define regUMCCH3_1_PerfMonCtr1_Lo 0x40f45 973 #define regUMCCH3_1_PerfMonCtr1_Lo_BASE_IDX 1 974 #define regUMCCH3_1_PerfMonCtr1_Hi 0x40f46 975 #define regUMCCH3_1_PerfMonCtr1_Hi_BASE_IDX 1 976 #define regUMCCH3_1_PerfMonCtl2 0x40f47 977 #define regUMCCH3_1_PerfMonCtl2_BASE_IDX 1 978 #define regUMCCH3_1_PerfMonCtr2_Lo 0x40f48 979 #define regUMCCH3_1_PerfMonCtr2_Lo_BASE_IDX 1 980 #define regUMCCH3_1_PerfMonCtr2_Hi 0x40f49 981 #define regUMCCH3_1_PerfMonCtr2_Hi_BASE_IDX 1 982 #define regUMCCH3_1_PerfMonCtl3 0x40f4a 983 #define regUMCCH3_1_PerfMonCtl3_BASE_IDX 1 984 #define regUMCCH3_1_PerfMonCtr3_Lo 0x40f4b 985 #define regUMCCH3_1_PerfMonCtr3_Lo_BASE_IDX 1 986 #define regUMCCH3_1_PerfMonCtr3_Hi 0x40f4c 987 #define regUMCCH3_1_PerfMonCtr3_Hi_BASE_IDX 1 988 #define regUMCCH3_1_PerfMonCtl4 0x40f4d 989 #define regUMCCH3_1_PerfMonCtl4_BASE_IDX 1 990 #define regUMCCH3_1_PerfMonCtr4_Lo 0x40f4e 991 #define regUMCCH3_1_PerfMonCtr4_Lo_BASE_IDX 1 992 #define regUMCCH3_1_PerfMonCtr4_Hi 0x40f4f 993 #define regUMCCH3_1_PerfMonCtr4_Hi_BASE_IDX 1 994 #define regUMCCH3_1_PerfMonCtl5 0x40f50 995 #define regUMCCH3_1_PerfMonCtl5_BASE_IDX 1 996 #define regUMCCH3_1_PerfMonCtr5_Lo 0x40f51 997 #define regUMCCH3_1_PerfMonCtr5_Lo_BASE_IDX 1 998 #define regUMCCH3_1_PerfMonCtr5_Hi 0x40f52 999 #define regUMCCH3_1_PerfMonCtr5_Hi_BASE_IDX 1 1000 #define regUMCCH3_1_PerfMonCtl6 0x40f53 1001 #define regUMCCH3_1_PerfMonCtl6_BASE_IDX 1 1002 #define regUMCCH3_1_PerfMonCtr6_Lo 0x40f54 1003 #define regUMCCH3_1_PerfMonCtr6_Lo_BASE_IDX 1 1004 #define regUMCCH3_1_PerfMonCtr6_Hi 0x40f55 1005 #define regUMCCH3_1_PerfMonCtr6_Hi_BASE_IDX 1 1006 #define regUMCCH3_1_PerfMonCtl7 0x40f56 1007 #define regUMCCH3_1_PerfMonCtl7_BASE_IDX 1 1008 #define regUMCCH3_1_PerfMonCtr7_Lo 0x40f57 1009 #define regUMCCH3_1_PerfMonCtr7_Lo_BASE_IDX 1 1010 #define regUMCCH3_1_PerfMonCtr7_Hi 0x40f58 1011 #define regUMCCH3_1_PerfMonCtr7_Hi_BASE_IDX 1 1012 #define regUMCCH3_1_PerfMonCtl8 0x40f59 1013 #define regUMCCH3_1_PerfMonCtl8_BASE_IDX 1 1014 #define regUMCCH3_1_PerfMonCtr8_Lo 0x40f5a 1015 #define regUMCCH3_1_PerfMonCtr8_Lo_BASE_IDX 1 1016 #define regUMCCH3_1_PerfMonCtr8_Hi 0x40f5b 1017 #define regUMCCH3_1_PerfMonCtr8_Hi_BASE_IDX 1 1018 1019 1020 // addressBlock: umc_w_phy_umc1_umcch4_umcchdec 1021 // base address: 0x350000 1022 #define regUMCCH4_1_BaseAddrCS0 0x80000 1023 #define regUMCCH4_1_BaseAddrCS0_BASE_IDX 1 1024 #define regUMCCH4_1_AddrMaskCS01 0x80008 1025 #define regUMCCH4_1_AddrMaskCS01_BASE_IDX 1 1026 #define regUMCCH4_1_AddrSelCS01 0x80010 1027 #define regUMCCH4_1_AddrSelCS01_BASE_IDX 1 1028 #define regUMCCH4_1_AddrHashBank0 0x80032 1029 #define regUMCCH4_1_AddrHashBank0_BASE_IDX 1 1030 #define regUMCCH4_1_AddrHashBank1 0x80033 1031 #define regUMCCH4_1_AddrHashBank1_BASE_IDX 1 1032 #define regUMCCH4_1_AddrHashBank2 0x80034 1033 #define regUMCCH4_1_AddrHashBank2_BASE_IDX 1 1034 #define regUMCCH4_1_AddrHashBank3 0x80035 1035 #define regUMCCH4_1_AddrHashBank3_BASE_IDX 1 1036 #define regUMCCH4_1_AddrHashBank4 0x80036 1037 #define regUMCCH4_1_AddrHashBank4_BASE_IDX 1 1038 #define regUMCCH4_1_AddrHashBank5 0x80037 1039 #define regUMCCH4_1_AddrHashBank5_BASE_IDX 1 1040 #define regUMCCH4_1_EccErrCntSel 0x80328 1041 #define regUMCCH4_1_EccErrCntSel_BASE_IDX 1 1042 #define regUMCCH4_1_EccErrCnt 0x80329 1043 #define regUMCCH4_1_EccErrCnt_BASE_IDX 1 1044 #define regUMCCH4_1_PerfMonCtlClk 0x80340 1045 #define regUMCCH4_1_PerfMonCtlClk_BASE_IDX 1 1046 #define regUMCCH4_1_PerfMonCtrClk_Lo 0x80341 1047 #define regUMCCH4_1_PerfMonCtrClk_Lo_BASE_IDX 1 1048 #define regUMCCH4_1_PerfMonCtrClk_Hi 0x80342 1049 #define regUMCCH4_1_PerfMonCtrClk_Hi_BASE_IDX 1 1050 #define regUMCCH4_1_PerfMonCtl1 0x80344 1051 #define regUMCCH4_1_PerfMonCtl1_BASE_IDX 1 1052 #define regUMCCH4_1_PerfMonCtr1_Lo 0x80345 1053 #define regUMCCH4_1_PerfMonCtr1_Lo_BASE_IDX 1 1054 #define regUMCCH4_1_PerfMonCtr1_Hi 0x80346 1055 #define regUMCCH4_1_PerfMonCtr1_Hi_BASE_IDX 1 1056 #define regUMCCH4_1_PerfMonCtl2 0x80347 1057 #define regUMCCH4_1_PerfMonCtl2_BASE_IDX 1 1058 #define regUMCCH4_1_PerfMonCtr2_Lo 0x80348 1059 #define regUMCCH4_1_PerfMonCtr2_Lo_BASE_IDX 1 1060 #define regUMCCH4_1_PerfMonCtr2_Hi 0x80349 1061 #define regUMCCH4_1_PerfMonCtr2_Hi_BASE_IDX 1 1062 #define regUMCCH4_1_PerfMonCtl3 0x8034a 1063 #define regUMCCH4_1_PerfMonCtl3_BASE_IDX 1 1064 #define regUMCCH4_1_PerfMonCtr3_Lo 0x8034b 1065 #define regUMCCH4_1_PerfMonCtr3_Lo_BASE_IDX 1 1066 #define regUMCCH4_1_PerfMonCtr3_Hi 0x8034c 1067 #define regUMCCH4_1_PerfMonCtr3_Hi_BASE_IDX 1 1068 #define regUMCCH4_1_PerfMonCtl4 0x8034d 1069 #define regUMCCH4_1_PerfMonCtl4_BASE_IDX 1 1070 #define regUMCCH4_1_PerfMonCtr4_Lo 0x8034e 1071 #define regUMCCH4_1_PerfMonCtr4_Lo_BASE_IDX 1 1072 #define regUMCCH4_1_PerfMonCtr4_Hi 0x8034f 1073 #define regUMCCH4_1_PerfMonCtr4_Hi_BASE_IDX 1 1074 #define regUMCCH4_1_PerfMonCtl5 0x80350 1075 #define regUMCCH4_1_PerfMonCtl5_BASE_IDX 1 1076 #define regUMCCH4_1_PerfMonCtr5_Lo 0x80351 1077 #define regUMCCH4_1_PerfMonCtr5_Lo_BASE_IDX 1 1078 #define regUMCCH4_1_PerfMonCtr5_Hi 0x80352 1079 #define regUMCCH4_1_PerfMonCtr5_Hi_BASE_IDX 1 1080 #define regUMCCH4_1_PerfMonCtl6 0x80353 1081 #define regUMCCH4_1_PerfMonCtl6_BASE_IDX 1 1082 #define regUMCCH4_1_PerfMonCtr6_Lo 0x80354 1083 #define regUMCCH4_1_PerfMonCtr6_Lo_BASE_IDX 1 1084 #define regUMCCH4_1_PerfMonCtr6_Hi 0x80355 1085 #define regUMCCH4_1_PerfMonCtr6_Hi_BASE_IDX 1 1086 #define regUMCCH4_1_PerfMonCtl7 0x80356 1087 #define regUMCCH4_1_PerfMonCtl7_BASE_IDX 1 1088 #define regUMCCH4_1_PerfMonCtr7_Lo 0x80357 1089 #define regUMCCH4_1_PerfMonCtr7_Lo_BASE_IDX 1 1090 #define regUMCCH4_1_PerfMonCtr7_Hi 0x80358 1091 #define regUMCCH4_1_PerfMonCtr7_Hi_BASE_IDX 1 1092 #define regUMCCH4_1_PerfMonCtl8 0x80359 1093 #define regUMCCH4_1_PerfMonCtl8_BASE_IDX 1 1094 #define regUMCCH4_1_PerfMonCtr8_Lo 0x8035a 1095 #define regUMCCH4_1_PerfMonCtr8_Lo_BASE_IDX 1 1096 #define regUMCCH4_1_PerfMonCtr8_Hi 0x8035b 1097 #define regUMCCH4_1_PerfMonCtr8_Hi_BASE_IDX 1 1098 1099 1100 // addressBlock: umc_w_phy_umc1_umcch5_umcchdec 1101 // base address: 0x351000 1102 #define regUMCCH5_1_BaseAddrCS0 0x80400 1103 #define regUMCCH5_1_BaseAddrCS0_BASE_IDX 1 1104 #define regUMCCH5_1_AddrMaskCS01 0x80408 1105 #define regUMCCH5_1_AddrMaskCS01_BASE_IDX 1 1106 #define regUMCCH5_1_AddrSelCS01 0x80410 1107 #define regUMCCH5_1_AddrSelCS01_BASE_IDX 1 1108 #define regUMCCH5_1_AddrHashBank0 0x80432 1109 #define regUMCCH5_1_AddrHashBank0_BASE_IDX 1 1110 #define regUMCCH5_1_AddrHashBank1 0x80433 1111 #define regUMCCH5_1_AddrHashBank1_BASE_IDX 1 1112 #define regUMCCH5_1_AddrHashBank2 0x80434 1113 #define regUMCCH5_1_AddrHashBank2_BASE_IDX 1 1114 #define regUMCCH5_1_AddrHashBank3 0x80435 1115 #define regUMCCH5_1_AddrHashBank3_BASE_IDX 1 1116 #define regUMCCH5_1_AddrHashBank4 0x80436 1117 #define regUMCCH5_1_AddrHashBank4_BASE_IDX 1 1118 #define regUMCCH5_1_AddrHashBank5 0x80437 1119 #define regUMCCH5_1_AddrHashBank5_BASE_IDX 1 1120 #define regUMCCH5_1_EccErrCntSel 0x80728 1121 #define regUMCCH5_1_EccErrCntSel_BASE_IDX 1 1122 #define regUMCCH5_1_EccErrCnt 0x80729 1123 #define regUMCCH5_1_EccErrCnt_BASE_IDX 1 1124 #define regUMCCH5_1_PerfMonCtlClk 0x80740 1125 #define regUMCCH5_1_PerfMonCtlClk_BASE_IDX 1 1126 #define regUMCCH5_1_PerfMonCtrClk_Lo 0x80741 1127 #define regUMCCH5_1_PerfMonCtrClk_Lo_BASE_IDX 1 1128 #define regUMCCH5_1_PerfMonCtrClk_Hi 0x80742 1129 #define regUMCCH5_1_PerfMonCtrClk_Hi_BASE_IDX 1 1130 #define regUMCCH5_1_PerfMonCtl1 0x80744 1131 #define regUMCCH5_1_PerfMonCtl1_BASE_IDX 1 1132 #define regUMCCH5_1_PerfMonCtr1_Lo 0x80745 1133 #define regUMCCH5_1_PerfMonCtr1_Lo_BASE_IDX 1 1134 #define regUMCCH5_1_PerfMonCtr1_Hi 0x80746 1135 #define regUMCCH5_1_PerfMonCtr1_Hi_BASE_IDX 1 1136 #define regUMCCH5_1_PerfMonCtl2 0x80747 1137 #define regUMCCH5_1_PerfMonCtl2_BASE_IDX 1 1138 #define regUMCCH5_1_PerfMonCtr2_Lo 0x80748 1139 #define regUMCCH5_1_PerfMonCtr2_Lo_BASE_IDX 1 1140 #define regUMCCH5_1_PerfMonCtr2_Hi 0x80749 1141 #define regUMCCH5_1_PerfMonCtr2_Hi_BASE_IDX 1 1142 #define regUMCCH5_1_PerfMonCtl3 0x8074a 1143 #define regUMCCH5_1_PerfMonCtl3_BASE_IDX 1 1144 #define regUMCCH5_1_PerfMonCtr3_Lo 0x8074b 1145 #define regUMCCH5_1_PerfMonCtr3_Lo_BASE_IDX 1 1146 #define regUMCCH5_1_PerfMonCtr3_Hi 0x8074c 1147 #define regUMCCH5_1_PerfMonCtr3_Hi_BASE_IDX 1 1148 #define regUMCCH5_1_PerfMonCtl4 0x8074d 1149 #define regUMCCH5_1_PerfMonCtl4_BASE_IDX 1 1150 #define regUMCCH5_1_PerfMonCtr4_Lo 0x8074e 1151 #define regUMCCH5_1_PerfMonCtr4_Lo_BASE_IDX 1 1152 #define regUMCCH5_1_PerfMonCtr4_Hi 0x8074f 1153 #define regUMCCH5_1_PerfMonCtr4_Hi_BASE_IDX 1 1154 #define regUMCCH5_1_PerfMonCtl5 0x80750 1155 #define regUMCCH5_1_PerfMonCtl5_BASE_IDX 1 1156 #define regUMCCH5_1_PerfMonCtr5_Lo 0x80751 1157 #define regUMCCH5_1_PerfMonCtr5_Lo_BASE_IDX 1 1158 #define regUMCCH5_1_PerfMonCtr5_Hi 0x80752 1159 #define regUMCCH5_1_PerfMonCtr5_Hi_BASE_IDX 1 1160 #define regUMCCH5_1_PerfMonCtl6 0x80753 1161 #define regUMCCH5_1_PerfMonCtl6_BASE_IDX 1 1162 #define regUMCCH5_1_PerfMonCtr6_Lo 0x80754 1163 #define regUMCCH5_1_PerfMonCtr6_Lo_BASE_IDX 1 1164 #define regUMCCH5_1_PerfMonCtr6_Hi 0x80755 1165 #define regUMCCH5_1_PerfMonCtr6_Hi_BASE_IDX 1 1166 #define regUMCCH5_1_PerfMonCtl7 0x80756 1167 #define regUMCCH5_1_PerfMonCtl7_BASE_IDX 1 1168 #define regUMCCH5_1_PerfMonCtr7_Lo 0x80757 1169 #define regUMCCH5_1_PerfMonCtr7_Lo_BASE_IDX 1 1170 #define regUMCCH5_1_PerfMonCtr7_Hi 0x80758 1171 #define regUMCCH5_1_PerfMonCtr7_Hi_BASE_IDX 1 1172 #define regUMCCH5_1_PerfMonCtl8 0x80759 1173 #define regUMCCH5_1_PerfMonCtl8_BASE_IDX 1 1174 #define regUMCCH5_1_PerfMonCtr8_Lo 0x8075a 1175 #define regUMCCH5_1_PerfMonCtr8_Lo_BASE_IDX 1 1176 #define regUMCCH5_1_PerfMonCtr8_Hi 0x8075b 1177 #define regUMCCH5_1_PerfMonCtr8_Hi_BASE_IDX 1 1178 1179 1180 // addressBlock: umc_w_phy_umc1_umcch6_umcchdec 1181 // base address: 0x352000 1182 #define regUMCCH6_1_BaseAddrCS0 0x80800 1183 #define regUMCCH6_1_BaseAddrCS0_BASE_IDX 1 1184 #define regUMCCH6_1_AddrMaskCS01 0x80808 1185 #define regUMCCH6_1_AddrMaskCS01_BASE_IDX 1 1186 #define regUMCCH6_1_AddrSelCS01 0x80810 1187 #define regUMCCH6_1_AddrSelCS01_BASE_IDX 1 1188 #define regUMCCH6_1_AddrHashBank0 0x80832 1189 #define regUMCCH6_1_AddrHashBank0_BASE_IDX 1 1190 #define regUMCCH6_1_AddrHashBank1 0x80833 1191 #define regUMCCH6_1_AddrHashBank1_BASE_IDX 1 1192 #define regUMCCH6_1_AddrHashBank2 0x80834 1193 #define regUMCCH6_1_AddrHashBank2_BASE_IDX 1 1194 #define regUMCCH6_1_AddrHashBank3 0x80835 1195 #define regUMCCH6_1_AddrHashBank3_BASE_IDX 1 1196 #define regUMCCH6_1_AddrHashBank4 0x80836 1197 #define regUMCCH6_1_AddrHashBank4_BASE_IDX 1 1198 #define regUMCCH6_1_AddrHashBank5 0x80837 1199 #define regUMCCH6_1_AddrHashBank5_BASE_IDX 1 1200 #define regUMCCH6_1_EccErrCntSel 0x80b28 1201 #define regUMCCH6_1_EccErrCntSel_BASE_IDX 1 1202 #define regUMCCH6_1_EccErrCnt 0x80b29 1203 #define regUMCCH6_1_EccErrCnt_BASE_IDX 1 1204 #define regUMCCH6_1_PerfMonCtlClk 0x80b40 1205 #define regUMCCH6_1_PerfMonCtlClk_BASE_IDX 1 1206 #define regUMCCH6_1_PerfMonCtrClk_Lo 0x80b41 1207 #define regUMCCH6_1_PerfMonCtrClk_Lo_BASE_IDX 1 1208 #define regUMCCH6_1_PerfMonCtrClk_Hi 0x80b42 1209 #define regUMCCH6_1_PerfMonCtrClk_Hi_BASE_IDX 1 1210 #define regUMCCH6_1_PerfMonCtl1 0x80b44 1211 #define regUMCCH6_1_PerfMonCtl1_BASE_IDX 1 1212 #define regUMCCH6_1_PerfMonCtr1_Lo 0x80b45 1213 #define regUMCCH6_1_PerfMonCtr1_Lo_BASE_IDX 1 1214 #define regUMCCH6_1_PerfMonCtr1_Hi 0x80b46 1215 #define regUMCCH6_1_PerfMonCtr1_Hi_BASE_IDX 1 1216 #define regUMCCH6_1_PerfMonCtl2 0x80b47 1217 #define regUMCCH6_1_PerfMonCtl2_BASE_IDX 1 1218 #define regUMCCH6_1_PerfMonCtr2_Lo 0x80b48 1219 #define regUMCCH6_1_PerfMonCtr2_Lo_BASE_IDX 1 1220 #define regUMCCH6_1_PerfMonCtr2_Hi 0x80b49 1221 #define regUMCCH6_1_PerfMonCtr2_Hi_BASE_IDX 1 1222 #define regUMCCH6_1_PerfMonCtl3 0x80b4a 1223 #define regUMCCH6_1_PerfMonCtl3_BASE_IDX 1 1224 #define regUMCCH6_1_PerfMonCtr3_Lo 0x80b4b 1225 #define regUMCCH6_1_PerfMonCtr3_Lo_BASE_IDX 1 1226 #define regUMCCH6_1_PerfMonCtr3_Hi 0x80b4c 1227 #define regUMCCH6_1_PerfMonCtr3_Hi_BASE_IDX 1 1228 #define regUMCCH6_1_PerfMonCtl4 0x80b4d 1229 #define regUMCCH6_1_PerfMonCtl4_BASE_IDX 1 1230 #define regUMCCH6_1_PerfMonCtr4_Lo 0x80b4e 1231 #define regUMCCH6_1_PerfMonCtr4_Lo_BASE_IDX 1 1232 #define regUMCCH6_1_PerfMonCtr4_Hi 0x80b4f 1233 #define regUMCCH6_1_PerfMonCtr4_Hi_BASE_IDX 1 1234 #define regUMCCH6_1_PerfMonCtl5 0x80b50 1235 #define regUMCCH6_1_PerfMonCtl5_BASE_IDX 1 1236 #define regUMCCH6_1_PerfMonCtr5_Lo 0x80b51 1237 #define regUMCCH6_1_PerfMonCtr5_Lo_BASE_IDX 1 1238 #define regUMCCH6_1_PerfMonCtr5_Hi 0x80b52 1239 #define regUMCCH6_1_PerfMonCtr5_Hi_BASE_IDX 1 1240 #define regUMCCH6_1_PerfMonCtl6 0x80b53 1241 #define regUMCCH6_1_PerfMonCtl6_BASE_IDX 1 1242 #define regUMCCH6_1_PerfMonCtr6_Lo 0x80b54 1243 #define regUMCCH6_1_PerfMonCtr6_Lo_BASE_IDX 1 1244 #define regUMCCH6_1_PerfMonCtr6_Hi 0x80b55 1245 #define regUMCCH6_1_PerfMonCtr6_Hi_BASE_IDX 1 1246 #define regUMCCH6_1_PerfMonCtl7 0x80b56 1247 #define regUMCCH6_1_PerfMonCtl7_BASE_IDX 1 1248 #define regUMCCH6_1_PerfMonCtr7_Lo 0x80b57 1249 #define regUMCCH6_1_PerfMonCtr7_Lo_BASE_IDX 1 1250 #define regUMCCH6_1_PerfMonCtr7_Hi 0x80b58 1251 #define regUMCCH6_1_PerfMonCtr7_Hi_BASE_IDX 1 1252 #define regUMCCH6_1_PerfMonCtl8 0x80b59 1253 #define regUMCCH6_1_PerfMonCtl8_BASE_IDX 1 1254 #define regUMCCH6_1_PerfMonCtr8_Lo 0x80b5a 1255 #define regUMCCH6_1_PerfMonCtr8_Lo_BASE_IDX 1 1256 #define regUMCCH6_1_PerfMonCtr8_Hi 0x80b5b 1257 #define regUMCCH6_1_PerfMonCtr8_Hi_BASE_IDX 1 1258 1259 1260 // addressBlock: umc_w_phy_umc1_umcch7_umcchdec 1261 // base address: 0x353000 1262 #define regUMCCH7_1_BaseAddrCS0 0x80c00 1263 #define regUMCCH7_1_BaseAddrCS0_BASE_IDX 1 1264 #define regUMCCH7_1_AddrMaskCS01 0x80c08 1265 #define regUMCCH7_1_AddrMaskCS01_BASE_IDX 1 1266 #define regUMCCH7_1_AddrSelCS01 0x80c10 1267 #define regUMCCH7_1_AddrSelCS01_BASE_IDX 1 1268 #define regUMCCH7_1_AddrHashBank0 0x80c32 1269 #define regUMCCH7_1_AddrHashBank0_BASE_IDX 1 1270 #define regUMCCH7_1_AddrHashBank1 0x80c33 1271 #define regUMCCH7_1_AddrHashBank1_BASE_IDX 1 1272 #define regUMCCH7_1_AddrHashBank2 0x80c34 1273 #define regUMCCH7_1_AddrHashBank2_BASE_IDX 1 1274 #define regUMCCH7_1_AddrHashBank3 0x80c35 1275 #define regUMCCH7_1_AddrHashBank3_BASE_IDX 1 1276 #define regUMCCH7_1_AddrHashBank4 0x80c36 1277 #define regUMCCH7_1_AddrHashBank4_BASE_IDX 1 1278 #define regUMCCH7_1_AddrHashBank5 0x80c37 1279 #define regUMCCH7_1_AddrHashBank5_BASE_IDX 1 1280 #define regUMCCH7_1_EccErrCntSel 0x80f28 1281 #define regUMCCH7_1_EccErrCntSel_BASE_IDX 1 1282 #define regUMCCH7_1_EccErrCnt 0x80f29 1283 #define regUMCCH7_1_EccErrCnt_BASE_IDX 1 1284 #define regUMCCH7_1_PerfMonCtlClk 0x80f40 1285 #define regUMCCH7_1_PerfMonCtlClk_BASE_IDX 1 1286 #define regUMCCH7_1_PerfMonCtrClk_Lo 0x80f41 1287 #define regUMCCH7_1_PerfMonCtrClk_Lo_BASE_IDX 1 1288 #define regUMCCH7_1_PerfMonCtrClk_Hi 0x80f42 1289 #define regUMCCH7_1_PerfMonCtrClk_Hi_BASE_IDX 1 1290 #define regUMCCH7_1_PerfMonCtl1 0x80f44 1291 #define regUMCCH7_1_PerfMonCtl1_BASE_IDX 1 1292 #define regUMCCH7_1_PerfMonCtr1_Lo 0x80f45 1293 #define regUMCCH7_1_PerfMonCtr1_Lo_BASE_IDX 1 1294 #define regUMCCH7_1_PerfMonCtr1_Hi 0x80f46 1295 #define regUMCCH7_1_PerfMonCtr1_Hi_BASE_IDX 1 1296 #define regUMCCH7_1_PerfMonCtl2 0x80f47 1297 #define regUMCCH7_1_PerfMonCtl2_BASE_IDX 1 1298 #define regUMCCH7_1_PerfMonCtr2_Lo 0x80f48 1299 #define regUMCCH7_1_PerfMonCtr2_Lo_BASE_IDX 1 1300 #define regUMCCH7_1_PerfMonCtr2_Hi 0x80f49 1301 #define regUMCCH7_1_PerfMonCtr2_Hi_BASE_IDX 1 1302 #define regUMCCH7_1_PerfMonCtl3 0x80f4a 1303 #define regUMCCH7_1_PerfMonCtl3_BASE_IDX 1 1304 #define regUMCCH7_1_PerfMonCtr3_Lo 0x80f4b 1305 #define regUMCCH7_1_PerfMonCtr3_Lo_BASE_IDX 1 1306 #define regUMCCH7_1_PerfMonCtr3_Hi 0x80f4c 1307 #define regUMCCH7_1_PerfMonCtr3_Hi_BASE_IDX 1 1308 #define regUMCCH7_1_PerfMonCtl4 0x80f4d 1309 #define regUMCCH7_1_PerfMonCtl4_BASE_IDX 1 1310 #define regUMCCH7_1_PerfMonCtr4_Lo 0x80f4e 1311 #define regUMCCH7_1_PerfMonCtr4_Lo_BASE_IDX 1 1312 #define regUMCCH7_1_PerfMonCtr4_Hi 0x80f4f 1313 #define regUMCCH7_1_PerfMonCtr4_Hi_BASE_IDX 1 1314 #define regUMCCH7_1_PerfMonCtl5 0x80f50 1315 #define regUMCCH7_1_PerfMonCtl5_BASE_IDX 1 1316 #define regUMCCH7_1_PerfMonCtr5_Lo 0x80f51 1317 #define regUMCCH7_1_PerfMonCtr5_Lo_BASE_IDX 1 1318 #define regUMCCH7_1_PerfMonCtr5_Hi 0x80f52 1319 #define regUMCCH7_1_PerfMonCtr5_Hi_BASE_IDX 1 1320 #define regUMCCH7_1_PerfMonCtl6 0x80f53 1321 #define regUMCCH7_1_PerfMonCtl6_BASE_IDX 1 1322 #define regUMCCH7_1_PerfMonCtr6_Lo 0x80f54 1323 #define regUMCCH7_1_PerfMonCtr6_Lo_BASE_IDX 1 1324 #define regUMCCH7_1_PerfMonCtr6_Hi 0x80f55 1325 #define regUMCCH7_1_PerfMonCtr6_Hi_BASE_IDX 1 1326 #define regUMCCH7_1_PerfMonCtl7 0x80f56 1327 #define regUMCCH7_1_PerfMonCtl7_BASE_IDX 1 1328 #define regUMCCH7_1_PerfMonCtr7_Lo 0x80f57 1329 #define regUMCCH7_1_PerfMonCtr7_Lo_BASE_IDX 1 1330 #define regUMCCH7_1_PerfMonCtr7_Hi 0x80f58 1331 #define regUMCCH7_1_PerfMonCtr7_Hi_BASE_IDX 1 1332 #define regUMCCH7_1_PerfMonCtl8 0x80f59 1333 #define regUMCCH7_1_PerfMonCtl8_BASE_IDX 1 1334 #define regUMCCH7_1_PerfMonCtr8_Lo 0x80f5a 1335 #define regUMCCH7_1_PerfMonCtr8_Lo_BASE_IDX 1 1336 #define regUMCCH7_1_PerfMonCtr8_Hi 0x80f5b 1337 #define regUMCCH7_1_PerfMonCtr8_Hi_BASE_IDX 1 1338 1339 1340 // addressBlock: umc_w_phy_umc2_umcch0_umcchdec 1341 // base address: 0x450000 1342 #define regUMCCH0_2_BaseAddrCS0 0xc0000 1343 #define regUMCCH0_2_BaseAddrCS0_BASE_IDX 1 1344 #define regUMCCH0_2_AddrMaskCS01 0xc0008 1345 #define regUMCCH0_2_AddrMaskCS01_BASE_IDX 1 1346 #define regUMCCH0_2_AddrSelCS01 0xc0010 1347 #define regUMCCH0_2_AddrSelCS01_BASE_IDX 1 1348 #define regUMCCH0_2_AddrHashBank0 0xc0032 1349 #define regUMCCH0_2_AddrHashBank0_BASE_IDX 1 1350 #define regUMCCH0_2_AddrHashBank1 0xc0033 1351 #define regUMCCH0_2_AddrHashBank1_BASE_IDX 1 1352 #define regUMCCH0_2_AddrHashBank2 0xc0034 1353 #define regUMCCH0_2_AddrHashBank2_BASE_IDX 1 1354 #define regUMCCH0_2_AddrHashBank3 0xc0035 1355 #define regUMCCH0_2_AddrHashBank3_BASE_IDX 1 1356 #define regUMCCH0_2_AddrHashBank4 0xc0036 1357 #define regUMCCH0_2_AddrHashBank4_BASE_IDX 1 1358 #define regUMCCH0_2_AddrHashBank5 0xc0037 1359 #define regUMCCH0_2_AddrHashBank5_BASE_IDX 1 1360 #define regUMCCH0_2_EccErrCntSel 0xc0328 1361 #define regUMCCH0_2_EccErrCntSel_BASE_IDX 1 1362 #define regUMCCH0_2_EccErrCnt 0xc0329 1363 #define regUMCCH0_2_EccErrCnt_BASE_IDX 1 1364 #define regUMCCH0_2_PerfMonCtlClk 0xc0340 1365 #define regUMCCH0_2_PerfMonCtlClk_BASE_IDX 1 1366 #define regUMCCH0_2_PerfMonCtrClk_Lo 0xc0341 1367 #define regUMCCH0_2_PerfMonCtrClk_Lo_BASE_IDX 1 1368 #define regUMCCH0_2_PerfMonCtrClk_Hi 0xc0342 1369 #define regUMCCH0_2_PerfMonCtrClk_Hi_BASE_IDX 1 1370 #define regUMCCH0_2_PerfMonCtl1 0xc0344 1371 #define regUMCCH0_2_PerfMonCtl1_BASE_IDX 1 1372 #define regUMCCH0_2_PerfMonCtr1_Lo 0xc0345 1373 #define regUMCCH0_2_PerfMonCtr1_Lo_BASE_IDX 1 1374 #define regUMCCH0_2_PerfMonCtr1_Hi 0xc0346 1375 #define regUMCCH0_2_PerfMonCtr1_Hi_BASE_IDX 1 1376 #define regUMCCH0_2_PerfMonCtl2 0xc0347 1377 #define regUMCCH0_2_PerfMonCtl2_BASE_IDX 1 1378 #define regUMCCH0_2_PerfMonCtr2_Lo 0xc0348 1379 #define regUMCCH0_2_PerfMonCtr2_Lo_BASE_IDX 1 1380 #define regUMCCH0_2_PerfMonCtr2_Hi 0xc0349 1381 #define regUMCCH0_2_PerfMonCtr2_Hi_BASE_IDX 1 1382 #define regUMCCH0_2_PerfMonCtl3 0xc034a 1383 #define regUMCCH0_2_PerfMonCtl3_BASE_IDX 1 1384 #define regUMCCH0_2_PerfMonCtr3_Lo 0xc034b 1385 #define regUMCCH0_2_PerfMonCtr3_Lo_BASE_IDX 1 1386 #define regUMCCH0_2_PerfMonCtr3_Hi 0xc034c 1387 #define regUMCCH0_2_PerfMonCtr3_Hi_BASE_IDX 1 1388 #define regUMCCH0_2_PerfMonCtl4 0xc034d 1389 #define regUMCCH0_2_PerfMonCtl4_BASE_IDX 1 1390 #define regUMCCH0_2_PerfMonCtr4_Lo 0xc034e 1391 #define regUMCCH0_2_PerfMonCtr4_Lo_BASE_IDX 1 1392 #define regUMCCH0_2_PerfMonCtr4_Hi 0xc034f 1393 #define regUMCCH0_2_PerfMonCtr4_Hi_BASE_IDX 1 1394 #define regUMCCH0_2_PerfMonCtl5 0xc0350 1395 #define regUMCCH0_2_PerfMonCtl5_BASE_IDX 1 1396 #define regUMCCH0_2_PerfMonCtr5_Lo 0xc0351 1397 #define regUMCCH0_2_PerfMonCtr5_Lo_BASE_IDX 1 1398 #define regUMCCH0_2_PerfMonCtr5_Hi 0xc0352 1399 #define regUMCCH0_2_PerfMonCtr5_Hi_BASE_IDX 1 1400 #define regUMCCH0_2_PerfMonCtl6 0xc0353 1401 #define regUMCCH0_2_PerfMonCtl6_BASE_IDX 1 1402 #define regUMCCH0_2_PerfMonCtr6_Lo 0xc0354 1403 #define regUMCCH0_2_PerfMonCtr6_Lo_BASE_IDX 1 1404 #define regUMCCH0_2_PerfMonCtr6_Hi 0xc0355 1405 #define regUMCCH0_2_PerfMonCtr6_Hi_BASE_IDX 1 1406 #define regUMCCH0_2_PerfMonCtl7 0xc0356 1407 #define regUMCCH0_2_PerfMonCtl7_BASE_IDX 1 1408 #define regUMCCH0_2_PerfMonCtr7_Lo 0xc0357 1409 #define regUMCCH0_2_PerfMonCtr7_Lo_BASE_IDX 1 1410 #define regUMCCH0_2_PerfMonCtr7_Hi 0xc0358 1411 #define regUMCCH0_2_PerfMonCtr7_Hi_BASE_IDX 1 1412 #define regUMCCH0_2_PerfMonCtl8 0xc0359 1413 #define regUMCCH0_2_PerfMonCtl8_BASE_IDX 1 1414 #define regUMCCH0_2_PerfMonCtr8_Lo 0xc035a 1415 #define regUMCCH0_2_PerfMonCtr8_Lo_BASE_IDX 1 1416 #define regUMCCH0_2_PerfMonCtr8_Hi 0xc035b 1417 #define regUMCCH0_2_PerfMonCtr8_Hi_BASE_IDX 1 1418 1419 1420 // addressBlock: umc_w_phy_umc2_umcch1_umcchdec 1421 // base address: 0x451000 1422 #define regUMCCH1_2_BaseAddrCS0 0xc0400 1423 #define regUMCCH1_2_BaseAddrCS0_BASE_IDX 1 1424 #define regUMCCH1_2_AddrMaskCS01 0xc0408 1425 #define regUMCCH1_2_AddrMaskCS01_BASE_IDX 1 1426 #define regUMCCH1_2_AddrSelCS01 0xc0410 1427 #define regUMCCH1_2_AddrSelCS01_BASE_IDX 1 1428 #define regUMCCH1_2_AddrHashBank0 0xc0432 1429 #define regUMCCH1_2_AddrHashBank0_BASE_IDX 1 1430 #define regUMCCH1_2_AddrHashBank1 0xc0433 1431 #define regUMCCH1_2_AddrHashBank1_BASE_IDX 1 1432 #define regUMCCH1_2_AddrHashBank2 0xc0434 1433 #define regUMCCH1_2_AddrHashBank2_BASE_IDX 1 1434 #define regUMCCH1_2_AddrHashBank3 0xc0435 1435 #define regUMCCH1_2_AddrHashBank3_BASE_IDX 1 1436 #define regUMCCH1_2_AddrHashBank4 0xc0436 1437 #define regUMCCH1_2_AddrHashBank4_BASE_IDX 1 1438 #define regUMCCH1_2_AddrHashBank5 0xc0437 1439 #define regUMCCH1_2_AddrHashBank5_BASE_IDX 1 1440 #define regUMCCH1_2_EccErrCntSel 0xc0728 1441 #define regUMCCH1_2_EccErrCntSel_BASE_IDX 1 1442 #define regUMCCH1_2_EccErrCnt 0xc0729 1443 #define regUMCCH1_2_EccErrCnt_BASE_IDX 1 1444 #define regUMCCH1_2_PerfMonCtlClk 0xc0740 1445 #define regUMCCH1_2_PerfMonCtlClk_BASE_IDX 1 1446 #define regUMCCH1_2_PerfMonCtrClk_Lo 0xc0741 1447 #define regUMCCH1_2_PerfMonCtrClk_Lo_BASE_IDX 1 1448 #define regUMCCH1_2_PerfMonCtrClk_Hi 0xc0742 1449 #define regUMCCH1_2_PerfMonCtrClk_Hi_BASE_IDX 1 1450 #define regUMCCH1_2_PerfMonCtl1 0xc0744 1451 #define regUMCCH1_2_PerfMonCtl1_BASE_IDX 1 1452 #define regUMCCH1_2_PerfMonCtr1_Lo 0xc0745 1453 #define regUMCCH1_2_PerfMonCtr1_Lo_BASE_IDX 1 1454 #define regUMCCH1_2_PerfMonCtr1_Hi 0xc0746 1455 #define regUMCCH1_2_PerfMonCtr1_Hi_BASE_IDX 1 1456 #define regUMCCH1_2_PerfMonCtl2 0xc0747 1457 #define regUMCCH1_2_PerfMonCtl2_BASE_IDX 1 1458 #define regUMCCH1_2_PerfMonCtr2_Lo 0xc0748 1459 #define regUMCCH1_2_PerfMonCtr2_Lo_BASE_IDX 1 1460 #define regUMCCH1_2_PerfMonCtr2_Hi 0xc0749 1461 #define regUMCCH1_2_PerfMonCtr2_Hi_BASE_IDX 1 1462 #define regUMCCH1_2_PerfMonCtl3 0xc074a 1463 #define regUMCCH1_2_PerfMonCtl3_BASE_IDX 1 1464 #define regUMCCH1_2_PerfMonCtr3_Lo 0xc074b 1465 #define regUMCCH1_2_PerfMonCtr3_Lo_BASE_IDX 1 1466 #define regUMCCH1_2_PerfMonCtr3_Hi 0xc074c 1467 #define regUMCCH1_2_PerfMonCtr3_Hi_BASE_IDX 1 1468 #define regUMCCH1_2_PerfMonCtl4 0xc074d 1469 #define regUMCCH1_2_PerfMonCtl4_BASE_IDX 1 1470 #define regUMCCH1_2_PerfMonCtr4_Lo 0xc074e 1471 #define regUMCCH1_2_PerfMonCtr4_Lo_BASE_IDX 1 1472 #define regUMCCH1_2_PerfMonCtr4_Hi 0xc074f 1473 #define regUMCCH1_2_PerfMonCtr4_Hi_BASE_IDX 1 1474 #define regUMCCH1_2_PerfMonCtl5 0xc0750 1475 #define regUMCCH1_2_PerfMonCtl5_BASE_IDX 1 1476 #define regUMCCH1_2_PerfMonCtr5_Lo 0xc0751 1477 #define regUMCCH1_2_PerfMonCtr5_Lo_BASE_IDX 1 1478 #define regUMCCH1_2_PerfMonCtr5_Hi 0xc0752 1479 #define regUMCCH1_2_PerfMonCtr5_Hi_BASE_IDX 1 1480 #define regUMCCH1_2_PerfMonCtl6 0xc0753 1481 #define regUMCCH1_2_PerfMonCtl6_BASE_IDX 1 1482 #define regUMCCH1_2_PerfMonCtr6_Lo 0xc0754 1483 #define regUMCCH1_2_PerfMonCtr6_Lo_BASE_IDX 1 1484 #define regUMCCH1_2_PerfMonCtr6_Hi 0xc0755 1485 #define regUMCCH1_2_PerfMonCtr6_Hi_BASE_IDX 1 1486 #define regUMCCH1_2_PerfMonCtl7 0xc0756 1487 #define regUMCCH1_2_PerfMonCtl7_BASE_IDX 1 1488 #define regUMCCH1_2_PerfMonCtr7_Lo 0xc0757 1489 #define regUMCCH1_2_PerfMonCtr7_Lo_BASE_IDX 1 1490 #define regUMCCH1_2_PerfMonCtr7_Hi 0xc0758 1491 #define regUMCCH1_2_PerfMonCtr7_Hi_BASE_IDX 1 1492 #define regUMCCH1_2_PerfMonCtl8 0xc0759 1493 #define regUMCCH1_2_PerfMonCtl8_BASE_IDX 1 1494 #define regUMCCH1_2_PerfMonCtr8_Lo 0xc075a 1495 #define regUMCCH1_2_PerfMonCtr8_Lo_BASE_IDX 1 1496 #define regUMCCH1_2_PerfMonCtr8_Hi 0xc075b 1497 #define regUMCCH1_2_PerfMonCtr8_Hi_BASE_IDX 1 1498 1499 1500 // addressBlock: umc_w_phy_umc2_umcch2_umcchdec 1501 // base address: 0x452000 1502 #define regUMCCH2_2_BaseAddrCS0 0xc0800 1503 #define regUMCCH2_2_BaseAddrCS0_BASE_IDX 1 1504 #define regUMCCH2_2_AddrMaskCS01 0xc0808 1505 #define regUMCCH2_2_AddrMaskCS01_BASE_IDX 1 1506 #define regUMCCH2_2_AddrSelCS01 0xc0810 1507 #define regUMCCH2_2_AddrSelCS01_BASE_IDX 1 1508 #define regUMCCH2_2_AddrHashBank0 0xc0832 1509 #define regUMCCH2_2_AddrHashBank0_BASE_IDX 1 1510 #define regUMCCH2_2_AddrHashBank1 0xc0833 1511 #define regUMCCH2_2_AddrHashBank1_BASE_IDX 1 1512 #define regUMCCH2_2_AddrHashBank2 0xc0834 1513 #define regUMCCH2_2_AddrHashBank2_BASE_IDX 1 1514 #define regUMCCH2_2_AddrHashBank3 0xc0835 1515 #define regUMCCH2_2_AddrHashBank3_BASE_IDX 1 1516 #define regUMCCH2_2_AddrHashBank4 0xc0836 1517 #define regUMCCH2_2_AddrHashBank4_BASE_IDX 1 1518 #define regUMCCH2_2_AddrHashBank5 0xc0837 1519 #define regUMCCH2_2_AddrHashBank5_BASE_IDX 1 1520 #define regUMCCH2_2_EccErrCntSel 0xc0b28 1521 #define regUMCCH2_2_EccErrCntSel_BASE_IDX 1 1522 #define regUMCCH2_2_EccErrCnt 0xc0b29 1523 #define regUMCCH2_2_EccErrCnt_BASE_IDX 1 1524 #define regUMCCH2_2_PerfMonCtlClk 0xc0b40 1525 #define regUMCCH2_2_PerfMonCtlClk_BASE_IDX 1 1526 #define regUMCCH2_2_PerfMonCtrClk_Lo 0xc0b41 1527 #define regUMCCH2_2_PerfMonCtrClk_Lo_BASE_IDX 1 1528 #define regUMCCH2_2_PerfMonCtrClk_Hi 0xc0b42 1529 #define regUMCCH2_2_PerfMonCtrClk_Hi_BASE_IDX 1 1530 #define regUMCCH2_2_PerfMonCtl1 0xc0b44 1531 #define regUMCCH2_2_PerfMonCtl1_BASE_IDX 1 1532 #define regUMCCH2_2_PerfMonCtr1_Lo 0xc0b45 1533 #define regUMCCH2_2_PerfMonCtr1_Lo_BASE_IDX 1 1534 #define regUMCCH2_2_PerfMonCtr1_Hi 0xc0b46 1535 #define regUMCCH2_2_PerfMonCtr1_Hi_BASE_IDX 1 1536 #define regUMCCH2_2_PerfMonCtl2 0xc0b47 1537 #define regUMCCH2_2_PerfMonCtl2_BASE_IDX 1 1538 #define regUMCCH2_2_PerfMonCtr2_Lo 0xc0b48 1539 #define regUMCCH2_2_PerfMonCtr2_Lo_BASE_IDX 1 1540 #define regUMCCH2_2_PerfMonCtr2_Hi 0xc0b49 1541 #define regUMCCH2_2_PerfMonCtr2_Hi_BASE_IDX 1 1542 #define regUMCCH2_2_PerfMonCtl3 0xc0b4a 1543 #define regUMCCH2_2_PerfMonCtl3_BASE_IDX 1 1544 #define regUMCCH2_2_PerfMonCtr3_Lo 0xc0b4b 1545 #define regUMCCH2_2_PerfMonCtr3_Lo_BASE_IDX 1 1546 #define regUMCCH2_2_PerfMonCtr3_Hi 0xc0b4c 1547 #define regUMCCH2_2_PerfMonCtr3_Hi_BASE_IDX 1 1548 #define regUMCCH2_2_PerfMonCtl4 0xc0b4d 1549 #define regUMCCH2_2_PerfMonCtl4_BASE_IDX 1 1550 #define regUMCCH2_2_PerfMonCtr4_Lo 0xc0b4e 1551 #define regUMCCH2_2_PerfMonCtr4_Lo_BASE_IDX 1 1552 #define regUMCCH2_2_PerfMonCtr4_Hi 0xc0b4f 1553 #define regUMCCH2_2_PerfMonCtr4_Hi_BASE_IDX 1 1554 #define regUMCCH2_2_PerfMonCtl5 0xc0b50 1555 #define regUMCCH2_2_PerfMonCtl5_BASE_IDX 1 1556 #define regUMCCH2_2_PerfMonCtr5_Lo 0xc0b51 1557 #define regUMCCH2_2_PerfMonCtr5_Lo_BASE_IDX 1 1558 #define regUMCCH2_2_PerfMonCtr5_Hi 0xc0b52 1559 #define regUMCCH2_2_PerfMonCtr5_Hi_BASE_IDX 1 1560 #define regUMCCH2_2_PerfMonCtl6 0xc0b53 1561 #define regUMCCH2_2_PerfMonCtl6_BASE_IDX 1 1562 #define regUMCCH2_2_PerfMonCtr6_Lo 0xc0b54 1563 #define regUMCCH2_2_PerfMonCtr6_Lo_BASE_IDX 1 1564 #define regUMCCH2_2_PerfMonCtr6_Hi 0xc0b55 1565 #define regUMCCH2_2_PerfMonCtr6_Hi_BASE_IDX 1 1566 #define regUMCCH2_2_PerfMonCtl7 0xc0b56 1567 #define regUMCCH2_2_PerfMonCtl7_BASE_IDX 1 1568 #define regUMCCH2_2_PerfMonCtr7_Lo 0xc0b57 1569 #define regUMCCH2_2_PerfMonCtr7_Lo_BASE_IDX 1 1570 #define regUMCCH2_2_PerfMonCtr7_Hi 0xc0b58 1571 #define regUMCCH2_2_PerfMonCtr7_Hi_BASE_IDX 1 1572 #define regUMCCH2_2_PerfMonCtl8 0xc0b59 1573 #define regUMCCH2_2_PerfMonCtl8_BASE_IDX 1 1574 #define regUMCCH2_2_PerfMonCtr8_Lo 0xc0b5a 1575 #define regUMCCH2_2_PerfMonCtr8_Lo_BASE_IDX 1 1576 #define regUMCCH2_2_PerfMonCtr8_Hi 0xc0b5b 1577 #define regUMCCH2_2_PerfMonCtr8_Hi_BASE_IDX 1 1578 1579 1580 // addressBlock: umc_w_phy_umc2_umcch3_umcchdec 1581 // base address: 0x453000 1582 #define regUMCCH3_2_BaseAddrCS0 0xc0c00 1583 #define regUMCCH3_2_BaseAddrCS0_BASE_IDX 1 1584 #define regUMCCH3_2_AddrMaskCS01 0xc0c08 1585 #define regUMCCH3_2_AddrMaskCS01_BASE_IDX 1 1586 #define regUMCCH3_2_AddrSelCS01 0xc0c10 1587 #define regUMCCH3_2_AddrSelCS01_BASE_IDX 1 1588 #define regUMCCH3_2_AddrHashBank0 0xc0c32 1589 #define regUMCCH3_2_AddrHashBank0_BASE_IDX 1 1590 #define regUMCCH3_2_AddrHashBank1 0xc0c33 1591 #define regUMCCH3_2_AddrHashBank1_BASE_IDX 1 1592 #define regUMCCH3_2_AddrHashBank2 0xc0c34 1593 #define regUMCCH3_2_AddrHashBank2_BASE_IDX 1 1594 #define regUMCCH3_2_AddrHashBank3 0xc0c35 1595 #define regUMCCH3_2_AddrHashBank3_BASE_IDX 1 1596 #define regUMCCH3_2_AddrHashBank4 0xc0c36 1597 #define regUMCCH3_2_AddrHashBank4_BASE_IDX 1 1598 #define regUMCCH3_2_AddrHashBank5 0xc0c37 1599 #define regUMCCH3_2_AddrHashBank5_BASE_IDX 1 1600 #define regUMCCH3_2_EccErrCntSel 0xc0f28 1601 #define regUMCCH3_2_EccErrCntSel_BASE_IDX 1 1602 #define regUMCCH3_2_EccErrCnt 0xc0f29 1603 #define regUMCCH3_2_EccErrCnt_BASE_IDX 1 1604 #define regUMCCH3_2_PerfMonCtlClk 0xc0f40 1605 #define regUMCCH3_2_PerfMonCtlClk_BASE_IDX 1 1606 #define regUMCCH3_2_PerfMonCtrClk_Lo 0xc0f41 1607 #define regUMCCH3_2_PerfMonCtrClk_Lo_BASE_IDX 1 1608 #define regUMCCH3_2_PerfMonCtrClk_Hi 0xc0f42 1609 #define regUMCCH3_2_PerfMonCtrClk_Hi_BASE_IDX 1 1610 #define regUMCCH3_2_PerfMonCtl1 0xc0f44 1611 #define regUMCCH3_2_PerfMonCtl1_BASE_IDX 1 1612 #define regUMCCH3_2_PerfMonCtr1_Lo 0xc0f45 1613 #define regUMCCH3_2_PerfMonCtr1_Lo_BASE_IDX 1 1614 #define regUMCCH3_2_PerfMonCtr1_Hi 0xc0f46 1615 #define regUMCCH3_2_PerfMonCtr1_Hi_BASE_IDX 1 1616 #define regUMCCH3_2_PerfMonCtl2 0xc0f47 1617 #define regUMCCH3_2_PerfMonCtl2_BASE_IDX 1 1618 #define regUMCCH3_2_PerfMonCtr2_Lo 0xc0f48 1619 #define regUMCCH3_2_PerfMonCtr2_Lo_BASE_IDX 1 1620 #define regUMCCH3_2_PerfMonCtr2_Hi 0xc0f49 1621 #define regUMCCH3_2_PerfMonCtr2_Hi_BASE_IDX 1 1622 #define regUMCCH3_2_PerfMonCtl3 0xc0f4a 1623 #define regUMCCH3_2_PerfMonCtl3_BASE_IDX 1 1624 #define regUMCCH3_2_PerfMonCtr3_Lo 0xc0f4b 1625 #define regUMCCH3_2_PerfMonCtr3_Lo_BASE_IDX 1 1626 #define regUMCCH3_2_PerfMonCtr3_Hi 0xc0f4c 1627 #define regUMCCH3_2_PerfMonCtr3_Hi_BASE_IDX 1 1628 #define regUMCCH3_2_PerfMonCtl4 0xc0f4d 1629 #define regUMCCH3_2_PerfMonCtl4_BASE_IDX 1 1630 #define regUMCCH3_2_PerfMonCtr4_Lo 0xc0f4e 1631 #define regUMCCH3_2_PerfMonCtr4_Lo_BASE_IDX 1 1632 #define regUMCCH3_2_PerfMonCtr4_Hi 0xc0f4f 1633 #define regUMCCH3_2_PerfMonCtr4_Hi_BASE_IDX 1 1634 #define regUMCCH3_2_PerfMonCtl5 0xc0f50 1635 #define regUMCCH3_2_PerfMonCtl5_BASE_IDX 1 1636 #define regUMCCH3_2_PerfMonCtr5_Lo 0xc0f51 1637 #define regUMCCH3_2_PerfMonCtr5_Lo_BASE_IDX 1 1638 #define regUMCCH3_2_PerfMonCtr5_Hi 0xc0f52 1639 #define regUMCCH3_2_PerfMonCtr5_Hi_BASE_IDX 1 1640 #define regUMCCH3_2_PerfMonCtl6 0xc0f53 1641 #define regUMCCH3_2_PerfMonCtl6_BASE_IDX 1 1642 #define regUMCCH3_2_PerfMonCtr6_Lo 0xc0f54 1643 #define regUMCCH3_2_PerfMonCtr6_Lo_BASE_IDX 1 1644 #define regUMCCH3_2_PerfMonCtr6_Hi 0xc0f55 1645 #define regUMCCH3_2_PerfMonCtr6_Hi_BASE_IDX 1 1646 #define regUMCCH3_2_PerfMonCtl7 0xc0f56 1647 #define regUMCCH3_2_PerfMonCtl7_BASE_IDX 1 1648 #define regUMCCH3_2_PerfMonCtr7_Lo 0xc0f57 1649 #define regUMCCH3_2_PerfMonCtr7_Lo_BASE_IDX 1 1650 #define regUMCCH3_2_PerfMonCtr7_Hi 0xc0f58 1651 #define regUMCCH3_2_PerfMonCtr7_Hi_BASE_IDX 1 1652 #define regUMCCH3_2_PerfMonCtl8 0xc0f59 1653 #define regUMCCH3_2_PerfMonCtl8_BASE_IDX 1 1654 #define regUMCCH3_2_PerfMonCtr8_Lo 0xc0f5a 1655 #define regUMCCH3_2_PerfMonCtr8_Lo_BASE_IDX 1 1656 #define regUMCCH3_2_PerfMonCtr8_Hi 0xc0f5b 1657 #define regUMCCH3_2_PerfMonCtr8_Hi_BASE_IDX 1 1658 1659 1660 // addressBlock: umc_w_phy_umc2_umcch4_umcchdec 1661 // base address: 0x550000 1662 #define regUMCCH4_2_BaseAddrCS0 0x100000 1663 #define regUMCCH4_2_BaseAddrCS0_BASE_IDX 1 1664 #define regUMCCH4_2_AddrMaskCS01 0x100008 1665 #define regUMCCH4_2_AddrMaskCS01_BASE_IDX 1 1666 #define regUMCCH4_2_AddrSelCS01 0x100010 1667 #define regUMCCH4_2_AddrSelCS01_BASE_IDX 1 1668 #define regUMCCH4_2_AddrHashBank0 0x100032 1669 #define regUMCCH4_2_AddrHashBank0_BASE_IDX 1 1670 #define regUMCCH4_2_AddrHashBank1 0x100033 1671 #define regUMCCH4_2_AddrHashBank1_BASE_IDX 1 1672 #define regUMCCH4_2_AddrHashBank2 0x100034 1673 #define regUMCCH4_2_AddrHashBank2_BASE_IDX 1 1674 #define regUMCCH4_2_AddrHashBank3 0x100035 1675 #define regUMCCH4_2_AddrHashBank3_BASE_IDX 1 1676 #define regUMCCH4_2_AddrHashBank4 0x100036 1677 #define regUMCCH4_2_AddrHashBank4_BASE_IDX 1 1678 #define regUMCCH4_2_AddrHashBank5 0x100037 1679 #define regUMCCH4_2_AddrHashBank5_BASE_IDX 1 1680 #define regUMCCH4_2_EccErrCntSel 0x100328 1681 #define regUMCCH4_2_EccErrCntSel_BASE_IDX 1 1682 #define regUMCCH4_2_EccErrCnt 0x100329 1683 #define regUMCCH4_2_EccErrCnt_BASE_IDX 1 1684 #define regUMCCH4_2_PerfMonCtlClk 0x100340 1685 #define regUMCCH4_2_PerfMonCtlClk_BASE_IDX 1 1686 #define regUMCCH4_2_PerfMonCtrClk_Lo 0x100341 1687 #define regUMCCH4_2_PerfMonCtrClk_Lo_BASE_IDX 1 1688 #define regUMCCH4_2_PerfMonCtrClk_Hi 0x100342 1689 #define regUMCCH4_2_PerfMonCtrClk_Hi_BASE_IDX 1 1690 #define regUMCCH4_2_PerfMonCtl1 0x100344 1691 #define regUMCCH4_2_PerfMonCtl1_BASE_IDX 1 1692 #define regUMCCH4_2_PerfMonCtr1_Lo 0x100345 1693 #define regUMCCH4_2_PerfMonCtr1_Lo_BASE_IDX 1 1694 #define regUMCCH4_2_PerfMonCtr1_Hi 0x100346 1695 #define regUMCCH4_2_PerfMonCtr1_Hi_BASE_IDX 1 1696 #define regUMCCH4_2_PerfMonCtl2 0x100347 1697 #define regUMCCH4_2_PerfMonCtl2_BASE_IDX 1 1698 #define regUMCCH4_2_PerfMonCtr2_Lo 0x100348 1699 #define regUMCCH4_2_PerfMonCtr2_Lo_BASE_IDX 1 1700 #define regUMCCH4_2_PerfMonCtr2_Hi 0x100349 1701 #define regUMCCH4_2_PerfMonCtr2_Hi_BASE_IDX 1 1702 #define regUMCCH4_2_PerfMonCtl3 0x10034a 1703 #define regUMCCH4_2_PerfMonCtl3_BASE_IDX 1 1704 #define regUMCCH4_2_PerfMonCtr3_Lo 0x10034b 1705 #define regUMCCH4_2_PerfMonCtr3_Lo_BASE_IDX 1 1706 #define regUMCCH4_2_PerfMonCtr3_Hi 0x10034c 1707 #define regUMCCH4_2_PerfMonCtr3_Hi_BASE_IDX 1 1708 #define regUMCCH4_2_PerfMonCtl4 0x10034d 1709 #define regUMCCH4_2_PerfMonCtl4_BASE_IDX 1 1710 #define regUMCCH4_2_PerfMonCtr4_Lo 0x10034e 1711 #define regUMCCH4_2_PerfMonCtr4_Lo_BASE_IDX 1 1712 #define regUMCCH4_2_PerfMonCtr4_Hi 0x10034f 1713 #define regUMCCH4_2_PerfMonCtr4_Hi_BASE_IDX 1 1714 #define regUMCCH4_2_PerfMonCtl5 0x100350 1715 #define regUMCCH4_2_PerfMonCtl5_BASE_IDX 1 1716 #define regUMCCH4_2_PerfMonCtr5_Lo 0x100351 1717 #define regUMCCH4_2_PerfMonCtr5_Lo_BASE_IDX 1 1718 #define regUMCCH4_2_PerfMonCtr5_Hi 0x100352 1719 #define regUMCCH4_2_PerfMonCtr5_Hi_BASE_IDX 1 1720 #define regUMCCH4_2_PerfMonCtl6 0x100353 1721 #define regUMCCH4_2_PerfMonCtl6_BASE_IDX 1 1722 #define regUMCCH4_2_PerfMonCtr6_Lo 0x100354 1723 #define regUMCCH4_2_PerfMonCtr6_Lo_BASE_IDX 1 1724 #define regUMCCH4_2_PerfMonCtr6_Hi 0x100355 1725 #define regUMCCH4_2_PerfMonCtr6_Hi_BASE_IDX 1 1726 #define regUMCCH4_2_PerfMonCtl7 0x100356 1727 #define regUMCCH4_2_PerfMonCtl7_BASE_IDX 1 1728 #define regUMCCH4_2_PerfMonCtr7_Lo 0x100357 1729 #define regUMCCH4_2_PerfMonCtr7_Lo_BASE_IDX 1 1730 #define regUMCCH4_2_PerfMonCtr7_Hi 0x100358 1731 #define regUMCCH4_2_PerfMonCtr7_Hi_BASE_IDX 1 1732 #define regUMCCH4_2_PerfMonCtl8 0x100359 1733 #define regUMCCH4_2_PerfMonCtl8_BASE_IDX 1 1734 #define regUMCCH4_2_PerfMonCtr8_Lo 0x10035a 1735 #define regUMCCH4_2_PerfMonCtr8_Lo_BASE_IDX 1 1736 #define regUMCCH4_2_PerfMonCtr8_Hi 0x10035b 1737 #define regUMCCH4_2_PerfMonCtr8_Hi_BASE_IDX 1 1738 1739 1740 // addressBlock: umc_w_phy_umc2_umcch5_umcchdec 1741 // base address: 0x551000 1742 #define regUMCCH5_2_BaseAddrCS0 0x100400 1743 #define regUMCCH5_2_BaseAddrCS0_BASE_IDX 1 1744 #define regUMCCH5_2_AddrMaskCS01 0x100408 1745 #define regUMCCH5_2_AddrMaskCS01_BASE_IDX 1 1746 #define regUMCCH5_2_AddrSelCS01 0x100410 1747 #define regUMCCH5_2_AddrSelCS01_BASE_IDX 1 1748 #define regUMCCH5_2_AddrHashBank0 0x100432 1749 #define regUMCCH5_2_AddrHashBank0_BASE_IDX 1 1750 #define regUMCCH5_2_AddrHashBank1 0x100433 1751 #define regUMCCH5_2_AddrHashBank1_BASE_IDX 1 1752 #define regUMCCH5_2_AddrHashBank2 0x100434 1753 #define regUMCCH5_2_AddrHashBank2_BASE_IDX 1 1754 #define regUMCCH5_2_AddrHashBank3 0x100435 1755 #define regUMCCH5_2_AddrHashBank3_BASE_IDX 1 1756 #define regUMCCH5_2_AddrHashBank4 0x100436 1757 #define regUMCCH5_2_AddrHashBank4_BASE_IDX 1 1758 #define regUMCCH5_2_AddrHashBank5 0x100437 1759 #define regUMCCH5_2_AddrHashBank5_BASE_IDX 1 1760 #define regUMCCH5_2_EccErrCntSel 0x100728 1761 #define regUMCCH5_2_EccErrCntSel_BASE_IDX 1 1762 #define regUMCCH5_2_EccErrCnt 0x100729 1763 #define regUMCCH5_2_EccErrCnt_BASE_IDX 1 1764 #define regUMCCH5_2_PerfMonCtlClk 0x100740 1765 #define regUMCCH5_2_PerfMonCtlClk_BASE_IDX 1 1766 #define regUMCCH5_2_PerfMonCtrClk_Lo 0x100741 1767 #define regUMCCH5_2_PerfMonCtrClk_Lo_BASE_IDX 1 1768 #define regUMCCH5_2_PerfMonCtrClk_Hi 0x100742 1769 #define regUMCCH5_2_PerfMonCtrClk_Hi_BASE_IDX 1 1770 #define regUMCCH5_2_PerfMonCtl1 0x100744 1771 #define regUMCCH5_2_PerfMonCtl1_BASE_IDX 1 1772 #define regUMCCH5_2_PerfMonCtr1_Lo 0x100745 1773 #define regUMCCH5_2_PerfMonCtr1_Lo_BASE_IDX 1 1774 #define regUMCCH5_2_PerfMonCtr1_Hi 0x100746 1775 #define regUMCCH5_2_PerfMonCtr1_Hi_BASE_IDX 1 1776 #define regUMCCH5_2_PerfMonCtl2 0x100747 1777 #define regUMCCH5_2_PerfMonCtl2_BASE_IDX 1 1778 #define regUMCCH5_2_PerfMonCtr2_Lo 0x100748 1779 #define regUMCCH5_2_PerfMonCtr2_Lo_BASE_IDX 1 1780 #define regUMCCH5_2_PerfMonCtr2_Hi 0x100749 1781 #define regUMCCH5_2_PerfMonCtr2_Hi_BASE_IDX 1 1782 #define regUMCCH5_2_PerfMonCtl3 0x10074a 1783 #define regUMCCH5_2_PerfMonCtl3_BASE_IDX 1 1784 #define regUMCCH5_2_PerfMonCtr3_Lo 0x10074b 1785 #define regUMCCH5_2_PerfMonCtr3_Lo_BASE_IDX 1 1786 #define regUMCCH5_2_PerfMonCtr3_Hi 0x10074c 1787 #define regUMCCH5_2_PerfMonCtr3_Hi_BASE_IDX 1 1788 #define regUMCCH5_2_PerfMonCtl4 0x10074d 1789 #define regUMCCH5_2_PerfMonCtl4_BASE_IDX 1 1790 #define regUMCCH5_2_PerfMonCtr4_Lo 0x10074e 1791 #define regUMCCH5_2_PerfMonCtr4_Lo_BASE_IDX 1 1792 #define regUMCCH5_2_PerfMonCtr4_Hi 0x10074f 1793 #define regUMCCH5_2_PerfMonCtr4_Hi_BASE_IDX 1 1794 #define regUMCCH5_2_PerfMonCtl5 0x100750 1795 #define regUMCCH5_2_PerfMonCtl5_BASE_IDX 1 1796 #define regUMCCH5_2_PerfMonCtr5_Lo 0x100751 1797 #define regUMCCH5_2_PerfMonCtr5_Lo_BASE_IDX 1 1798 #define regUMCCH5_2_PerfMonCtr5_Hi 0x100752 1799 #define regUMCCH5_2_PerfMonCtr5_Hi_BASE_IDX 1 1800 #define regUMCCH5_2_PerfMonCtl6 0x100753 1801 #define regUMCCH5_2_PerfMonCtl6_BASE_IDX 1 1802 #define regUMCCH5_2_PerfMonCtr6_Lo 0x100754 1803 #define regUMCCH5_2_PerfMonCtr6_Lo_BASE_IDX 1 1804 #define regUMCCH5_2_PerfMonCtr6_Hi 0x100755 1805 #define regUMCCH5_2_PerfMonCtr6_Hi_BASE_IDX 1 1806 #define regUMCCH5_2_PerfMonCtl7 0x100756 1807 #define regUMCCH5_2_PerfMonCtl7_BASE_IDX 1 1808 #define regUMCCH5_2_PerfMonCtr7_Lo 0x100757 1809 #define regUMCCH5_2_PerfMonCtr7_Lo_BASE_IDX 1 1810 #define regUMCCH5_2_PerfMonCtr7_Hi 0x100758 1811 #define regUMCCH5_2_PerfMonCtr7_Hi_BASE_IDX 1 1812 #define regUMCCH5_2_PerfMonCtl8 0x100759 1813 #define regUMCCH5_2_PerfMonCtl8_BASE_IDX 1 1814 #define regUMCCH5_2_PerfMonCtr8_Lo 0x10075a 1815 #define regUMCCH5_2_PerfMonCtr8_Lo_BASE_IDX 1 1816 #define regUMCCH5_2_PerfMonCtr8_Hi 0x10075b 1817 #define regUMCCH5_2_PerfMonCtr8_Hi_BASE_IDX 1 1818 1819 1820 // addressBlock: umc_w_phy_umc2_umcch6_umcchdec 1821 // base address: 0x552000 1822 #define regUMCCH6_2_BaseAddrCS0 0x100800 1823 #define regUMCCH6_2_BaseAddrCS0_BASE_IDX 1 1824 #define regUMCCH6_2_AddrMaskCS01 0x100808 1825 #define regUMCCH6_2_AddrMaskCS01_BASE_IDX 1 1826 #define regUMCCH6_2_AddrSelCS01 0x100810 1827 #define regUMCCH6_2_AddrSelCS01_BASE_IDX 1 1828 #define regUMCCH6_2_AddrHashBank0 0x100832 1829 #define regUMCCH6_2_AddrHashBank0_BASE_IDX 1 1830 #define regUMCCH6_2_AddrHashBank1 0x100833 1831 #define regUMCCH6_2_AddrHashBank1_BASE_IDX 1 1832 #define regUMCCH6_2_AddrHashBank2 0x100834 1833 #define regUMCCH6_2_AddrHashBank2_BASE_IDX 1 1834 #define regUMCCH6_2_AddrHashBank3 0x100835 1835 #define regUMCCH6_2_AddrHashBank3_BASE_IDX 1 1836 #define regUMCCH6_2_AddrHashBank4 0x100836 1837 #define regUMCCH6_2_AddrHashBank4_BASE_IDX 1 1838 #define regUMCCH6_2_AddrHashBank5 0x100837 1839 #define regUMCCH6_2_AddrHashBank5_BASE_IDX 1 1840 #define regUMCCH6_2_EccErrCntSel 0x100b28 1841 #define regUMCCH6_2_EccErrCntSel_BASE_IDX 1 1842 #define regUMCCH6_2_EccErrCnt 0x100b29 1843 #define regUMCCH6_2_EccErrCnt_BASE_IDX 1 1844 #define regUMCCH6_2_PerfMonCtlClk 0x100b40 1845 #define regUMCCH6_2_PerfMonCtlClk_BASE_IDX 1 1846 #define regUMCCH6_2_PerfMonCtrClk_Lo 0x100b41 1847 #define regUMCCH6_2_PerfMonCtrClk_Lo_BASE_IDX 1 1848 #define regUMCCH6_2_PerfMonCtrClk_Hi 0x100b42 1849 #define regUMCCH6_2_PerfMonCtrClk_Hi_BASE_IDX 1 1850 #define regUMCCH6_2_PerfMonCtl1 0x100b44 1851 #define regUMCCH6_2_PerfMonCtl1_BASE_IDX 1 1852 #define regUMCCH6_2_PerfMonCtr1_Lo 0x100b45 1853 #define regUMCCH6_2_PerfMonCtr1_Lo_BASE_IDX 1 1854 #define regUMCCH6_2_PerfMonCtr1_Hi 0x100b46 1855 #define regUMCCH6_2_PerfMonCtr1_Hi_BASE_IDX 1 1856 #define regUMCCH6_2_PerfMonCtl2 0x100b47 1857 #define regUMCCH6_2_PerfMonCtl2_BASE_IDX 1 1858 #define regUMCCH6_2_PerfMonCtr2_Lo 0x100b48 1859 #define regUMCCH6_2_PerfMonCtr2_Lo_BASE_IDX 1 1860 #define regUMCCH6_2_PerfMonCtr2_Hi 0x100b49 1861 #define regUMCCH6_2_PerfMonCtr2_Hi_BASE_IDX 1 1862 #define regUMCCH6_2_PerfMonCtl3 0x100b4a 1863 #define regUMCCH6_2_PerfMonCtl3_BASE_IDX 1 1864 #define regUMCCH6_2_PerfMonCtr3_Lo 0x100b4b 1865 #define regUMCCH6_2_PerfMonCtr3_Lo_BASE_IDX 1 1866 #define regUMCCH6_2_PerfMonCtr3_Hi 0x100b4c 1867 #define regUMCCH6_2_PerfMonCtr3_Hi_BASE_IDX 1 1868 #define regUMCCH6_2_PerfMonCtl4 0x100b4d 1869 #define regUMCCH6_2_PerfMonCtl4_BASE_IDX 1 1870 #define regUMCCH6_2_PerfMonCtr4_Lo 0x100b4e 1871 #define regUMCCH6_2_PerfMonCtr4_Lo_BASE_IDX 1 1872 #define regUMCCH6_2_PerfMonCtr4_Hi 0x100b4f 1873 #define regUMCCH6_2_PerfMonCtr4_Hi_BASE_IDX 1 1874 #define regUMCCH6_2_PerfMonCtl5 0x100b50 1875 #define regUMCCH6_2_PerfMonCtl5_BASE_IDX 1 1876 #define regUMCCH6_2_PerfMonCtr5_Lo 0x100b51 1877 #define regUMCCH6_2_PerfMonCtr5_Lo_BASE_IDX 1 1878 #define regUMCCH6_2_PerfMonCtr5_Hi 0x100b52 1879 #define regUMCCH6_2_PerfMonCtr5_Hi_BASE_IDX 1 1880 #define regUMCCH6_2_PerfMonCtl6 0x100b53 1881 #define regUMCCH6_2_PerfMonCtl6_BASE_IDX 1 1882 #define regUMCCH6_2_PerfMonCtr6_Lo 0x100b54 1883 #define regUMCCH6_2_PerfMonCtr6_Lo_BASE_IDX 1 1884 #define regUMCCH6_2_PerfMonCtr6_Hi 0x100b55 1885 #define regUMCCH6_2_PerfMonCtr6_Hi_BASE_IDX 1 1886 #define regUMCCH6_2_PerfMonCtl7 0x100b56 1887 #define regUMCCH6_2_PerfMonCtl7_BASE_IDX 1 1888 #define regUMCCH6_2_PerfMonCtr7_Lo 0x100b57 1889 #define regUMCCH6_2_PerfMonCtr7_Lo_BASE_IDX 1 1890 #define regUMCCH6_2_PerfMonCtr7_Hi 0x100b58 1891 #define regUMCCH6_2_PerfMonCtr7_Hi_BASE_IDX 1 1892 #define regUMCCH6_2_PerfMonCtl8 0x100b59 1893 #define regUMCCH6_2_PerfMonCtl8_BASE_IDX 1 1894 #define regUMCCH6_2_PerfMonCtr8_Lo 0x100b5a 1895 #define regUMCCH6_2_PerfMonCtr8_Lo_BASE_IDX 1 1896 #define regUMCCH6_2_PerfMonCtr8_Hi 0x100b5b 1897 #define regUMCCH6_2_PerfMonCtr8_Hi_BASE_IDX 1 1898 1899 1900 // addressBlock: umc_w_phy_umc2_umcch7_umcchdec 1901 // base address: 0x553000 1902 #define regUMCCH7_2_BaseAddrCS0 0x100c00 1903 #define regUMCCH7_2_BaseAddrCS0_BASE_IDX 1 1904 #define regUMCCH7_2_AddrMaskCS01 0x100c08 1905 #define regUMCCH7_2_AddrMaskCS01_BASE_IDX 1 1906 #define regUMCCH7_2_AddrSelCS01 0x100c10 1907 #define regUMCCH7_2_AddrSelCS01_BASE_IDX 1 1908 #define regUMCCH7_2_AddrHashBank0 0x100c32 1909 #define regUMCCH7_2_AddrHashBank0_BASE_IDX 1 1910 #define regUMCCH7_2_AddrHashBank1 0x100c33 1911 #define regUMCCH7_2_AddrHashBank1_BASE_IDX 1 1912 #define regUMCCH7_2_AddrHashBank2 0x100c34 1913 #define regUMCCH7_2_AddrHashBank2_BASE_IDX 1 1914 #define regUMCCH7_2_AddrHashBank3 0x100c35 1915 #define regUMCCH7_2_AddrHashBank3_BASE_IDX 1 1916 #define regUMCCH7_2_AddrHashBank4 0x100c36 1917 #define regUMCCH7_2_AddrHashBank4_BASE_IDX 1 1918 #define regUMCCH7_2_AddrHashBank5 0x100c37 1919 #define regUMCCH7_2_AddrHashBank5_BASE_IDX 1 1920 #define regUMCCH7_2_EccErrCntSel 0x100f28 1921 #define regUMCCH7_2_EccErrCntSel_BASE_IDX 1 1922 #define regUMCCH7_2_EccErrCnt 0x100f29 1923 #define regUMCCH7_2_EccErrCnt_BASE_IDX 1 1924 #define regUMCCH7_2_PerfMonCtlClk 0x100f40 1925 #define regUMCCH7_2_PerfMonCtlClk_BASE_IDX 1 1926 #define regUMCCH7_2_PerfMonCtrClk_Lo 0x100f41 1927 #define regUMCCH7_2_PerfMonCtrClk_Lo_BASE_IDX 1 1928 #define regUMCCH7_2_PerfMonCtrClk_Hi 0x100f42 1929 #define regUMCCH7_2_PerfMonCtrClk_Hi_BASE_IDX 1 1930 #define regUMCCH7_2_PerfMonCtl1 0x100f44 1931 #define regUMCCH7_2_PerfMonCtl1_BASE_IDX 1 1932 #define regUMCCH7_2_PerfMonCtr1_Lo 0x100f45 1933 #define regUMCCH7_2_PerfMonCtr1_Lo_BASE_IDX 1 1934 #define regUMCCH7_2_PerfMonCtr1_Hi 0x100f46 1935 #define regUMCCH7_2_PerfMonCtr1_Hi_BASE_IDX 1 1936 #define regUMCCH7_2_PerfMonCtl2 0x100f47 1937 #define regUMCCH7_2_PerfMonCtl2_BASE_IDX 1 1938 #define regUMCCH7_2_PerfMonCtr2_Lo 0x100f48 1939 #define regUMCCH7_2_PerfMonCtr2_Lo_BASE_IDX 1 1940 #define regUMCCH7_2_PerfMonCtr2_Hi 0x100f49 1941 #define regUMCCH7_2_PerfMonCtr2_Hi_BASE_IDX 1 1942 #define regUMCCH7_2_PerfMonCtl3 0x100f4a 1943 #define regUMCCH7_2_PerfMonCtl3_BASE_IDX 1 1944 #define regUMCCH7_2_PerfMonCtr3_Lo 0x100f4b 1945 #define regUMCCH7_2_PerfMonCtr3_Lo_BASE_IDX 1 1946 #define regUMCCH7_2_PerfMonCtr3_Hi 0x100f4c 1947 #define regUMCCH7_2_PerfMonCtr3_Hi_BASE_IDX 1 1948 #define regUMCCH7_2_PerfMonCtl4 0x100f4d 1949 #define regUMCCH7_2_PerfMonCtl4_BASE_IDX 1 1950 #define regUMCCH7_2_PerfMonCtr4_Lo 0x100f4e 1951 #define regUMCCH7_2_PerfMonCtr4_Lo_BASE_IDX 1 1952 #define regUMCCH7_2_PerfMonCtr4_Hi 0x100f4f 1953 #define regUMCCH7_2_PerfMonCtr4_Hi_BASE_IDX 1 1954 #define regUMCCH7_2_PerfMonCtl5 0x100f50 1955 #define regUMCCH7_2_PerfMonCtl5_BASE_IDX 1 1956 #define regUMCCH7_2_PerfMonCtr5_Lo 0x100f51 1957 #define regUMCCH7_2_PerfMonCtr5_Lo_BASE_IDX 1 1958 #define regUMCCH7_2_PerfMonCtr5_Hi 0x100f52 1959 #define regUMCCH7_2_PerfMonCtr5_Hi_BASE_IDX 1 1960 #define regUMCCH7_2_PerfMonCtl6 0x100f53 1961 #define regUMCCH7_2_PerfMonCtl6_BASE_IDX 1 1962 #define regUMCCH7_2_PerfMonCtr6_Lo 0x100f54 1963 #define regUMCCH7_2_PerfMonCtr6_Lo_BASE_IDX 1 1964 #define regUMCCH7_2_PerfMonCtr6_Hi 0x100f55 1965 #define regUMCCH7_2_PerfMonCtr6_Hi_BASE_IDX 1 1966 #define regUMCCH7_2_PerfMonCtl7 0x100f56 1967 #define regUMCCH7_2_PerfMonCtl7_BASE_IDX 1 1968 #define regUMCCH7_2_PerfMonCtr7_Lo 0x100f57 1969 #define regUMCCH7_2_PerfMonCtr7_Lo_BASE_IDX 1 1970 #define regUMCCH7_2_PerfMonCtr7_Hi 0x100f58 1971 #define regUMCCH7_2_PerfMonCtr7_Hi_BASE_IDX 1 1972 #define regUMCCH7_2_PerfMonCtl8 0x100f59 1973 #define regUMCCH7_2_PerfMonCtl8_BASE_IDX 1 1974 #define regUMCCH7_2_PerfMonCtr8_Lo 0x100f5a 1975 #define regUMCCH7_2_PerfMonCtr8_Lo_BASE_IDX 1 1976 #define regUMCCH7_2_PerfMonCtr8_Hi 0x100f5b 1977 #define regUMCCH7_2_PerfMonCtr8_Hi_BASE_IDX 1 1978 1979 1980 // addressBlock: umc_w_phy_umc3_umcch0_umcchdec 1981 // base address: 0x650000 1982 #define regUMCCH0_3_BaseAddrCS0 0x140000 1983 #define regUMCCH0_3_BaseAddrCS0_BASE_IDX 1 1984 #define regUMCCH0_3_AddrMaskCS01 0x140008 1985 #define regUMCCH0_3_AddrMaskCS01_BASE_IDX 1 1986 #define regUMCCH0_3_AddrSelCS01 0x140010 1987 #define regUMCCH0_3_AddrSelCS01_BASE_IDX 1 1988 #define regUMCCH0_3_AddrHashBank0 0x140032 1989 #define regUMCCH0_3_AddrHashBank0_BASE_IDX 1 1990 #define regUMCCH0_3_AddrHashBank1 0x140033 1991 #define regUMCCH0_3_AddrHashBank1_BASE_IDX 1 1992 #define regUMCCH0_3_AddrHashBank2 0x140034 1993 #define regUMCCH0_3_AddrHashBank2_BASE_IDX 1 1994 #define regUMCCH0_3_AddrHashBank3 0x140035 1995 #define regUMCCH0_3_AddrHashBank3_BASE_IDX 1 1996 #define regUMCCH0_3_AddrHashBank4 0x140036 1997 #define regUMCCH0_3_AddrHashBank4_BASE_IDX 1 1998 #define regUMCCH0_3_AddrHashBank5 0x140037 1999 #define regUMCCH0_3_AddrHashBank5_BASE_IDX 1 2000 #define regUMCCH0_3_EccErrCntSel 0x140328 2001 #define regUMCCH0_3_EccErrCntSel_BASE_IDX 1 2002 #define regUMCCH0_3_EccErrCnt 0x140329 2003 #define regUMCCH0_3_EccErrCnt_BASE_IDX 1 2004 #define regUMCCH0_3_PerfMonCtlClk 0x140340 2005 #define regUMCCH0_3_PerfMonCtlClk_BASE_IDX 1 2006 #define regUMCCH0_3_PerfMonCtrClk_Lo 0x140341 2007 #define regUMCCH0_3_PerfMonCtrClk_Lo_BASE_IDX 1 2008 #define regUMCCH0_3_PerfMonCtrClk_Hi 0x140342 2009 #define regUMCCH0_3_PerfMonCtrClk_Hi_BASE_IDX 1 2010 #define regUMCCH0_3_PerfMonCtl1 0x140344 2011 #define regUMCCH0_3_PerfMonCtl1_BASE_IDX 1 2012 #define regUMCCH0_3_PerfMonCtr1_Lo 0x140345 2013 #define regUMCCH0_3_PerfMonCtr1_Lo_BASE_IDX 1 2014 #define regUMCCH0_3_PerfMonCtr1_Hi 0x140346 2015 #define regUMCCH0_3_PerfMonCtr1_Hi_BASE_IDX 1 2016 #define regUMCCH0_3_PerfMonCtl2 0x140347 2017 #define regUMCCH0_3_PerfMonCtl2_BASE_IDX 1 2018 #define regUMCCH0_3_PerfMonCtr2_Lo 0x140348 2019 #define regUMCCH0_3_PerfMonCtr2_Lo_BASE_IDX 1 2020 #define regUMCCH0_3_PerfMonCtr2_Hi 0x140349 2021 #define regUMCCH0_3_PerfMonCtr2_Hi_BASE_IDX 1 2022 #define regUMCCH0_3_PerfMonCtl3 0x14034a 2023 #define regUMCCH0_3_PerfMonCtl3_BASE_IDX 1 2024 #define regUMCCH0_3_PerfMonCtr3_Lo 0x14034b 2025 #define regUMCCH0_3_PerfMonCtr3_Lo_BASE_IDX 1 2026 #define regUMCCH0_3_PerfMonCtr3_Hi 0x14034c 2027 #define regUMCCH0_3_PerfMonCtr3_Hi_BASE_IDX 1 2028 #define regUMCCH0_3_PerfMonCtl4 0x14034d 2029 #define regUMCCH0_3_PerfMonCtl4_BASE_IDX 1 2030 #define regUMCCH0_3_PerfMonCtr4_Lo 0x14034e 2031 #define regUMCCH0_3_PerfMonCtr4_Lo_BASE_IDX 1 2032 #define regUMCCH0_3_PerfMonCtr4_Hi 0x14034f 2033 #define regUMCCH0_3_PerfMonCtr4_Hi_BASE_IDX 1 2034 #define regUMCCH0_3_PerfMonCtl5 0x140350 2035 #define regUMCCH0_3_PerfMonCtl5_BASE_IDX 1 2036 #define regUMCCH0_3_PerfMonCtr5_Lo 0x140351 2037 #define regUMCCH0_3_PerfMonCtr5_Lo_BASE_IDX 1 2038 #define regUMCCH0_3_PerfMonCtr5_Hi 0x140352 2039 #define regUMCCH0_3_PerfMonCtr5_Hi_BASE_IDX 1 2040 #define regUMCCH0_3_PerfMonCtl6 0x140353 2041 #define regUMCCH0_3_PerfMonCtl6_BASE_IDX 1 2042 #define regUMCCH0_3_PerfMonCtr6_Lo 0x140354 2043 #define regUMCCH0_3_PerfMonCtr6_Lo_BASE_IDX 1 2044 #define regUMCCH0_3_PerfMonCtr6_Hi 0x140355 2045 #define regUMCCH0_3_PerfMonCtr6_Hi_BASE_IDX 1 2046 #define regUMCCH0_3_PerfMonCtl7 0x140356 2047 #define regUMCCH0_3_PerfMonCtl7_BASE_IDX 1 2048 #define regUMCCH0_3_PerfMonCtr7_Lo 0x140357 2049 #define regUMCCH0_3_PerfMonCtr7_Lo_BASE_IDX 1 2050 #define regUMCCH0_3_PerfMonCtr7_Hi 0x140358 2051 #define regUMCCH0_3_PerfMonCtr7_Hi_BASE_IDX 1 2052 #define regUMCCH0_3_PerfMonCtl8 0x140359 2053 #define regUMCCH0_3_PerfMonCtl8_BASE_IDX 1 2054 #define regUMCCH0_3_PerfMonCtr8_Lo 0x14035a 2055 #define regUMCCH0_3_PerfMonCtr8_Lo_BASE_IDX 1 2056 #define regUMCCH0_3_PerfMonCtr8_Hi 0x14035b 2057 #define regUMCCH0_3_PerfMonCtr8_Hi_BASE_IDX 1 2058 2059 2060 // addressBlock: umc_w_phy_umc3_umcch1_umcchdec 2061 // base address: 0x651000 2062 #define regUMCCH1_3_BaseAddrCS0 0x140400 2063 #define regUMCCH1_3_BaseAddrCS0_BASE_IDX 1 2064 #define regUMCCH1_3_AddrMaskCS01 0x140408 2065 #define regUMCCH1_3_AddrMaskCS01_BASE_IDX 1 2066 #define regUMCCH1_3_AddrSelCS01 0x140410 2067 #define regUMCCH1_3_AddrSelCS01_BASE_IDX 1 2068 #define regUMCCH1_3_AddrHashBank0 0x140432 2069 #define regUMCCH1_3_AddrHashBank0_BASE_IDX 1 2070 #define regUMCCH1_3_AddrHashBank1 0x140433 2071 #define regUMCCH1_3_AddrHashBank1_BASE_IDX 1 2072 #define regUMCCH1_3_AddrHashBank2 0x140434 2073 #define regUMCCH1_3_AddrHashBank2_BASE_IDX 1 2074 #define regUMCCH1_3_AddrHashBank3 0x140435 2075 #define regUMCCH1_3_AddrHashBank3_BASE_IDX 1 2076 #define regUMCCH1_3_AddrHashBank4 0x140436 2077 #define regUMCCH1_3_AddrHashBank4_BASE_IDX 1 2078 #define regUMCCH1_3_AddrHashBank5 0x140437 2079 #define regUMCCH1_3_AddrHashBank5_BASE_IDX 1 2080 #define regUMCCH1_3_EccErrCntSel 0x140728 2081 #define regUMCCH1_3_EccErrCntSel_BASE_IDX 1 2082 #define regUMCCH1_3_EccErrCnt 0x140729 2083 #define regUMCCH1_3_EccErrCnt_BASE_IDX 1 2084 #define regUMCCH1_3_PerfMonCtlClk 0x140740 2085 #define regUMCCH1_3_PerfMonCtlClk_BASE_IDX 1 2086 #define regUMCCH1_3_PerfMonCtrClk_Lo 0x140741 2087 #define regUMCCH1_3_PerfMonCtrClk_Lo_BASE_IDX 1 2088 #define regUMCCH1_3_PerfMonCtrClk_Hi 0x140742 2089 #define regUMCCH1_3_PerfMonCtrClk_Hi_BASE_IDX 1 2090 #define regUMCCH1_3_PerfMonCtl1 0x140744 2091 #define regUMCCH1_3_PerfMonCtl1_BASE_IDX 1 2092 #define regUMCCH1_3_PerfMonCtr1_Lo 0x140745 2093 #define regUMCCH1_3_PerfMonCtr1_Lo_BASE_IDX 1 2094 #define regUMCCH1_3_PerfMonCtr1_Hi 0x140746 2095 #define regUMCCH1_3_PerfMonCtr1_Hi_BASE_IDX 1 2096 #define regUMCCH1_3_PerfMonCtl2 0x140747 2097 #define regUMCCH1_3_PerfMonCtl2_BASE_IDX 1 2098 #define regUMCCH1_3_PerfMonCtr2_Lo 0x140748 2099 #define regUMCCH1_3_PerfMonCtr2_Lo_BASE_IDX 1 2100 #define regUMCCH1_3_PerfMonCtr2_Hi 0x140749 2101 #define regUMCCH1_3_PerfMonCtr2_Hi_BASE_IDX 1 2102 #define regUMCCH1_3_PerfMonCtl3 0x14074a 2103 #define regUMCCH1_3_PerfMonCtl3_BASE_IDX 1 2104 #define regUMCCH1_3_PerfMonCtr3_Lo 0x14074b 2105 #define regUMCCH1_3_PerfMonCtr3_Lo_BASE_IDX 1 2106 #define regUMCCH1_3_PerfMonCtr3_Hi 0x14074c 2107 #define regUMCCH1_3_PerfMonCtr3_Hi_BASE_IDX 1 2108 #define regUMCCH1_3_PerfMonCtl4 0x14074d 2109 #define regUMCCH1_3_PerfMonCtl4_BASE_IDX 1 2110 #define regUMCCH1_3_PerfMonCtr4_Lo 0x14074e 2111 #define regUMCCH1_3_PerfMonCtr4_Lo_BASE_IDX 1 2112 #define regUMCCH1_3_PerfMonCtr4_Hi 0x14074f 2113 #define regUMCCH1_3_PerfMonCtr4_Hi_BASE_IDX 1 2114 #define regUMCCH1_3_PerfMonCtl5 0x140750 2115 #define regUMCCH1_3_PerfMonCtl5_BASE_IDX 1 2116 #define regUMCCH1_3_PerfMonCtr5_Lo 0x140751 2117 #define regUMCCH1_3_PerfMonCtr5_Lo_BASE_IDX 1 2118 #define regUMCCH1_3_PerfMonCtr5_Hi 0x140752 2119 #define regUMCCH1_3_PerfMonCtr5_Hi_BASE_IDX 1 2120 #define regUMCCH1_3_PerfMonCtl6 0x140753 2121 #define regUMCCH1_3_PerfMonCtl6_BASE_IDX 1 2122 #define regUMCCH1_3_PerfMonCtr6_Lo 0x140754 2123 #define regUMCCH1_3_PerfMonCtr6_Lo_BASE_IDX 1 2124 #define regUMCCH1_3_PerfMonCtr6_Hi 0x140755 2125 #define regUMCCH1_3_PerfMonCtr6_Hi_BASE_IDX 1 2126 #define regUMCCH1_3_PerfMonCtl7 0x140756 2127 #define regUMCCH1_3_PerfMonCtl7_BASE_IDX 1 2128 #define regUMCCH1_3_PerfMonCtr7_Lo 0x140757 2129 #define regUMCCH1_3_PerfMonCtr7_Lo_BASE_IDX 1 2130 #define regUMCCH1_3_PerfMonCtr7_Hi 0x140758 2131 #define regUMCCH1_3_PerfMonCtr7_Hi_BASE_IDX 1 2132 #define regUMCCH1_3_PerfMonCtl8 0x140759 2133 #define regUMCCH1_3_PerfMonCtl8_BASE_IDX 1 2134 #define regUMCCH1_3_PerfMonCtr8_Lo 0x14075a 2135 #define regUMCCH1_3_PerfMonCtr8_Lo_BASE_IDX 1 2136 #define regUMCCH1_3_PerfMonCtr8_Hi 0x14075b 2137 #define regUMCCH1_3_PerfMonCtr8_Hi_BASE_IDX 1 2138 2139 2140 // addressBlock: umc_w_phy_umc3_umcch2_umcchdec 2141 // base address: 0x652000 2142 #define regUMCCH2_3_BaseAddrCS0 0x140800 2143 #define regUMCCH2_3_BaseAddrCS0_BASE_IDX 1 2144 #define regUMCCH2_3_AddrMaskCS01 0x140808 2145 #define regUMCCH2_3_AddrMaskCS01_BASE_IDX 1 2146 #define regUMCCH2_3_AddrSelCS01 0x140810 2147 #define regUMCCH2_3_AddrSelCS01_BASE_IDX 1 2148 #define regUMCCH2_3_AddrHashBank0 0x140832 2149 #define regUMCCH2_3_AddrHashBank0_BASE_IDX 1 2150 #define regUMCCH2_3_AddrHashBank1 0x140833 2151 #define regUMCCH2_3_AddrHashBank1_BASE_IDX 1 2152 #define regUMCCH2_3_AddrHashBank2 0x140834 2153 #define regUMCCH2_3_AddrHashBank2_BASE_IDX 1 2154 #define regUMCCH2_3_AddrHashBank3 0x140835 2155 #define regUMCCH2_3_AddrHashBank3_BASE_IDX 1 2156 #define regUMCCH2_3_AddrHashBank4 0x140836 2157 #define regUMCCH2_3_AddrHashBank4_BASE_IDX 1 2158 #define regUMCCH2_3_AddrHashBank5 0x140837 2159 #define regUMCCH2_3_AddrHashBank5_BASE_IDX 1 2160 #define regUMCCH2_3_EccErrCntSel 0x140b28 2161 #define regUMCCH2_3_EccErrCntSel_BASE_IDX 1 2162 #define regUMCCH2_3_EccErrCnt 0x140b29 2163 #define regUMCCH2_3_EccErrCnt_BASE_IDX 1 2164 #define regUMCCH2_3_PerfMonCtlClk 0x140b40 2165 #define regUMCCH2_3_PerfMonCtlClk_BASE_IDX 1 2166 #define regUMCCH2_3_PerfMonCtrClk_Lo 0x140b41 2167 #define regUMCCH2_3_PerfMonCtrClk_Lo_BASE_IDX 1 2168 #define regUMCCH2_3_PerfMonCtrClk_Hi 0x140b42 2169 #define regUMCCH2_3_PerfMonCtrClk_Hi_BASE_IDX 1 2170 #define regUMCCH2_3_PerfMonCtl1 0x140b44 2171 #define regUMCCH2_3_PerfMonCtl1_BASE_IDX 1 2172 #define regUMCCH2_3_PerfMonCtr1_Lo 0x140b45 2173 #define regUMCCH2_3_PerfMonCtr1_Lo_BASE_IDX 1 2174 #define regUMCCH2_3_PerfMonCtr1_Hi 0x140b46 2175 #define regUMCCH2_3_PerfMonCtr1_Hi_BASE_IDX 1 2176 #define regUMCCH2_3_PerfMonCtl2 0x140b47 2177 #define regUMCCH2_3_PerfMonCtl2_BASE_IDX 1 2178 #define regUMCCH2_3_PerfMonCtr2_Lo 0x140b48 2179 #define regUMCCH2_3_PerfMonCtr2_Lo_BASE_IDX 1 2180 #define regUMCCH2_3_PerfMonCtr2_Hi 0x140b49 2181 #define regUMCCH2_3_PerfMonCtr2_Hi_BASE_IDX 1 2182 #define regUMCCH2_3_PerfMonCtl3 0x140b4a 2183 #define regUMCCH2_3_PerfMonCtl3_BASE_IDX 1 2184 #define regUMCCH2_3_PerfMonCtr3_Lo 0x140b4b 2185 #define regUMCCH2_3_PerfMonCtr3_Lo_BASE_IDX 1 2186 #define regUMCCH2_3_PerfMonCtr3_Hi 0x140b4c 2187 #define regUMCCH2_3_PerfMonCtr3_Hi_BASE_IDX 1 2188 #define regUMCCH2_3_PerfMonCtl4 0x140b4d 2189 #define regUMCCH2_3_PerfMonCtl4_BASE_IDX 1 2190 #define regUMCCH2_3_PerfMonCtr4_Lo 0x140b4e 2191 #define regUMCCH2_3_PerfMonCtr4_Lo_BASE_IDX 1 2192 #define regUMCCH2_3_PerfMonCtr4_Hi 0x140b4f 2193 #define regUMCCH2_3_PerfMonCtr4_Hi_BASE_IDX 1 2194 #define regUMCCH2_3_PerfMonCtl5 0x140b50 2195 #define regUMCCH2_3_PerfMonCtl5_BASE_IDX 1 2196 #define regUMCCH2_3_PerfMonCtr5_Lo 0x140b51 2197 #define regUMCCH2_3_PerfMonCtr5_Lo_BASE_IDX 1 2198 #define regUMCCH2_3_PerfMonCtr5_Hi 0x140b52 2199 #define regUMCCH2_3_PerfMonCtr5_Hi_BASE_IDX 1 2200 #define regUMCCH2_3_PerfMonCtl6 0x140b53 2201 #define regUMCCH2_3_PerfMonCtl6_BASE_IDX 1 2202 #define regUMCCH2_3_PerfMonCtr6_Lo 0x140b54 2203 #define regUMCCH2_3_PerfMonCtr6_Lo_BASE_IDX 1 2204 #define regUMCCH2_3_PerfMonCtr6_Hi 0x140b55 2205 #define regUMCCH2_3_PerfMonCtr6_Hi_BASE_IDX 1 2206 #define regUMCCH2_3_PerfMonCtl7 0x140b56 2207 #define regUMCCH2_3_PerfMonCtl7_BASE_IDX 1 2208 #define regUMCCH2_3_PerfMonCtr7_Lo 0x140b57 2209 #define regUMCCH2_3_PerfMonCtr7_Lo_BASE_IDX 1 2210 #define regUMCCH2_3_PerfMonCtr7_Hi 0x140b58 2211 #define regUMCCH2_3_PerfMonCtr7_Hi_BASE_IDX 1 2212 #define regUMCCH2_3_PerfMonCtl8 0x140b59 2213 #define regUMCCH2_3_PerfMonCtl8_BASE_IDX 1 2214 #define regUMCCH2_3_PerfMonCtr8_Lo 0x140b5a 2215 #define regUMCCH2_3_PerfMonCtr8_Lo_BASE_IDX 1 2216 #define regUMCCH2_3_PerfMonCtr8_Hi 0x140b5b 2217 #define regUMCCH2_3_PerfMonCtr8_Hi_BASE_IDX 1 2218 2219 2220 // addressBlock: umc_w_phy_umc3_umcch3_umcchdec 2221 // base address: 0x653000 2222 #define regUMCCH3_3_BaseAddrCS0 0x140c00 2223 #define regUMCCH3_3_BaseAddrCS0_BASE_IDX 1 2224 #define regUMCCH3_3_AddrMaskCS01 0x140c08 2225 #define regUMCCH3_3_AddrMaskCS01_BASE_IDX 1 2226 #define regUMCCH3_3_AddrSelCS01 0x140c10 2227 #define regUMCCH3_3_AddrSelCS01_BASE_IDX 1 2228 #define regUMCCH3_3_AddrHashBank0 0x140c32 2229 #define regUMCCH3_3_AddrHashBank0_BASE_IDX 1 2230 #define regUMCCH3_3_AddrHashBank1 0x140c33 2231 #define regUMCCH3_3_AddrHashBank1_BASE_IDX 1 2232 #define regUMCCH3_3_AddrHashBank2 0x140c34 2233 #define regUMCCH3_3_AddrHashBank2_BASE_IDX 1 2234 #define regUMCCH3_3_AddrHashBank3 0x140c35 2235 #define regUMCCH3_3_AddrHashBank3_BASE_IDX 1 2236 #define regUMCCH3_3_AddrHashBank4 0x140c36 2237 #define regUMCCH3_3_AddrHashBank4_BASE_IDX 1 2238 #define regUMCCH3_3_AddrHashBank5 0x140c37 2239 #define regUMCCH3_3_AddrHashBank5_BASE_IDX 1 2240 #define regUMCCH3_3_EccErrCntSel 0x140f28 2241 #define regUMCCH3_3_EccErrCntSel_BASE_IDX 1 2242 #define regUMCCH3_3_EccErrCnt 0x140f29 2243 #define regUMCCH3_3_EccErrCnt_BASE_IDX 1 2244 #define regUMCCH3_3_PerfMonCtlClk 0x140f40 2245 #define regUMCCH3_3_PerfMonCtlClk_BASE_IDX 1 2246 #define regUMCCH3_3_PerfMonCtrClk_Lo 0x140f41 2247 #define regUMCCH3_3_PerfMonCtrClk_Lo_BASE_IDX 1 2248 #define regUMCCH3_3_PerfMonCtrClk_Hi 0x140f42 2249 #define regUMCCH3_3_PerfMonCtrClk_Hi_BASE_IDX 1 2250 #define regUMCCH3_3_PerfMonCtl1 0x140f44 2251 #define regUMCCH3_3_PerfMonCtl1_BASE_IDX 1 2252 #define regUMCCH3_3_PerfMonCtr1_Lo 0x140f45 2253 #define regUMCCH3_3_PerfMonCtr1_Lo_BASE_IDX 1 2254 #define regUMCCH3_3_PerfMonCtr1_Hi 0x140f46 2255 #define regUMCCH3_3_PerfMonCtr1_Hi_BASE_IDX 1 2256 #define regUMCCH3_3_PerfMonCtl2 0x140f47 2257 #define regUMCCH3_3_PerfMonCtl2_BASE_IDX 1 2258 #define regUMCCH3_3_PerfMonCtr2_Lo 0x140f48 2259 #define regUMCCH3_3_PerfMonCtr2_Lo_BASE_IDX 1 2260 #define regUMCCH3_3_PerfMonCtr2_Hi 0x140f49 2261 #define regUMCCH3_3_PerfMonCtr2_Hi_BASE_IDX 1 2262 #define regUMCCH3_3_PerfMonCtl3 0x140f4a 2263 #define regUMCCH3_3_PerfMonCtl3_BASE_IDX 1 2264 #define regUMCCH3_3_PerfMonCtr3_Lo 0x140f4b 2265 #define regUMCCH3_3_PerfMonCtr3_Lo_BASE_IDX 1 2266 #define regUMCCH3_3_PerfMonCtr3_Hi 0x140f4c 2267 #define regUMCCH3_3_PerfMonCtr3_Hi_BASE_IDX 1 2268 #define regUMCCH3_3_PerfMonCtl4 0x140f4d 2269 #define regUMCCH3_3_PerfMonCtl4_BASE_IDX 1 2270 #define regUMCCH3_3_PerfMonCtr4_Lo 0x140f4e 2271 #define regUMCCH3_3_PerfMonCtr4_Lo_BASE_IDX 1 2272 #define regUMCCH3_3_PerfMonCtr4_Hi 0x140f4f 2273 #define regUMCCH3_3_PerfMonCtr4_Hi_BASE_IDX 1 2274 #define regUMCCH3_3_PerfMonCtl5 0x140f50 2275 #define regUMCCH3_3_PerfMonCtl5_BASE_IDX 1 2276 #define regUMCCH3_3_PerfMonCtr5_Lo 0x140f51 2277 #define regUMCCH3_3_PerfMonCtr5_Lo_BASE_IDX 1 2278 #define regUMCCH3_3_PerfMonCtr5_Hi 0x140f52 2279 #define regUMCCH3_3_PerfMonCtr5_Hi_BASE_IDX 1 2280 #define regUMCCH3_3_PerfMonCtl6 0x140f53 2281 #define regUMCCH3_3_PerfMonCtl6_BASE_IDX 1 2282 #define regUMCCH3_3_PerfMonCtr6_Lo 0x140f54 2283 #define regUMCCH3_3_PerfMonCtr6_Lo_BASE_IDX 1 2284 #define regUMCCH3_3_PerfMonCtr6_Hi 0x140f55 2285 #define regUMCCH3_3_PerfMonCtr6_Hi_BASE_IDX 1 2286 #define regUMCCH3_3_PerfMonCtl7 0x140f56 2287 #define regUMCCH3_3_PerfMonCtl7_BASE_IDX 1 2288 #define regUMCCH3_3_PerfMonCtr7_Lo 0x140f57 2289 #define regUMCCH3_3_PerfMonCtr7_Lo_BASE_IDX 1 2290 #define regUMCCH3_3_PerfMonCtr7_Hi 0x140f58 2291 #define regUMCCH3_3_PerfMonCtr7_Hi_BASE_IDX 1 2292 #define regUMCCH3_3_PerfMonCtl8 0x140f59 2293 #define regUMCCH3_3_PerfMonCtl8_BASE_IDX 1 2294 #define regUMCCH3_3_PerfMonCtr8_Lo 0x140f5a 2295 #define regUMCCH3_3_PerfMonCtr8_Lo_BASE_IDX 1 2296 #define regUMCCH3_3_PerfMonCtr8_Hi 0x140f5b 2297 #define regUMCCH3_3_PerfMonCtr8_Hi_BASE_IDX 1 2298 2299 2300 // addressBlock: umc_w_phy_umc3_umcch4_umcchdec 2301 // base address: 0x750000 2302 #define regUMCCH4_3_BaseAddrCS0 0x180000 2303 #define regUMCCH4_3_BaseAddrCS0_BASE_IDX 1 2304 #define regUMCCH4_3_AddrMaskCS01 0x180008 2305 #define regUMCCH4_3_AddrMaskCS01_BASE_IDX 1 2306 #define regUMCCH4_3_AddrSelCS01 0x180010 2307 #define regUMCCH4_3_AddrSelCS01_BASE_IDX 1 2308 #define regUMCCH4_3_AddrHashBank0 0x180032 2309 #define regUMCCH4_3_AddrHashBank0_BASE_IDX 1 2310 #define regUMCCH4_3_AddrHashBank1 0x180033 2311 #define regUMCCH4_3_AddrHashBank1_BASE_IDX 1 2312 #define regUMCCH4_3_AddrHashBank2 0x180034 2313 #define regUMCCH4_3_AddrHashBank2_BASE_IDX 1 2314 #define regUMCCH4_3_AddrHashBank3 0x180035 2315 #define regUMCCH4_3_AddrHashBank3_BASE_IDX 1 2316 #define regUMCCH4_3_AddrHashBank4 0x180036 2317 #define regUMCCH4_3_AddrHashBank4_BASE_IDX 1 2318 #define regUMCCH4_3_AddrHashBank5 0x180037 2319 #define regUMCCH4_3_AddrHashBank5_BASE_IDX 1 2320 #define regUMCCH4_3_EccErrCntSel 0x180328 2321 #define regUMCCH4_3_EccErrCntSel_BASE_IDX 1 2322 #define regUMCCH4_3_EccErrCnt 0x180329 2323 #define regUMCCH4_3_EccErrCnt_BASE_IDX 1 2324 #define regUMCCH4_3_PerfMonCtlClk 0x180340 2325 #define regUMCCH4_3_PerfMonCtlClk_BASE_IDX 1 2326 #define regUMCCH4_3_PerfMonCtrClk_Lo 0x180341 2327 #define regUMCCH4_3_PerfMonCtrClk_Lo_BASE_IDX 1 2328 #define regUMCCH4_3_PerfMonCtrClk_Hi 0x180342 2329 #define regUMCCH4_3_PerfMonCtrClk_Hi_BASE_IDX 1 2330 #define regUMCCH4_3_PerfMonCtl1 0x180344 2331 #define regUMCCH4_3_PerfMonCtl1_BASE_IDX 1 2332 #define regUMCCH4_3_PerfMonCtr1_Lo 0x180345 2333 #define regUMCCH4_3_PerfMonCtr1_Lo_BASE_IDX 1 2334 #define regUMCCH4_3_PerfMonCtr1_Hi 0x180346 2335 #define regUMCCH4_3_PerfMonCtr1_Hi_BASE_IDX 1 2336 #define regUMCCH4_3_PerfMonCtl2 0x180347 2337 #define regUMCCH4_3_PerfMonCtl2_BASE_IDX 1 2338 #define regUMCCH4_3_PerfMonCtr2_Lo 0x180348 2339 #define regUMCCH4_3_PerfMonCtr2_Lo_BASE_IDX 1 2340 #define regUMCCH4_3_PerfMonCtr2_Hi 0x180349 2341 #define regUMCCH4_3_PerfMonCtr2_Hi_BASE_IDX 1 2342 #define regUMCCH4_3_PerfMonCtl3 0x18034a 2343 #define regUMCCH4_3_PerfMonCtl3_BASE_IDX 1 2344 #define regUMCCH4_3_PerfMonCtr3_Lo 0x18034b 2345 #define regUMCCH4_3_PerfMonCtr3_Lo_BASE_IDX 1 2346 #define regUMCCH4_3_PerfMonCtr3_Hi 0x18034c 2347 #define regUMCCH4_3_PerfMonCtr3_Hi_BASE_IDX 1 2348 #define regUMCCH4_3_PerfMonCtl4 0x18034d 2349 #define regUMCCH4_3_PerfMonCtl4_BASE_IDX 1 2350 #define regUMCCH4_3_PerfMonCtr4_Lo 0x18034e 2351 #define regUMCCH4_3_PerfMonCtr4_Lo_BASE_IDX 1 2352 #define regUMCCH4_3_PerfMonCtr4_Hi 0x18034f 2353 #define regUMCCH4_3_PerfMonCtr4_Hi_BASE_IDX 1 2354 #define regUMCCH4_3_PerfMonCtl5 0x180350 2355 #define regUMCCH4_3_PerfMonCtl5_BASE_IDX 1 2356 #define regUMCCH4_3_PerfMonCtr5_Lo 0x180351 2357 #define regUMCCH4_3_PerfMonCtr5_Lo_BASE_IDX 1 2358 #define regUMCCH4_3_PerfMonCtr5_Hi 0x180352 2359 #define regUMCCH4_3_PerfMonCtr5_Hi_BASE_IDX 1 2360 #define regUMCCH4_3_PerfMonCtl6 0x180353 2361 #define regUMCCH4_3_PerfMonCtl6_BASE_IDX 1 2362 #define regUMCCH4_3_PerfMonCtr6_Lo 0x180354 2363 #define regUMCCH4_3_PerfMonCtr6_Lo_BASE_IDX 1 2364 #define regUMCCH4_3_PerfMonCtr6_Hi 0x180355 2365 #define regUMCCH4_3_PerfMonCtr6_Hi_BASE_IDX 1 2366 #define regUMCCH4_3_PerfMonCtl7 0x180356 2367 #define regUMCCH4_3_PerfMonCtl7_BASE_IDX 1 2368 #define regUMCCH4_3_PerfMonCtr7_Lo 0x180357 2369 #define regUMCCH4_3_PerfMonCtr7_Lo_BASE_IDX 1 2370 #define regUMCCH4_3_PerfMonCtr7_Hi 0x180358 2371 #define regUMCCH4_3_PerfMonCtr7_Hi_BASE_IDX 1 2372 #define regUMCCH4_3_PerfMonCtl8 0x180359 2373 #define regUMCCH4_3_PerfMonCtl8_BASE_IDX 1 2374 #define regUMCCH4_3_PerfMonCtr8_Lo 0x18035a 2375 #define regUMCCH4_3_PerfMonCtr8_Lo_BASE_IDX 1 2376 #define regUMCCH4_3_PerfMonCtr8_Hi 0x18035b 2377 #define regUMCCH4_3_PerfMonCtr8_Hi_BASE_IDX 1 2378 2379 2380 // addressBlock: umc_w_phy_umc3_umcch5_umcchdec 2381 // base address: 0x751000 2382 #define regUMCCH5_3_BaseAddrCS0 0x180400 2383 #define regUMCCH5_3_BaseAddrCS0_BASE_IDX 1 2384 #define regUMCCH5_3_AddrMaskCS01 0x180408 2385 #define regUMCCH5_3_AddrMaskCS01_BASE_IDX 1 2386 #define regUMCCH5_3_AddrSelCS01 0x180410 2387 #define regUMCCH5_3_AddrSelCS01_BASE_IDX 1 2388 #define regUMCCH5_3_AddrHashBank0 0x180432 2389 #define regUMCCH5_3_AddrHashBank0_BASE_IDX 1 2390 #define regUMCCH5_3_AddrHashBank1 0x180433 2391 #define regUMCCH5_3_AddrHashBank1_BASE_IDX 1 2392 #define regUMCCH5_3_AddrHashBank2 0x180434 2393 #define regUMCCH5_3_AddrHashBank2_BASE_IDX 1 2394 #define regUMCCH5_3_AddrHashBank3 0x180435 2395 #define regUMCCH5_3_AddrHashBank3_BASE_IDX 1 2396 #define regUMCCH5_3_AddrHashBank4 0x180436 2397 #define regUMCCH5_3_AddrHashBank4_BASE_IDX 1 2398 #define regUMCCH5_3_AddrHashBank5 0x180437 2399 #define regUMCCH5_3_AddrHashBank5_BASE_IDX 1 2400 #define regUMCCH5_3_EccErrCntSel 0x180728 2401 #define regUMCCH5_3_EccErrCntSel_BASE_IDX 1 2402 #define regUMCCH5_3_EccErrCnt 0x180729 2403 #define regUMCCH5_3_EccErrCnt_BASE_IDX 1 2404 #define regUMCCH5_3_PerfMonCtlClk 0x180740 2405 #define regUMCCH5_3_PerfMonCtlClk_BASE_IDX 1 2406 #define regUMCCH5_3_PerfMonCtrClk_Lo 0x180741 2407 #define regUMCCH5_3_PerfMonCtrClk_Lo_BASE_IDX 1 2408 #define regUMCCH5_3_PerfMonCtrClk_Hi 0x180742 2409 #define regUMCCH5_3_PerfMonCtrClk_Hi_BASE_IDX 1 2410 #define regUMCCH5_3_PerfMonCtl1 0x180744 2411 #define regUMCCH5_3_PerfMonCtl1_BASE_IDX 1 2412 #define regUMCCH5_3_PerfMonCtr1_Lo 0x180745 2413 #define regUMCCH5_3_PerfMonCtr1_Lo_BASE_IDX 1 2414 #define regUMCCH5_3_PerfMonCtr1_Hi 0x180746 2415 #define regUMCCH5_3_PerfMonCtr1_Hi_BASE_IDX 1 2416 #define regUMCCH5_3_PerfMonCtl2 0x180747 2417 #define regUMCCH5_3_PerfMonCtl2_BASE_IDX 1 2418 #define regUMCCH5_3_PerfMonCtr2_Lo 0x180748 2419 #define regUMCCH5_3_PerfMonCtr2_Lo_BASE_IDX 1 2420 #define regUMCCH5_3_PerfMonCtr2_Hi 0x180749 2421 #define regUMCCH5_3_PerfMonCtr2_Hi_BASE_IDX 1 2422 #define regUMCCH5_3_PerfMonCtl3 0x18074a 2423 #define regUMCCH5_3_PerfMonCtl3_BASE_IDX 1 2424 #define regUMCCH5_3_PerfMonCtr3_Lo 0x18074b 2425 #define regUMCCH5_3_PerfMonCtr3_Lo_BASE_IDX 1 2426 #define regUMCCH5_3_PerfMonCtr3_Hi 0x18074c 2427 #define regUMCCH5_3_PerfMonCtr3_Hi_BASE_IDX 1 2428 #define regUMCCH5_3_PerfMonCtl4 0x18074d 2429 #define regUMCCH5_3_PerfMonCtl4_BASE_IDX 1 2430 #define regUMCCH5_3_PerfMonCtr4_Lo 0x18074e 2431 #define regUMCCH5_3_PerfMonCtr4_Lo_BASE_IDX 1 2432 #define regUMCCH5_3_PerfMonCtr4_Hi 0x18074f 2433 #define regUMCCH5_3_PerfMonCtr4_Hi_BASE_IDX 1 2434 #define regUMCCH5_3_PerfMonCtl5 0x180750 2435 #define regUMCCH5_3_PerfMonCtl5_BASE_IDX 1 2436 #define regUMCCH5_3_PerfMonCtr5_Lo 0x180751 2437 #define regUMCCH5_3_PerfMonCtr5_Lo_BASE_IDX 1 2438 #define regUMCCH5_3_PerfMonCtr5_Hi 0x180752 2439 #define regUMCCH5_3_PerfMonCtr5_Hi_BASE_IDX 1 2440 #define regUMCCH5_3_PerfMonCtl6 0x180753 2441 #define regUMCCH5_3_PerfMonCtl6_BASE_IDX 1 2442 #define regUMCCH5_3_PerfMonCtr6_Lo 0x180754 2443 #define regUMCCH5_3_PerfMonCtr6_Lo_BASE_IDX 1 2444 #define regUMCCH5_3_PerfMonCtr6_Hi 0x180755 2445 #define regUMCCH5_3_PerfMonCtr6_Hi_BASE_IDX 1 2446 #define regUMCCH5_3_PerfMonCtl7 0x180756 2447 #define regUMCCH5_3_PerfMonCtl7_BASE_IDX 1 2448 #define regUMCCH5_3_PerfMonCtr7_Lo 0x180757 2449 #define regUMCCH5_3_PerfMonCtr7_Lo_BASE_IDX 1 2450 #define regUMCCH5_3_PerfMonCtr7_Hi 0x180758 2451 #define regUMCCH5_3_PerfMonCtr7_Hi_BASE_IDX 1 2452 #define regUMCCH5_3_PerfMonCtl8 0x180759 2453 #define regUMCCH5_3_PerfMonCtl8_BASE_IDX 1 2454 #define regUMCCH5_3_PerfMonCtr8_Lo 0x18075a 2455 #define regUMCCH5_3_PerfMonCtr8_Lo_BASE_IDX 1 2456 #define regUMCCH5_3_PerfMonCtr8_Hi 0x18075b 2457 #define regUMCCH5_3_PerfMonCtr8_Hi_BASE_IDX 1 2458 2459 2460 // addressBlock: umc_w_phy_umc3_umcch6_umcchdec 2461 // base address: 0x752000 2462 #define regUMCCH6_3_BaseAddrCS0 0x180800 2463 #define regUMCCH6_3_BaseAddrCS0_BASE_IDX 1 2464 #define regUMCCH6_3_AddrMaskCS01 0x180808 2465 #define regUMCCH6_3_AddrMaskCS01_BASE_IDX 1 2466 #define regUMCCH6_3_AddrSelCS01 0x180810 2467 #define regUMCCH6_3_AddrSelCS01_BASE_IDX 1 2468 #define regUMCCH6_3_AddrHashBank0 0x180832 2469 #define regUMCCH6_3_AddrHashBank0_BASE_IDX 1 2470 #define regUMCCH6_3_AddrHashBank1 0x180833 2471 #define regUMCCH6_3_AddrHashBank1_BASE_IDX 1 2472 #define regUMCCH6_3_AddrHashBank2 0x180834 2473 #define regUMCCH6_3_AddrHashBank2_BASE_IDX 1 2474 #define regUMCCH6_3_AddrHashBank3 0x180835 2475 #define regUMCCH6_3_AddrHashBank3_BASE_IDX 1 2476 #define regUMCCH6_3_AddrHashBank4 0x180836 2477 #define regUMCCH6_3_AddrHashBank4_BASE_IDX 1 2478 #define regUMCCH6_3_AddrHashBank5 0x180837 2479 #define regUMCCH6_3_AddrHashBank5_BASE_IDX 1 2480 #define regUMCCH6_3_EccErrCntSel 0x180b28 2481 #define regUMCCH6_3_EccErrCntSel_BASE_IDX 1 2482 #define regUMCCH6_3_EccErrCnt 0x180b29 2483 #define regUMCCH6_3_EccErrCnt_BASE_IDX 1 2484 #define regUMCCH6_3_PerfMonCtlClk 0x180b40 2485 #define regUMCCH6_3_PerfMonCtlClk_BASE_IDX 1 2486 #define regUMCCH6_3_PerfMonCtrClk_Lo 0x180b41 2487 #define regUMCCH6_3_PerfMonCtrClk_Lo_BASE_IDX 1 2488 #define regUMCCH6_3_PerfMonCtrClk_Hi 0x180b42 2489 #define regUMCCH6_3_PerfMonCtrClk_Hi_BASE_IDX 1 2490 #define regUMCCH6_3_PerfMonCtl1 0x180b44 2491 #define regUMCCH6_3_PerfMonCtl1_BASE_IDX 1 2492 #define regUMCCH6_3_PerfMonCtr1_Lo 0x180b45 2493 #define regUMCCH6_3_PerfMonCtr1_Lo_BASE_IDX 1 2494 #define regUMCCH6_3_PerfMonCtr1_Hi 0x180b46 2495 #define regUMCCH6_3_PerfMonCtr1_Hi_BASE_IDX 1 2496 #define regUMCCH6_3_PerfMonCtl2 0x180b47 2497 #define regUMCCH6_3_PerfMonCtl2_BASE_IDX 1 2498 #define regUMCCH6_3_PerfMonCtr2_Lo 0x180b48 2499 #define regUMCCH6_3_PerfMonCtr2_Lo_BASE_IDX 1 2500 #define regUMCCH6_3_PerfMonCtr2_Hi 0x180b49 2501 #define regUMCCH6_3_PerfMonCtr2_Hi_BASE_IDX 1 2502 #define regUMCCH6_3_PerfMonCtl3 0x180b4a 2503 #define regUMCCH6_3_PerfMonCtl3_BASE_IDX 1 2504 #define regUMCCH6_3_PerfMonCtr3_Lo 0x180b4b 2505 #define regUMCCH6_3_PerfMonCtr3_Lo_BASE_IDX 1 2506 #define regUMCCH6_3_PerfMonCtr3_Hi 0x180b4c 2507 #define regUMCCH6_3_PerfMonCtr3_Hi_BASE_IDX 1 2508 #define regUMCCH6_3_PerfMonCtl4 0x180b4d 2509 #define regUMCCH6_3_PerfMonCtl4_BASE_IDX 1 2510 #define regUMCCH6_3_PerfMonCtr4_Lo 0x180b4e 2511 #define regUMCCH6_3_PerfMonCtr4_Lo_BASE_IDX 1 2512 #define regUMCCH6_3_PerfMonCtr4_Hi 0x180b4f 2513 #define regUMCCH6_3_PerfMonCtr4_Hi_BASE_IDX 1 2514 #define regUMCCH6_3_PerfMonCtl5 0x180b50 2515 #define regUMCCH6_3_PerfMonCtl5_BASE_IDX 1 2516 #define regUMCCH6_3_PerfMonCtr5_Lo 0x180b51 2517 #define regUMCCH6_3_PerfMonCtr5_Lo_BASE_IDX 1 2518 #define regUMCCH6_3_PerfMonCtr5_Hi 0x180b52 2519 #define regUMCCH6_3_PerfMonCtr5_Hi_BASE_IDX 1 2520 #define regUMCCH6_3_PerfMonCtl6 0x180b53 2521 #define regUMCCH6_3_PerfMonCtl6_BASE_IDX 1 2522 #define regUMCCH6_3_PerfMonCtr6_Lo 0x180b54 2523 #define regUMCCH6_3_PerfMonCtr6_Lo_BASE_IDX 1 2524 #define regUMCCH6_3_PerfMonCtr6_Hi 0x180b55 2525 #define regUMCCH6_3_PerfMonCtr6_Hi_BASE_IDX 1 2526 #define regUMCCH6_3_PerfMonCtl7 0x180b56 2527 #define regUMCCH6_3_PerfMonCtl7_BASE_IDX 1 2528 #define regUMCCH6_3_PerfMonCtr7_Lo 0x180b57 2529 #define regUMCCH6_3_PerfMonCtr7_Lo_BASE_IDX 1 2530 #define regUMCCH6_3_PerfMonCtr7_Hi 0x180b58 2531 #define regUMCCH6_3_PerfMonCtr7_Hi_BASE_IDX 1 2532 #define regUMCCH6_3_PerfMonCtl8 0x180b59 2533 #define regUMCCH6_3_PerfMonCtl8_BASE_IDX 1 2534 #define regUMCCH6_3_PerfMonCtr8_Lo 0x180b5a 2535 #define regUMCCH6_3_PerfMonCtr8_Lo_BASE_IDX 1 2536 #define regUMCCH6_3_PerfMonCtr8_Hi 0x180b5b 2537 #define regUMCCH6_3_PerfMonCtr8_Hi_BASE_IDX 1 2538 2539 2540 // addressBlock: umc_w_phy_umc3_umcch7_umcchdec 2541 // base address: 0x753000 2542 #define regUMCCH7_3_BaseAddrCS0 0x180c00 2543 #define regUMCCH7_3_BaseAddrCS0_BASE_IDX 1 2544 #define regUMCCH7_3_AddrMaskCS01 0x180c08 2545 #define regUMCCH7_3_AddrMaskCS01_BASE_IDX 1 2546 #define regUMCCH7_3_AddrSelCS01 0x180c10 2547 #define regUMCCH7_3_AddrSelCS01_BASE_IDX 1 2548 #define regUMCCH7_3_AddrHashBank0 0x180c32 2549 #define regUMCCH7_3_AddrHashBank0_BASE_IDX 1 2550 #define regUMCCH7_3_AddrHashBank1 0x180c33 2551 #define regUMCCH7_3_AddrHashBank1_BASE_IDX 1 2552 #define regUMCCH7_3_AddrHashBank2 0x180c34 2553 #define regUMCCH7_3_AddrHashBank2_BASE_IDX 1 2554 #define regUMCCH7_3_AddrHashBank3 0x180c35 2555 #define regUMCCH7_3_AddrHashBank3_BASE_IDX 1 2556 #define regUMCCH7_3_AddrHashBank4 0x180c36 2557 #define regUMCCH7_3_AddrHashBank4_BASE_IDX 1 2558 #define regUMCCH7_3_AddrHashBank5 0x180c37 2559 #define regUMCCH7_3_AddrHashBank5_BASE_IDX 1 2560 #define regUMCCH7_3_EccErrCntSel 0x180f28 2561 #define regUMCCH7_3_EccErrCntSel_BASE_IDX 1 2562 #define regUMCCH7_3_EccErrCnt 0x180f29 2563 #define regUMCCH7_3_EccErrCnt_BASE_IDX 1 2564 #define regUMCCH7_3_PerfMonCtlClk 0x180f40 2565 #define regUMCCH7_3_PerfMonCtlClk_BASE_IDX 1 2566 #define regUMCCH7_3_PerfMonCtrClk_Lo 0x180f41 2567 #define regUMCCH7_3_PerfMonCtrClk_Lo_BASE_IDX 1 2568 #define regUMCCH7_3_PerfMonCtrClk_Hi 0x180f42 2569 #define regUMCCH7_3_PerfMonCtrClk_Hi_BASE_IDX 1 2570 #define regUMCCH7_3_PerfMonCtl1 0x180f44 2571 #define regUMCCH7_3_PerfMonCtl1_BASE_IDX 1 2572 #define regUMCCH7_3_PerfMonCtr1_Lo 0x180f45 2573 #define regUMCCH7_3_PerfMonCtr1_Lo_BASE_IDX 1 2574 #define regUMCCH7_3_PerfMonCtr1_Hi 0x180f46 2575 #define regUMCCH7_3_PerfMonCtr1_Hi_BASE_IDX 1 2576 #define regUMCCH7_3_PerfMonCtl2 0x180f47 2577 #define regUMCCH7_3_PerfMonCtl2_BASE_IDX 1 2578 #define regUMCCH7_3_PerfMonCtr2_Lo 0x180f48 2579 #define regUMCCH7_3_PerfMonCtr2_Lo_BASE_IDX 1 2580 #define regUMCCH7_3_PerfMonCtr2_Hi 0x180f49 2581 #define regUMCCH7_3_PerfMonCtr2_Hi_BASE_IDX 1 2582 #define regUMCCH7_3_PerfMonCtl3 0x180f4a 2583 #define regUMCCH7_3_PerfMonCtl3_BASE_IDX 1 2584 #define regUMCCH7_3_PerfMonCtr3_Lo 0x180f4b 2585 #define regUMCCH7_3_PerfMonCtr3_Lo_BASE_IDX 1 2586 #define regUMCCH7_3_PerfMonCtr3_Hi 0x180f4c 2587 #define regUMCCH7_3_PerfMonCtr3_Hi_BASE_IDX 1 2588 #define regUMCCH7_3_PerfMonCtl4 0x180f4d 2589 #define regUMCCH7_3_PerfMonCtl4_BASE_IDX 1 2590 #define regUMCCH7_3_PerfMonCtr4_Lo 0x180f4e 2591 #define regUMCCH7_3_PerfMonCtr4_Lo_BASE_IDX 1 2592 #define regUMCCH7_3_PerfMonCtr4_Hi 0x180f4f 2593 #define regUMCCH7_3_PerfMonCtr4_Hi_BASE_IDX 1 2594 #define regUMCCH7_3_PerfMonCtl5 0x180f50 2595 #define regUMCCH7_3_PerfMonCtl5_BASE_IDX 1 2596 #define regUMCCH7_3_PerfMonCtr5_Lo 0x180f51 2597 #define regUMCCH7_3_PerfMonCtr5_Lo_BASE_IDX 1 2598 #define regUMCCH7_3_PerfMonCtr5_Hi 0x180f52 2599 #define regUMCCH7_3_PerfMonCtr5_Hi_BASE_IDX 1 2600 #define regUMCCH7_3_PerfMonCtl6 0x180f53 2601 #define regUMCCH7_3_PerfMonCtl6_BASE_IDX 1 2602 #define regUMCCH7_3_PerfMonCtr6_Lo 0x180f54 2603 #define regUMCCH7_3_PerfMonCtr6_Lo_BASE_IDX 1 2604 #define regUMCCH7_3_PerfMonCtr6_Hi 0x180f55 2605 #define regUMCCH7_3_PerfMonCtr6_Hi_BASE_IDX 1 2606 #define regUMCCH7_3_PerfMonCtl7 0x180f56 2607 #define regUMCCH7_3_PerfMonCtl7_BASE_IDX 1 2608 #define regUMCCH7_3_PerfMonCtr7_Lo 0x180f57 2609 #define regUMCCH7_3_PerfMonCtr7_Lo_BASE_IDX 1 2610 #define regUMCCH7_3_PerfMonCtr7_Hi 0x180f58 2611 #define regUMCCH7_3_PerfMonCtr7_Hi_BASE_IDX 1 2612 #define regUMCCH7_3_PerfMonCtl8 0x180f59 2613 #define regUMCCH7_3_PerfMonCtl8_BASE_IDX 1 2614 #define regUMCCH7_3_PerfMonCtr8_Lo 0x180f5a 2615 #define regUMCCH7_3_PerfMonCtr8_Lo_BASE_IDX 1 2616 #define regUMCCH7_3_PerfMonCtr8_Hi 0x180f5b 2617 #define regUMCCH7_3_PerfMonCtr8_Hi_BASE_IDX 1 2618 2619 2620 #endif 2621