/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _umc_6_7_0_OFFSET_HEADER #define _umc_6_7_0_OFFSET_HEADER // addressBlock: umc_w_phy_umc0_mca_ip_umc0_mca_map // base address: 0x50f00 #define regMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2 #define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0 #define regMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4 #define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0 // addressBlock: umc_w_phy_umc0_umcch0_umcchdec // base address: 0x50000 #define regUMCCH0_0_BaseAddrCS0 0x0000 #define regUMCCH0_0_BaseAddrCS0_BASE_IDX 0 #define regUMCCH0_0_AddrMaskCS01 0x0008 #define regUMCCH0_0_AddrMaskCS01_BASE_IDX 0 #define regUMCCH0_0_AddrSelCS01 0x0010 #define regUMCCH0_0_AddrSelCS01_BASE_IDX 0 #define regUMCCH0_0_AddrHashBank0 0x0032 #define regUMCCH0_0_AddrHashBank0_BASE_IDX 0 #define regUMCCH0_0_AddrHashBank1 0x0033 #define regUMCCH0_0_AddrHashBank1_BASE_IDX 0 #define regUMCCH0_0_AddrHashBank2 0x0034 #define regUMCCH0_0_AddrHashBank2_BASE_IDX 0 #define regUMCCH0_0_AddrHashBank3 0x0035 #define regUMCCH0_0_AddrHashBank3_BASE_IDX 0 #define regUMCCH0_0_AddrHashBank4 0x0036 #define regUMCCH0_0_AddrHashBank4_BASE_IDX 0 #define regUMCCH0_0_AddrHashBank5 0x0037 #define regUMCCH0_0_AddrHashBank5_BASE_IDX 0 #define regUMCCH0_0_UMC_CONFIG 0x0040 #define regUMCCH0_0_UMC_CONFIG_BASE_IDX 0 #define regUMCCH0_0_EccCtrl 0x0053 #define regUMCCH0_0_EccCtrl_BASE_IDX 0 #define regUMCCH0_0_UmcLocalCap 0x0306 #define regUMCCH0_0_UmcLocalCap_BASE_IDX 0 #define regUMCCH0_0_EccErrCntSel 0x0328 #define regUMCCH0_0_EccErrCntSel_BASE_IDX 0 #define regUMCCH0_0_EccErrCnt 0x0329 #define regUMCCH0_0_EccErrCnt_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtlClk 0x0340 #define regUMCCH0_0_PerfMonCtlClk_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtrClk_Lo 0x0341 #define regUMCCH0_0_PerfMonCtrClk_Lo_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtrClk_Hi 0x0342 #define regUMCCH0_0_PerfMonCtrClk_Hi_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtl1 0x0344 #define regUMCCH0_0_PerfMonCtl1_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr1_Lo 0x0345 #define regUMCCH0_0_PerfMonCtr1_Lo_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr1_Hi 0x0346 #define regUMCCH0_0_PerfMonCtr1_Hi_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtl2 0x0347 #define regUMCCH0_0_PerfMonCtl2_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr2_Lo 0x0348 #define regUMCCH0_0_PerfMonCtr2_Lo_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr2_Hi 0x0349 #define regUMCCH0_0_PerfMonCtr2_Hi_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtl3 0x034a #define regUMCCH0_0_PerfMonCtl3_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr3_Lo 0x034b #define regUMCCH0_0_PerfMonCtr3_Lo_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr3_Hi 0x034c #define regUMCCH0_0_PerfMonCtr3_Hi_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtl4 0x034d #define regUMCCH0_0_PerfMonCtl4_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr4_Lo 0x034e #define regUMCCH0_0_PerfMonCtr4_Lo_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr4_Hi 0x034f #define regUMCCH0_0_PerfMonCtr4_Hi_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtl5 0x0350 #define regUMCCH0_0_PerfMonCtl5_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr5_Lo 0x0351 #define regUMCCH0_0_PerfMonCtr5_Lo_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr5_Hi 0x0352 #define regUMCCH0_0_PerfMonCtr5_Hi_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtl6 0x0353 #define regUMCCH0_0_PerfMonCtl6_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr6_Lo 0x0354 #define regUMCCH0_0_PerfMonCtr6_Lo_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr6_Hi 0x0355 #define regUMCCH0_0_PerfMonCtr6_Hi_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtl7 0x0356 #define regUMCCH0_0_PerfMonCtl7_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr7_Lo 0x0357 #define regUMCCH0_0_PerfMonCtr7_Lo_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr7_Hi 0x0358 #define regUMCCH0_0_PerfMonCtr7_Hi_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtl8 0x0359 #define regUMCCH0_0_PerfMonCtl8_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr8_Lo 0x035a #define regUMCCH0_0_PerfMonCtr8_Lo_BASE_IDX 0 #define regUMCCH0_0_PerfMonCtr8_Hi 0x035b #define regUMCCH0_0_PerfMonCtr8_Hi_BASE_IDX 0 // addressBlock: umc_w_phy_umc0_umcch1_umcchdec // base address: 0x51000 #define regUMCCH1_0_BaseAddrCS0 0x0400 #define regUMCCH1_0_BaseAddrCS0_BASE_IDX 0 #define regUMCCH1_0_AddrMaskCS01 0x0408 #define regUMCCH1_0_AddrMaskCS01_BASE_IDX 0 #define regUMCCH1_0_AddrSelCS01 0x0410 #define regUMCCH1_0_AddrSelCS01_BASE_IDX 0 #define regUMCCH1_0_AddrHashBank0 0x0432 #define regUMCCH1_0_AddrHashBank0_BASE_IDX 0 #define regUMCCH1_0_AddrHashBank1 0x0433 #define regUMCCH1_0_AddrHashBank1_BASE_IDX 0 #define regUMCCH1_0_AddrHashBank2 0x0434 #define regUMCCH1_0_AddrHashBank2_BASE_IDX 0 #define regUMCCH1_0_AddrHashBank3 0x0435 #define regUMCCH1_0_AddrHashBank3_BASE_IDX 0 #define regUMCCH1_0_AddrHashBank4 0x0436 #define regUMCCH1_0_AddrHashBank4_BASE_IDX 0 #define regUMCCH1_0_AddrHashBank5 0x0437 #define regUMCCH1_0_AddrHashBank5_BASE_IDX 0 #define regUMCCH1_0_UMC_CONFIG 0x0440 #define regUMCCH1_0_UMC_CONFIG_BASE_IDX 0 #define regUMCCH1_0_EccCtrl 0x0453 #define regUMCCH1_0_EccCtrl_BASE_IDX 0 #define regUMCCH1_0_UmcLocalCap 0x0706 #define regUMCCH1_0_UmcLocalCap_BASE_IDX 0 #define regUMCCH1_0_EccErrCntSel 0x0728 #define regUMCCH1_0_EccErrCntSel_BASE_IDX 0 #define regUMCCH1_0_EccErrCnt 0x0729 #define regUMCCH1_0_EccErrCnt_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtlClk 0x0740 #define regUMCCH1_0_PerfMonCtlClk_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtrClk_Lo 0x0741 #define regUMCCH1_0_PerfMonCtrClk_Lo_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtrClk_Hi 0x0742 #define regUMCCH1_0_PerfMonCtrClk_Hi_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtl1 0x0744 #define regUMCCH1_0_PerfMonCtl1_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr1_Lo 0x0745 #define regUMCCH1_0_PerfMonCtr1_Lo_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr1_Hi 0x0746 #define regUMCCH1_0_PerfMonCtr1_Hi_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtl2 0x0747 #define regUMCCH1_0_PerfMonCtl2_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr2_Lo 0x0748 #define regUMCCH1_0_PerfMonCtr2_Lo_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr2_Hi 0x0749 #define regUMCCH1_0_PerfMonCtr2_Hi_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtl3 0x074a #define regUMCCH1_0_PerfMonCtl3_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr3_Lo 0x074b #define regUMCCH1_0_PerfMonCtr3_Lo_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr3_Hi 0x074c #define regUMCCH1_0_PerfMonCtr3_Hi_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtl4 0x074d #define regUMCCH1_0_PerfMonCtl4_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr4_Lo 0x074e #define regUMCCH1_0_PerfMonCtr4_Lo_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr4_Hi 0x074f #define regUMCCH1_0_PerfMonCtr4_Hi_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtl5 0x0750 #define regUMCCH1_0_PerfMonCtl5_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr5_Lo 0x0751 #define regUMCCH1_0_PerfMonCtr5_Lo_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr5_Hi 0x0752 #define regUMCCH1_0_PerfMonCtr5_Hi_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtl6 0x0753 #define regUMCCH1_0_PerfMonCtl6_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr6_Lo 0x0754 #define regUMCCH1_0_PerfMonCtr6_Lo_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr6_Hi 0x0755 #define regUMCCH1_0_PerfMonCtr6_Hi_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtl7 0x0756 #define regUMCCH1_0_PerfMonCtl7_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr7_Lo 0x0757 #define regUMCCH1_0_PerfMonCtr7_Lo_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr7_Hi 0x0758 #define regUMCCH1_0_PerfMonCtr7_Hi_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtl8 0x0759 #define regUMCCH1_0_PerfMonCtl8_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr8_Lo 0x075a #define regUMCCH1_0_PerfMonCtr8_Lo_BASE_IDX 0 #define regUMCCH1_0_PerfMonCtr8_Hi 0x075b #define regUMCCH1_0_PerfMonCtr8_Hi_BASE_IDX 0 // addressBlock: umc_w_phy_umc0_umcch2_umcchdec // base address: 0x52000 #define regUMCCH2_0_BaseAddrCS0 0x0800 #define regUMCCH2_0_BaseAddrCS0_BASE_IDX 0 #define regUMCCH2_0_AddrMaskCS01 0x0808 #define regUMCCH2_0_AddrMaskCS01_BASE_IDX 0 #define regUMCCH2_0_AddrSelCS01 0x0810 #define regUMCCH2_0_AddrSelCS01_BASE_IDX 0 #define regUMCCH2_0_AddrHashBank0 0x0832 #define regUMCCH2_0_AddrHashBank0_BASE_IDX 0 #define regUMCCH2_0_AddrHashBank1 0x0833 #define regUMCCH2_0_AddrHashBank1_BASE_IDX 0 #define regUMCCH2_0_AddrHashBank2 0x0834 #define regUMCCH2_0_AddrHashBank2_BASE_IDX 0 #define regUMCCH2_0_AddrHashBank3 0x0835 #define regUMCCH2_0_AddrHashBank3_BASE_IDX 0 #define regUMCCH2_0_AddrHashBank4 0x0836 #define regUMCCH2_0_AddrHashBank4_BASE_IDX 0 #define regUMCCH2_0_AddrHashBank5 0x0837 #define regUMCCH2_0_AddrHashBank5_BASE_IDX 0 #define regUMCCH2_0_UMC_CONFIG 0x0840 #define regUMCCH2_0_UMC_CONFIG_BASE_IDX 0 #define regUMCCH2_0_EccCtrl 0x0853 #define regUMCCH2_0_EccCtrl_BASE_IDX 0 #define regUMCCH2_0_UmcLocalCap 0x0b06 #define regUMCCH2_0_UmcLocalCap_BASE_IDX 0 #define regUMCCH2_0_EccErrCntSel 0x0b28 #define regUMCCH2_0_EccErrCntSel_BASE_IDX 0 #define regUMCCH2_0_EccErrCnt 0x0b29 #define regUMCCH2_0_EccErrCnt_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtlClk 0x0b40 #define regUMCCH2_0_PerfMonCtlClk_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtrClk_Lo 0x0b41 #define regUMCCH2_0_PerfMonCtrClk_Lo_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtrClk_Hi 0x0b42 #define regUMCCH2_0_PerfMonCtrClk_Hi_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtl1 0x0b44 #define regUMCCH2_0_PerfMonCtl1_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr1_Lo 0x0b45 #define regUMCCH2_0_PerfMonCtr1_Lo_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr1_Hi 0x0b46 #define regUMCCH2_0_PerfMonCtr1_Hi_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtl2 0x0b47 #define regUMCCH2_0_PerfMonCtl2_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr2_Lo 0x0b48 #define regUMCCH2_0_PerfMonCtr2_Lo_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr2_Hi 0x0b49 #define regUMCCH2_0_PerfMonCtr2_Hi_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtl3 0x0b4a #define regUMCCH2_0_PerfMonCtl3_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr3_Lo 0x0b4b #define regUMCCH2_0_PerfMonCtr3_Lo_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr3_Hi 0x0b4c #define regUMCCH2_0_PerfMonCtr3_Hi_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtl4 0x0b4d #define regUMCCH2_0_PerfMonCtl4_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr4_Lo 0x0b4e #define regUMCCH2_0_PerfMonCtr4_Lo_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr4_Hi 0x0b4f #define regUMCCH2_0_PerfMonCtr4_Hi_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtl5 0x0b50 #define regUMCCH2_0_PerfMonCtl5_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr5_Lo 0x0b51 #define regUMCCH2_0_PerfMonCtr5_Lo_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr5_Hi 0x0b52 #define regUMCCH2_0_PerfMonCtr5_Hi_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtl6 0x0b53 #define regUMCCH2_0_PerfMonCtl6_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr6_Lo 0x0b54 #define regUMCCH2_0_PerfMonCtr6_Lo_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr6_Hi 0x0b55 #define regUMCCH2_0_PerfMonCtr6_Hi_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtl7 0x0b56 #define regUMCCH2_0_PerfMonCtl7_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr7_Lo 0x0b57 #define regUMCCH2_0_PerfMonCtr7_Lo_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr7_Hi 0x0b58 #define regUMCCH2_0_PerfMonCtr7_Hi_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtl8 0x0b59 #define regUMCCH2_0_PerfMonCtl8_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr8_Lo 0x0b5a #define regUMCCH2_0_PerfMonCtr8_Lo_BASE_IDX 0 #define regUMCCH2_0_PerfMonCtr8_Hi 0x0b5b #define regUMCCH2_0_PerfMonCtr8_Hi_BASE_IDX 0 // addressBlock: umc_w_phy_umc0_umcch3_umcchdec // base address: 0x53000 #define regUMCCH3_0_BaseAddrCS0 0x0c00 #define regUMCCH3_0_BaseAddrCS0_BASE_IDX 0 #define regUMCCH3_0_AddrMaskCS01 0x0c08 #define regUMCCH3_0_AddrMaskCS01_BASE_IDX 0 #define regUMCCH3_0_AddrSelCS01 0x0c10 #define regUMCCH3_0_AddrSelCS01_BASE_IDX 0 #define regUMCCH3_0_AddrHashBank0 0x0c32 #define regUMCCH3_0_AddrHashBank0_BASE_IDX 0 #define regUMCCH3_0_AddrHashBank1 0x0c33 #define regUMCCH3_0_AddrHashBank1_BASE_IDX 0 #define regUMCCH3_0_AddrHashBank2 0x0c34 #define regUMCCH3_0_AddrHashBank2_BASE_IDX 0 #define regUMCCH3_0_AddrHashBank3 0x0c35 #define regUMCCH3_0_AddrHashBank3_BASE_IDX 0 #define regUMCCH3_0_AddrHashBank4 0x0c36 #define regUMCCH3_0_AddrHashBank4_BASE_IDX 0 #define regUMCCH3_0_AddrHashBank5 0x0c37 #define regUMCCH3_0_AddrHashBank5_BASE_IDX 0 #define regUMCCH3_0_UMC_CONFIG 0x0c40 #define regUMCCH3_0_UMC_CONFIG_BASE_IDX 0 #define regUMCCH3_0_EccCtrl 0x0c53 #define regUMCCH3_0_EccCtrl_BASE_IDX 0 #define regUMCCH3_0_UmcLocalCap 0x0f06 #define regUMCCH3_0_UmcLocalCap_BASE_IDX 0 #define regUMCCH3_0_EccErrCntSel 0x0f28 #define regUMCCH3_0_EccErrCntSel_BASE_IDX 0 #define regUMCCH3_0_EccErrCnt 0x0f29 #define regUMCCH3_0_EccErrCnt_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtlClk 0x0f40 #define regUMCCH3_0_PerfMonCtlClk_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtrClk_Lo 0x0f41 #define regUMCCH3_0_PerfMonCtrClk_Lo_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtrClk_Hi 0x0f42 #define regUMCCH3_0_PerfMonCtrClk_Hi_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtl1 0x0f44 #define regUMCCH3_0_PerfMonCtl1_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr1_Lo 0x0f45 #define regUMCCH3_0_PerfMonCtr1_Lo_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr1_Hi 0x0f46 #define regUMCCH3_0_PerfMonCtr1_Hi_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtl2 0x0f47 #define regUMCCH3_0_PerfMonCtl2_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr2_Lo 0x0f48 #define regUMCCH3_0_PerfMonCtr2_Lo_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr2_Hi 0x0f49 #define regUMCCH3_0_PerfMonCtr2_Hi_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtl3 0x0f4a #define regUMCCH3_0_PerfMonCtl3_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr3_Lo 0x0f4b #define regUMCCH3_0_PerfMonCtr3_Lo_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr3_Hi 0x0f4c #define regUMCCH3_0_PerfMonCtr3_Hi_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtl4 0x0f4d #define regUMCCH3_0_PerfMonCtl4_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr4_Lo 0x0f4e #define regUMCCH3_0_PerfMonCtr4_Lo_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr4_Hi 0x0f4f #define regUMCCH3_0_PerfMonCtr4_Hi_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtl5 0x0f50 #define regUMCCH3_0_PerfMonCtl5_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr5_Lo 0x0f51 #define regUMCCH3_0_PerfMonCtr5_Lo_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr5_Hi 0x0f52 #define regUMCCH3_0_PerfMonCtr5_Hi_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtl6 0x0f53 #define regUMCCH3_0_PerfMonCtl6_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr6_Lo 0x0f54 #define regUMCCH3_0_PerfMonCtr6_Lo_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr6_Hi 0x0f55 #define regUMCCH3_0_PerfMonCtr6_Hi_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtl7 0x0f56 #define regUMCCH3_0_PerfMonCtl7_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr7_Lo 0x0f57 #define regUMCCH3_0_PerfMonCtr7_Lo_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr7_Hi 0x0f58 #define regUMCCH3_0_PerfMonCtr7_Hi_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtl8 0x0f59 #define regUMCCH3_0_PerfMonCtl8_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr8_Lo 0x0f5a #define regUMCCH3_0_PerfMonCtr8_Lo_BASE_IDX 0 #define regUMCCH3_0_PerfMonCtr8_Hi 0x0f5b #define regUMCCH3_0_PerfMonCtr8_Hi_BASE_IDX 0 // addressBlock: umc_w_phy_umc0_umcch4_umcchdec // base address: 0x150000 #define regUMCCH4_0_BaseAddrCS0 0x0000 #define regUMCCH4_0_BaseAddrCS0_BASE_IDX 1 #define regUMCCH4_0_AddrMaskCS01 0x0008 #define regUMCCH4_0_AddrMaskCS01_BASE_IDX 1 #define regUMCCH4_0_AddrSelCS01 0x0010 #define regUMCCH4_0_AddrSelCS01_BASE_IDX 1 #define regUMCCH4_0_AddrHashBank0 0x0032 #define regUMCCH4_0_AddrHashBank0_BASE_IDX 1 #define regUMCCH4_0_AddrHashBank1 0x0033 #define regUMCCH4_0_AddrHashBank1_BASE_IDX 1 #define regUMCCH4_0_AddrHashBank2 0x0034 #define regUMCCH4_0_AddrHashBank2_BASE_IDX 1 #define regUMCCH4_0_AddrHashBank3 0x0035 #define regUMCCH4_0_AddrHashBank3_BASE_IDX 1 #define regUMCCH4_0_AddrHashBank4 0x0036 #define regUMCCH4_0_AddrHashBank4_BASE_IDX 1 #define regUMCCH4_0_AddrHashBank5 0x0037 #define regUMCCH4_0_AddrHashBank5_BASE_IDX 1 #define regUMCCH4_0_EccErrCntSel 0x0328 #define regUMCCH4_0_EccErrCntSel_BASE_IDX 1 #define regUMCCH4_0_EccErrCnt 0x0329 #define regUMCCH4_0_EccErrCnt_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtlClk 0x0340 #define regUMCCH4_0_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtrClk_Lo 0x0341 #define regUMCCH4_0_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtrClk_Hi 0x0342 #define regUMCCH4_0_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtl1 0x0344 #define regUMCCH4_0_PerfMonCtl1_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr1_Lo 0x0345 #define regUMCCH4_0_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr1_Hi 0x0346 #define regUMCCH4_0_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtl2 0x0347 #define regUMCCH4_0_PerfMonCtl2_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr2_Lo 0x0348 #define regUMCCH4_0_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr2_Hi 0x0349 #define regUMCCH4_0_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtl3 0x034a #define regUMCCH4_0_PerfMonCtl3_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr3_Lo 0x034b #define regUMCCH4_0_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr3_Hi 0x034c #define regUMCCH4_0_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtl4 0x034d #define regUMCCH4_0_PerfMonCtl4_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr4_Lo 0x034e #define regUMCCH4_0_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr4_Hi 0x034f #define regUMCCH4_0_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtl5 0x0350 #define regUMCCH4_0_PerfMonCtl5_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr5_Lo 0x0351 #define regUMCCH4_0_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr5_Hi 0x0352 #define regUMCCH4_0_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtl6 0x0353 #define regUMCCH4_0_PerfMonCtl6_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr6_Lo 0x0354 #define regUMCCH4_0_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr6_Hi 0x0355 #define regUMCCH4_0_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtl7 0x0356 #define regUMCCH4_0_PerfMonCtl7_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr7_Lo 0x0357 #define regUMCCH4_0_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr7_Hi 0x0358 #define regUMCCH4_0_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtl8 0x0359 #define regUMCCH4_0_PerfMonCtl8_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr8_Lo 0x035a #define regUMCCH4_0_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH4_0_PerfMonCtr8_Hi 0x035b #define regUMCCH4_0_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc0_umcch5_umcchdec // base address: 0x151000 #define regUMCCH5_0_BaseAddrCS0 0x0400 #define regUMCCH5_0_BaseAddrCS0_BASE_IDX 1 #define regUMCCH5_0_AddrMaskCS01 0x0408 #define regUMCCH5_0_AddrMaskCS01_BASE_IDX 1 #define regUMCCH5_0_AddrSelCS01 0x0410 #define regUMCCH5_0_AddrSelCS01_BASE_IDX 1 #define regUMCCH5_0_AddrHashBank0 0x0432 #define regUMCCH5_0_AddrHashBank0_BASE_IDX 1 #define regUMCCH5_0_AddrHashBank1 0x0433 #define regUMCCH5_0_AddrHashBank1_BASE_IDX 1 #define regUMCCH5_0_AddrHashBank2 0x0434 #define regUMCCH5_0_AddrHashBank2_BASE_IDX 1 #define regUMCCH5_0_AddrHashBank3 0x0435 #define regUMCCH5_0_AddrHashBank3_BASE_IDX 1 #define regUMCCH5_0_AddrHashBank4 0x0436 #define regUMCCH5_0_AddrHashBank4_BASE_IDX 1 #define regUMCCH5_0_AddrHashBank5 0x0437 #define regUMCCH5_0_AddrHashBank5_BASE_IDX 1 #define regUMCCH5_0_EccErrCntSel 0x0728 #define regUMCCH5_0_EccErrCntSel_BASE_IDX 1 #define regUMCCH5_0_EccErrCnt 0x0729 #define regUMCCH5_0_EccErrCnt_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtlClk 0x0740 #define regUMCCH5_0_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtrClk_Lo 0x0741 #define regUMCCH5_0_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtrClk_Hi 0x0742 #define regUMCCH5_0_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtl1 0x0744 #define regUMCCH5_0_PerfMonCtl1_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr1_Lo 0x0745 #define regUMCCH5_0_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr1_Hi 0x0746 #define regUMCCH5_0_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtl2 0x0747 #define regUMCCH5_0_PerfMonCtl2_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr2_Lo 0x0748 #define regUMCCH5_0_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr2_Hi 0x0749 #define regUMCCH5_0_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtl3 0x074a #define regUMCCH5_0_PerfMonCtl3_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr3_Lo 0x074b #define regUMCCH5_0_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr3_Hi 0x074c #define regUMCCH5_0_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtl4 0x074d #define regUMCCH5_0_PerfMonCtl4_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr4_Lo 0x074e #define regUMCCH5_0_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr4_Hi 0x074f #define regUMCCH5_0_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtl5 0x0750 #define regUMCCH5_0_PerfMonCtl5_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr5_Lo 0x0751 #define regUMCCH5_0_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr5_Hi 0x0752 #define regUMCCH5_0_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtl6 0x0753 #define regUMCCH5_0_PerfMonCtl6_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr6_Lo 0x0754 #define regUMCCH5_0_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr6_Hi 0x0755 #define regUMCCH5_0_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtl7 0x0756 #define regUMCCH5_0_PerfMonCtl7_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr7_Lo 0x0757 #define regUMCCH5_0_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr7_Hi 0x0758 #define regUMCCH5_0_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtl8 0x0759 #define regUMCCH5_0_PerfMonCtl8_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr8_Lo 0x075a #define regUMCCH5_0_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH5_0_PerfMonCtr8_Hi 0x075b #define regUMCCH5_0_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc0_umcch6_umcchdec // base address: 0x152000 #define regUMCCH6_0_BaseAddrCS0 0x0800 #define regUMCCH6_0_BaseAddrCS0_BASE_IDX 1 #define regUMCCH6_0_AddrMaskCS01 0x0808 #define regUMCCH6_0_AddrMaskCS01_BASE_IDX 1 #define regUMCCH6_0_AddrSelCS01 0x0810 #define regUMCCH6_0_AddrSelCS01_BASE_IDX 1 #define regUMCCH6_0_AddrHashBank0 0x0832 #define regUMCCH6_0_AddrHashBank0_BASE_IDX 1 #define regUMCCH6_0_AddrHashBank1 0x0833 #define regUMCCH6_0_AddrHashBank1_BASE_IDX 1 #define regUMCCH6_0_AddrHashBank2 0x0834 #define regUMCCH6_0_AddrHashBank2_BASE_IDX 1 #define regUMCCH6_0_AddrHashBank3 0x0835 #define regUMCCH6_0_AddrHashBank3_BASE_IDX 1 #define regUMCCH6_0_AddrHashBank4 0x0836 #define regUMCCH6_0_AddrHashBank4_BASE_IDX 1 #define regUMCCH6_0_AddrHashBank5 0x0837 #define regUMCCH6_0_AddrHashBank5_BASE_IDX 1 #define regUMCCH6_0_EccErrCntSel 0x0b28 #define regUMCCH6_0_EccErrCntSel_BASE_IDX 1 #define regUMCCH6_0_EccErrCnt 0x0b29 #define regUMCCH6_0_EccErrCnt_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtlClk 0x0b40 #define regUMCCH6_0_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtrClk_Lo 0x0b41 #define regUMCCH6_0_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtrClk_Hi 0x0b42 #define regUMCCH6_0_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtl1 0x0b44 #define regUMCCH6_0_PerfMonCtl1_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr1_Lo 0x0b45 #define regUMCCH6_0_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr1_Hi 0x0b46 #define regUMCCH6_0_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtl2 0x0b47 #define regUMCCH6_0_PerfMonCtl2_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr2_Lo 0x0b48 #define regUMCCH6_0_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr2_Hi 0x0b49 #define regUMCCH6_0_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtl3 0x0b4a #define regUMCCH6_0_PerfMonCtl3_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr3_Lo 0x0b4b #define regUMCCH6_0_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr3_Hi 0x0b4c #define regUMCCH6_0_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtl4 0x0b4d #define regUMCCH6_0_PerfMonCtl4_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr4_Lo 0x0b4e #define regUMCCH6_0_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr4_Hi 0x0b4f #define regUMCCH6_0_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtl5 0x0b50 #define regUMCCH6_0_PerfMonCtl5_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr5_Lo 0x0b51 #define regUMCCH6_0_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr5_Hi 0x0b52 #define regUMCCH6_0_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtl6 0x0b53 #define regUMCCH6_0_PerfMonCtl6_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr6_Lo 0x0b54 #define regUMCCH6_0_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr6_Hi 0x0b55 #define regUMCCH6_0_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtl7 0x0b56 #define regUMCCH6_0_PerfMonCtl7_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr7_Lo 0x0b57 #define regUMCCH6_0_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr7_Hi 0x0b58 #define regUMCCH6_0_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtl8 0x0b59 #define regUMCCH6_0_PerfMonCtl8_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr8_Lo 0x0b5a #define regUMCCH6_0_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH6_0_PerfMonCtr8_Hi 0x0b5b #define regUMCCH6_0_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc0_umcch7_umcchdec // base address: 0x153000 #define regUMCCH7_0_BaseAddrCS0 0x0c00 #define regUMCCH7_0_BaseAddrCS0_BASE_IDX 1 #define regUMCCH7_0_AddrMaskCS01 0x0c08 #define regUMCCH7_0_AddrMaskCS01_BASE_IDX 1 #define regUMCCH7_0_AddrSelCS01 0x0c10 #define regUMCCH7_0_AddrSelCS01_BASE_IDX 1 #define regUMCCH7_0_AddrHashBank0 0x0c32 #define regUMCCH7_0_AddrHashBank0_BASE_IDX 1 #define regUMCCH7_0_AddrHashBank1 0x0c33 #define regUMCCH7_0_AddrHashBank1_BASE_IDX 1 #define regUMCCH7_0_AddrHashBank2 0x0c34 #define regUMCCH7_0_AddrHashBank2_BASE_IDX 1 #define regUMCCH7_0_AddrHashBank3 0x0c35 #define regUMCCH7_0_AddrHashBank3_BASE_IDX 1 #define regUMCCH7_0_AddrHashBank4 0x0c36 #define regUMCCH7_0_AddrHashBank4_BASE_IDX 1 #define regUMCCH7_0_AddrHashBank5 0x0c37 #define regUMCCH7_0_AddrHashBank5_BASE_IDX 1 #define regUMCCH7_0_EccErrCntSel 0x0f28 #define regUMCCH7_0_EccErrCntSel_BASE_IDX 1 #define regUMCCH7_0_EccErrCnt 0x0f29 #define regUMCCH7_0_EccErrCnt_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtlClk 0x0f40 #define regUMCCH7_0_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtrClk_Lo 0x0f41 #define regUMCCH7_0_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtrClk_Hi 0x0f42 #define regUMCCH7_0_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtl1 0x0f44 #define regUMCCH7_0_PerfMonCtl1_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr1_Lo 0x0f45 #define regUMCCH7_0_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr1_Hi 0x0f46 #define regUMCCH7_0_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtl2 0x0f47 #define regUMCCH7_0_PerfMonCtl2_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr2_Lo 0x0f48 #define regUMCCH7_0_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr2_Hi 0x0f49 #define regUMCCH7_0_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtl3 0x0f4a #define regUMCCH7_0_PerfMonCtl3_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr3_Lo 0x0f4b #define regUMCCH7_0_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr3_Hi 0x0f4c #define regUMCCH7_0_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtl4 0x0f4d #define regUMCCH7_0_PerfMonCtl4_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr4_Lo 0x0f4e #define regUMCCH7_0_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr4_Hi 0x0f4f #define regUMCCH7_0_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtl5 0x0f50 #define regUMCCH7_0_PerfMonCtl5_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr5_Lo 0x0f51 #define regUMCCH7_0_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr5_Hi 0x0f52 #define regUMCCH7_0_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtl6 0x0f53 #define regUMCCH7_0_PerfMonCtl6_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr6_Lo 0x0f54 #define regUMCCH7_0_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr6_Hi 0x0f55 #define regUMCCH7_0_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtl7 0x0f56 #define regUMCCH7_0_PerfMonCtl7_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr7_Lo 0x0f57 #define regUMCCH7_0_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr7_Hi 0x0f58 #define regUMCCH7_0_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtl8 0x0f59 #define regUMCCH7_0_PerfMonCtl8_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr8_Lo 0x0f5a #define regUMCCH7_0_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH7_0_PerfMonCtr8_Hi 0x0f5b #define regUMCCH7_0_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc1_umcch0_umcchdec // base address: 0x250000 #define regUMCCH0_1_BaseAddrCS0 0x40000 #define regUMCCH0_1_BaseAddrCS0_BASE_IDX 1 #define regUMCCH0_1_AddrMaskCS01 0x40008 #define regUMCCH0_1_AddrMaskCS01_BASE_IDX 1 #define regUMCCH0_1_AddrSelCS01 0x40010 #define regUMCCH0_1_AddrSelCS01_BASE_IDX 1 #define regUMCCH0_1_AddrHashBank0 0x40032 #define regUMCCH0_1_AddrHashBank0_BASE_IDX 1 #define regUMCCH0_1_AddrHashBank1 0x40033 #define regUMCCH0_1_AddrHashBank1_BASE_IDX 1 #define regUMCCH0_1_AddrHashBank2 0x40034 #define regUMCCH0_1_AddrHashBank2_BASE_IDX 1 #define regUMCCH0_1_AddrHashBank3 0x40035 #define regUMCCH0_1_AddrHashBank3_BASE_IDX 1 #define regUMCCH0_1_AddrHashBank4 0x40036 #define regUMCCH0_1_AddrHashBank4_BASE_IDX 1 #define regUMCCH0_1_AddrHashBank5 0x40037 #define regUMCCH0_1_AddrHashBank5_BASE_IDX 1 #define regUMCCH0_1_EccErrCntSel 0x40328 #define regUMCCH0_1_EccErrCntSel_BASE_IDX 1 #define regUMCCH0_1_EccErrCnt 0x40329 #define regUMCCH0_1_EccErrCnt_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtlClk 0x40340 #define regUMCCH0_1_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtrClk_Lo 0x40341 #define regUMCCH0_1_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtrClk_Hi 0x40342 #define regUMCCH0_1_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtl1 0x40344 #define regUMCCH0_1_PerfMonCtl1_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr1_Lo 0x40345 #define regUMCCH0_1_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr1_Hi 0x40346 #define regUMCCH0_1_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtl2 0x40347 #define regUMCCH0_1_PerfMonCtl2_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr2_Lo 0x40348 #define regUMCCH0_1_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr2_Hi 0x40349 #define regUMCCH0_1_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtl3 0x4034a #define regUMCCH0_1_PerfMonCtl3_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr3_Lo 0x4034b #define regUMCCH0_1_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr3_Hi 0x4034c #define regUMCCH0_1_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtl4 0x4034d #define regUMCCH0_1_PerfMonCtl4_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr4_Lo 0x4034e #define regUMCCH0_1_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr4_Hi 0x4034f #define regUMCCH0_1_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtl5 0x40350 #define regUMCCH0_1_PerfMonCtl5_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr5_Lo 0x40351 #define regUMCCH0_1_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr5_Hi 0x40352 #define regUMCCH0_1_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtl6 0x40353 #define regUMCCH0_1_PerfMonCtl6_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr6_Lo 0x40354 #define regUMCCH0_1_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr6_Hi 0x40355 #define regUMCCH0_1_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtl7 0x40356 #define regUMCCH0_1_PerfMonCtl7_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr7_Lo 0x40357 #define regUMCCH0_1_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr7_Hi 0x40358 #define regUMCCH0_1_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtl8 0x40359 #define regUMCCH0_1_PerfMonCtl8_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr8_Lo 0x4035a #define regUMCCH0_1_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH0_1_PerfMonCtr8_Hi 0x4035b #define regUMCCH0_1_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc1_umcch1_umcchdec // base address: 0x251000 #define regUMCCH1_1_BaseAddrCS0 0x40400 #define regUMCCH1_1_BaseAddrCS0_BASE_IDX 1 #define regUMCCH1_1_AddrMaskCS01 0x40408 #define regUMCCH1_1_AddrMaskCS01_BASE_IDX 1 #define regUMCCH1_1_AddrSelCS01 0x40410 #define regUMCCH1_1_AddrSelCS01_BASE_IDX 1 #define regUMCCH1_1_AddrHashBank0 0x40432 #define regUMCCH1_1_AddrHashBank0_BASE_IDX 1 #define regUMCCH1_1_AddrHashBank1 0x40433 #define regUMCCH1_1_AddrHashBank1_BASE_IDX 1 #define regUMCCH1_1_AddrHashBank2 0x40434 #define regUMCCH1_1_AddrHashBank2_BASE_IDX 1 #define regUMCCH1_1_AddrHashBank3 0x40435 #define regUMCCH1_1_AddrHashBank3_BASE_IDX 1 #define regUMCCH1_1_AddrHashBank4 0x40436 #define regUMCCH1_1_AddrHashBank4_BASE_IDX 1 #define regUMCCH1_1_AddrHashBank5 0x40437 #define regUMCCH1_1_AddrHashBank5_BASE_IDX 1 #define regUMCCH1_1_EccErrCntSel 0x40728 #define regUMCCH1_1_EccErrCntSel_BASE_IDX 1 #define regUMCCH1_1_EccErrCnt 0x40729 #define regUMCCH1_1_EccErrCnt_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtlClk 0x40740 #define regUMCCH1_1_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtrClk_Lo 0x40741 #define regUMCCH1_1_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtrClk_Hi 0x40742 #define regUMCCH1_1_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtl1 0x40744 #define regUMCCH1_1_PerfMonCtl1_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr1_Lo 0x40745 #define regUMCCH1_1_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr1_Hi 0x40746 #define regUMCCH1_1_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtl2 0x40747 #define regUMCCH1_1_PerfMonCtl2_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr2_Lo 0x40748 #define regUMCCH1_1_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr2_Hi 0x40749 #define regUMCCH1_1_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtl3 0x4074a #define regUMCCH1_1_PerfMonCtl3_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr3_Lo 0x4074b #define regUMCCH1_1_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr3_Hi 0x4074c #define regUMCCH1_1_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtl4 0x4074d #define regUMCCH1_1_PerfMonCtl4_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr4_Lo 0x4074e #define regUMCCH1_1_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr4_Hi 0x4074f #define regUMCCH1_1_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtl5 0x40750 #define regUMCCH1_1_PerfMonCtl5_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr5_Lo 0x40751 #define regUMCCH1_1_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr5_Hi 0x40752 #define regUMCCH1_1_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtl6 0x40753 #define regUMCCH1_1_PerfMonCtl6_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr6_Lo 0x40754 #define regUMCCH1_1_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr6_Hi 0x40755 #define regUMCCH1_1_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtl7 0x40756 #define regUMCCH1_1_PerfMonCtl7_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr7_Lo 0x40757 #define regUMCCH1_1_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr7_Hi 0x40758 #define regUMCCH1_1_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtl8 0x40759 #define regUMCCH1_1_PerfMonCtl8_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr8_Lo 0x4075a #define regUMCCH1_1_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH1_1_PerfMonCtr8_Hi 0x4075b #define regUMCCH1_1_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc1_umcch2_umcchdec // base address: 0x252000 #define regUMCCH2_1_BaseAddrCS0 0x40800 #define regUMCCH2_1_BaseAddrCS0_BASE_IDX 1 #define regUMCCH2_1_AddrMaskCS01 0x40808 #define regUMCCH2_1_AddrMaskCS01_BASE_IDX 1 #define regUMCCH2_1_AddrSelCS01 0x40810 #define regUMCCH2_1_AddrSelCS01_BASE_IDX 1 #define regUMCCH2_1_AddrHashBank0 0x40832 #define regUMCCH2_1_AddrHashBank0_BASE_IDX 1 #define regUMCCH2_1_AddrHashBank1 0x40833 #define regUMCCH2_1_AddrHashBank1_BASE_IDX 1 #define regUMCCH2_1_AddrHashBank2 0x40834 #define regUMCCH2_1_AddrHashBank2_BASE_IDX 1 #define regUMCCH2_1_AddrHashBank3 0x40835 #define regUMCCH2_1_AddrHashBank3_BASE_IDX 1 #define regUMCCH2_1_AddrHashBank4 0x40836 #define regUMCCH2_1_AddrHashBank4_BASE_IDX 1 #define regUMCCH2_1_AddrHashBank5 0x40837 #define regUMCCH2_1_AddrHashBank5_BASE_IDX 1 #define regUMCCH2_1_EccErrCntSel 0x40b28 #define regUMCCH2_1_EccErrCntSel_BASE_IDX 1 #define regUMCCH2_1_EccErrCnt 0x40b29 #define regUMCCH2_1_EccErrCnt_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtlClk 0x40b40 #define regUMCCH2_1_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtrClk_Lo 0x40b41 #define regUMCCH2_1_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtrClk_Hi 0x40b42 #define regUMCCH2_1_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtl1 0x40b44 #define regUMCCH2_1_PerfMonCtl1_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr1_Lo 0x40b45 #define regUMCCH2_1_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr1_Hi 0x40b46 #define regUMCCH2_1_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtl2 0x40b47 #define regUMCCH2_1_PerfMonCtl2_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr2_Lo 0x40b48 #define regUMCCH2_1_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr2_Hi 0x40b49 #define regUMCCH2_1_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtl3 0x40b4a #define regUMCCH2_1_PerfMonCtl3_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr3_Lo 0x40b4b #define regUMCCH2_1_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr3_Hi 0x40b4c #define regUMCCH2_1_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtl4 0x40b4d #define regUMCCH2_1_PerfMonCtl4_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr4_Lo 0x40b4e #define regUMCCH2_1_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr4_Hi 0x40b4f #define regUMCCH2_1_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtl5 0x40b50 #define regUMCCH2_1_PerfMonCtl5_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr5_Lo 0x40b51 #define regUMCCH2_1_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr5_Hi 0x40b52 #define regUMCCH2_1_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtl6 0x40b53 #define regUMCCH2_1_PerfMonCtl6_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr6_Lo 0x40b54 #define regUMCCH2_1_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr6_Hi 0x40b55 #define regUMCCH2_1_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtl7 0x40b56 #define regUMCCH2_1_PerfMonCtl7_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr7_Lo 0x40b57 #define regUMCCH2_1_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr7_Hi 0x40b58 #define regUMCCH2_1_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtl8 0x40b59 #define regUMCCH2_1_PerfMonCtl8_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr8_Lo 0x40b5a #define regUMCCH2_1_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH2_1_PerfMonCtr8_Hi 0x40b5b #define regUMCCH2_1_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc1_umcch3_umcchdec // base address: 0x253000 #define regUMCCH3_1_BaseAddrCS0 0x40c00 #define regUMCCH3_1_BaseAddrCS0_BASE_IDX 1 #define regUMCCH3_1_AddrMaskCS01 0x40c08 #define regUMCCH3_1_AddrMaskCS01_BASE_IDX 1 #define regUMCCH3_1_AddrSelCS01 0x40c10 #define regUMCCH3_1_AddrSelCS01_BASE_IDX 1 #define regUMCCH3_1_AddrHashBank0 0x40c32 #define regUMCCH3_1_AddrHashBank0_BASE_IDX 1 #define regUMCCH3_1_AddrHashBank1 0x40c33 #define regUMCCH3_1_AddrHashBank1_BASE_IDX 1 #define regUMCCH3_1_AddrHashBank2 0x40c34 #define regUMCCH3_1_AddrHashBank2_BASE_IDX 1 #define regUMCCH3_1_AddrHashBank3 0x40c35 #define regUMCCH3_1_AddrHashBank3_BASE_IDX 1 #define regUMCCH3_1_AddrHashBank4 0x40c36 #define regUMCCH3_1_AddrHashBank4_BASE_IDX 1 #define regUMCCH3_1_AddrHashBank5 0x40c37 #define regUMCCH3_1_AddrHashBank5_BASE_IDX 1 #define regUMCCH3_1_EccErrCntSel 0x40f28 #define regUMCCH3_1_EccErrCntSel_BASE_IDX 1 #define regUMCCH3_1_EccErrCnt 0x40f29 #define regUMCCH3_1_EccErrCnt_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtlClk 0x40f40 #define regUMCCH3_1_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtrClk_Lo 0x40f41 #define regUMCCH3_1_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtrClk_Hi 0x40f42 #define regUMCCH3_1_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtl1 0x40f44 #define regUMCCH3_1_PerfMonCtl1_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr1_Lo 0x40f45 #define regUMCCH3_1_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr1_Hi 0x40f46 #define regUMCCH3_1_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtl2 0x40f47 #define regUMCCH3_1_PerfMonCtl2_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr2_Lo 0x40f48 #define regUMCCH3_1_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr2_Hi 0x40f49 #define regUMCCH3_1_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtl3 0x40f4a #define regUMCCH3_1_PerfMonCtl3_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr3_Lo 0x40f4b #define regUMCCH3_1_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr3_Hi 0x40f4c #define regUMCCH3_1_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtl4 0x40f4d #define regUMCCH3_1_PerfMonCtl4_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr4_Lo 0x40f4e #define regUMCCH3_1_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr4_Hi 0x40f4f #define regUMCCH3_1_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtl5 0x40f50 #define regUMCCH3_1_PerfMonCtl5_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr5_Lo 0x40f51 #define regUMCCH3_1_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr5_Hi 0x40f52 #define regUMCCH3_1_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtl6 0x40f53 #define regUMCCH3_1_PerfMonCtl6_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr6_Lo 0x40f54 #define regUMCCH3_1_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr6_Hi 0x40f55 #define regUMCCH3_1_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtl7 0x40f56 #define regUMCCH3_1_PerfMonCtl7_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr7_Lo 0x40f57 #define regUMCCH3_1_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr7_Hi 0x40f58 #define regUMCCH3_1_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtl8 0x40f59 #define regUMCCH3_1_PerfMonCtl8_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr8_Lo 0x40f5a #define regUMCCH3_1_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH3_1_PerfMonCtr8_Hi 0x40f5b #define regUMCCH3_1_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc1_umcch4_umcchdec // base address: 0x350000 #define regUMCCH4_1_BaseAddrCS0 0x80000 #define regUMCCH4_1_BaseAddrCS0_BASE_IDX 1 #define regUMCCH4_1_AddrMaskCS01 0x80008 #define regUMCCH4_1_AddrMaskCS01_BASE_IDX 1 #define regUMCCH4_1_AddrSelCS01 0x80010 #define regUMCCH4_1_AddrSelCS01_BASE_IDX 1 #define regUMCCH4_1_AddrHashBank0 0x80032 #define regUMCCH4_1_AddrHashBank0_BASE_IDX 1 #define regUMCCH4_1_AddrHashBank1 0x80033 #define regUMCCH4_1_AddrHashBank1_BASE_IDX 1 #define regUMCCH4_1_AddrHashBank2 0x80034 #define regUMCCH4_1_AddrHashBank2_BASE_IDX 1 #define regUMCCH4_1_AddrHashBank3 0x80035 #define regUMCCH4_1_AddrHashBank3_BASE_IDX 1 #define regUMCCH4_1_AddrHashBank4 0x80036 #define regUMCCH4_1_AddrHashBank4_BASE_IDX 1 #define regUMCCH4_1_AddrHashBank5 0x80037 #define regUMCCH4_1_AddrHashBank5_BASE_IDX 1 #define regUMCCH4_1_EccErrCntSel 0x80328 #define regUMCCH4_1_EccErrCntSel_BASE_IDX 1 #define regUMCCH4_1_EccErrCnt 0x80329 #define regUMCCH4_1_EccErrCnt_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtlClk 0x80340 #define regUMCCH4_1_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtrClk_Lo 0x80341 #define regUMCCH4_1_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtrClk_Hi 0x80342 #define regUMCCH4_1_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtl1 0x80344 #define regUMCCH4_1_PerfMonCtl1_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr1_Lo 0x80345 #define regUMCCH4_1_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr1_Hi 0x80346 #define regUMCCH4_1_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtl2 0x80347 #define regUMCCH4_1_PerfMonCtl2_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr2_Lo 0x80348 #define regUMCCH4_1_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr2_Hi 0x80349 #define regUMCCH4_1_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtl3 0x8034a #define regUMCCH4_1_PerfMonCtl3_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr3_Lo 0x8034b #define regUMCCH4_1_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr3_Hi 0x8034c #define regUMCCH4_1_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtl4 0x8034d #define regUMCCH4_1_PerfMonCtl4_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr4_Lo 0x8034e #define regUMCCH4_1_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr4_Hi 0x8034f #define regUMCCH4_1_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtl5 0x80350 #define regUMCCH4_1_PerfMonCtl5_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr5_Lo 0x80351 #define regUMCCH4_1_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr5_Hi 0x80352 #define regUMCCH4_1_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtl6 0x80353 #define regUMCCH4_1_PerfMonCtl6_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr6_Lo 0x80354 #define regUMCCH4_1_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr6_Hi 0x80355 #define regUMCCH4_1_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtl7 0x80356 #define regUMCCH4_1_PerfMonCtl7_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr7_Lo 0x80357 #define regUMCCH4_1_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr7_Hi 0x80358 #define regUMCCH4_1_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtl8 0x80359 #define regUMCCH4_1_PerfMonCtl8_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr8_Lo 0x8035a #define regUMCCH4_1_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH4_1_PerfMonCtr8_Hi 0x8035b #define regUMCCH4_1_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc1_umcch5_umcchdec // base address: 0x351000 #define regUMCCH5_1_BaseAddrCS0 0x80400 #define regUMCCH5_1_BaseAddrCS0_BASE_IDX 1 #define regUMCCH5_1_AddrMaskCS01 0x80408 #define regUMCCH5_1_AddrMaskCS01_BASE_IDX 1 #define regUMCCH5_1_AddrSelCS01 0x80410 #define regUMCCH5_1_AddrSelCS01_BASE_IDX 1 #define regUMCCH5_1_AddrHashBank0 0x80432 #define regUMCCH5_1_AddrHashBank0_BASE_IDX 1 #define regUMCCH5_1_AddrHashBank1 0x80433 #define regUMCCH5_1_AddrHashBank1_BASE_IDX 1 #define regUMCCH5_1_AddrHashBank2 0x80434 #define regUMCCH5_1_AddrHashBank2_BASE_IDX 1 #define regUMCCH5_1_AddrHashBank3 0x80435 #define regUMCCH5_1_AddrHashBank3_BASE_IDX 1 #define regUMCCH5_1_AddrHashBank4 0x80436 #define regUMCCH5_1_AddrHashBank4_BASE_IDX 1 #define regUMCCH5_1_AddrHashBank5 0x80437 #define regUMCCH5_1_AddrHashBank5_BASE_IDX 1 #define regUMCCH5_1_EccErrCntSel 0x80728 #define regUMCCH5_1_EccErrCntSel_BASE_IDX 1 #define regUMCCH5_1_EccErrCnt 0x80729 #define regUMCCH5_1_EccErrCnt_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtlClk 0x80740 #define regUMCCH5_1_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtrClk_Lo 0x80741 #define regUMCCH5_1_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtrClk_Hi 0x80742 #define regUMCCH5_1_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtl1 0x80744 #define regUMCCH5_1_PerfMonCtl1_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr1_Lo 0x80745 #define regUMCCH5_1_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr1_Hi 0x80746 #define regUMCCH5_1_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtl2 0x80747 #define regUMCCH5_1_PerfMonCtl2_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr2_Lo 0x80748 #define regUMCCH5_1_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr2_Hi 0x80749 #define regUMCCH5_1_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtl3 0x8074a #define regUMCCH5_1_PerfMonCtl3_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr3_Lo 0x8074b #define regUMCCH5_1_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr3_Hi 0x8074c #define regUMCCH5_1_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtl4 0x8074d #define regUMCCH5_1_PerfMonCtl4_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr4_Lo 0x8074e #define regUMCCH5_1_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr4_Hi 0x8074f #define regUMCCH5_1_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtl5 0x80750 #define regUMCCH5_1_PerfMonCtl5_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr5_Lo 0x80751 #define regUMCCH5_1_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr5_Hi 0x80752 #define regUMCCH5_1_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtl6 0x80753 #define regUMCCH5_1_PerfMonCtl6_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr6_Lo 0x80754 #define regUMCCH5_1_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr6_Hi 0x80755 #define regUMCCH5_1_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtl7 0x80756 #define regUMCCH5_1_PerfMonCtl7_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr7_Lo 0x80757 #define regUMCCH5_1_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr7_Hi 0x80758 #define regUMCCH5_1_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtl8 0x80759 #define regUMCCH5_1_PerfMonCtl8_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr8_Lo 0x8075a #define regUMCCH5_1_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH5_1_PerfMonCtr8_Hi 0x8075b #define regUMCCH5_1_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc1_umcch6_umcchdec // base address: 0x352000 #define regUMCCH6_1_BaseAddrCS0 0x80800 #define regUMCCH6_1_BaseAddrCS0_BASE_IDX 1 #define regUMCCH6_1_AddrMaskCS01 0x80808 #define regUMCCH6_1_AddrMaskCS01_BASE_IDX 1 #define regUMCCH6_1_AddrSelCS01 0x80810 #define regUMCCH6_1_AddrSelCS01_BASE_IDX 1 #define regUMCCH6_1_AddrHashBank0 0x80832 #define regUMCCH6_1_AddrHashBank0_BASE_IDX 1 #define regUMCCH6_1_AddrHashBank1 0x80833 #define regUMCCH6_1_AddrHashBank1_BASE_IDX 1 #define regUMCCH6_1_AddrHashBank2 0x80834 #define regUMCCH6_1_AddrHashBank2_BASE_IDX 1 #define regUMCCH6_1_AddrHashBank3 0x80835 #define regUMCCH6_1_AddrHashBank3_BASE_IDX 1 #define regUMCCH6_1_AddrHashBank4 0x80836 #define regUMCCH6_1_AddrHashBank4_BASE_IDX 1 #define regUMCCH6_1_AddrHashBank5 0x80837 #define regUMCCH6_1_AddrHashBank5_BASE_IDX 1 #define regUMCCH6_1_EccErrCntSel 0x80b28 #define regUMCCH6_1_EccErrCntSel_BASE_IDX 1 #define regUMCCH6_1_EccErrCnt 0x80b29 #define regUMCCH6_1_EccErrCnt_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtlClk 0x80b40 #define regUMCCH6_1_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtrClk_Lo 0x80b41 #define regUMCCH6_1_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtrClk_Hi 0x80b42 #define regUMCCH6_1_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtl1 0x80b44 #define regUMCCH6_1_PerfMonCtl1_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr1_Lo 0x80b45 #define regUMCCH6_1_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr1_Hi 0x80b46 #define regUMCCH6_1_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtl2 0x80b47 #define regUMCCH6_1_PerfMonCtl2_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr2_Lo 0x80b48 #define regUMCCH6_1_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr2_Hi 0x80b49 #define regUMCCH6_1_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtl3 0x80b4a #define regUMCCH6_1_PerfMonCtl3_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr3_Lo 0x80b4b #define regUMCCH6_1_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr3_Hi 0x80b4c #define regUMCCH6_1_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtl4 0x80b4d #define regUMCCH6_1_PerfMonCtl4_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr4_Lo 0x80b4e #define regUMCCH6_1_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr4_Hi 0x80b4f #define regUMCCH6_1_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtl5 0x80b50 #define regUMCCH6_1_PerfMonCtl5_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr5_Lo 0x80b51 #define regUMCCH6_1_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr5_Hi 0x80b52 #define regUMCCH6_1_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtl6 0x80b53 #define regUMCCH6_1_PerfMonCtl6_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr6_Lo 0x80b54 #define regUMCCH6_1_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr6_Hi 0x80b55 #define regUMCCH6_1_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtl7 0x80b56 #define regUMCCH6_1_PerfMonCtl7_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr7_Lo 0x80b57 #define regUMCCH6_1_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr7_Hi 0x80b58 #define regUMCCH6_1_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtl8 0x80b59 #define regUMCCH6_1_PerfMonCtl8_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr8_Lo 0x80b5a #define regUMCCH6_1_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH6_1_PerfMonCtr8_Hi 0x80b5b #define regUMCCH6_1_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc1_umcch7_umcchdec // base address: 0x353000 #define regUMCCH7_1_BaseAddrCS0 0x80c00 #define regUMCCH7_1_BaseAddrCS0_BASE_IDX 1 #define regUMCCH7_1_AddrMaskCS01 0x80c08 #define regUMCCH7_1_AddrMaskCS01_BASE_IDX 1 #define regUMCCH7_1_AddrSelCS01 0x80c10 #define regUMCCH7_1_AddrSelCS01_BASE_IDX 1 #define regUMCCH7_1_AddrHashBank0 0x80c32 #define regUMCCH7_1_AddrHashBank0_BASE_IDX 1 #define regUMCCH7_1_AddrHashBank1 0x80c33 #define regUMCCH7_1_AddrHashBank1_BASE_IDX 1 #define regUMCCH7_1_AddrHashBank2 0x80c34 #define regUMCCH7_1_AddrHashBank2_BASE_IDX 1 #define regUMCCH7_1_AddrHashBank3 0x80c35 #define regUMCCH7_1_AddrHashBank3_BASE_IDX 1 #define regUMCCH7_1_AddrHashBank4 0x80c36 #define regUMCCH7_1_AddrHashBank4_BASE_IDX 1 #define regUMCCH7_1_AddrHashBank5 0x80c37 #define regUMCCH7_1_AddrHashBank5_BASE_IDX 1 #define regUMCCH7_1_EccErrCntSel 0x80f28 #define regUMCCH7_1_EccErrCntSel_BASE_IDX 1 #define regUMCCH7_1_EccErrCnt 0x80f29 #define regUMCCH7_1_EccErrCnt_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtlClk 0x80f40 #define regUMCCH7_1_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtrClk_Lo 0x80f41 #define regUMCCH7_1_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtrClk_Hi 0x80f42 #define regUMCCH7_1_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtl1 0x80f44 #define regUMCCH7_1_PerfMonCtl1_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr1_Lo 0x80f45 #define regUMCCH7_1_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr1_Hi 0x80f46 #define regUMCCH7_1_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtl2 0x80f47 #define regUMCCH7_1_PerfMonCtl2_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr2_Lo 0x80f48 #define regUMCCH7_1_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr2_Hi 0x80f49 #define regUMCCH7_1_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtl3 0x80f4a #define regUMCCH7_1_PerfMonCtl3_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr3_Lo 0x80f4b #define regUMCCH7_1_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr3_Hi 0x80f4c #define regUMCCH7_1_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtl4 0x80f4d #define regUMCCH7_1_PerfMonCtl4_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr4_Lo 0x80f4e #define regUMCCH7_1_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr4_Hi 0x80f4f #define regUMCCH7_1_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtl5 0x80f50 #define regUMCCH7_1_PerfMonCtl5_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr5_Lo 0x80f51 #define regUMCCH7_1_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr5_Hi 0x80f52 #define regUMCCH7_1_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtl6 0x80f53 #define regUMCCH7_1_PerfMonCtl6_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr6_Lo 0x80f54 #define regUMCCH7_1_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr6_Hi 0x80f55 #define regUMCCH7_1_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtl7 0x80f56 #define regUMCCH7_1_PerfMonCtl7_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr7_Lo 0x80f57 #define regUMCCH7_1_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr7_Hi 0x80f58 #define regUMCCH7_1_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtl8 0x80f59 #define regUMCCH7_1_PerfMonCtl8_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr8_Lo 0x80f5a #define regUMCCH7_1_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH7_1_PerfMonCtr8_Hi 0x80f5b #define regUMCCH7_1_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc2_umcch0_umcchdec // base address: 0x450000 #define regUMCCH0_2_BaseAddrCS0 0xc0000 #define regUMCCH0_2_BaseAddrCS0_BASE_IDX 1 #define regUMCCH0_2_AddrMaskCS01 0xc0008 #define regUMCCH0_2_AddrMaskCS01_BASE_IDX 1 #define regUMCCH0_2_AddrSelCS01 0xc0010 #define regUMCCH0_2_AddrSelCS01_BASE_IDX 1 #define regUMCCH0_2_AddrHashBank0 0xc0032 #define regUMCCH0_2_AddrHashBank0_BASE_IDX 1 #define regUMCCH0_2_AddrHashBank1 0xc0033 #define regUMCCH0_2_AddrHashBank1_BASE_IDX 1 #define regUMCCH0_2_AddrHashBank2 0xc0034 #define regUMCCH0_2_AddrHashBank2_BASE_IDX 1 #define regUMCCH0_2_AddrHashBank3 0xc0035 #define regUMCCH0_2_AddrHashBank3_BASE_IDX 1 #define regUMCCH0_2_AddrHashBank4 0xc0036 #define regUMCCH0_2_AddrHashBank4_BASE_IDX 1 #define regUMCCH0_2_AddrHashBank5 0xc0037 #define regUMCCH0_2_AddrHashBank5_BASE_IDX 1 #define regUMCCH0_2_EccErrCntSel 0xc0328 #define regUMCCH0_2_EccErrCntSel_BASE_IDX 1 #define regUMCCH0_2_EccErrCnt 0xc0329 #define regUMCCH0_2_EccErrCnt_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtlClk 0xc0340 #define regUMCCH0_2_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtrClk_Lo 0xc0341 #define regUMCCH0_2_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtrClk_Hi 0xc0342 #define regUMCCH0_2_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtl1 0xc0344 #define regUMCCH0_2_PerfMonCtl1_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr1_Lo 0xc0345 #define regUMCCH0_2_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr1_Hi 0xc0346 #define regUMCCH0_2_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtl2 0xc0347 #define regUMCCH0_2_PerfMonCtl2_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr2_Lo 0xc0348 #define regUMCCH0_2_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr2_Hi 0xc0349 #define regUMCCH0_2_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtl3 0xc034a #define regUMCCH0_2_PerfMonCtl3_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr3_Lo 0xc034b #define regUMCCH0_2_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr3_Hi 0xc034c #define regUMCCH0_2_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtl4 0xc034d #define regUMCCH0_2_PerfMonCtl4_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr4_Lo 0xc034e #define regUMCCH0_2_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr4_Hi 0xc034f #define regUMCCH0_2_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtl5 0xc0350 #define regUMCCH0_2_PerfMonCtl5_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr5_Lo 0xc0351 #define regUMCCH0_2_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr5_Hi 0xc0352 #define regUMCCH0_2_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtl6 0xc0353 #define regUMCCH0_2_PerfMonCtl6_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr6_Lo 0xc0354 #define regUMCCH0_2_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr6_Hi 0xc0355 #define regUMCCH0_2_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtl7 0xc0356 #define regUMCCH0_2_PerfMonCtl7_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr7_Lo 0xc0357 #define regUMCCH0_2_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr7_Hi 0xc0358 #define regUMCCH0_2_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtl8 0xc0359 #define regUMCCH0_2_PerfMonCtl8_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr8_Lo 0xc035a #define regUMCCH0_2_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH0_2_PerfMonCtr8_Hi 0xc035b #define regUMCCH0_2_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc2_umcch1_umcchdec // base address: 0x451000 #define regUMCCH1_2_BaseAddrCS0 0xc0400 #define regUMCCH1_2_BaseAddrCS0_BASE_IDX 1 #define regUMCCH1_2_AddrMaskCS01 0xc0408 #define regUMCCH1_2_AddrMaskCS01_BASE_IDX 1 #define regUMCCH1_2_AddrSelCS01 0xc0410 #define regUMCCH1_2_AddrSelCS01_BASE_IDX 1 #define regUMCCH1_2_AddrHashBank0 0xc0432 #define regUMCCH1_2_AddrHashBank0_BASE_IDX 1 #define regUMCCH1_2_AddrHashBank1 0xc0433 #define regUMCCH1_2_AddrHashBank1_BASE_IDX 1 #define regUMCCH1_2_AddrHashBank2 0xc0434 #define regUMCCH1_2_AddrHashBank2_BASE_IDX 1 #define regUMCCH1_2_AddrHashBank3 0xc0435 #define regUMCCH1_2_AddrHashBank3_BASE_IDX 1 #define regUMCCH1_2_AddrHashBank4 0xc0436 #define regUMCCH1_2_AddrHashBank4_BASE_IDX 1 #define regUMCCH1_2_AddrHashBank5 0xc0437 #define regUMCCH1_2_AddrHashBank5_BASE_IDX 1 #define regUMCCH1_2_EccErrCntSel 0xc0728 #define regUMCCH1_2_EccErrCntSel_BASE_IDX 1 #define regUMCCH1_2_EccErrCnt 0xc0729 #define regUMCCH1_2_EccErrCnt_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtlClk 0xc0740 #define regUMCCH1_2_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtrClk_Lo 0xc0741 #define regUMCCH1_2_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtrClk_Hi 0xc0742 #define regUMCCH1_2_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtl1 0xc0744 #define regUMCCH1_2_PerfMonCtl1_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr1_Lo 0xc0745 #define regUMCCH1_2_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr1_Hi 0xc0746 #define regUMCCH1_2_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtl2 0xc0747 #define regUMCCH1_2_PerfMonCtl2_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr2_Lo 0xc0748 #define regUMCCH1_2_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr2_Hi 0xc0749 #define regUMCCH1_2_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtl3 0xc074a #define regUMCCH1_2_PerfMonCtl3_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr3_Lo 0xc074b #define regUMCCH1_2_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr3_Hi 0xc074c #define regUMCCH1_2_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtl4 0xc074d #define regUMCCH1_2_PerfMonCtl4_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr4_Lo 0xc074e #define regUMCCH1_2_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr4_Hi 0xc074f #define regUMCCH1_2_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtl5 0xc0750 #define regUMCCH1_2_PerfMonCtl5_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr5_Lo 0xc0751 #define regUMCCH1_2_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr5_Hi 0xc0752 #define regUMCCH1_2_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtl6 0xc0753 #define regUMCCH1_2_PerfMonCtl6_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr6_Lo 0xc0754 #define regUMCCH1_2_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr6_Hi 0xc0755 #define regUMCCH1_2_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtl7 0xc0756 #define regUMCCH1_2_PerfMonCtl7_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr7_Lo 0xc0757 #define regUMCCH1_2_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr7_Hi 0xc0758 #define regUMCCH1_2_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtl8 0xc0759 #define regUMCCH1_2_PerfMonCtl8_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr8_Lo 0xc075a #define regUMCCH1_2_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH1_2_PerfMonCtr8_Hi 0xc075b #define regUMCCH1_2_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc2_umcch2_umcchdec // base address: 0x452000 #define regUMCCH2_2_BaseAddrCS0 0xc0800 #define regUMCCH2_2_BaseAddrCS0_BASE_IDX 1 #define regUMCCH2_2_AddrMaskCS01 0xc0808 #define regUMCCH2_2_AddrMaskCS01_BASE_IDX 1 #define regUMCCH2_2_AddrSelCS01 0xc0810 #define regUMCCH2_2_AddrSelCS01_BASE_IDX 1 #define regUMCCH2_2_AddrHashBank0 0xc0832 #define regUMCCH2_2_AddrHashBank0_BASE_IDX 1 #define regUMCCH2_2_AddrHashBank1 0xc0833 #define regUMCCH2_2_AddrHashBank1_BASE_IDX 1 #define regUMCCH2_2_AddrHashBank2 0xc0834 #define regUMCCH2_2_AddrHashBank2_BASE_IDX 1 #define regUMCCH2_2_AddrHashBank3 0xc0835 #define regUMCCH2_2_AddrHashBank3_BASE_IDX 1 #define regUMCCH2_2_AddrHashBank4 0xc0836 #define regUMCCH2_2_AddrHashBank4_BASE_IDX 1 #define regUMCCH2_2_AddrHashBank5 0xc0837 #define regUMCCH2_2_AddrHashBank5_BASE_IDX 1 #define regUMCCH2_2_EccErrCntSel 0xc0b28 #define regUMCCH2_2_EccErrCntSel_BASE_IDX 1 #define regUMCCH2_2_EccErrCnt 0xc0b29 #define regUMCCH2_2_EccErrCnt_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtlClk 0xc0b40 #define regUMCCH2_2_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtrClk_Lo 0xc0b41 #define regUMCCH2_2_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtrClk_Hi 0xc0b42 #define regUMCCH2_2_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtl1 0xc0b44 #define regUMCCH2_2_PerfMonCtl1_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr1_Lo 0xc0b45 #define regUMCCH2_2_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr1_Hi 0xc0b46 #define regUMCCH2_2_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtl2 0xc0b47 #define regUMCCH2_2_PerfMonCtl2_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr2_Lo 0xc0b48 #define regUMCCH2_2_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr2_Hi 0xc0b49 #define regUMCCH2_2_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtl3 0xc0b4a #define regUMCCH2_2_PerfMonCtl3_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr3_Lo 0xc0b4b #define regUMCCH2_2_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr3_Hi 0xc0b4c #define regUMCCH2_2_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtl4 0xc0b4d #define regUMCCH2_2_PerfMonCtl4_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr4_Lo 0xc0b4e #define regUMCCH2_2_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr4_Hi 0xc0b4f #define regUMCCH2_2_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtl5 0xc0b50 #define regUMCCH2_2_PerfMonCtl5_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr5_Lo 0xc0b51 #define regUMCCH2_2_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr5_Hi 0xc0b52 #define regUMCCH2_2_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtl6 0xc0b53 #define regUMCCH2_2_PerfMonCtl6_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr6_Lo 0xc0b54 #define regUMCCH2_2_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr6_Hi 0xc0b55 #define regUMCCH2_2_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtl7 0xc0b56 #define regUMCCH2_2_PerfMonCtl7_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr7_Lo 0xc0b57 #define regUMCCH2_2_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr7_Hi 0xc0b58 #define regUMCCH2_2_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtl8 0xc0b59 #define regUMCCH2_2_PerfMonCtl8_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr8_Lo 0xc0b5a #define regUMCCH2_2_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH2_2_PerfMonCtr8_Hi 0xc0b5b #define regUMCCH2_2_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc2_umcch3_umcchdec // base address: 0x453000 #define regUMCCH3_2_BaseAddrCS0 0xc0c00 #define regUMCCH3_2_BaseAddrCS0_BASE_IDX 1 #define regUMCCH3_2_AddrMaskCS01 0xc0c08 #define regUMCCH3_2_AddrMaskCS01_BASE_IDX 1 #define regUMCCH3_2_AddrSelCS01 0xc0c10 #define regUMCCH3_2_AddrSelCS01_BASE_IDX 1 #define regUMCCH3_2_AddrHashBank0 0xc0c32 #define regUMCCH3_2_AddrHashBank0_BASE_IDX 1 #define regUMCCH3_2_AddrHashBank1 0xc0c33 #define regUMCCH3_2_AddrHashBank1_BASE_IDX 1 #define regUMCCH3_2_AddrHashBank2 0xc0c34 #define regUMCCH3_2_AddrHashBank2_BASE_IDX 1 #define regUMCCH3_2_AddrHashBank3 0xc0c35 #define regUMCCH3_2_AddrHashBank3_BASE_IDX 1 #define regUMCCH3_2_AddrHashBank4 0xc0c36 #define regUMCCH3_2_AddrHashBank4_BASE_IDX 1 #define regUMCCH3_2_AddrHashBank5 0xc0c37 #define regUMCCH3_2_AddrHashBank5_BASE_IDX 1 #define regUMCCH3_2_EccErrCntSel 0xc0f28 #define regUMCCH3_2_EccErrCntSel_BASE_IDX 1 #define regUMCCH3_2_EccErrCnt 0xc0f29 #define regUMCCH3_2_EccErrCnt_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtlClk 0xc0f40 #define regUMCCH3_2_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtrClk_Lo 0xc0f41 #define regUMCCH3_2_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtrClk_Hi 0xc0f42 #define regUMCCH3_2_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtl1 0xc0f44 #define regUMCCH3_2_PerfMonCtl1_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr1_Lo 0xc0f45 #define regUMCCH3_2_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr1_Hi 0xc0f46 #define regUMCCH3_2_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtl2 0xc0f47 #define regUMCCH3_2_PerfMonCtl2_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr2_Lo 0xc0f48 #define regUMCCH3_2_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr2_Hi 0xc0f49 #define regUMCCH3_2_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtl3 0xc0f4a #define regUMCCH3_2_PerfMonCtl3_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr3_Lo 0xc0f4b #define regUMCCH3_2_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr3_Hi 0xc0f4c #define regUMCCH3_2_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtl4 0xc0f4d #define regUMCCH3_2_PerfMonCtl4_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr4_Lo 0xc0f4e #define regUMCCH3_2_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr4_Hi 0xc0f4f #define regUMCCH3_2_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtl5 0xc0f50 #define regUMCCH3_2_PerfMonCtl5_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr5_Lo 0xc0f51 #define regUMCCH3_2_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr5_Hi 0xc0f52 #define regUMCCH3_2_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtl6 0xc0f53 #define regUMCCH3_2_PerfMonCtl6_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr6_Lo 0xc0f54 #define regUMCCH3_2_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr6_Hi 0xc0f55 #define regUMCCH3_2_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtl7 0xc0f56 #define regUMCCH3_2_PerfMonCtl7_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr7_Lo 0xc0f57 #define regUMCCH3_2_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr7_Hi 0xc0f58 #define regUMCCH3_2_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtl8 0xc0f59 #define regUMCCH3_2_PerfMonCtl8_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr8_Lo 0xc0f5a #define regUMCCH3_2_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH3_2_PerfMonCtr8_Hi 0xc0f5b #define regUMCCH3_2_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc2_umcch4_umcchdec // base address: 0x550000 #define regUMCCH4_2_BaseAddrCS0 0x100000 #define regUMCCH4_2_BaseAddrCS0_BASE_IDX 1 #define regUMCCH4_2_AddrMaskCS01 0x100008 #define regUMCCH4_2_AddrMaskCS01_BASE_IDX 1 #define regUMCCH4_2_AddrSelCS01 0x100010 #define regUMCCH4_2_AddrSelCS01_BASE_IDX 1 #define regUMCCH4_2_AddrHashBank0 0x100032 #define regUMCCH4_2_AddrHashBank0_BASE_IDX 1 #define regUMCCH4_2_AddrHashBank1 0x100033 #define regUMCCH4_2_AddrHashBank1_BASE_IDX 1 #define regUMCCH4_2_AddrHashBank2 0x100034 #define regUMCCH4_2_AddrHashBank2_BASE_IDX 1 #define regUMCCH4_2_AddrHashBank3 0x100035 #define regUMCCH4_2_AddrHashBank3_BASE_IDX 1 #define regUMCCH4_2_AddrHashBank4 0x100036 #define regUMCCH4_2_AddrHashBank4_BASE_IDX 1 #define regUMCCH4_2_AddrHashBank5 0x100037 #define regUMCCH4_2_AddrHashBank5_BASE_IDX 1 #define regUMCCH4_2_EccErrCntSel 0x100328 #define regUMCCH4_2_EccErrCntSel_BASE_IDX 1 #define regUMCCH4_2_EccErrCnt 0x100329 #define regUMCCH4_2_EccErrCnt_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtlClk 0x100340 #define regUMCCH4_2_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtrClk_Lo 0x100341 #define regUMCCH4_2_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtrClk_Hi 0x100342 #define regUMCCH4_2_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtl1 0x100344 #define regUMCCH4_2_PerfMonCtl1_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr1_Lo 0x100345 #define regUMCCH4_2_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr1_Hi 0x100346 #define regUMCCH4_2_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtl2 0x100347 #define regUMCCH4_2_PerfMonCtl2_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr2_Lo 0x100348 #define regUMCCH4_2_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr2_Hi 0x100349 #define regUMCCH4_2_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtl3 0x10034a #define regUMCCH4_2_PerfMonCtl3_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr3_Lo 0x10034b #define regUMCCH4_2_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr3_Hi 0x10034c #define regUMCCH4_2_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtl4 0x10034d #define regUMCCH4_2_PerfMonCtl4_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr4_Lo 0x10034e #define regUMCCH4_2_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr4_Hi 0x10034f #define regUMCCH4_2_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtl5 0x100350 #define regUMCCH4_2_PerfMonCtl5_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr5_Lo 0x100351 #define regUMCCH4_2_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr5_Hi 0x100352 #define regUMCCH4_2_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtl6 0x100353 #define regUMCCH4_2_PerfMonCtl6_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr6_Lo 0x100354 #define regUMCCH4_2_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr6_Hi 0x100355 #define regUMCCH4_2_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtl7 0x100356 #define regUMCCH4_2_PerfMonCtl7_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr7_Lo 0x100357 #define regUMCCH4_2_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr7_Hi 0x100358 #define regUMCCH4_2_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtl8 0x100359 #define regUMCCH4_2_PerfMonCtl8_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr8_Lo 0x10035a #define regUMCCH4_2_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH4_2_PerfMonCtr8_Hi 0x10035b #define regUMCCH4_2_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc2_umcch5_umcchdec // base address: 0x551000 #define regUMCCH5_2_BaseAddrCS0 0x100400 #define regUMCCH5_2_BaseAddrCS0_BASE_IDX 1 #define regUMCCH5_2_AddrMaskCS01 0x100408 #define regUMCCH5_2_AddrMaskCS01_BASE_IDX 1 #define regUMCCH5_2_AddrSelCS01 0x100410 #define regUMCCH5_2_AddrSelCS01_BASE_IDX 1 #define regUMCCH5_2_AddrHashBank0 0x100432 #define regUMCCH5_2_AddrHashBank0_BASE_IDX 1 #define regUMCCH5_2_AddrHashBank1 0x100433 #define regUMCCH5_2_AddrHashBank1_BASE_IDX 1 #define regUMCCH5_2_AddrHashBank2 0x100434 #define regUMCCH5_2_AddrHashBank2_BASE_IDX 1 #define regUMCCH5_2_AddrHashBank3 0x100435 #define regUMCCH5_2_AddrHashBank3_BASE_IDX 1 #define regUMCCH5_2_AddrHashBank4 0x100436 #define regUMCCH5_2_AddrHashBank4_BASE_IDX 1 #define regUMCCH5_2_AddrHashBank5 0x100437 #define regUMCCH5_2_AddrHashBank5_BASE_IDX 1 #define regUMCCH5_2_EccErrCntSel 0x100728 #define regUMCCH5_2_EccErrCntSel_BASE_IDX 1 #define regUMCCH5_2_EccErrCnt 0x100729 #define regUMCCH5_2_EccErrCnt_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtlClk 0x100740 #define regUMCCH5_2_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtrClk_Lo 0x100741 #define regUMCCH5_2_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtrClk_Hi 0x100742 #define regUMCCH5_2_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtl1 0x100744 #define regUMCCH5_2_PerfMonCtl1_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr1_Lo 0x100745 #define regUMCCH5_2_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr1_Hi 0x100746 #define regUMCCH5_2_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtl2 0x100747 #define regUMCCH5_2_PerfMonCtl2_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr2_Lo 0x100748 #define regUMCCH5_2_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr2_Hi 0x100749 #define regUMCCH5_2_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtl3 0x10074a #define regUMCCH5_2_PerfMonCtl3_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr3_Lo 0x10074b #define regUMCCH5_2_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr3_Hi 0x10074c #define regUMCCH5_2_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtl4 0x10074d #define regUMCCH5_2_PerfMonCtl4_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr4_Lo 0x10074e #define regUMCCH5_2_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr4_Hi 0x10074f #define regUMCCH5_2_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtl5 0x100750 #define regUMCCH5_2_PerfMonCtl5_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr5_Lo 0x100751 #define regUMCCH5_2_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr5_Hi 0x100752 #define regUMCCH5_2_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtl6 0x100753 #define regUMCCH5_2_PerfMonCtl6_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr6_Lo 0x100754 #define regUMCCH5_2_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr6_Hi 0x100755 #define regUMCCH5_2_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtl7 0x100756 #define regUMCCH5_2_PerfMonCtl7_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr7_Lo 0x100757 #define regUMCCH5_2_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr7_Hi 0x100758 #define regUMCCH5_2_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtl8 0x100759 #define regUMCCH5_2_PerfMonCtl8_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr8_Lo 0x10075a #define regUMCCH5_2_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH5_2_PerfMonCtr8_Hi 0x10075b #define regUMCCH5_2_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc2_umcch6_umcchdec // base address: 0x552000 #define regUMCCH6_2_BaseAddrCS0 0x100800 #define regUMCCH6_2_BaseAddrCS0_BASE_IDX 1 #define regUMCCH6_2_AddrMaskCS01 0x100808 #define regUMCCH6_2_AddrMaskCS01_BASE_IDX 1 #define regUMCCH6_2_AddrSelCS01 0x100810 #define regUMCCH6_2_AddrSelCS01_BASE_IDX 1 #define regUMCCH6_2_AddrHashBank0 0x100832 #define regUMCCH6_2_AddrHashBank0_BASE_IDX 1 #define regUMCCH6_2_AddrHashBank1 0x100833 #define regUMCCH6_2_AddrHashBank1_BASE_IDX 1 #define regUMCCH6_2_AddrHashBank2 0x100834 #define regUMCCH6_2_AddrHashBank2_BASE_IDX 1 #define regUMCCH6_2_AddrHashBank3 0x100835 #define regUMCCH6_2_AddrHashBank3_BASE_IDX 1 #define regUMCCH6_2_AddrHashBank4 0x100836 #define regUMCCH6_2_AddrHashBank4_BASE_IDX 1 #define regUMCCH6_2_AddrHashBank5 0x100837 #define regUMCCH6_2_AddrHashBank5_BASE_IDX 1 #define regUMCCH6_2_EccErrCntSel 0x100b28 #define regUMCCH6_2_EccErrCntSel_BASE_IDX 1 #define regUMCCH6_2_EccErrCnt 0x100b29 #define regUMCCH6_2_EccErrCnt_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtlClk 0x100b40 #define regUMCCH6_2_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtrClk_Lo 0x100b41 #define regUMCCH6_2_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtrClk_Hi 0x100b42 #define regUMCCH6_2_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtl1 0x100b44 #define regUMCCH6_2_PerfMonCtl1_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr1_Lo 0x100b45 #define regUMCCH6_2_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr1_Hi 0x100b46 #define regUMCCH6_2_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtl2 0x100b47 #define regUMCCH6_2_PerfMonCtl2_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr2_Lo 0x100b48 #define regUMCCH6_2_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr2_Hi 0x100b49 #define regUMCCH6_2_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtl3 0x100b4a #define regUMCCH6_2_PerfMonCtl3_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr3_Lo 0x100b4b #define regUMCCH6_2_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr3_Hi 0x100b4c #define regUMCCH6_2_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtl4 0x100b4d #define regUMCCH6_2_PerfMonCtl4_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr4_Lo 0x100b4e #define regUMCCH6_2_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr4_Hi 0x100b4f #define regUMCCH6_2_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtl5 0x100b50 #define regUMCCH6_2_PerfMonCtl5_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr5_Lo 0x100b51 #define regUMCCH6_2_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr5_Hi 0x100b52 #define regUMCCH6_2_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtl6 0x100b53 #define regUMCCH6_2_PerfMonCtl6_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr6_Lo 0x100b54 #define regUMCCH6_2_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr6_Hi 0x100b55 #define regUMCCH6_2_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtl7 0x100b56 #define regUMCCH6_2_PerfMonCtl7_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr7_Lo 0x100b57 #define regUMCCH6_2_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr7_Hi 0x100b58 #define regUMCCH6_2_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtl8 0x100b59 #define regUMCCH6_2_PerfMonCtl8_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr8_Lo 0x100b5a #define regUMCCH6_2_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH6_2_PerfMonCtr8_Hi 0x100b5b #define regUMCCH6_2_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc2_umcch7_umcchdec // base address: 0x553000 #define regUMCCH7_2_BaseAddrCS0 0x100c00 #define regUMCCH7_2_BaseAddrCS0_BASE_IDX 1 #define regUMCCH7_2_AddrMaskCS01 0x100c08 #define regUMCCH7_2_AddrMaskCS01_BASE_IDX 1 #define regUMCCH7_2_AddrSelCS01 0x100c10 #define regUMCCH7_2_AddrSelCS01_BASE_IDX 1 #define regUMCCH7_2_AddrHashBank0 0x100c32 #define regUMCCH7_2_AddrHashBank0_BASE_IDX 1 #define regUMCCH7_2_AddrHashBank1 0x100c33 #define regUMCCH7_2_AddrHashBank1_BASE_IDX 1 #define regUMCCH7_2_AddrHashBank2 0x100c34 #define regUMCCH7_2_AddrHashBank2_BASE_IDX 1 #define regUMCCH7_2_AddrHashBank3 0x100c35 #define regUMCCH7_2_AddrHashBank3_BASE_IDX 1 #define regUMCCH7_2_AddrHashBank4 0x100c36 #define regUMCCH7_2_AddrHashBank4_BASE_IDX 1 #define regUMCCH7_2_AddrHashBank5 0x100c37 #define regUMCCH7_2_AddrHashBank5_BASE_IDX 1 #define regUMCCH7_2_EccErrCntSel 0x100f28 #define regUMCCH7_2_EccErrCntSel_BASE_IDX 1 #define regUMCCH7_2_EccErrCnt 0x100f29 #define regUMCCH7_2_EccErrCnt_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtlClk 0x100f40 #define regUMCCH7_2_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtrClk_Lo 0x100f41 #define regUMCCH7_2_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtrClk_Hi 0x100f42 #define regUMCCH7_2_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtl1 0x100f44 #define regUMCCH7_2_PerfMonCtl1_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr1_Lo 0x100f45 #define regUMCCH7_2_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr1_Hi 0x100f46 #define regUMCCH7_2_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtl2 0x100f47 #define regUMCCH7_2_PerfMonCtl2_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr2_Lo 0x100f48 #define regUMCCH7_2_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr2_Hi 0x100f49 #define regUMCCH7_2_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtl3 0x100f4a #define regUMCCH7_2_PerfMonCtl3_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr3_Lo 0x100f4b #define regUMCCH7_2_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr3_Hi 0x100f4c #define regUMCCH7_2_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtl4 0x100f4d #define regUMCCH7_2_PerfMonCtl4_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr4_Lo 0x100f4e #define regUMCCH7_2_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr4_Hi 0x100f4f #define regUMCCH7_2_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtl5 0x100f50 #define regUMCCH7_2_PerfMonCtl5_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr5_Lo 0x100f51 #define regUMCCH7_2_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr5_Hi 0x100f52 #define regUMCCH7_2_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtl6 0x100f53 #define regUMCCH7_2_PerfMonCtl6_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr6_Lo 0x100f54 #define regUMCCH7_2_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr6_Hi 0x100f55 #define regUMCCH7_2_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtl7 0x100f56 #define regUMCCH7_2_PerfMonCtl7_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr7_Lo 0x100f57 #define regUMCCH7_2_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr7_Hi 0x100f58 #define regUMCCH7_2_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtl8 0x100f59 #define regUMCCH7_2_PerfMonCtl8_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr8_Lo 0x100f5a #define regUMCCH7_2_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH7_2_PerfMonCtr8_Hi 0x100f5b #define regUMCCH7_2_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc3_umcch0_umcchdec // base address: 0x650000 #define regUMCCH0_3_BaseAddrCS0 0x140000 #define regUMCCH0_3_BaseAddrCS0_BASE_IDX 1 #define regUMCCH0_3_AddrMaskCS01 0x140008 #define regUMCCH0_3_AddrMaskCS01_BASE_IDX 1 #define regUMCCH0_3_AddrSelCS01 0x140010 #define regUMCCH0_3_AddrSelCS01_BASE_IDX 1 #define regUMCCH0_3_AddrHashBank0 0x140032 #define regUMCCH0_3_AddrHashBank0_BASE_IDX 1 #define regUMCCH0_3_AddrHashBank1 0x140033 #define regUMCCH0_3_AddrHashBank1_BASE_IDX 1 #define regUMCCH0_3_AddrHashBank2 0x140034 #define regUMCCH0_3_AddrHashBank2_BASE_IDX 1 #define regUMCCH0_3_AddrHashBank3 0x140035 #define regUMCCH0_3_AddrHashBank3_BASE_IDX 1 #define regUMCCH0_3_AddrHashBank4 0x140036 #define regUMCCH0_3_AddrHashBank4_BASE_IDX 1 #define regUMCCH0_3_AddrHashBank5 0x140037 #define regUMCCH0_3_AddrHashBank5_BASE_IDX 1 #define regUMCCH0_3_EccErrCntSel 0x140328 #define regUMCCH0_3_EccErrCntSel_BASE_IDX 1 #define regUMCCH0_3_EccErrCnt 0x140329 #define regUMCCH0_3_EccErrCnt_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtlClk 0x140340 #define regUMCCH0_3_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtrClk_Lo 0x140341 #define regUMCCH0_3_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtrClk_Hi 0x140342 #define regUMCCH0_3_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtl1 0x140344 #define regUMCCH0_3_PerfMonCtl1_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr1_Lo 0x140345 #define regUMCCH0_3_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr1_Hi 0x140346 #define regUMCCH0_3_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtl2 0x140347 #define regUMCCH0_3_PerfMonCtl2_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr2_Lo 0x140348 #define regUMCCH0_3_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr2_Hi 0x140349 #define regUMCCH0_3_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtl3 0x14034a #define regUMCCH0_3_PerfMonCtl3_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr3_Lo 0x14034b #define regUMCCH0_3_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr3_Hi 0x14034c #define regUMCCH0_3_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtl4 0x14034d #define regUMCCH0_3_PerfMonCtl4_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr4_Lo 0x14034e #define regUMCCH0_3_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr4_Hi 0x14034f #define regUMCCH0_3_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtl5 0x140350 #define regUMCCH0_3_PerfMonCtl5_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr5_Lo 0x140351 #define regUMCCH0_3_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr5_Hi 0x140352 #define regUMCCH0_3_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtl6 0x140353 #define regUMCCH0_3_PerfMonCtl6_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr6_Lo 0x140354 #define regUMCCH0_3_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr6_Hi 0x140355 #define regUMCCH0_3_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtl7 0x140356 #define regUMCCH0_3_PerfMonCtl7_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr7_Lo 0x140357 #define regUMCCH0_3_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr7_Hi 0x140358 #define regUMCCH0_3_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtl8 0x140359 #define regUMCCH0_3_PerfMonCtl8_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr8_Lo 0x14035a #define regUMCCH0_3_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH0_3_PerfMonCtr8_Hi 0x14035b #define regUMCCH0_3_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc3_umcch1_umcchdec // base address: 0x651000 #define regUMCCH1_3_BaseAddrCS0 0x140400 #define regUMCCH1_3_BaseAddrCS0_BASE_IDX 1 #define regUMCCH1_3_AddrMaskCS01 0x140408 #define regUMCCH1_3_AddrMaskCS01_BASE_IDX 1 #define regUMCCH1_3_AddrSelCS01 0x140410 #define regUMCCH1_3_AddrSelCS01_BASE_IDX 1 #define regUMCCH1_3_AddrHashBank0 0x140432 #define regUMCCH1_3_AddrHashBank0_BASE_IDX 1 #define regUMCCH1_3_AddrHashBank1 0x140433 #define regUMCCH1_3_AddrHashBank1_BASE_IDX 1 #define regUMCCH1_3_AddrHashBank2 0x140434 #define regUMCCH1_3_AddrHashBank2_BASE_IDX 1 #define regUMCCH1_3_AddrHashBank3 0x140435 #define regUMCCH1_3_AddrHashBank3_BASE_IDX 1 #define regUMCCH1_3_AddrHashBank4 0x140436 #define regUMCCH1_3_AddrHashBank4_BASE_IDX 1 #define regUMCCH1_3_AddrHashBank5 0x140437 #define regUMCCH1_3_AddrHashBank5_BASE_IDX 1 #define regUMCCH1_3_EccErrCntSel 0x140728 #define regUMCCH1_3_EccErrCntSel_BASE_IDX 1 #define regUMCCH1_3_EccErrCnt 0x140729 #define regUMCCH1_3_EccErrCnt_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtlClk 0x140740 #define regUMCCH1_3_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtrClk_Lo 0x140741 #define regUMCCH1_3_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtrClk_Hi 0x140742 #define regUMCCH1_3_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtl1 0x140744 #define regUMCCH1_3_PerfMonCtl1_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr1_Lo 0x140745 #define regUMCCH1_3_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr1_Hi 0x140746 #define regUMCCH1_3_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtl2 0x140747 #define regUMCCH1_3_PerfMonCtl2_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr2_Lo 0x140748 #define regUMCCH1_3_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr2_Hi 0x140749 #define regUMCCH1_3_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtl3 0x14074a #define regUMCCH1_3_PerfMonCtl3_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr3_Lo 0x14074b #define regUMCCH1_3_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr3_Hi 0x14074c #define regUMCCH1_3_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtl4 0x14074d #define regUMCCH1_3_PerfMonCtl4_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr4_Lo 0x14074e #define regUMCCH1_3_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr4_Hi 0x14074f #define regUMCCH1_3_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtl5 0x140750 #define regUMCCH1_3_PerfMonCtl5_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr5_Lo 0x140751 #define regUMCCH1_3_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr5_Hi 0x140752 #define regUMCCH1_3_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtl6 0x140753 #define regUMCCH1_3_PerfMonCtl6_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr6_Lo 0x140754 #define regUMCCH1_3_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr6_Hi 0x140755 #define regUMCCH1_3_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtl7 0x140756 #define regUMCCH1_3_PerfMonCtl7_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr7_Lo 0x140757 #define regUMCCH1_3_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr7_Hi 0x140758 #define regUMCCH1_3_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtl8 0x140759 #define regUMCCH1_3_PerfMonCtl8_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr8_Lo 0x14075a #define regUMCCH1_3_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH1_3_PerfMonCtr8_Hi 0x14075b #define regUMCCH1_3_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc3_umcch2_umcchdec // base address: 0x652000 #define regUMCCH2_3_BaseAddrCS0 0x140800 #define regUMCCH2_3_BaseAddrCS0_BASE_IDX 1 #define regUMCCH2_3_AddrMaskCS01 0x140808 #define regUMCCH2_3_AddrMaskCS01_BASE_IDX 1 #define regUMCCH2_3_AddrSelCS01 0x140810 #define regUMCCH2_3_AddrSelCS01_BASE_IDX 1 #define regUMCCH2_3_AddrHashBank0 0x140832 #define regUMCCH2_3_AddrHashBank0_BASE_IDX 1 #define regUMCCH2_3_AddrHashBank1 0x140833 #define regUMCCH2_3_AddrHashBank1_BASE_IDX 1 #define regUMCCH2_3_AddrHashBank2 0x140834 #define regUMCCH2_3_AddrHashBank2_BASE_IDX 1 #define regUMCCH2_3_AddrHashBank3 0x140835 #define regUMCCH2_3_AddrHashBank3_BASE_IDX 1 #define regUMCCH2_3_AddrHashBank4 0x140836 #define regUMCCH2_3_AddrHashBank4_BASE_IDX 1 #define regUMCCH2_3_AddrHashBank5 0x140837 #define regUMCCH2_3_AddrHashBank5_BASE_IDX 1 #define regUMCCH2_3_EccErrCntSel 0x140b28 #define regUMCCH2_3_EccErrCntSel_BASE_IDX 1 #define regUMCCH2_3_EccErrCnt 0x140b29 #define regUMCCH2_3_EccErrCnt_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtlClk 0x140b40 #define regUMCCH2_3_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtrClk_Lo 0x140b41 #define regUMCCH2_3_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtrClk_Hi 0x140b42 #define regUMCCH2_3_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtl1 0x140b44 #define regUMCCH2_3_PerfMonCtl1_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr1_Lo 0x140b45 #define regUMCCH2_3_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr1_Hi 0x140b46 #define regUMCCH2_3_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtl2 0x140b47 #define regUMCCH2_3_PerfMonCtl2_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr2_Lo 0x140b48 #define regUMCCH2_3_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr2_Hi 0x140b49 #define regUMCCH2_3_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtl3 0x140b4a #define regUMCCH2_3_PerfMonCtl3_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr3_Lo 0x140b4b #define regUMCCH2_3_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr3_Hi 0x140b4c #define regUMCCH2_3_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtl4 0x140b4d #define regUMCCH2_3_PerfMonCtl4_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr4_Lo 0x140b4e #define regUMCCH2_3_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr4_Hi 0x140b4f #define regUMCCH2_3_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtl5 0x140b50 #define regUMCCH2_3_PerfMonCtl5_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr5_Lo 0x140b51 #define regUMCCH2_3_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr5_Hi 0x140b52 #define regUMCCH2_3_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtl6 0x140b53 #define regUMCCH2_3_PerfMonCtl6_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr6_Lo 0x140b54 #define regUMCCH2_3_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr6_Hi 0x140b55 #define regUMCCH2_3_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtl7 0x140b56 #define regUMCCH2_3_PerfMonCtl7_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr7_Lo 0x140b57 #define regUMCCH2_3_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr7_Hi 0x140b58 #define regUMCCH2_3_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtl8 0x140b59 #define regUMCCH2_3_PerfMonCtl8_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr8_Lo 0x140b5a #define regUMCCH2_3_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH2_3_PerfMonCtr8_Hi 0x140b5b #define regUMCCH2_3_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc3_umcch3_umcchdec // base address: 0x653000 #define regUMCCH3_3_BaseAddrCS0 0x140c00 #define regUMCCH3_3_BaseAddrCS0_BASE_IDX 1 #define regUMCCH3_3_AddrMaskCS01 0x140c08 #define regUMCCH3_3_AddrMaskCS01_BASE_IDX 1 #define regUMCCH3_3_AddrSelCS01 0x140c10 #define regUMCCH3_3_AddrSelCS01_BASE_IDX 1 #define regUMCCH3_3_AddrHashBank0 0x140c32 #define regUMCCH3_3_AddrHashBank0_BASE_IDX 1 #define regUMCCH3_3_AddrHashBank1 0x140c33 #define regUMCCH3_3_AddrHashBank1_BASE_IDX 1 #define regUMCCH3_3_AddrHashBank2 0x140c34 #define regUMCCH3_3_AddrHashBank2_BASE_IDX 1 #define regUMCCH3_3_AddrHashBank3 0x140c35 #define regUMCCH3_3_AddrHashBank3_BASE_IDX 1 #define regUMCCH3_3_AddrHashBank4 0x140c36 #define regUMCCH3_3_AddrHashBank4_BASE_IDX 1 #define regUMCCH3_3_AddrHashBank5 0x140c37 #define regUMCCH3_3_AddrHashBank5_BASE_IDX 1 #define regUMCCH3_3_EccErrCntSel 0x140f28 #define regUMCCH3_3_EccErrCntSel_BASE_IDX 1 #define regUMCCH3_3_EccErrCnt 0x140f29 #define regUMCCH3_3_EccErrCnt_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtlClk 0x140f40 #define regUMCCH3_3_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtrClk_Lo 0x140f41 #define regUMCCH3_3_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtrClk_Hi 0x140f42 #define regUMCCH3_3_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtl1 0x140f44 #define regUMCCH3_3_PerfMonCtl1_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr1_Lo 0x140f45 #define regUMCCH3_3_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr1_Hi 0x140f46 #define regUMCCH3_3_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtl2 0x140f47 #define regUMCCH3_3_PerfMonCtl2_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr2_Lo 0x140f48 #define regUMCCH3_3_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr2_Hi 0x140f49 #define regUMCCH3_3_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtl3 0x140f4a #define regUMCCH3_3_PerfMonCtl3_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr3_Lo 0x140f4b #define regUMCCH3_3_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr3_Hi 0x140f4c #define regUMCCH3_3_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtl4 0x140f4d #define regUMCCH3_3_PerfMonCtl4_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr4_Lo 0x140f4e #define regUMCCH3_3_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr4_Hi 0x140f4f #define regUMCCH3_3_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtl5 0x140f50 #define regUMCCH3_3_PerfMonCtl5_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr5_Lo 0x140f51 #define regUMCCH3_3_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr5_Hi 0x140f52 #define regUMCCH3_3_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtl6 0x140f53 #define regUMCCH3_3_PerfMonCtl6_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr6_Lo 0x140f54 #define regUMCCH3_3_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr6_Hi 0x140f55 #define regUMCCH3_3_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtl7 0x140f56 #define regUMCCH3_3_PerfMonCtl7_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr7_Lo 0x140f57 #define regUMCCH3_3_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr7_Hi 0x140f58 #define regUMCCH3_3_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtl8 0x140f59 #define regUMCCH3_3_PerfMonCtl8_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr8_Lo 0x140f5a #define regUMCCH3_3_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH3_3_PerfMonCtr8_Hi 0x140f5b #define regUMCCH3_3_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc3_umcch4_umcchdec // base address: 0x750000 #define regUMCCH4_3_BaseAddrCS0 0x180000 #define regUMCCH4_3_BaseAddrCS0_BASE_IDX 1 #define regUMCCH4_3_AddrMaskCS01 0x180008 #define regUMCCH4_3_AddrMaskCS01_BASE_IDX 1 #define regUMCCH4_3_AddrSelCS01 0x180010 #define regUMCCH4_3_AddrSelCS01_BASE_IDX 1 #define regUMCCH4_3_AddrHashBank0 0x180032 #define regUMCCH4_3_AddrHashBank0_BASE_IDX 1 #define regUMCCH4_3_AddrHashBank1 0x180033 #define regUMCCH4_3_AddrHashBank1_BASE_IDX 1 #define regUMCCH4_3_AddrHashBank2 0x180034 #define regUMCCH4_3_AddrHashBank2_BASE_IDX 1 #define regUMCCH4_3_AddrHashBank3 0x180035 #define regUMCCH4_3_AddrHashBank3_BASE_IDX 1 #define regUMCCH4_3_AddrHashBank4 0x180036 #define regUMCCH4_3_AddrHashBank4_BASE_IDX 1 #define regUMCCH4_3_AddrHashBank5 0x180037 #define regUMCCH4_3_AddrHashBank5_BASE_IDX 1 #define regUMCCH4_3_EccErrCntSel 0x180328 #define regUMCCH4_3_EccErrCntSel_BASE_IDX 1 #define regUMCCH4_3_EccErrCnt 0x180329 #define regUMCCH4_3_EccErrCnt_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtlClk 0x180340 #define regUMCCH4_3_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtrClk_Lo 0x180341 #define regUMCCH4_3_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtrClk_Hi 0x180342 #define regUMCCH4_3_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtl1 0x180344 #define regUMCCH4_3_PerfMonCtl1_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr1_Lo 0x180345 #define regUMCCH4_3_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr1_Hi 0x180346 #define regUMCCH4_3_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtl2 0x180347 #define regUMCCH4_3_PerfMonCtl2_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr2_Lo 0x180348 #define regUMCCH4_3_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr2_Hi 0x180349 #define regUMCCH4_3_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtl3 0x18034a #define regUMCCH4_3_PerfMonCtl3_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr3_Lo 0x18034b #define regUMCCH4_3_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr3_Hi 0x18034c #define regUMCCH4_3_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtl4 0x18034d #define regUMCCH4_3_PerfMonCtl4_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr4_Lo 0x18034e #define regUMCCH4_3_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr4_Hi 0x18034f #define regUMCCH4_3_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtl5 0x180350 #define regUMCCH4_3_PerfMonCtl5_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr5_Lo 0x180351 #define regUMCCH4_3_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr5_Hi 0x180352 #define regUMCCH4_3_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtl6 0x180353 #define regUMCCH4_3_PerfMonCtl6_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr6_Lo 0x180354 #define regUMCCH4_3_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr6_Hi 0x180355 #define regUMCCH4_3_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtl7 0x180356 #define regUMCCH4_3_PerfMonCtl7_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr7_Lo 0x180357 #define regUMCCH4_3_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr7_Hi 0x180358 #define regUMCCH4_3_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtl8 0x180359 #define regUMCCH4_3_PerfMonCtl8_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr8_Lo 0x18035a #define regUMCCH4_3_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH4_3_PerfMonCtr8_Hi 0x18035b #define regUMCCH4_3_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc3_umcch5_umcchdec // base address: 0x751000 #define regUMCCH5_3_BaseAddrCS0 0x180400 #define regUMCCH5_3_BaseAddrCS0_BASE_IDX 1 #define regUMCCH5_3_AddrMaskCS01 0x180408 #define regUMCCH5_3_AddrMaskCS01_BASE_IDX 1 #define regUMCCH5_3_AddrSelCS01 0x180410 #define regUMCCH5_3_AddrSelCS01_BASE_IDX 1 #define regUMCCH5_3_AddrHashBank0 0x180432 #define regUMCCH5_3_AddrHashBank0_BASE_IDX 1 #define regUMCCH5_3_AddrHashBank1 0x180433 #define regUMCCH5_3_AddrHashBank1_BASE_IDX 1 #define regUMCCH5_3_AddrHashBank2 0x180434 #define regUMCCH5_3_AddrHashBank2_BASE_IDX 1 #define regUMCCH5_3_AddrHashBank3 0x180435 #define regUMCCH5_3_AddrHashBank3_BASE_IDX 1 #define regUMCCH5_3_AddrHashBank4 0x180436 #define regUMCCH5_3_AddrHashBank4_BASE_IDX 1 #define regUMCCH5_3_AddrHashBank5 0x180437 #define regUMCCH5_3_AddrHashBank5_BASE_IDX 1 #define regUMCCH5_3_EccErrCntSel 0x180728 #define regUMCCH5_3_EccErrCntSel_BASE_IDX 1 #define regUMCCH5_3_EccErrCnt 0x180729 #define regUMCCH5_3_EccErrCnt_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtlClk 0x180740 #define regUMCCH5_3_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtrClk_Lo 0x180741 #define regUMCCH5_3_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtrClk_Hi 0x180742 #define regUMCCH5_3_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtl1 0x180744 #define regUMCCH5_3_PerfMonCtl1_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr1_Lo 0x180745 #define regUMCCH5_3_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr1_Hi 0x180746 #define regUMCCH5_3_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtl2 0x180747 #define regUMCCH5_3_PerfMonCtl2_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr2_Lo 0x180748 #define regUMCCH5_3_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr2_Hi 0x180749 #define regUMCCH5_3_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtl3 0x18074a #define regUMCCH5_3_PerfMonCtl3_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr3_Lo 0x18074b #define regUMCCH5_3_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr3_Hi 0x18074c #define regUMCCH5_3_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtl4 0x18074d #define regUMCCH5_3_PerfMonCtl4_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr4_Lo 0x18074e #define regUMCCH5_3_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr4_Hi 0x18074f #define regUMCCH5_3_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtl5 0x180750 #define regUMCCH5_3_PerfMonCtl5_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr5_Lo 0x180751 #define regUMCCH5_3_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr5_Hi 0x180752 #define regUMCCH5_3_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtl6 0x180753 #define regUMCCH5_3_PerfMonCtl6_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr6_Lo 0x180754 #define regUMCCH5_3_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr6_Hi 0x180755 #define regUMCCH5_3_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtl7 0x180756 #define regUMCCH5_3_PerfMonCtl7_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr7_Lo 0x180757 #define regUMCCH5_3_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr7_Hi 0x180758 #define regUMCCH5_3_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtl8 0x180759 #define regUMCCH5_3_PerfMonCtl8_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr8_Lo 0x18075a #define regUMCCH5_3_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH5_3_PerfMonCtr8_Hi 0x18075b #define regUMCCH5_3_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc3_umcch6_umcchdec // base address: 0x752000 #define regUMCCH6_3_BaseAddrCS0 0x180800 #define regUMCCH6_3_BaseAddrCS0_BASE_IDX 1 #define regUMCCH6_3_AddrMaskCS01 0x180808 #define regUMCCH6_3_AddrMaskCS01_BASE_IDX 1 #define regUMCCH6_3_AddrSelCS01 0x180810 #define regUMCCH6_3_AddrSelCS01_BASE_IDX 1 #define regUMCCH6_3_AddrHashBank0 0x180832 #define regUMCCH6_3_AddrHashBank0_BASE_IDX 1 #define regUMCCH6_3_AddrHashBank1 0x180833 #define regUMCCH6_3_AddrHashBank1_BASE_IDX 1 #define regUMCCH6_3_AddrHashBank2 0x180834 #define regUMCCH6_3_AddrHashBank2_BASE_IDX 1 #define regUMCCH6_3_AddrHashBank3 0x180835 #define regUMCCH6_3_AddrHashBank3_BASE_IDX 1 #define regUMCCH6_3_AddrHashBank4 0x180836 #define regUMCCH6_3_AddrHashBank4_BASE_IDX 1 #define regUMCCH6_3_AddrHashBank5 0x180837 #define regUMCCH6_3_AddrHashBank5_BASE_IDX 1 #define regUMCCH6_3_EccErrCntSel 0x180b28 #define regUMCCH6_3_EccErrCntSel_BASE_IDX 1 #define regUMCCH6_3_EccErrCnt 0x180b29 #define regUMCCH6_3_EccErrCnt_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtlClk 0x180b40 #define regUMCCH6_3_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtrClk_Lo 0x180b41 #define regUMCCH6_3_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtrClk_Hi 0x180b42 #define regUMCCH6_3_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtl1 0x180b44 #define regUMCCH6_3_PerfMonCtl1_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr1_Lo 0x180b45 #define regUMCCH6_3_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr1_Hi 0x180b46 #define regUMCCH6_3_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtl2 0x180b47 #define regUMCCH6_3_PerfMonCtl2_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr2_Lo 0x180b48 #define regUMCCH6_3_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr2_Hi 0x180b49 #define regUMCCH6_3_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtl3 0x180b4a #define regUMCCH6_3_PerfMonCtl3_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr3_Lo 0x180b4b #define regUMCCH6_3_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr3_Hi 0x180b4c #define regUMCCH6_3_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtl4 0x180b4d #define regUMCCH6_3_PerfMonCtl4_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr4_Lo 0x180b4e #define regUMCCH6_3_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr4_Hi 0x180b4f #define regUMCCH6_3_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtl5 0x180b50 #define regUMCCH6_3_PerfMonCtl5_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr5_Lo 0x180b51 #define regUMCCH6_3_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr5_Hi 0x180b52 #define regUMCCH6_3_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtl6 0x180b53 #define regUMCCH6_3_PerfMonCtl6_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr6_Lo 0x180b54 #define regUMCCH6_3_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr6_Hi 0x180b55 #define regUMCCH6_3_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtl7 0x180b56 #define regUMCCH6_3_PerfMonCtl7_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr7_Lo 0x180b57 #define regUMCCH6_3_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr7_Hi 0x180b58 #define regUMCCH6_3_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtl8 0x180b59 #define regUMCCH6_3_PerfMonCtl8_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr8_Lo 0x180b5a #define regUMCCH6_3_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH6_3_PerfMonCtr8_Hi 0x180b5b #define regUMCCH6_3_PerfMonCtr8_Hi_BASE_IDX 1 // addressBlock: umc_w_phy_umc3_umcch7_umcchdec // base address: 0x753000 #define regUMCCH7_3_BaseAddrCS0 0x180c00 #define regUMCCH7_3_BaseAddrCS0_BASE_IDX 1 #define regUMCCH7_3_AddrMaskCS01 0x180c08 #define regUMCCH7_3_AddrMaskCS01_BASE_IDX 1 #define regUMCCH7_3_AddrSelCS01 0x180c10 #define regUMCCH7_3_AddrSelCS01_BASE_IDX 1 #define regUMCCH7_3_AddrHashBank0 0x180c32 #define regUMCCH7_3_AddrHashBank0_BASE_IDX 1 #define regUMCCH7_3_AddrHashBank1 0x180c33 #define regUMCCH7_3_AddrHashBank1_BASE_IDX 1 #define regUMCCH7_3_AddrHashBank2 0x180c34 #define regUMCCH7_3_AddrHashBank2_BASE_IDX 1 #define regUMCCH7_3_AddrHashBank3 0x180c35 #define regUMCCH7_3_AddrHashBank3_BASE_IDX 1 #define regUMCCH7_3_AddrHashBank4 0x180c36 #define regUMCCH7_3_AddrHashBank4_BASE_IDX 1 #define regUMCCH7_3_AddrHashBank5 0x180c37 #define regUMCCH7_3_AddrHashBank5_BASE_IDX 1 #define regUMCCH7_3_EccErrCntSel 0x180f28 #define regUMCCH7_3_EccErrCntSel_BASE_IDX 1 #define regUMCCH7_3_EccErrCnt 0x180f29 #define regUMCCH7_3_EccErrCnt_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtlClk 0x180f40 #define regUMCCH7_3_PerfMonCtlClk_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtrClk_Lo 0x180f41 #define regUMCCH7_3_PerfMonCtrClk_Lo_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtrClk_Hi 0x180f42 #define regUMCCH7_3_PerfMonCtrClk_Hi_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtl1 0x180f44 #define regUMCCH7_3_PerfMonCtl1_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr1_Lo 0x180f45 #define regUMCCH7_3_PerfMonCtr1_Lo_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr1_Hi 0x180f46 #define regUMCCH7_3_PerfMonCtr1_Hi_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtl2 0x180f47 #define regUMCCH7_3_PerfMonCtl2_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr2_Lo 0x180f48 #define regUMCCH7_3_PerfMonCtr2_Lo_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr2_Hi 0x180f49 #define regUMCCH7_3_PerfMonCtr2_Hi_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtl3 0x180f4a #define regUMCCH7_3_PerfMonCtl3_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr3_Lo 0x180f4b #define regUMCCH7_3_PerfMonCtr3_Lo_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr3_Hi 0x180f4c #define regUMCCH7_3_PerfMonCtr3_Hi_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtl4 0x180f4d #define regUMCCH7_3_PerfMonCtl4_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr4_Lo 0x180f4e #define regUMCCH7_3_PerfMonCtr4_Lo_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr4_Hi 0x180f4f #define regUMCCH7_3_PerfMonCtr4_Hi_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtl5 0x180f50 #define regUMCCH7_3_PerfMonCtl5_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr5_Lo 0x180f51 #define regUMCCH7_3_PerfMonCtr5_Lo_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr5_Hi 0x180f52 #define regUMCCH7_3_PerfMonCtr5_Hi_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtl6 0x180f53 #define regUMCCH7_3_PerfMonCtl6_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr6_Lo 0x180f54 #define regUMCCH7_3_PerfMonCtr6_Lo_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr6_Hi 0x180f55 #define regUMCCH7_3_PerfMonCtr6_Hi_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtl7 0x180f56 #define regUMCCH7_3_PerfMonCtl7_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr7_Lo 0x180f57 #define regUMCCH7_3_PerfMonCtr7_Lo_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr7_Hi 0x180f58 #define regUMCCH7_3_PerfMonCtr7_Hi_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtl8 0x180f59 #define regUMCCH7_3_PerfMonCtl8_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr8_Lo 0x180f5a #define regUMCCH7_3_PerfMonCtr8_Lo_BASE_IDX 1 #define regUMCCH7_3_PerfMonCtr8_Hi 0x180f5b #define regUMCCH7_3_PerfMonCtr8_Hi_BASE_IDX 1 #endif