1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright (C) 2020 Advanced Micro Devices, Inc.
4  *
5  * Authors: AMD
6  */
7 
8 #ifndef _dpcs_3_0_0_OFFSET_HEADER
9 #define _dpcs_3_0_0_OFFSET_HEADER
10 
11 
12 
13 // addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
14 // base address: 0x0
15 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                                                 0x2928
16 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
17 #define mmDPCSTX0_DPCSTX_TX_CNTL                                                                       0x2929
18 #define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX                                                              2
19 #define mmDPCSTX0_DPCSTX_CBUS_CNTL                                                                     0x292a
20 #define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
21 #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL                                                                0x292b
22 #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
23 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                                               0x292c
24 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
25 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                                               0x292d
26 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
27 
28 
29 // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
30 // base address: 0x0
31 #define mmRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
32 #define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
33 #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
34 #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
35 #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
36 #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
37 #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA                                                             0x2933
38 #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
39 #define mmRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
40 #define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
41 #define mmRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
42 #define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
43 #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
44 #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
45 #define mmRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
46 #define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
47 #define mmRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
48 #define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
49 #define mmRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
50 #define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
51 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
52 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
53 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
54 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
55 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
56 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
57 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
58 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
59 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
60 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
61 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
62 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
63 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
64 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
65 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
66 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
67 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
68 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
69 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
70 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
71 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
72 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
73 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
74 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
75 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
76 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
77 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
78 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
79 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
80 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
81 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
82 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
83 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
84 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
85 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
86 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
87 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
88 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
89 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
90 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
91 #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
92 #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
93 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
94 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
95 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
96 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
97 #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
98 #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
99 
100 
101 // addressBlock: dpcssys_dpcssys_cr0_dispdec
102 // base address: 0x0
103 #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
104 #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
105 #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
106 #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
107 
108 
109 // addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
110 // base address: 0x360
111 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                                                 0x2a00
112 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
113 #define mmDPCSTX1_DPCSTX_TX_CNTL                                                                       0x2a01
114 #define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX                                                              2
115 #define mmDPCSTX1_DPCSTX_CBUS_CNTL                                                                     0x2a02
116 #define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
117 #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL                                                                0x2a03
118 #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
119 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                                               0x2a04
120 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
121 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                                               0x2a05
122 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
123 
124 
125 // addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
126 // base address: 0x360
127 #define mmRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
128 #define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
129 #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
130 #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
131 #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
132 #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
133 #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA                                                             0x2a0b
134 #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
135 #define mmRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
136 #define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
137 #define mmRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
138 #define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
139 #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
140 #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
141 #define mmRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
142 #define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
143 #define mmRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
144 #define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
145 #define mmRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
146 #define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
147 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
148 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
149 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
150 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
151 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
152 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
153 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
154 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
155 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
156 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
157 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
158 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
159 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
160 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
161 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
162 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
163 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
164 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
165 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
166 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
167 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
168 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
169 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
170 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
171 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
172 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
173 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
174 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
175 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
176 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
177 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
178 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
179 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
180 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
181 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
182 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
183 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
184 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
185 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
186 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
187 #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
188 #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
189 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
190 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
191 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
192 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
193 #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
194 #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
195 
196 
197 // addressBlock: dpcssys_dpcssys_cr1_dispdec
198 // base address: 0x360
199 #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
200 #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
201 #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
202 #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
203 
204 
205 // addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
206 // base address: 0x6c0
207 #define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL                                                                 0x2ad8
208 #define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
209 #define mmDPCSTX2_DPCSTX_TX_CNTL                                                                       0x2ad9
210 #define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX                                                              2
211 #define mmDPCSTX2_DPCSTX_CBUS_CNTL                                                                     0x2ada
212 #define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
213 #define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL                                                                0x2adb
214 #define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
215 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR                                                               0x2adc
216 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
217 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA                                                               0x2add
218 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
219 
220 
221 // addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
222 // base address: 0x6c0
223 #define mmRDPCSTX2_RDPCSTX_CNTL                                                                        0x2ae0
224 #define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX                                                               2
225 #define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL                                                                  0x2ae1
226 #define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
227 #define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL                                                           0x2ae2
228 #define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
229 #define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA                                                             0x2ae3
230 #define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
231 #define mmRDPCSTX2_RDPCS_TX_CR_ADDR                                                                    0x2ae4
232 #define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
233 #define mmRDPCSTX2_RDPCS_TX_CR_DATA                                                                    0x2ae5
234 #define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
235 #define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL                                                                  0x2ae6
236 #define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
237 #define mmRDPCSTX2_RDPCSTX_SCRATCH                                                                     0x2ae7
238 #define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX                                                            2
239 #define mmRDPCSTX2_RDPCSTX_SPARE                                                                       0x2ae8
240 #define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX                                                              2
241 #define mmRDPCSTX2_RDPCSTX_CNTL2                                                                       0x2ae9
242 #define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2
243 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2aec
244 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
245 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0
246 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
247 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1
248 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
249 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL2                                                                   0x2af2
250 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
251 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL3                                                                   0x2af3
252 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
253 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL4                                                                   0x2af4
254 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
255 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL5                                                                   0x2af5
256 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
257 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL6                                                                   0x2af6
258 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
259 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL7                                                                   0x2af7
260 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
261 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL8                                                                   0x2af8
262 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
263 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL9                                                                   0x2af9
264 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
265 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL10                                                                  0x2afa
266 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
267 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL11                                                                  0x2afb
268 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
269 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL12                                                                  0x2afc
270 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
271 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL13                                                                  0x2afd
272 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
273 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL14                                                                  0x2afe
274 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
275 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE0                                                                   0x2aff
276 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
277 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE1                                                                   0x2b00
278 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
279 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE2                                                                   0x2b01
280 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
281 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE3                                                                   0x2b02
282 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
283 #define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL                                                               0x2b03
284 #define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
285 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2b04
286 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
287 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2b05
288 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
289 #define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG                                                           0x2b06
290 #define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
291 
292 
293 // addressBlock: dpcssys_dpcssys_cr2_dispdec
294 // base address: 0x6c0
295 #define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR                                                                  0x2ae4
296 #define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
297 #define mmDPCSSYS_CR2_DPCSSYS_CR_DATA                                                                  0x2ae5
298 #define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX                                                         2
299 
300 
301 // addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
302 // base address: 0xa20
303 #define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL                                                                 0x2bb0
304 #define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
305 #define mmDPCSTX3_DPCSTX_TX_CNTL                                                                       0x2bb1
306 #define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX                                                              2
307 #define mmDPCSTX3_DPCSTX_CBUS_CNTL                                                                     0x2bb2
308 #define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
309 #define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL                                                                0x2bb3
310 #define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
311 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR                                                               0x2bb4
312 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
313 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA                                                               0x2bb5
314 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
315 
316 
317 // addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
318 // base address: 0xa20
319 #define mmRDPCSTX3_RDPCSTX_CNTL                                                                        0x2bb8
320 #define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX                                                               2
321 #define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL                                                                  0x2bb9
322 #define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
323 #define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL                                                           0x2bba
324 #define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
325 #define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA                                                             0x2bbb
326 #define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
327 #define mmRDPCSTX3_RDPCS_TX_CR_ADDR                                                                    0x2bbc
328 #define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
329 #define mmRDPCSTX3_RDPCS_TX_CR_DATA                                                                    0x2bbd
330 #define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
331 #define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL                                                                  0x2bbe
332 #define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
333 #define mmRDPCSTX3_RDPCSTX_SCRATCH                                                                     0x2bbf
334 #define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX                                                            2
335 #define mmRDPCSTX3_RDPCSTX_SPARE                                                                       0x2bc0
336 #define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX                                                              2
337 #define mmRDPCSTX3_RDPCSTX_CNTL2                                                                       0x2bc1
338 #define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2
339 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2bc4
340 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
341 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8
342 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
343 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9
344 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
345 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL2                                                                   0x2bca
346 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
347 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL3                                                                   0x2bcb
348 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
349 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL4                                                                   0x2bcc
350 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
351 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL5                                                                   0x2bcd
352 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
353 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL6                                                                   0x2bce
354 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
355 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL7                                                                   0x2bcf
356 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
357 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL8                                                                   0x2bd0
358 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
359 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL9                                                                   0x2bd1
360 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
361 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL10                                                                  0x2bd2
362 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
363 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL11                                                                  0x2bd3
364 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
365 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL12                                                                  0x2bd4
366 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
367 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL13                                                                  0x2bd5
368 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
369 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL14                                                                  0x2bd6
370 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
371 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE0                                                                   0x2bd7
372 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
373 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE1                                                                   0x2bd8
374 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
375 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE2                                                                   0x2bd9
376 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
377 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE3                                                                   0x2bda
378 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
379 #define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL                                                               0x2bdb
380 #define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
381 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2bdc
382 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
383 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2bdd
384 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
385 #define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG                                                           0x2bde
386 #define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
387 
388 
389 // addressBlock: dpcssys_dpcssys_cr3_dispdec
390 // base address: 0xa20
391 #define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR                                                                  0x2bbc
392 #define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
393 #define mmDPCSSYS_CR3_DPCSSYS_CR_DATA                                                                  0x2bbd
394 #define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX                                                         2
395 
396 
397 // addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
398 // base address: 0xd80
399 #define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL                                                                 0x2c88
400 #define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
401 #define mmDPCSTX4_DPCSTX_TX_CNTL                                                                       0x2c89
402 #define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX                                                              2
403 #define mmDPCSTX4_DPCSTX_CBUS_CNTL                                                                     0x2c8a
404 #define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
405 #define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL                                                                0x2c8b
406 #define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
407 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR                                                               0x2c8c
408 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
409 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA                                                               0x2c8d
410 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
411 
412 
413 // addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
414 // base address: 0xd80
415 #define mmRDPCSTX4_RDPCSTX_CNTL                                                                        0x2c90
416 #define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX                                                               2
417 #define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL                                                                  0x2c91
418 #define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
419 #define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL                                                           0x2c92
420 #define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
421 #define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA                                                             0x2c93
422 #define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
423 #define mmRDPCSTX4_RDPCS_TX_CR_ADDR                                                                    0x2c94
424 #define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
425 #define mmRDPCSTX4_RDPCS_TX_CR_DATA                                                                    0x2c95
426 #define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
427 #define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL                                                                  0x2c96
428 #define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
429 #define mmRDPCSTX4_RDPCSTX_SCRATCH                                                                     0x2c97
430 #define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX                                                            2
431 #define mmRDPCSTX4_RDPCSTX_SPARE                                                                       0x2c98
432 #define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX                                                              2
433 #define mmRDPCSTX4_RDPCSTX_CNTL2                                                                       0x2c99
434 #define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX                                                              2
435 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2c9c
436 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
437 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL0                                                                   0x2ca0
438 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
439 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL1                                                                   0x2ca1
440 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
441 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL2                                                                   0x2ca2
442 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
443 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL3                                                                   0x2ca3
444 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
445 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL4                                                                   0x2ca4
446 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
447 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL5                                                                   0x2ca5
448 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
449 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL6                                                                   0x2ca6
450 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
451 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL7                                                                   0x2ca7
452 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
453 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL8                                                                   0x2ca8
454 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
455 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL9                                                                   0x2ca9
456 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
457 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL10                                                                  0x2caa
458 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
459 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL11                                                                  0x2cab
460 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
461 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL12                                                                  0x2cac
462 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
463 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL13                                                                  0x2cad
464 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
465 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL14                                                                  0x2cae
466 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
467 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE0                                                                   0x2caf
468 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
469 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE1                                                                   0x2cb0
470 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
471 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE2                                                                   0x2cb1
472 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
473 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE3                                                                   0x2cb2
474 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
475 #define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL                                                               0x2cb3
476 #define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
477 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2cb4
478 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
479 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2cb5
480 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
481 #define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG                                                           0x2cb6
482 #define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
483 
484 
485 // addressBlock: dpcssys_dpcssys_cr4_dispdec
486 // base address: 0xd80
487 #define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR                                                                  0x2c94
488 #define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
489 #define mmDPCSSYS_CR4_DPCSSYS_CR_DATA                                                                  0x2c95
490 #define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX                                                         2
491 
492 
493 // addressBlock: dpcssys_dpcs0_dpcstx5_dispdec
494 // base address: 0x10e0
495 #define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL                                                                 0x2d60
496 #define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
497 #define mmDPCSTX5_DPCSTX_TX_CNTL                                                                       0x2d61
498 #define mmDPCSTX5_DPCSTX_TX_CNTL_BASE_IDX                                                              2
499 #define mmDPCSTX5_DPCSTX_CBUS_CNTL                                                                     0x2d62
500 #define mmDPCSTX5_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
501 #define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL                                                                0x2d63
502 #define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
503 #define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR                                                               0x2d64
504 #define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
505 #define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA                                                               0x2d65
506 #define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
507 
508 
509 // addressBlock: dpcssys_dpcs0_rdpcstx5_dispdec
510 // base address: 0x10e0
511 #define mmRDPCSTX5_RDPCSTX_CNTL                                                                        0x2d68
512 #define mmRDPCSTX5_RDPCSTX_CNTL_BASE_IDX                                                               2
513 #define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL                                                                  0x2d69
514 #define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
515 #define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL                                                           0x2d6a
516 #define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
517 #define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA                                                             0x2d6b
518 #define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
519 #define mmRDPCSTX5_RDPCS_TX_CR_ADDR                                                                    0x2d6c
520 #define mmRDPCSTX5_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
521 #define mmRDPCSTX5_RDPCS_TX_CR_DATA                                                                    0x2d6d
522 #define mmRDPCSTX5_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
523 #define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL                                                                  0x2d6e
524 #define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
525 #define mmRDPCSTX5_RDPCSTX_SCRATCH                                                                     0x2d6f
526 #define mmRDPCSTX5_RDPCSTX_SCRATCH_BASE_IDX                                                            2
527 #define mmRDPCSTX5_RDPCSTX_SPARE                                                                       0x2d70
528 #define mmRDPCSTX5_RDPCSTX_SPARE_BASE_IDX                                                              2
529 #define mmRDPCSTX5_RDPCSTX_CNTL2                                                                       0x2d71
530 #define mmRDPCSTX5_RDPCSTX_CNTL2_BASE_IDX                                                              2
531 #define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2d74
532 #define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
533 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL0                                                                   0x2d78
534 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
535 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL1                                                                   0x2d79
536 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
537 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL2                                                                   0x2d7a
538 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
539 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL3                                                                   0x2d7b
540 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
541 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL4                                                                   0x2d7c
542 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
543 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL5                                                                   0x2d7d
544 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
545 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL6                                                                   0x2d7e
546 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
547 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL7                                                                   0x2d7f
548 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
549 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL8                                                                   0x2d80
550 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
551 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL9                                                                   0x2d81
552 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
553 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL10                                                                  0x2d82
554 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
555 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL11                                                                  0x2d83
556 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
557 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL12                                                                  0x2d84
558 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
559 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL13                                                                  0x2d85
560 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
561 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL14                                                                  0x2d86
562 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
563 #define mmRDPCSTX5_RDPCSTX_PHY_FUSE0                                                                   0x2d87
564 #define mmRDPCSTX5_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
565 #define mmRDPCSTX5_RDPCSTX_PHY_FUSE1                                                                   0x2d88
566 #define mmRDPCSTX5_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
567 #define mmRDPCSTX5_RDPCSTX_PHY_FUSE2                                                                   0x2d89
568 #define mmRDPCSTX5_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
569 #define mmRDPCSTX5_RDPCSTX_PHY_FUSE3                                                                   0x2d8a
570 #define mmRDPCSTX5_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
571 #define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL                                                               0x2d8b
572 #define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
573 #define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2d8c
574 #define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
575 #define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2d8d
576 #define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
577 #define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG                                                           0x2d8e
578 #define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
579 
580 #endif
581