1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dml/dcn30/dcn30_fpu.h" 47 48 #include "dcn10/dcn10_resource.h" 49 50 #include "dce/dce_abm.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_clock_source.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_i2c_hw.h" 56 #include "dce/dce_panel_cntl.h" 57 #include "dce/dmub_abm.h" 58 #include "dce/dmub_psr.h" 59 #include "clk_mgr.h" 60 61 #include "hw_sequencer_private.h" 62 #include "reg_helper.h" 63 #include "resource.h" 64 #include "vm_helper.h" 65 66 #include "dml/dcn302/dcn302_fpu.h" 67 68 #include "dimgrey_cavefish_ip_offset.h" 69 #include "dcn/dcn_3_0_2_offset.h" 70 #include "dcn/dcn_3_0_2_sh_mask.h" 71 #include "dpcs/dpcs_3_0_0_offset.h" 72 #include "dpcs/dpcs_3_0_0_sh_mask.h" 73 #include "nbio/nbio_7_4_offset.h" 74 #include "amdgpu_socbb.h" 75 76 #define DC_LOGGER_INIT(logger) 77 78 static const struct dc_debug_options debug_defaults_drv = { 79 .disable_dmcu = true, 80 .force_abm_enable = false, 81 .timing_trace = false, 82 .clock_trace = true, 83 .disable_pplib_clock_request = true, 84 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 85 .force_single_disp_pipe_split = false, 86 .disable_dcc = DCC_ENABLE, 87 .vsr_support = true, 88 .performance_trace = false, 89 .max_downscale_src_width = 7680,/*upto 8K*/ 90 .disable_pplib_wm_range = false, 91 .scl_reset_length10 = true, 92 .sanity_checks = false, 93 .underflow_assert_delay_us = 0xFFFFFFFF, 94 .dwb_fi_phase = -1, // -1 = disable, 95 .dmub_command_table = true, 96 .use_max_lb = true, 97 .exit_idle_opt_for_cursor_updates = true 98 }; 99 100 static const struct dc_debug_options debug_defaults_diags = { 101 .disable_dmcu = true, 102 .force_abm_enable = false, 103 .timing_trace = true, 104 .clock_trace = true, 105 .disable_dpp_power_gate = true, 106 .disable_hubp_power_gate = true, 107 .disable_clock_gate = true, 108 .disable_pplib_clock_request = true, 109 .disable_pplib_wm_range = true, 110 .disable_stutter = false, 111 .scl_reset_length10 = true, 112 .dwb_fi_phase = -1, // -1 = disable 113 .dmub_command_table = true, 114 .enable_tri_buf = true, 115 .use_max_lb = true 116 }; 117 118 static const struct dc_panel_config panel_config_defaults = { 119 .psr = { 120 .disable_psr = false, 121 .disallow_psrsu = false, 122 }, 123 }; 124 125 enum dcn302_clk_src_array_id { 126 DCN302_CLK_SRC_PLL0, 127 DCN302_CLK_SRC_PLL1, 128 DCN302_CLK_SRC_PLL2, 129 DCN302_CLK_SRC_PLL3, 130 DCN302_CLK_SRC_PLL4, 131 DCN302_CLK_SRC_TOTAL 132 }; 133 134 static const struct resource_caps res_cap_dcn302 = { 135 .num_timing_generator = 5, 136 .num_opp = 5, 137 .num_video_plane = 5, 138 .num_audio = 5, 139 .num_stream_encoder = 5, 140 .num_dwb = 1, 141 .num_ddc = 5, 142 .num_vmid = 16, 143 .num_mpc_3dlut = 2, 144 .num_dsc = 5, 145 }; 146 147 static const struct dc_plane_cap plane_cap = { 148 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 149 .blends_with_above = true, 150 .blends_with_below = true, 151 .per_pixel_alpha = true, 152 .pixel_format_support = { 153 .argb8888 = true, 154 .nv12 = true, 155 .fp16 = true, 156 .p010 = true, 157 .ayuv = false, 158 }, 159 .max_upscale_factor = { 160 .argb8888 = 16000, 161 .nv12 = 16000, 162 .fp16 = 16000 163 }, 164 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 165 .max_downscale_factor = { 166 .argb8888 = 167, 167 .nv12 = 167, 168 .fp16 = 167 169 }, 170 16, 171 16 172 }; 173 174 /* NBIO */ 175 #define NBIO_BASE_INNER(seg) \ 176 NBIO_BASE__INST0_SEG ## seg 177 178 #define NBIO_BASE(seg) \ 179 NBIO_BASE_INNER(seg) 180 181 #define NBIO_SR(reg_name)\ 182 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 183 mm ## reg_name 184 185 /* DCN */ 186 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 187 188 #define BASE(seg) BASE_INNER(seg) 189 190 #define SR(reg_name)\ 191 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 192 193 #define SF(reg_name, field_name, post_fix)\ 194 .field_name = reg_name ## __ ## field_name ## post_fix 195 196 #define SRI(reg_name, block, id)\ 197 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 198 199 #define SRI2(reg_name, block, id)\ 200 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 201 202 #define SRII(reg_name, block, id)\ 203 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 204 mm ## block ## id ## _ ## reg_name 205 206 #define DCCG_SRII(reg_name, block, id)\ 207 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 208 mm ## block ## id ## _ ## reg_name 209 210 #define VUPDATE_SRII(reg_name, block, id)\ 211 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 212 mm ## reg_name ## _ ## block ## id 213 214 #define SRII_DWB(reg_name, temp_name, block, id)\ 215 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 216 mm ## block ## id ## _ ## temp_name 217 218 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 219 .field_name = reg_name ## __ ## field_name ## post_fix 220 221 #define SRII_MPC_RMU(reg_name, block, id)\ 222 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 223 mm ## block ## id ## _ ## reg_name 224 225 static const struct dcn_hubbub_registers hubbub_reg = { 226 HUBBUB_REG_LIST_DCN30(0) 227 }; 228 229 static const struct dcn_hubbub_shift hubbub_shift = { 230 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 231 }; 232 233 static const struct dcn_hubbub_mask hubbub_mask = { 234 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 235 }; 236 237 #define vmid_regs(id)\ 238 [id] = { DCN20_VMID_REG_LIST(id) } 239 240 static const struct dcn_vmid_registers vmid_regs[] = { 241 vmid_regs(0), 242 vmid_regs(1), 243 vmid_regs(2), 244 vmid_regs(3), 245 vmid_regs(4), 246 vmid_regs(5), 247 vmid_regs(6), 248 vmid_regs(7), 249 vmid_regs(8), 250 vmid_regs(9), 251 vmid_regs(10), 252 vmid_regs(11), 253 vmid_regs(12), 254 vmid_regs(13), 255 vmid_regs(14), 256 vmid_regs(15) 257 }; 258 259 static const struct dcn20_vmid_shift vmid_shifts = { 260 DCN20_VMID_MASK_SH_LIST(__SHIFT) 261 }; 262 263 static const struct dcn20_vmid_mask vmid_masks = { 264 DCN20_VMID_MASK_SH_LIST(_MASK) 265 }; 266 267 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 268 { 269 int i; 270 271 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 272 273 if (!hubbub3) 274 return NULL; 275 276 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 277 278 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 279 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 280 281 vmid->ctx = ctx; 282 283 vmid->regs = &vmid_regs[i]; 284 vmid->shifts = &vmid_shifts; 285 vmid->masks = &vmid_masks; 286 } 287 288 return &hubbub3->base; 289 } 290 291 #define vpg_regs(id)\ 292 [id] = { VPG_DCN3_REG_LIST(id) } 293 294 static const struct dcn30_vpg_registers vpg_regs[] = { 295 vpg_regs(0), 296 vpg_regs(1), 297 vpg_regs(2), 298 vpg_regs(3), 299 vpg_regs(4), 300 vpg_regs(5) 301 }; 302 303 static const struct dcn30_vpg_shift vpg_shift = { 304 DCN3_VPG_MASK_SH_LIST(__SHIFT) 305 }; 306 307 static const struct dcn30_vpg_mask vpg_mask = { 308 DCN3_VPG_MASK_SH_LIST(_MASK) 309 }; 310 311 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 312 { 313 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 314 315 if (!vpg3) 316 return NULL; 317 318 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 319 320 return &vpg3->base; 321 } 322 323 #define afmt_regs(id)\ 324 [id] = { AFMT_DCN3_REG_LIST(id) } 325 326 static const struct dcn30_afmt_registers afmt_regs[] = { 327 afmt_regs(0), 328 afmt_regs(1), 329 afmt_regs(2), 330 afmt_regs(3), 331 afmt_regs(4), 332 afmt_regs(5) 333 }; 334 335 static const struct dcn30_afmt_shift afmt_shift = { 336 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 337 }; 338 339 static const struct dcn30_afmt_mask afmt_mask = { 340 DCN3_AFMT_MASK_SH_LIST(_MASK) 341 }; 342 343 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 344 { 345 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 346 347 if (!afmt3) 348 return NULL; 349 350 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 351 352 return &afmt3->base; 353 } 354 355 #define audio_regs(id)\ 356 [id] = { AUD_COMMON_REG_LIST(id) } 357 358 static const struct dce_audio_registers audio_regs[] = { 359 audio_regs(0), 360 audio_regs(1), 361 audio_regs(2), 362 audio_regs(3), 363 audio_regs(4), 364 audio_regs(5), 365 audio_regs(6) 366 }; 367 368 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 369 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 370 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 371 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 372 373 static const struct dce_audio_shift audio_shift = { 374 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 375 }; 376 377 static const struct dce_audio_mask audio_mask = { 378 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 379 }; 380 381 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 382 { 383 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 384 } 385 386 #define stream_enc_regs(id)\ 387 [id] = { SE_DCN3_REG_LIST(id) } 388 389 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 390 stream_enc_regs(0), 391 stream_enc_regs(1), 392 stream_enc_regs(2), 393 stream_enc_regs(3), 394 stream_enc_regs(4) 395 }; 396 397 static const struct dcn10_stream_encoder_shift se_shift = { 398 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 399 }; 400 401 static const struct dcn10_stream_encoder_mask se_mask = { 402 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 403 }; 404 405 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 406 { 407 struct dcn10_stream_encoder *enc1; 408 struct vpg *vpg; 409 struct afmt *afmt; 410 int vpg_inst; 411 int afmt_inst; 412 413 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 414 if (eng_id <= ENGINE_ID_DIGE) { 415 vpg_inst = eng_id; 416 afmt_inst = eng_id; 417 } else 418 return NULL; 419 420 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 421 vpg = dcn302_vpg_create(ctx, vpg_inst); 422 afmt = dcn302_afmt_create(ctx, afmt_inst); 423 424 if (!enc1 || !vpg || !afmt) { 425 kfree(enc1); 426 kfree(vpg); 427 kfree(afmt); 428 return NULL; 429 } 430 431 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 432 &se_shift, &se_mask); 433 434 return &enc1->base; 435 } 436 437 #define clk_src_regs(index, pllid)\ 438 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 439 440 static const struct dce110_clk_src_regs clk_src_regs[] = { 441 clk_src_regs(0, A), 442 clk_src_regs(1, B), 443 clk_src_regs(2, C), 444 clk_src_regs(3, D), 445 clk_src_regs(4, E) 446 }; 447 448 static const struct dce110_clk_src_shift cs_shift = { 449 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 450 }; 451 452 static const struct dce110_clk_src_mask cs_mask = { 453 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 454 }; 455 456 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 457 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 458 { 459 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 460 461 if (!clk_src) 462 return NULL; 463 464 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 465 clk_src->base.dp_clk_src = dp_clk_src; 466 return &clk_src->base; 467 } 468 469 kfree(clk_src); 470 BREAK_TO_DEBUGGER(); 471 return NULL; 472 } 473 474 static const struct dce_hwseq_registers hwseq_reg = { 475 HWSEQ_DCN302_REG_LIST() 476 }; 477 478 static const struct dce_hwseq_shift hwseq_shift = { 479 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 480 }; 481 482 static const struct dce_hwseq_mask hwseq_mask = { 483 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 484 }; 485 486 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 487 { 488 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 489 490 if (hws) { 491 hws->ctx = ctx; 492 hws->regs = &hwseq_reg; 493 hws->shifts = &hwseq_shift; 494 hws->masks = &hwseq_mask; 495 } 496 return hws; 497 } 498 499 #define hubp_regs(id)\ 500 [id] = { HUBP_REG_LIST_DCN30(id) } 501 502 static const struct dcn_hubp2_registers hubp_regs[] = { 503 hubp_regs(0), 504 hubp_regs(1), 505 hubp_regs(2), 506 hubp_regs(3), 507 hubp_regs(4) 508 }; 509 510 static const struct dcn_hubp2_shift hubp_shift = { 511 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 512 }; 513 514 static const struct dcn_hubp2_mask hubp_mask = { 515 HUBP_MASK_SH_LIST_DCN30(_MASK) 516 }; 517 518 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 519 { 520 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 521 522 if (!hubp2) 523 return NULL; 524 525 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 526 return &hubp2->base; 527 528 BREAK_TO_DEBUGGER(); 529 kfree(hubp2); 530 return NULL; 531 } 532 533 #define dpp_regs(id)\ 534 [id] = { DPP_REG_LIST_DCN30(id) } 535 536 static const struct dcn3_dpp_registers dpp_regs[] = { 537 dpp_regs(0), 538 dpp_regs(1), 539 dpp_regs(2), 540 dpp_regs(3), 541 dpp_regs(4) 542 }; 543 544 static const struct dcn3_dpp_shift tf_shift = { 545 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 546 }; 547 548 static const struct dcn3_dpp_mask tf_mask = { 549 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 550 }; 551 552 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 553 { 554 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 555 556 if (!dpp) 557 return NULL; 558 559 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 560 return &dpp->base; 561 562 BREAK_TO_DEBUGGER(); 563 kfree(dpp); 564 return NULL; 565 } 566 567 #define opp_regs(id)\ 568 [id] = { OPP_REG_LIST_DCN30(id) } 569 570 static const struct dcn20_opp_registers opp_regs[] = { 571 opp_regs(0), 572 opp_regs(1), 573 opp_regs(2), 574 opp_regs(3), 575 opp_regs(4) 576 }; 577 578 static const struct dcn20_opp_shift opp_shift = { 579 OPP_MASK_SH_LIST_DCN20(__SHIFT) 580 }; 581 582 static const struct dcn20_opp_mask opp_mask = { 583 OPP_MASK_SH_LIST_DCN20(_MASK) 584 }; 585 586 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 587 { 588 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 589 590 if (!opp) { 591 BREAK_TO_DEBUGGER(); 592 return NULL; 593 } 594 595 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 596 return &opp->base; 597 } 598 599 #define optc_regs(id)\ 600 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 601 602 static const struct dcn_optc_registers optc_regs[] = { 603 optc_regs(0), 604 optc_regs(1), 605 optc_regs(2), 606 optc_regs(3), 607 optc_regs(4) 608 }; 609 610 static const struct dcn_optc_shift optc_shift = { 611 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 612 }; 613 614 static const struct dcn_optc_mask optc_mask = { 615 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 616 }; 617 618 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 619 { 620 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 621 622 if (!tgn10) 623 return NULL; 624 625 tgn10->base.inst = instance; 626 tgn10->base.ctx = ctx; 627 628 tgn10->tg_regs = &optc_regs[instance]; 629 tgn10->tg_shift = &optc_shift; 630 tgn10->tg_mask = &optc_mask; 631 632 dcn30_timing_generator_init(tgn10); 633 634 return &tgn10->base; 635 } 636 637 static const struct dcn30_mpc_registers mpc_regs = { 638 MPC_REG_LIST_DCN3_0(0), 639 MPC_REG_LIST_DCN3_0(1), 640 MPC_REG_LIST_DCN3_0(2), 641 MPC_REG_LIST_DCN3_0(3), 642 MPC_REG_LIST_DCN3_0(4), 643 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 644 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 645 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 646 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 647 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 648 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 649 MPC_RMU_REG_LIST_DCN3AG(0), 650 MPC_RMU_REG_LIST_DCN3AG(1), 651 MPC_RMU_REG_LIST_DCN3AG(2), 652 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 653 }; 654 655 static const struct dcn30_mpc_shift mpc_shift = { 656 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 657 }; 658 659 static const struct dcn30_mpc_mask mpc_mask = { 660 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 661 }; 662 663 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 664 { 665 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 666 667 if (!mpc30) 668 return NULL; 669 670 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 671 672 return &mpc30->base; 673 } 674 675 #define dsc_regsDCN20(id)\ 676 [id] = { DSC_REG_LIST_DCN20(id) } 677 678 static const struct dcn20_dsc_registers dsc_regs[] = { 679 dsc_regsDCN20(0), 680 dsc_regsDCN20(1), 681 dsc_regsDCN20(2), 682 dsc_regsDCN20(3), 683 dsc_regsDCN20(4) 684 }; 685 686 static const struct dcn20_dsc_shift dsc_shift = { 687 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 688 }; 689 690 static const struct dcn20_dsc_mask dsc_mask = { 691 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 692 }; 693 694 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 695 { 696 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 697 698 if (!dsc) { 699 BREAK_TO_DEBUGGER(); 700 return NULL; 701 } 702 703 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 704 return &dsc->base; 705 } 706 707 #define dwbc_regs_dcn3(id)\ 708 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 709 710 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 711 dwbc_regs_dcn3(0) 712 }; 713 714 static const struct dcn30_dwbc_shift dwbc30_shift = { 715 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 716 }; 717 718 static const struct dcn30_dwbc_mask dwbc30_mask = { 719 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 720 }; 721 722 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 723 { 724 int i; 725 uint32_t pipe_count = pool->res_cap->num_dwb; 726 727 for (i = 0; i < pipe_count; i++) { 728 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 729 730 if (!dwbc30) { 731 dm_error("DC: failed to create dwbc30!\n"); 732 return false; 733 } 734 735 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 736 737 pool->dwbc[i] = &dwbc30->base; 738 } 739 return true; 740 } 741 742 #define mcif_wb_regs_dcn3(id)\ 743 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 744 745 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 746 mcif_wb_regs_dcn3(0) 747 }; 748 749 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 750 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 751 }; 752 753 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 754 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 755 }; 756 757 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 758 { 759 int i; 760 uint32_t pipe_count = pool->res_cap->num_dwb; 761 762 for (i = 0; i < pipe_count; i++) { 763 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 764 765 if (!mcif_wb30) { 766 dm_error("DC: failed to create mcif_wb30!\n"); 767 return false; 768 } 769 770 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 771 772 pool->mcif_wb[i] = &mcif_wb30->base; 773 } 774 return true; 775 } 776 777 #define aux_engine_regs(id)\ 778 [id] = {\ 779 AUX_COMMON_REG_LIST0(id), \ 780 .AUXN_IMPCAL = 0, \ 781 .AUXP_IMPCAL = 0, \ 782 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 783 } 784 785 static const struct dce110_aux_registers aux_engine_regs[] = { 786 aux_engine_regs(0), 787 aux_engine_regs(1), 788 aux_engine_regs(2), 789 aux_engine_regs(3), 790 aux_engine_regs(4) 791 }; 792 793 static const struct dce110_aux_registers_shift aux_shift = { 794 DCN_AUX_MASK_SH_LIST(__SHIFT) 795 }; 796 797 static const struct dce110_aux_registers_mask aux_mask = { 798 DCN_AUX_MASK_SH_LIST(_MASK) 799 }; 800 801 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 802 { 803 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 804 805 if (!aux_engine) 806 return NULL; 807 808 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 809 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 810 811 return &aux_engine->base; 812 } 813 814 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 815 816 static const struct dce_i2c_registers i2c_hw_regs[] = { 817 i2c_inst_regs(1), 818 i2c_inst_regs(2), 819 i2c_inst_regs(3), 820 i2c_inst_regs(4), 821 i2c_inst_regs(5) 822 }; 823 824 static const struct dce_i2c_shift i2c_shifts = { 825 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 826 }; 827 828 static const struct dce_i2c_mask i2c_masks = { 829 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 830 }; 831 832 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 833 { 834 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 835 836 if (!dce_i2c_hw) 837 return NULL; 838 839 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 840 841 return dce_i2c_hw; 842 } 843 844 static const struct encoder_feature_support link_enc_feature = { 845 .max_hdmi_deep_color = COLOR_DEPTH_121212, 846 .max_hdmi_pixel_clock = 600000, 847 .hdmi_ycbcr420_supported = true, 848 .dp_ycbcr420_supported = true, 849 .fec_supported = true, 850 .flags.bits.IS_HBR2_CAPABLE = true, 851 .flags.bits.IS_HBR3_CAPABLE = true, 852 .flags.bits.IS_TPS3_CAPABLE = true, 853 .flags.bits.IS_TPS4_CAPABLE = true 854 }; 855 856 #define link_regs(id, phyid)\ 857 [id] = {\ 858 LE_DCN3_REG_LIST(id), \ 859 UNIPHY_DCN2_REG_LIST(phyid), \ 860 DPCS_DCN2_REG_LIST(id), \ 861 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 862 } 863 864 static const struct dcn10_link_enc_registers link_enc_regs[] = { 865 link_regs(0, A), 866 link_regs(1, B), 867 link_regs(2, C), 868 link_regs(3, D), 869 link_regs(4, E) 870 }; 871 872 static const struct dcn10_link_enc_shift le_shift = { 873 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 874 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 875 }; 876 877 static const struct dcn10_link_enc_mask le_mask = { 878 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 879 DPCS_DCN2_MASK_SH_LIST(_MASK) 880 }; 881 882 #define aux_regs(id)\ 883 [id] = { DCN2_AUX_REG_LIST(id) } 884 885 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 886 aux_regs(0), 887 aux_regs(1), 888 aux_regs(2), 889 aux_regs(3), 890 aux_regs(4) 891 }; 892 893 #define hpd_regs(id)\ 894 [id] = { HPD_REG_LIST(id) } 895 896 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 897 hpd_regs(0), 898 hpd_regs(1), 899 hpd_regs(2), 900 hpd_regs(3), 901 hpd_regs(4) 902 }; 903 904 static struct link_encoder *dcn302_link_encoder_create( 905 struct dc_context *ctx, 906 const struct encoder_init_data *enc_init_data) 907 { 908 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 909 910 if (!enc20) 911 return NULL; 912 913 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 914 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 915 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 916 917 return &enc20->enc10.base; 918 } 919 920 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 921 { DCN_PANEL_CNTL_REG_LIST() } 922 }; 923 924 static const struct dce_panel_cntl_shift panel_cntl_shift = { 925 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 926 }; 927 928 static const struct dce_panel_cntl_mask panel_cntl_mask = { 929 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 930 }; 931 932 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 933 { 934 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 935 936 if (!panel_cntl) 937 return NULL; 938 939 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 940 &panel_cntl_shift, &panel_cntl_mask); 941 942 return &panel_cntl->base; 943 } 944 945 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 946 { 947 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 948 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 949 } 950 951 static const struct resource_create_funcs res_create_funcs = { 952 .read_dce_straps = read_dce_straps, 953 .create_audio = dcn302_create_audio, 954 .create_stream_encoder = dcn302_stream_encoder_create, 955 .create_hwseq = dcn302_hwseq_create, 956 }; 957 958 static const struct resource_create_funcs res_create_maximus_funcs = { 959 .read_dce_straps = NULL, 960 .create_audio = NULL, 961 .create_stream_encoder = NULL, 962 .create_hwseq = dcn302_hwseq_create, 963 }; 964 965 static bool is_soc_bounding_box_valid(struct dc *dc) 966 { 967 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 968 969 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 970 return true; 971 972 return false; 973 } 974 975 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 976 { 977 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 978 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 979 980 DC_LOGGER_INIT(dc->ctx->logger); 981 982 if (!is_soc_bounding_box_valid(dc)) { 983 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 984 return false; 985 } 986 987 loaded_ip->max_num_otg = pool->pipe_count; 988 loaded_ip->max_num_dpp = pool->pipe_count; 989 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 990 DC_FP_START(); 991 dcn20_patch_bounding_box(dc, loaded_bb); 992 DC_FP_END(); 993 994 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 995 struct bp_soc_bb_info bb_info = { 0 }; 996 997 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 998 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 999 1000 DC_FP_START(); 1001 dcn302_fpu_init_soc_bounding_box(bb_info); 1002 DC_FP_END(); 1003 } 1004 } 1005 1006 return true; 1007 } 1008 1009 static void dcn302_resource_destruct(struct resource_pool *pool) 1010 { 1011 unsigned int i; 1012 1013 for (i = 0; i < pool->stream_enc_count; i++) { 1014 if (pool->stream_enc[i] != NULL) { 1015 if (pool->stream_enc[i]->vpg != NULL) { 1016 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1017 pool->stream_enc[i]->vpg = NULL; 1018 } 1019 if (pool->stream_enc[i]->afmt != NULL) { 1020 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1021 pool->stream_enc[i]->afmt = NULL; 1022 } 1023 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1024 pool->stream_enc[i] = NULL; 1025 } 1026 } 1027 1028 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1029 if (pool->dscs[i] != NULL) 1030 dcn20_dsc_destroy(&pool->dscs[i]); 1031 } 1032 1033 if (pool->mpc != NULL) { 1034 kfree(TO_DCN20_MPC(pool->mpc)); 1035 pool->mpc = NULL; 1036 } 1037 1038 if (pool->hubbub != NULL) { 1039 kfree(pool->hubbub); 1040 pool->hubbub = NULL; 1041 } 1042 1043 for (i = 0; i < pool->pipe_count; i++) { 1044 if (pool->dpps[i] != NULL) { 1045 kfree(TO_DCN20_DPP(pool->dpps[i])); 1046 pool->dpps[i] = NULL; 1047 } 1048 1049 if (pool->hubps[i] != NULL) { 1050 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1051 pool->hubps[i] = NULL; 1052 } 1053 1054 if (pool->irqs != NULL) 1055 dal_irq_service_destroy(&pool->irqs); 1056 } 1057 1058 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1059 if (pool->engines[i] != NULL) 1060 dce110_engine_destroy(&pool->engines[i]); 1061 if (pool->hw_i2cs[i] != NULL) { 1062 kfree(pool->hw_i2cs[i]); 1063 pool->hw_i2cs[i] = NULL; 1064 } 1065 if (pool->sw_i2cs[i] != NULL) { 1066 kfree(pool->sw_i2cs[i]); 1067 pool->sw_i2cs[i] = NULL; 1068 } 1069 } 1070 1071 for (i = 0; i < pool->res_cap->num_opp; i++) { 1072 if (pool->opps[i] != NULL) 1073 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1074 } 1075 1076 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1077 if (pool->timing_generators[i] != NULL) { 1078 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1079 pool->timing_generators[i] = NULL; 1080 } 1081 } 1082 1083 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1084 if (pool->dwbc[i] != NULL) { 1085 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1086 pool->dwbc[i] = NULL; 1087 } 1088 if (pool->mcif_wb[i] != NULL) { 1089 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1090 pool->mcif_wb[i] = NULL; 1091 } 1092 } 1093 1094 for (i = 0; i < pool->audio_count; i++) { 1095 if (pool->audios[i]) 1096 dce_aud_destroy(&pool->audios[i]); 1097 } 1098 1099 for (i = 0; i < pool->clk_src_count; i++) { 1100 if (pool->clock_sources[i] != NULL) 1101 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1102 } 1103 1104 if (pool->dp_clock_source != NULL) 1105 dcn20_clock_source_destroy(&pool->dp_clock_source); 1106 1107 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1108 if (pool->mpc_lut[i] != NULL) { 1109 dc_3dlut_func_release(pool->mpc_lut[i]); 1110 pool->mpc_lut[i] = NULL; 1111 } 1112 if (pool->mpc_shaper[i] != NULL) { 1113 dc_transfer_func_release(pool->mpc_shaper[i]); 1114 pool->mpc_shaper[i] = NULL; 1115 } 1116 } 1117 1118 for (i = 0; i < pool->pipe_count; i++) { 1119 if (pool->multiple_abms[i] != NULL) 1120 dce_abm_destroy(&pool->multiple_abms[i]); 1121 } 1122 1123 if (pool->psr != NULL) 1124 dmub_psr_destroy(&pool->psr); 1125 1126 if (pool->dccg != NULL) 1127 dcn_dccg_destroy(&pool->dccg); 1128 } 1129 1130 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1131 { 1132 dcn302_resource_destruct(*pool); 1133 kfree(*pool); 1134 *pool = NULL; 1135 } 1136 1137 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1138 { 1139 DC_FP_START(); 1140 dcn302_fpu_update_bw_bounding_box(dc, bw_params); 1141 DC_FP_END(); 1142 } 1143 1144 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config) 1145 { 1146 *panel_config = panel_config_defaults; 1147 } 1148 1149 static struct resource_funcs dcn302_res_pool_funcs = { 1150 .destroy = dcn302_destroy_resource_pool, 1151 .link_enc_create = dcn302_link_encoder_create, 1152 .panel_cntl_create = dcn302_panel_cntl_create, 1153 .validate_bandwidth = dcn30_validate_bandwidth, 1154 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1155 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1156 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1157 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1158 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1159 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1160 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1161 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1162 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1163 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1164 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1165 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1166 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1167 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1168 .get_panel_config_defaults = dcn302_get_panel_config_defaults, 1169 }; 1170 1171 static struct dc_cap_funcs cap_funcs = { 1172 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1173 }; 1174 1175 static const struct bios_registers bios_regs = { 1176 NBIO_SR(BIOS_SCRATCH_3), 1177 NBIO_SR(BIOS_SCRATCH_6) 1178 }; 1179 1180 static const struct dccg_registers dccg_regs = { 1181 DCCG_REG_LIST_DCN3_02() 1182 }; 1183 1184 static const struct dccg_shift dccg_shift = { 1185 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1186 }; 1187 1188 static const struct dccg_mask dccg_mask = { 1189 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1190 }; 1191 1192 #define abm_regs(id)\ 1193 [id] = { ABM_DCN302_REG_LIST(id) } 1194 1195 static const struct dce_abm_registers abm_regs[] = { 1196 abm_regs(0), 1197 abm_regs(1), 1198 abm_regs(2), 1199 abm_regs(3), 1200 abm_regs(4) 1201 }; 1202 1203 static const struct dce_abm_shift abm_shift = { 1204 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1205 }; 1206 1207 static const struct dce_abm_mask abm_mask = { 1208 ABM_MASK_SH_LIST_DCN30(_MASK) 1209 }; 1210 1211 static bool dcn302_resource_construct( 1212 uint8_t num_virtual_links, 1213 struct dc *dc, 1214 struct resource_pool *pool) 1215 { 1216 int i; 1217 struct dc_context *ctx = dc->ctx; 1218 struct irq_service_init_data init_data; 1219 1220 ctx->dc_bios->regs = &bios_regs; 1221 1222 pool->res_cap = &res_cap_dcn302; 1223 1224 pool->funcs = &dcn302_res_pool_funcs; 1225 1226 /************************************************* 1227 * Resource + asic cap harcoding * 1228 *************************************************/ 1229 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1230 pool->pipe_count = pool->res_cap->num_timing_generator; 1231 pool->mpcc_count = pool->res_cap->num_timing_generator; 1232 dc->caps.max_downscale_ratio = 600; 1233 dc->caps.i2c_speed_in_khz = 100; 1234 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1235 dc->caps.max_cursor_size = 256; 1236 dc->caps.min_horizontal_blanking_period = 80; 1237 dc->caps.dmdata_alloc_size = 2048; 1238 dc->caps.mall_size_per_mem_channel = 4; 1239 /* total size = mall per channel * num channels * 1024 * 1024 */ 1240 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1241 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1242 dc->caps.max_slave_planes = 2; 1243 dc->caps.max_slave_yuv_planes = 2; 1244 dc->caps.max_slave_rgb_planes = 2; 1245 dc->caps.post_blend_color_processing = true; 1246 dc->caps.force_dp_tps4_for_cp2520 = true; 1247 dc->caps.extended_aux_timeout_support = true; 1248 dc->caps.dmcub_support = true; 1249 1250 /* Color pipeline capabilities */ 1251 dc->caps.color.dpp.dcn_arch = 1; 1252 dc->caps.color.dpp.input_lut_shared = 0; 1253 dc->caps.color.dpp.icsc = 1; 1254 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1255 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1256 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1257 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1258 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1259 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1260 dc->caps.color.dpp.post_csc = 1; 1261 dc->caps.color.dpp.gamma_corr = 1; 1262 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1263 1264 dc->caps.color.dpp.hw_3d_lut = 1; 1265 dc->caps.color.dpp.ogam_ram = 1; 1266 // no OGAM ROM on DCN3 1267 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1268 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1269 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1270 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1271 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1272 dc->caps.color.dpp.ocsc = 0; 1273 1274 dc->caps.color.mpc.gamut_remap = 1; 1275 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1276 dc->caps.color.mpc.ogam_ram = 1; 1277 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1278 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1279 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1280 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1281 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1282 dc->caps.color.mpc.ocsc = 1; 1283 1284 dc->caps.dp_hdmi21_pcon_support = true; 1285 1286 /* read VBIOS LTTPR caps */ 1287 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1288 enum bp_result bp_query_result; 1289 uint8_t is_vbios_lttpr_enable = 0; 1290 1291 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1292 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1293 } 1294 1295 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1296 enum bp_result bp_query_result; 1297 uint8_t is_vbios_interop_enabled = 0; 1298 1299 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 1300 &is_vbios_interop_enabled); 1301 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1302 } 1303 1304 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1305 dc->debug = debug_defaults_drv; 1306 else 1307 dc->debug = debug_defaults_diags; 1308 1309 // Init the vm_helper 1310 if (dc->vm_helper) 1311 vm_helper_init(dc->vm_helper, 16); 1312 1313 /************************************************* 1314 * Create resources * 1315 *************************************************/ 1316 1317 /* Clock Sources for Pixel Clock*/ 1318 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1319 dcn302_clock_source_create(ctx, ctx->dc_bios, 1320 CLOCK_SOURCE_COMBO_PHY_PLL0, 1321 &clk_src_regs[0], false); 1322 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1323 dcn302_clock_source_create(ctx, ctx->dc_bios, 1324 CLOCK_SOURCE_COMBO_PHY_PLL1, 1325 &clk_src_regs[1], false); 1326 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1327 dcn302_clock_source_create(ctx, ctx->dc_bios, 1328 CLOCK_SOURCE_COMBO_PHY_PLL2, 1329 &clk_src_regs[2], false); 1330 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1331 dcn302_clock_source_create(ctx, ctx->dc_bios, 1332 CLOCK_SOURCE_COMBO_PHY_PLL3, 1333 &clk_src_regs[3], false); 1334 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1335 dcn302_clock_source_create(ctx, ctx->dc_bios, 1336 CLOCK_SOURCE_COMBO_PHY_PLL4, 1337 &clk_src_regs[4], false); 1338 1339 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1340 1341 /* todo: not reuse phy_pll registers */ 1342 pool->dp_clock_source = 1343 dcn302_clock_source_create(ctx, ctx->dc_bios, 1344 CLOCK_SOURCE_ID_DP_DTO, 1345 &clk_src_regs[0], true); 1346 1347 for (i = 0; i < pool->clk_src_count; i++) { 1348 if (pool->clock_sources[i] == NULL) { 1349 dm_error("DC: failed to create clock sources!\n"); 1350 BREAK_TO_DEBUGGER(); 1351 goto create_fail; 1352 } 1353 } 1354 1355 /* DCCG */ 1356 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1357 if (pool->dccg == NULL) { 1358 dm_error("DC: failed to create dccg!\n"); 1359 BREAK_TO_DEBUGGER(); 1360 goto create_fail; 1361 } 1362 1363 /* PP Lib and SMU interfaces */ 1364 init_soc_bounding_box(dc, pool); 1365 1366 /* DML */ 1367 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1368 1369 /* IRQ */ 1370 init_data.ctx = dc->ctx; 1371 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1372 if (!pool->irqs) 1373 goto create_fail; 1374 1375 /* HUBBUB */ 1376 pool->hubbub = dcn302_hubbub_create(ctx); 1377 if (pool->hubbub == NULL) { 1378 BREAK_TO_DEBUGGER(); 1379 dm_error("DC: failed to create hubbub!\n"); 1380 goto create_fail; 1381 } 1382 1383 /* HUBPs, DPPs, OPPs and TGs */ 1384 for (i = 0; i < pool->pipe_count; i++) { 1385 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1386 if (pool->hubps[i] == NULL) { 1387 BREAK_TO_DEBUGGER(); 1388 dm_error("DC: failed to create hubps!\n"); 1389 goto create_fail; 1390 } 1391 1392 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1393 if (pool->dpps[i] == NULL) { 1394 BREAK_TO_DEBUGGER(); 1395 dm_error("DC: failed to create dpps!\n"); 1396 goto create_fail; 1397 } 1398 } 1399 1400 for (i = 0; i < pool->res_cap->num_opp; i++) { 1401 pool->opps[i] = dcn302_opp_create(ctx, i); 1402 if (pool->opps[i] == NULL) { 1403 BREAK_TO_DEBUGGER(); 1404 dm_error("DC: failed to create output pixel processor!\n"); 1405 goto create_fail; 1406 } 1407 } 1408 1409 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1410 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1411 if (pool->timing_generators[i] == NULL) { 1412 BREAK_TO_DEBUGGER(); 1413 dm_error("DC: failed to create tg!\n"); 1414 goto create_fail; 1415 } 1416 } 1417 pool->timing_generator_count = i; 1418 1419 /* PSR */ 1420 pool->psr = dmub_psr_create(ctx); 1421 if (pool->psr == NULL) { 1422 dm_error("DC: failed to create psr!\n"); 1423 BREAK_TO_DEBUGGER(); 1424 goto create_fail; 1425 } 1426 1427 /* ABMs */ 1428 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1429 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1430 if (pool->multiple_abms[i] == NULL) { 1431 dm_error("DC: failed to create abm for pipe %d!\n", i); 1432 BREAK_TO_DEBUGGER(); 1433 goto create_fail; 1434 } 1435 } 1436 1437 /* MPC and DSC */ 1438 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1439 if (pool->mpc == NULL) { 1440 BREAK_TO_DEBUGGER(); 1441 dm_error("DC: failed to create mpc!\n"); 1442 goto create_fail; 1443 } 1444 1445 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1446 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1447 if (pool->dscs[i] == NULL) { 1448 BREAK_TO_DEBUGGER(); 1449 dm_error("DC: failed to create display stream compressor %d!\n", i); 1450 goto create_fail; 1451 } 1452 } 1453 1454 /* DWB and MMHUBBUB */ 1455 if (!dcn302_dwbc_create(ctx, pool)) { 1456 BREAK_TO_DEBUGGER(); 1457 dm_error("DC: failed to create dwbc!\n"); 1458 goto create_fail; 1459 } 1460 1461 if (!dcn302_mmhubbub_create(ctx, pool)) { 1462 BREAK_TO_DEBUGGER(); 1463 dm_error("DC: failed to create mcif_wb!\n"); 1464 goto create_fail; 1465 } 1466 1467 /* AUX and I2C */ 1468 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1469 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1470 if (pool->engines[i] == NULL) { 1471 BREAK_TO_DEBUGGER(); 1472 dm_error("DC:failed to create aux engine!!\n"); 1473 goto create_fail; 1474 } 1475 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1476 if (pool->hw_i2cs[i] == NULL) { 1477 BREAK_TO_DEBUGGER(); 1478 dm_error("DC:failed to create hw i2c!!\n"); 1479 goto create_fail; 1480 } 1481 pool->sw_i2cs[i] = NULL; 1482 } 1483 1484 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1485 if (!resource_construct(num_virtual_links, dc, pool, 1486 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1487 &res_create_funcs : &res_create_maximus_funcs))) 1488 goto create_fail; 1489 1490 /* HW Sequencer and Plane caps */ 1491 dcn302_hw_sequencer_construct(dc); 1492 1493 dc->caps.max_planes = pool->pipe_count; 1494 1495 for (i = 0; i < dc->caps.max_planes; ++i) 1496 dc->caps.planes[i] = plane_cap; 1497 1498 dc->cap_funcs = cap_funcs; 1499 1500 return true; 1501 1502 create_fail: 1503 1504 dcn302_resource_destruct(pool); 1505 1506 return false; 1507 } 1508 1509 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1510 { 1511 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1512 1513 if (!pool) 1514 return NULL; 1515 1516 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1517 return pool; 1518 1519 BREAK_TO_DEBUGGER(); 1520 kfree(pool); 1521 return NULL; 1522 } 1523