Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42 |
|
#
198f0e89 |
| 26-Jul-2023 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: rename acquire_idle_pipe_for_layer to acquire_free_pipe_as_sec_dpp_pipe
[why] Secondary DPP pipes are used for rendering secondary layers of planes. The name "for layer" doesn't mak
drm/amd/display: rename acquire_idle_pipe_for_layer to acquire_free_pipe_as_sec_dpp_pipe
[why] Secondary DPP pipes are used for rendering secondary layers of planes. The name "for layer" doesn't make it obvious. The function is acquiring a free pipe as secondary dpp pipe only. We rename it so it is more obvious. In a future follow up change, we want to add functions to acquire free pipe as opp head pipe or otg master pipe as well. They will have their separate allocation priority.
Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29 |
|
#
e0138644 |
| 12-May-2023 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Add structs for Freesync Panel Replay
In some instances, the GPU is transmitting repeated frame to the sink without any updates or changes in the content. These repeat transmission
drm/amd/display: Add structs for Freesync Panel Replay
In some instances, the GPU is transmitting repeated frame to the sink without any updates or changes in the content. These repeat transmission are wasteful, resulting in power draw in different aspects of the system
1. DCN is fetching the frame of data from DF/UMC/DRAM. This memory traffic prevents power down of parts of this HW path.
2. GPU is transmitting pixel data to the display through the main link of the DisplayPort interface. This prevents power down of both the Source transmitter (TX) and the Sink receiver (RX) The concepts of utilizing replay is similar to PSR, but there is a benefit of: Source and Sink remaining synchronized which allows for - lower latency when switching from replay to live frames - enable the possibility of more use cases - easy control of the sink's refresh rate during replay
Due to Source and Sink remaining timing synchronized, Replay can be activated in more UI scenarios.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
724617b9 |
| 06-Jun-2023 |
Alvin Lee <alvin.lee2@amd.com> |
drm/amd/display: enable the new fast update path for supported ASICs
The new fast update sequence is now supported on some ASICs. So, enable it by default for all applicable ASICs.
Reviewed-by: Sam
drm/amd/display: enable the new fast update path for supported ASICs
The new fast update sequence is now supported on some ASICs. So, enable it by default for all applicable ASICs.
Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
da55037a |
| 01-Jun-2023 |
Austin Zheng <austin.zheng@amd.com> |
drm/amd/display: Limit Minimum FreeSync Refresh Rate
Why: Some EDIDs report a minimum refresh rate lower than what HW can support
How: Add a check to calculate minimum supported refresh rate with c
drm/amd/display: Limit Minimum FreeSync Refresh Rate
Why: Some EDIDs report a minimum refresh rate lower than what HW can support
How: Add a check to calculate minimum supported refresh rate with current timing and use that as the minimum if a lower one is passed in
Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Austin Zheng <austin.zheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
aab9b215 |
| 23-May-2023 |
Yang Li <yang.lee@linux.alibaba.com> |
drm/amd/display: remove unused definition
Eliminate the following warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:957:43: warning: unused variable 'res_create_maximus_fun
drm/amd/display: remove unused definition
Eliminate the following warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:957:43: warning: unused variable 'res_create_maximus_funcs' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:101:38: warning: unused variable 'debug_defaults_diags'
Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5296 Fixes: 25879d7b4986 ("drm/amd/display: Clean FPGA code in dc") Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20 |
|
#
25879d7b |
| 16-Mar-2023 |
Qingqing Zhuo <qingqing.zhuo@amd.com> |
drm/amd/display: Clean FPGA code in dc
[Why] Drop dead code for Linux.
[How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com> Acked-by: Tom Chung
drm/amd/display: Clean FPGA code in dc
[Why] Drop dead code for Linux.
[How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14 |
|
#
98ce7d32 |
| 23-Feb-2023 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: convert link.h functions to function pointer style
[Why & How] All dc subcomponents should call another dc component via function pointers stored in a component structure. This is p
drm/amd/display: convert link.h functions to function pointer style
[Why & How] All dc subcomponents should call another dc component via function pointers stored in a component structure. This is part of dc coding convention since the beginning. The reason behind this is to improve encapsulation and polymorphism. The function contract is extracted into a single link service structure defined in link.h header file and implemented only in link_factory.c instead of spreading across multiple files in link component file structure.
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
c0a76ae8 |
| 07-Mar-2023 |
David Tadokoro <davidbtadokoro@usp.br> |
drm/amd/display: remove legacy fields of dc_plane_cap struct
The fields blends_with_above and blends_with_below of struct dc_plane_cap (defined in dc/dc.h) are boolean and set to true by default. Al
drm/amd/display: remove legacy fields of dc_plane_cap struct
The fields blends_with_above and blends_with_below of struct dc_plane_cap (defined in dc/dc.h) are boolean and set to true by default. All instances of a dc_plane_cap maintain the default values of both. Also, there is only one if statement that checks those fields and there would be the same effect if it was deleted (assuming that those fields are always going to be true).
For this reason, considering both fields as legacy ones, this commit removes them and the aforementioned if statement.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: David Tadokoro <davidbtadokoro@usp.br> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13 |
|
#
a98cdd8c |
| 12-Dec-2022 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: refactor ddc logic from dc_link_ddc to link_ddc
[why] 1. Move dd_link_ddc functions to link_ddc. 2. Move link ddc functions declaration exposed in dc to link.h 3. Move link ddc func
drm/amd/display: refactor ddc logic from dc_link_ddc to link_ddc
[why] 1. Move dd_link_ddc functions to link_ddc. 2. Move link ddc functions declaration exposed in dc to link.h 3. Move link ddc functions declaration exposed in dm to dc_link.h 4. Remove i2caux_interface.h file
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80 |
|
#
39173f24 |
| 18-Nov-2022 |
David Galiffi <David.Galiffi@amd.com> |
drm/amd/display: Enable dp_hdmi21_pcon support
[Why] It is not enabled for DCN3.0.1, 3.0.2, 3.0.3.
[How] Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions.
Reviewed-by: Martin Leu
drm/amd/display: Enable dp_hdmi21_pcon support
[Why] It is not enabled for DCN3.0.1, 3.0.2, 3.0.3.
[How] Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions.
Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: David Galiffi <David.Galiffi@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38 |
|
#
158858bf |
| 06-May-2022 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/display: rework macros for DWB register access
[Why] A hack was used to access DWB register due to difference in the register naming convention which was not compatible with existing SR/SRI*
drm/amd/display: rework macros for DWB register access
[Why] A hack was used to access DWB register due to difference in the register naming convention which was not compatible with existing SR/SRI* macros. The additional macro needed were added to dwb ip specific header file (dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in turn needed us to undefine them in the resource file.
[How] Add a separate macro for DWB access to the resource files that need it instead of defining them in DWB ip header file. This will enable us to reuse the BASE macro defined in the resource file.
Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
fcb4f919 |
| 04-Nov-2022 |
LongJun Tang <tanglongjun@kylinos.cn> |
drm/amd/display: Have risk for memory exhaustion
In dcn*_clock_source_create when dcn*_clk_src_construct fails allocated clk_src needs release. A local attack could use this to cause memory exhausti
drm/amd/display: Have risk for memory exhaustion
In dcn*_clock_source_create when dcn*_clk_src_construct fails allocated clk_src needs release. A local attack could use this to cause memory exhaustion.
Signed-off-by: LongJun Tang <tanglongjun@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
bd829d57 |
| 20-Oct-2022 |
Ian Chen <ian.chen@amd.com> |
drm/amd/display: Refactor eDP PSR codes
We split out PSR config from "global" to "per-panel" config settings.
Tested-by: Mark Broadworth <mark.broadworth@amd.com> Reviewed-by: Robin Chen <robin.che
drm/amd/display: Refactor eDP PSR codes
We split out PSR config from "global" to "per-panel" config settings.
Tested-by: Mark Broadworth <mark.broadworth@amd.com> Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
93667546 |
| 15-Sep-2022 |
Brandon Syu <Brandon.Syu@amd.com> |
drm/amd/display: Add debug option for exiting idle optimizations on cursor updates
[Description] - Have option to exit idle opt on cursor updates for debug and optimizations purposes
Reviewed-by: A
drm/amd/display: Add debug option for exiting idle optimizations on cursor updates
[Description] - Have option to exit idle opt on cursor updates for debug and optimizations purposes
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Brandon Syu<Brandon.Syu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33 |
|
#
e216431b |
| 01-Apr-2022 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/display: Add dc_ctx to link_enc_create() parameters
[Why&How] Preparation to enable run time initialization of register offsets to add dc_context to the link_enc_create callback. This is nee
drm/amd/display: Add dc_ctx to link_enc_create() parameters
[Why&How] Preparation to enable run time initialization of register offsets to add dc_context to the link_enc_create callback. This is needed to get the dc_ctx handle where register offset initialization routine is called.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
e4b0eac3 |
| 06-May-2022 |
Jasdeep Dhillon <jdhillon@amd.com> |
drm/amd/display: Move FPU associated DCN30 code to DML folder
[why & how] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU
drm/amd/display: Move FPU associated DCN30 code to DML folder
[why & how] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN30 to DML, where all FPU code should locate.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.15.32 |
|
#
0191d384 |
| 25-Mar-2022 |
Krunoslav Kovac <Krunoslav.Kovac@amd.com> |
drm/amd/display: Enable 3 plane for DCN 3.0 and 3.02
[WHY&HOW] Increase num of bottom planes to 2. Note that DCN 3.03 is left out since it has max 2 planes.
Tested-by: Daniel Wheeler <daniel.wheele
drm/amd/display: Enable 3 plane for DCN 3.0 and 3.02
[WHY&HOW] Increase num of bottom planes to 2. Note that DCN 3.03 is left out since it has max 2 planes.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20 |
|
#
68550cbc |
| 03-Feb-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move dpcs_3_0_0 headers from dcn to dpcs
To align with other headers.
Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
Revision tags: v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16 |
|
#
f369e4eb |
| 05-Jan-2022 |
Jasdeep Dhillon <jdhillon@amd.com> |
drm/amd/display: move FPU associated DCN302 code to DML folder (#2266)
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that
drm/amd/display: move FPU associated DCN302 code to DML folder (#2266)
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN302 to DML, where all FPU code should locate.
Co-authored-by: Jasdeep Dhillon <jdhillon@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.15.10, v5.15.9, v5.15.8 |
|
#
458c79a8 |
| 09-Dec-2021 |
Angus Wang <angus.wang@amd.com> |
drm/amd/display: Changed pipe split policy to allow for multi-display pipe split
[WHY] Current implementation of pipe split policy prevents pipe split with multiple displays connected, which caused
drm/amd/display: Changed pipe split policy to allow for multi-display pipe split
[WHY] Current implementation of pipe split policy prevents pipe split with multiple displays connected, which caused the MCLK speed to be stuck at max
[HOW] Changed the pipe split policies so that pipe split is allowed for multi-display configurations
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1522 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1709 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1655 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
ee2698cf |
| 09-Dec-2021 |
Angus Wang <angus.wang@amd.com> |
drm/amd/display: Changed pipe split policy to allow for multi-display pipe split
[WHY] Current implementation of pipe split policy prevents pipe split with multiple displays connected, which caused
drm/amd/display: Changed pipe split policy to allow for multi-display pipe split
[WHY] Current implementation of pipe split policy prevents pipe split with multiple displays connected, which caused the MCLK speed to be stuck at max
[HOW] Changed the pipe split policies so that pipe split is allowed for multi-display configurations
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1522 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1709 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1655 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403
Note this is a backport of this commit from amdgpu drm-next for 5.16.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
show more ...
|
Revision tags: v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2 |
|
#
ebe5ffd8 |
| 12-Nov-2021 |
Stylon Wang <stylon.wang@amd.com> |
drm/amd/display: Enable P010 for DCN3x ASICs
[Why + How] Enable P010 for SDR video applications.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawa
drm/amd/display: Enable P010 for DCN3x ASICs
[Why + How] Enable P010 for SDR video applications.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
2430be71 |
| 12-Nov-2021 |
Angus Wang <angus.wang@amd.com> |
drm/amd/display: Fix LTTPR not Enabled
[WHY] Previous LTTPR change has caused a regression that led to an issue where LTTPR is disabled
[HOW] Extended changes from previous fix to DCN30X
Reviewed-
drm/amd/display: Fix LTTPR not Enabled
[WHY] Previous LTTPR change has caused a regression that led to an issue where LTTPR is disabled
[HOW] Extended changes from previous fix to DCN30X
Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.15.1 |
|
#
fd3b2e21 |
| 03-Nov-2021 |
Angus Wang <angus.wang@amd.com> |
drm/amd/display: Revert changes for MPO underflow
[WHY] The previous changes for fixing MPO underflow with multiple display connected caused a regression where the machine runs into a hang when doin
drm/amd/display: Revert changes for MPO underflow
[WHY] The previous changes for fixing MPO underflow with multiple display connected caused a regression where the machine runs into a hang when doing multiple driver pnp with multiple displays connected
[HOW] Reverted offending change
Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
80c5f69b |
| 04-Nov-2021 |
Angus Wang <angus.wang@amd.com> |
drm/amd/display: Fix RGB MPO underflow with multiple displays
[WHY] With RGB MPO enabled, playing a video with multiple displays connected results in underflow when closing the video window
[HOW] R
drm/amd/display: Fix RGB MPO underflow with multiple displays
[WHY] With RGB MPO enabled, playing a video with multiple displays connected results in underflow when closing the video window
[HOW] Reverted the old change to fix this problem, which prevented pipe splits for multiple display configurations and caused high MCLK speeds during idle. Added a two step call to dc_update_planes_and_stream, first time with pipe split disabled and the second time with pipe split enabled, which fixed the underflow issue
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|