1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dcn10/dcn10_resource.h" 47 48 #include "dce/dce_abm.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_clock_source.h" 52 #include "dce/dce_hwseq.h" 53 #include "dce/dce_i2c_hw.h" 54 #include "dce/dce_panel_cntl.h" 55 #include "dce/dmub_abm.h" 56 57 #include "hw_sequencer_private.h" 58 #include "reg_helper.h" 59 #include "resource.h" 60 #include "vm_helper.h" 61 62 #include "dimgrey_cavefish_ip_offset.h" 63 #include "dcn/dcn_3_0_2_offset.h" 64 #include "dcn/dcn_3_0_2_sh_mask.h" 65 #include "dcn/dpcs_3_0_0_offset.h" 66 #include "dcn/dpcs_3_0_0_sh_mask.h" 67 #include "nbio/nbio_7_4_offset.h" 68 #include "amdgpu_socbb.h" 69 70 #define DC_LOGGER_INIT(logger) 71 72 struct _vcs_dpi_ip_params_st dcn3_02_ip = { 73 .use_min_dcfclk = 0, 74 .clamp_min_dcfclk = 0, 75 .odm_capable = 1, 76 .gpuvm_enable = 1, 77 .hostvm_enable = 0, 78 .gpuvm_max_page_table_levels = 4, 79 .hostvm_max_page_table_levels = 4, 80 .hostvm_cached_page_table_levels = 0, 81 .pte_group_size_bytes = 2048, 82 .num_dsc = 5, 83 .rob_buffer_size_kbytes = 184, 84 .det_buffer_size_kbytes = 184, 85 .dpte_buffer_size_in_pte_reqs_luma = 64, 86 .dpte_buffer_size_in_pte_reqs_chroma = 34, 87 .pde_proc_buffer_size_64k_reqs = 48, 88 .dpp_output_buffer_pixels = 2560, 89 .opp_output_buffer_lines = 1, 90 .pixel_chunk_size_kbytes = 8, 91 .pte_enable = 1, 92 .max_page_table_levels = 2, 93 .pte_chunk_size_kbytes = 2, // ? 94 .meta_chunk_size_kbytes = 2, 95 .writeback_chunk_size_kbytes = 8, 96 .line_buffer_size_bits = 789504, 97 .is_line_buffer_bpp_fixed = 0, // ? 98 .line_buffer_fixed_bpp = 0, // ? 99 .dcc_supported = true, 100 .writeback_interface_buffer_size_kbytes = 90, 101 .writeback_line_buffer_buffer_size = 0, 102 .max_line_buffer_lines = 12, 103 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 104 .writeback_chroma_buffer_size_kbytes = 8, 105 .writeback_chroma_line_buffer_width_pixels = 4, 106 .writeback_max_hscl_ratio = 1, 107 .writeback_max_vscl_ratio = 1, 108 .writeback_min_hscl_ratio = 1, 109 .writeback_min_vscl_ratio = 1, 110 .writeback_max_hscl_taps = 1, 111 .writeback_max_vscl_taps = 1, 112 .writeback_line_buffer_luma_buffer_size = 0, 113 .writeback_line_buffer_chroma_buffer_size = 14643, 114 .cursor_buffer_size = 8, 115 .cursor_chunk_size = 2, 116 .max_num_otg = 5, 117 .max_num_dpp = 5, 118 .max_num_wb = 1, 119 .max_dchub_pscl_bw_pix_per_clk = 4, 120 .max_pscl_lb_bw_pix_per_clk = 2, 121 .max_lb_vscl_bw_pix_per_clk = 4, 122 .max_vscl_hscl_bw_pix_per_clk = 4, 123 .max_hscl_ratio = 6, 124 .max_vscl_ratio = 6, 125 .hscl_mults = 4, 126 .vscl_mults = 4, 127 .max_hscl_taps = 8, 128 .max_vscl_taps = 8, 129 .dispclk_ramp_margin_percent = 1, 130 .underscan_factor = 1.11, 131 .min_vblank_lines = 32, 132 .dppclk_delay_subtotal = 46, 133 .dynamic_metadata_vm_enabled = true, 134 .dppclk_delay_scl_lb_only = 16, 135 .dppclk_delay_scl = 50, 136 .dppclk_delay_cnvc_formatter = 27, 137 .dppclk_delay_cnvc_cursor = 6, 138 .dispclk_delay_subtotal = 119, 139 .dcfclk_cstate_latency = 5.2, // SRExitTime 140 .max_inter_dcn_tile_repeaters = 8, 141 .max_num_hdmi_frl_outputs = 1, 142 .odm_combine_4to1_supported = true, 143 144 .xfc_supported = false, 145 .xfc_fill_bw_overhead_percent = 10.0, 146 .xfc_fill_constant_bytes = 0, 147 .gfx7_compat_tiling_supported = 0, 148 .number_of_cursors = 1, 149 }; 150 151 struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = { 152 .clock_limits = { 153 { 154 .state = 0, 155 .dispclk_mhz = 562.0, 156 .dppclk_mhz = 300.0, 157 .phyclk_mhz = 300.0, 158 .phyclk_d18_mhz = 667.0, 159 .dscclk_mhz = 405.6, 160 }, 161 }, 162 163 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 164 .num_states = 1, 165 .sr_exit_time_us = 5.20, 166 .sr_enter_plus_exit_time_us = 9.60, 167 .urgent_latency_us = 4.0, 168 .urgent_latency_pixel_data_only_us = 4.0, 169 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 170 .urgent_latency_vm_data_only_us = 4.0, 171 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 172 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 173 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 174 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 175 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 176 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 177 .max_avg_sdp_bw_use_normal_percent = 60.0, 178 .max_avg_dram_bw_use_normal_percent = 40.0, 179 .writeback_latency_us = 12.0, 180 .max_request_size_bytes = 256, 181 .fabric_datapath_to_dcn_data_return_bytes = 64, 182 .dcn_downspread_percent = 0.5, 183 .downspread_percent = 0.38, 184 .dram_page_open_time_ns = 50.0, 185 .dram_rw_turnaround_time_ns = 17.5, 186 .dram_return_buffer_per_channel_bytes = 8192, 187 .round_trip_ping_latency_dcfclk_cycles = 156, 188 .urgent_out_of_order_return_per_channel_bytes = 4096, 189 .channel_interleave_bytes = 256, 190 .num_banks = 8, 191 .gpuvm_min_page_size_bytes = 4096, 192 .hostvm_min_page_size_bytes = 4096, 193 .dram_clock_change_latency_us = 350, 194 .dummy_pstate_latency_us = 5, 195 .writeback_dram_clock_change_latency_us = 23.0, 196 .return_bus_width_bytes = 64, 197 .dispclk_dppclk_vco_speed_mhz = 3650, 198 .xfc_bus_transport_time_us = 20, // ? 199 .xfc_xbuf_latency_tolerance_us = 4, // ? 200 .use_urgent_burst_bw = 1, // ? 201 .do_urgent_latency_adjustment = true, 202 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 203 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 204 }; 205 206 static const struct dc_debug_options debug_defaults_drv = { 207 .disable_dmcu = true, 208 .force_abm_enable = false, 209 .timing_trace = false, 210 .clock_trace = true, 211 .disable_pplib_clock_request = true, 212 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 213 .force_single_disp_pipe_split = false, 214 .disable_dcc = DCC_ENABLE, 215 .vsr_support = true, 216 .performance_trace = false, 217 .max_downscale_src_width = 7680,/*upto 8K*/ 218 .disable_pplib_wm_range = false, 219 .scl_reset_length10 = true, 220 .sanity_checks = false, 221 .underflow_assert_delay_us = 0xFFFFFFFF, 222 .dwb_fi_phase = -1, // -1 = disable, 223 .dmub_command_table = true, 224 }; 225 226 static const struct dc_debug_options debug_defaults_diags = { 227 .disable_dmcu = true, 228 .force_abm_enable = false, 229 .timing_trace = true, 230 .clock_trace = true, 231 .disable_dpp_power_gate = true, 232 .disable_hubp_power_gate = true, 233 .disable_clock_gate = true, 234 .disable_pplib_clock_request = true, 235 .disable_pplib_wm_range = true, 236 .disable_stutter = false, 237 .scl_reset_length10 = true, 238 .dwb_fi_phase = -1, // -1 = disable 239 .dmub_command_table = true, 240 .enable_tri_buf = true, 241 }; 242 243 enum dcn302_clk_src_array_id { 244 DCN302_CLK_SRC_PLL0, 245 DCN302_CLK_SRC_PLL1, 246 DCN302_CLK_SRC_PLL2, 247 DCN302_CLK_SRC_PLL3, 248 DCN302_CLK_SRC_PLL4, 249 DCN302_CLK_SRC_TOTAL 250 }; 251 252 static const struct resource_caps res_cap_dcn302 = { 253 .num_timing_generator = 5, 254 .num_opp = 5, 255 .num_video_plane = 5, 256 .num_audio = 5, 257 .num_stream_encoder = 5, 258 .num_dwb = 1, 259 .num_ddc = 5, 260 .num_vmid = 16, 261 .num_mpc_3dlut = 2, 262 .num_dsc = 5, 263 }; 264 265 static const struct dc_plane_cap plane_cap = { 266 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 267 .blends_with_above = true, 268 .blends_with_below = true, 269 .per_pixel_alpha = true, 270 .pixel_format_support = { 271 .argb8888 = true, 272 .nv12 = true, 273 .fp16 = true, 274 .p010 = false, 275 .ayuv = false, 276 }, 277 .max_upscale_factor = { 278 .argb8888 = 16000, 279 .nv12 = 16000, 280 .fp16 = 16000 281 }, 282 .max_downscale_factor = { 283 .argb8888 = 600, 284 .nv12 = 600, 285 .fp16 = 600 286 }, 287 16, 288 16 289 }; 290 291 /* NBIO */ 292 #define NBIO_BASE_INNER(seg) \ 293 NBIO_BASE__INST0_SEG ## seg 294 295 #define NBIO_BASE(seg) \ 296 NBIO_BASE_INNER(seg) 297 298 #define NBIO_SR(reg_name)\ 299 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 300 mm ## reg_name 301 302 /* DCN */ 303 #undef BASE_INNER 304 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 305 306 #define BASE(seg) BASE_INNER(seg) 307 308 #define SR(reg_name)\ 309 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 310 311 #define SF(reg_name, field_name, post_fix)\ 312 .field_name = reg_name ## __ ## field_name ## post_fix 313 314 #define SRI(reg_name, block, id)\ 315 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 316 317 #define SRI2(reg_name, block, id)\ 318 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 319 320 #define SRII(reg_name, block, id)\ 321 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 322 mm ## block ## id ## _ ## reg_name 323 324 #define DCCG_SRII(reg_name, block, id)\ 325 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 326 mm ## block ## id ## _ ## reg_name 327 328 #define VUPDATE_SRII(reg_name, block, id)\ 329 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 330 mm ## reg_name ## _ ## block ## id 331 332 #define SRII_DWB(reg_name, temp_name, block, id)\ 333 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 334 mm ## block ## id ## _ ## temp_name 335 336 #define SRII_MPC_RMU(reg_name, block, id)\ 337 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 338 mm ## block ## id ## _ ## reg_name 339 340 static const struct dcn_hubbub_registers hubbub_reg = { 341 HUBBUB_REG_LIST_DCN30(0) 342 }; 343 344 static const struct dcn_hubbub_shift hubbub_shift = { 345 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 346 }; 347 348 static const struct dcn_hubbub_mask hubbub_mask = { 349 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 350 }; 351 352 #define vmid_regs(id)\ 353 [id] = { DCN20_VMID_REG_LIST(id) } 354 355 static const struct dcn_vmid_registers vmid_regs[] = { 356 vmid_regs(0), 357 vmid_regs(1), 358 vmid_regs(2), 359 vmid_regs(3), 360 vmid_regs(4), 361 vmid_regs(5), 362 vmid_regs(6), 363 vmid_regs(7), 364 vmid_regs(8), 365 vmid_regs(9), 366 vmid_regs(10), 367 vmid_regs(11), 368 vmid_regs(12), 369 vmid_regs(13), 370 vmid_regs(14), 371 vmid_regs(15) 372 }; 373 374 static const struct dcn20_vmid_shift vmid_shifts = { 375 DCN20_VMID_MASK_SH_LIST(__SHIFT) 376 }; 377 378 static const struct dcn20_vmid_mask vmid_masks = { 379 DCN20_VMID_MASK_SH_LIST(_MASK) 380 }; 381 382 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 383 { 384 int i; 385 386 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 387 388 if (!hubbub3) 389 return NULL; 390 391 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 392 393 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 394 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 395 396 vmid->ctx = ctx; 397 398 vmid->regs = &vmid_regs[i]; 399 vmid->shifts = &vmid_shifts; 400 vmid->masks = &vmid_masks; 401 } 402 403 return &hubbub3->base; 404 } 405 406 #define vpg_regs(id)\ 407 [id] = { VPG_DCN3_REG_LIST(id) } 408 409 static const struct dcn30_vpg_registers vpg_regs[] = { 410 vpg_regs(0), 411 vpg_regs(1), 412 vpg_regs(2), 413 vpg_regs(3), 414 vpg_regs(4), 415 vpg_regs(5) 416 }; 417 418 static const struct dcn30_vpg_shift vpg_shift = { 419 DCN3_VPG_MASK_SH_LIST(__SHIFT) 420 }; 421 422 static const struct dcn30_vpg_mask vpg_mask = { 423 DCN3_VPG_MASK_SH_LIST(_MASK) 424 }; 425 426 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 427 { 428 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 429 430 if (!vpg3) 431 return NULL; 432 433 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 434 435 return &vpg3->base; 436 } 437 438 #define afmt_regs(id)\ 439 [id] = { AFMT_DCN3_REG_LIST(id) } 440 441 static const struct dcn30_afmt_registers afmt_regs[] = { 442 afmt_regs(0), 443 afmt_regs(1), 444 afmt_regs(2), 445 afmt_regs(3), 446 afmt_regs(4), 447 afmt_regs(5) 448 }; 449 450 static const struct dcn30_afmt_shift afmt_shift = { 451 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 452 }; 453 454 static const struct dcn30_afmt_mask afmt_mask = { 455 DCN3_AFMT_MASK_SH_LIST(_MASK) 456 }; 457 458 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 459 { 460 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 461 462 if (!afmt3) 463 return NULL; 464 465 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 466 467 return &afmt3->base; 468 } 469 470 #define audio_regs(id)\ 471 [id] = { AUD_COMMON_REG_LIST(id) } 472 473 static const struct dce_audio_registers audio_regs[] = { 474 audio_regs(0), 475 audio_regs(1), 476 audio_regs(2), 477 audio_regs(3), 478 audio_regs(4), 479 audio_regs(5), 480 audio_regs(6) 481 }; 482 483 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 484 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 485 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 486 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 487 488 static const struct dce_audio_shift audio_shift = { 489 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 490 }; 491 492 static const struct dce_audio_mask audio_mask = { 493 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 494 }; 495 496 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 497 { 498 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 499 } 500 501 #define stream_enc_regs(id)\ 502 [id] = { SE_DCN3_REG_LIST(id) } 503 504 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 505 stream_enc_regs(0), 506 stream_enc_regs(1), 507 stream_enc_regs(2), 508 stream_enc_regs(3), 509 stream_enc_regs(4) 510 }; 511 512 static const struct dcn10_stream_encoder_shift se_shift = { 513 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 514 }; 515 516 static const struct dcn10_stream_encoder_mask se_mask = { 517 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 518 }; 519 520 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 521 { 522 struct dcn10_stream_encoder *enc1; 523 struct vpg *vpg; 524 struct afmt *afmt; 525 int vpg_inst; 526 int afmt_inst; 527 528 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 529 if (eng_id <= ENGINE_ID_DIGE) { 530 vpg_inst = eng_id; 531 afmt_inst = eng_id; 532 } else 533 return NULL; 534 535 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 536 vpg = dcn302_vpg_create(ctx, vpg_inst); 537 afmt = dcn302_afmt_create(ctx, afmt_inst); 538 539 if (!enc1 || !vpg || !afmt) 540 return NULL; 541 542 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 543 &se_shift, &se_mask); 544 545 return &enc1->base; 546 } 547 548 #define clk_src_regs(index, pllid)\ 549 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 550 551 static const struct dce110_clk_src_regs clk_src_regs[] = { 552 clk_src_regs(0, A), 553 clk_src_regs(1, B), 554 clk_src_regs(2, C), 555 clk_src_regs(3, D), 556 clk_src_regs(4, E) 557 }; 558 559 static const struct dce110_clk_src_shift cs_shift = { 560 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 561 }; 562 563 static const struct dce110_clk_src_mask cs_mask = { 564 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 565 }; 566 567 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 568 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 569 { 570 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 571 572 if (!clk_src) 573 return NULL; 574 575 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 576 clk_src->base.dp_clk_src = dp_clk_src; 577 return &clk_src->base; 578 } 579 580 BREAK_TO_DEBUGGER(); 581 return NULL; 582 } 583 584 static const struct dce_hwseq_registers hwseq_reg = { 585 HWSEQ_DCN302_REG_LIST() 586 }; 587 588 static const struct dce_hwseq_shift hwseq_shift = { 589 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 590 }; 591 592 static const struct dce_hwseq_mask hwseq_mask = { 593 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 594 }; 595 596 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 597 { 598 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 599 600 if (hws) { 601 hws->ctx = ctx; 602 hws->regs = &hwseq_reg; 603 hws->shifts = &hwseq_shift; 604 hws->masks = &hwseq_mask; 605 } 606 return hws; 607 } 608 609 #define hubp_regs(id)\ 610 [id] = { HUBP_REG_LIST_DCN30(id) } 611 612 static const struct dcn_hubp2_registers hubp_regs[] = { 613 hubp_regs(0), 614 hubp_regs(1), 615 hubp_regs(2), 616 hubp_regs(3), 617 hubp_regs(4) 618 }; 619 620 static const struct dcn_hubp2_shift hubp_shift = { 621 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 622 }; 623 624 static const struct dcn_hubp2_mask hubp_mask = { 625 HUBP_MASK_SH_LIST_DCN30(_MASK) 626 }; 627 628 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 629 { 630 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 631 632 if (!hubp2) 633 return NULL; 634 635 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 636 return &hubp2->base; 637 638 BREAK_TO_DEBUGGER(); 639 kfree(hubp2); 640 return NULL; 641 } 642 643 #define dpp_regs(id)\ 644 [id] = { DPP_REG_LIST_DCN30(id) } 645 646 static const struct dcn3_dpp_registers dpp_regs[] = { 647 dpp_regs(0), 648 dpp_regs(1), 649 dpp_regs(2), 650 dpp_regs(3), 651 dpp_regs(4) 652 }; 653 654 static const struct dcn3_dpp_shift tf_shift = { 655 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 656 }; 657 658 static const struct dcn3_dpp_mask tf_mask = { 659 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 660 }; 661 662 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 663 { 664 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 665 666 if (!dpp) 667 return NULL; 668 669 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 670 return &dpp->base; 671 672 BREAK_TO_DEBUGGER(); 673 kfree(dpp); 674 return NULL; 675 } 676 677 #define opp_regs(id)\ 678 [id] = { OPP_REG_LIST_DCN30(id) } 679 680 static const struct dcn20_opp_registers opp_regs[] = { 681 opp_regs(0), 682 opp_regs(1), 683 opp_regs(2), 684 opp_regs(3), 685 opp_regs(4) 686 }; 687 688 static const struct dcn20_opp_shift opp_shift = { 689 OPP_MASK_SH_LIST_DCN20(__SHIFT) 690 }; 691 692 static const struct dcn20_opp_mask opp_mask = { 693 OPP_MASK_SH_LIST_DCN20(_MASK) 694 }; 695 696 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 697 { 698 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 699 700 if (!opp) { 701 BREAK_TO_DEBUGGER(); 702 return NULL; 703 } 704 705 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 706 return &opp->base; 707 } 708 709 #define optc_regs(id)\ 710 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 711 712 static const struct dcn_optc_registers optc_regs[] = { 713 optc_regs(0), 714 optc_regs(1), 715 optc_regs(2), 716 optc_regs(3), 717 optc_regs(4) 718 }; 719 720 static const struct dcn_optc_shift optc_shift = { 721 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 722 }; 723 724 static const struct dcn_optc_mask optc_mask = { 725 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 726 }; 727 728 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 729 { 730 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 731 732 if (!tgn10) 733 return NULL; 734 735 tgn10->base.inst = instance; 736 tgn10->base.ctx = ctx; 737 738 tgn10->tg_regs = &optc_regs[instance]; 739 tgn10->tg_shift = &optc_shift; 740 tgn10->tg_mask = &optc_mask; 741 742 dcn30_timing_generator_init(tgn10); 743 744 return &tgn10->base; 745 } 746 747 static const struct dcn30_mpc_registers mpc_regs = { 748 MPC_REG_LIST_DCN3_0(0), 749 MPC_REG_LIST_DCN3_0(1), 750 MPC_REG_LIST_DCN3_0(2), 751 MPC_REG_LIST_DCN3_0(3), 752 MPC_REG_LIST_DCN3_0(4), 753 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 754 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 755 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 756 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 757 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 758 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 759 MPC_RMU_REG_LIST_DCN3AG(0), 760 MPC_RMU_REG_LIST_DCN3AG(1), 761 MPC_RMU_REG_LIST_DCN3AG(2), 762 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 763 }; 764 765 static const struct dcn30_mpc_shift mpc_shift = { 766 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 767 }; 768 769 static const struct dcn30_mpc_mask mpc_mask = { 770 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 771 }; 772 773 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 774 { 775 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 776 777 if (!mpc30) 778 return NULL; 779 780 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 781 782 return &mpc30->base; 783 } 784 785 #define dsc_regsDCN20(id)\ 786 [id] = { DSC_REG_LIST_DCN20(id) } 787 788 static const struct dcn20_dsc_registers dsc_regs[] = { 789 dsc_regsDCN20(0), 790 dsc_regsDCN20(1), 791 dsc_regsDCN20(2), 792 dsc_regsDCN20(3), 793 dsc_regsDCN20(4) 794 }; 795 796 static const struct dcn20_dsc_shift dsc_shift = { 797 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 798 }; 799 800 static const struct dcn20_dsc_mask dsc_mask = { 801 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 802 }; 803 804 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 805 { 806 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 807 808 if (!dsc) { 809 BREAK_TO_DEBUGGER(); 810 return NULL; 811 } 812 813 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 814 return &dsc->base; 815 } 816 817 #define dwbc_regs_dcn3(id)\ 818 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 819 820 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 821 dwbc_regs_dcn3(0) 822 }; 823 824 static const struct dcn30_dwbc_shift dwbc30_shift = { 825 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 826 }; 827 828 static const struct dcn30_dwbc_mask dwbc30_mask = { 829 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 830 }; 831 832 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 833 { 834 int i; 835 uint32_t pipe_count = pool->res_cap->num_dwb; 836 837 for (i = 0; i < pipe_count; i++) { 838 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 839 840 if (!dwbc30) { 841 dm_error("DC: failed to create dwbc30!\n"); 842 return false; 843 } 844 845 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 846 847 pool->dwbc[i] = &dwbc30->base; 848 } 849 return true; 850 } 851 852 #define mcif_wb_regs_dcn3(id)\ 853 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 854 855 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 856 mcif_wb_regs_dcn3(0) 857 }; 858 859 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 860 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 861 }; 862 863 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 864 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 865 }; 866 867 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 868 { 869 int i; 870 uint32_t pipe_count = pool->res_cap->num_dwb; 871 872 for (i = 0; i < pipe_count; i++) { 873 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 874 875 if (!mcif_wb30) { 876 dm_error("DC: failed to create mcif_wb30!\n"); 877 return false; 878 } 879 880 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 881 882 pool->mcif_wb[i] = &mcif_wb30->base; 883 } 884 return true; 885 } 886 887 #define aux_engine_regs(id)\ 888 [id] = {\ 889 AUX_COMMON_REG_LIST0(id), \ 890 .AUXN_IMPCAL = 0, \ 891 .AUXP_IMPCAL = 0, \ 892 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 893 } 894 895 static const struct dce110_aux_registers aux_engine_regs[] = { 896 aux_engine_regs(0), 897 aux_engine_regs(1), 898 aux_engine_regs(2), 899 aux_engine_regs(3), 900 aux_engine_regs(4) 901 }; 902 903 static const struct dce110_aux_registers_shift aux_shift = { 904 DCN_AUX_MASK_SH_LIST(__SHIFT) 905 }; 906 907 static const struct dce110_aux_registers_mask aux_mask = { 908 DCN_AUX_MASK_SH_LIST(_MASK) 909 }; 910 911 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 912 { 913 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 914 915 if (!aux_engine) 916 return NULL; 917 918 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 919 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 920 921 return &aux_engine->base; 922 } 923 924 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 925 926 static const struct dce_i2c_registers i2c_hw_regs[] = { 927 i2c_inst_regs(1), 928 i2c_inst_regs(2), 929 i2c_inst_regs(3), 930 i2c_inst_regs(4), 931 i2c_inst_regs(5) 932 }; 933 934 static const struct dce_i2c_shift i2c_shifts = { 935 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 936 }; 937 938 static const struct dce_i2c_mask i2c_masks = { 939 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 940 }; 941 942 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 943 { 944 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 945 946 if (!dce_i2c_hw) 947 return NULL; 948 949 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 950 951 return dce_i2c_hw; 952 } 953 954 static const struct encoder_feature_support link_enc_feature = { 955 .max_hdmi_deep_color = COLOR_DEPTH_121212, 956 .max_hdmi_pixel_clock = 600000, 957 .hdmi_ycbcr420_supported = true, 958 .dp_ycbcr420_supported = true, 959 .fec_supported = true, 960 .flags.bits.IS_HBR2_CAPABLE = true, 961 .flags.bits.IS_HBR3_CAPABLE = true, 962 .flags.bits.IS_TPS3_CAPABLE = true, 963 .flags.bits.IS_TPS4_CAPABLE = true 964 }; 965 966 #define link_regs(id, phyid)\ 967 [id] = {\ 968 LE_DCN3_REG_LIST(id), \ 969 UNIPHY_DCN2_REG_LIST(phyid), \ 970 DPCS_DCN2_REG_LIST(id), \ 971 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 972 } 973 974 static const struct dcn10_link_enc_registers link_enc_regs[] = { 975 link_regs(0, A), 976 link_regs(1, B), 977 link_regs(2, C), 978 link_regs(3, D), 979 link_regs(4, E) 980 }; 981 982 static const struct dcn10_link_enc_shift le_shift = { 983 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 984 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 985 }; 986 987 static const struct dcn10_link_enc_mask le_mask = { 988 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 989 DPCS_DCN2_MASK_SH_LIST(_MASK) 990 }; 991 992 #define aux_regs(id)\ 993 [id] = { DCN2_AUX_REG_LIST(id) } 994 995 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 996 aux_regs(0), 997 aux_regs(1), 998 aux_regs(2), 999 aux_regs(3), 1000 aux_regs(4) 1001 }; 1002 1003 #define hpd_regs(id)\ 1004 [id] = { HPD_REG_LIST(id) } 1005 1006 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1007 hpd_regs(0), 1008 hpd_regs(1), 1009 hpd_regs(2), 1010 hpd_regs(3), 1011 hpd_regs(4) 1012 }; 1013 1014 static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data) 1015 { 1016 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1017 1018 if (!enc20) 1019 return NULL; 1020 1021 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 1022 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 1023 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 1024 1025 return &enc20->enc10.base; 1026 } 1027 1028 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1029 { DCN_PANEL_CNTL_REG_LIST() } 1030 }; 1031 1032 static const struct dce_panel_cntl_shift panel_cntl_shift = { 1033 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1034 }; 1035 1036 static const struct dce_panel_cntl_mask panel_cntl_mask = { 1037 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1038 }; 1039 1040 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1041 { 1042 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1043 1044 if (!panel_cntl) 1045 return NULL; 1046 1047 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 1048 &panel_cntl_shift, &panel_cntl_mask); 1049 1050 return &panel_cntl->base; 1051 } 1052 1053 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 1054 { 1055 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1056 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1057 } 1058 1059 static const struct resource_create_funcs res_create_funcs = { 1060 .read_dce_straps = read_dce_straps, 1061 .create_audio = dcn302_create_audio, 1062 .create_stream_encoder = dcn302_stream_encoder_create, 1063 .create_hwseq = dcn302_hwseq_create, 1064 }; 1065 1066 static const struct resource_create_funcs res_create_maximus_funcs = { 1067 .read_dce_straps = NULL, 1068 .create_audio = NULL, 1069 .create_stream_encoder = NULL, 1070 .create_hwseq = dcn302_hwseq_create, 1071 }; 1072 1073 static bool is_soc_bounding_box_valid(struct dc *dc) 1074 { 1075 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1076 1077 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 1078 return true; 1079 1080 return false; 1081 } 1082 1083 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 1084 { 1085 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 1086 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 1087 1088 DC_LOGGER_INIT(dc->ctx->logger); 1089 1090 if (!is_soc_bounding_box_valid(dc)) { 1091 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1092 return false; 1093 } 1094 1095 loaded_ip->max_num_otg = pool->pipe_count; 1096 loaded_ip->max_num_dpp = pool->pipe_count; 1097 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1098 dcn20_patch_bounding_box(dc, loaded_bb); 1099 return true; 1100 } 1101 1102 static void dcn302_resource_destruct(struct resource_pool *pool) 1103 { 1104 unsigned int i; 1105 1106 for (i = 0; i < pool->stream_enc_count; i++) { 1107 if (pool->stream_enc[i] != NULL) { 1108 if (pool->stream_enc[i]->vpg != NULL) { 1109 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1110 pool->stream_enc[i]->vpg = NULL; 1111 } 1112 if (pool->stream_enc[i]->afmt != NULL) { 1113 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1114 pool->stream_enc[i]->afmt = NULL; 1115 } 1116 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1117 pool->stream_enc[i] = NULL; 1118 } 1119 } 1120 1121 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1122 if (pool->dscs[i] != NULL) 1123 dcn20_dsc_destroy(&pool->dscs[i]); 1124 } 1125 1126 if (pool->mpc != NULL) { 1127 kfree(TO_DCN20_MPC(pool->mpc)); 1128 pool->mpc = NULL; 1129 } 1130 1131 if (pool->hubbub != NULL) { 1132 kfree(pool->hubbub); 1133 pool->hubbub = NULL; 1134 } 1135 1136 for (i = 0; i < pool->pipe_count; i++) { 1137 if (pool->dpps[i] != NULL) { 1138 kfree(TO_DCN20_DPP(pool->dpps[i])); 1139 pool->dpps[i] = NULL; 1140 } 1141 1142 if (pool->hubps[i] != NULL) { 1143 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1144 pool->hubps[i] = NULL; 1145 } 1146 1147 if (pool->irqs != NULL) 1148 dal_irq_service_destroy(&pool->irqs); 1149 } 1150 1151 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1152 if (pool->engines[i] != NULL) 1153 dce110_engine_destroy(&pool->engines[i]); 1154 if (pool->hw_i2cs[i] != NULL) { 1155 kfree(pool->hw_i2cs[i]); 1156 pool->hw_i2cs[i] = NULL; 1157 } 1158 if (pool->sw_i2cs[i] != NULL) { 1159 kfree(pool->sw_i2cs[i]); 1160 pool->sw_i2cs[i] = NULL; 1161 } 1162 } 1163 1164 for (i = 0; i < pool->res_cap->num_opp; i++) { 1165 if (pool->opps[i] != NULL) 1166 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1167 } 1168 1169 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1170 if (pool->timing_generators[i] != NULL) { 1171 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1172 pool->timing_generators[i] = NULL; 1173 } 1174 } 1175 1176 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1177 if (pool->dwbc[i] != NULL) { 1178 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1179 pool->dwbc[i] = NULL; 1180 } 1181 if (pool->mcif_wb[i] != NULL) { 1182 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1183 pool->mcif_wb[i] = NULL; 1184 } 1185 } 1186 1187 for (i = 0; i < pool->audio_count; i++) { 1188 if (pool->audios[i]) 1189 dce_aud_destroy(&pool->audios[i]); 1190 } 1191 1192 for (i = 0; i < pool->clk_src_count; i++) { 1193 if (pool->clock_sources[i] != NULL) 1194 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1195 } 1196 1197 if (pool->dp_clock_source != NULL) 1198 dcn20_clock_source_destroy(&pool->dp_clock_source); 1199 1200 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1201 if (pool->mpc_lut[i] != NULL) { 1202 dc_3dlut_func_release(pool->mpc_lut[i]); 1203 pool->mpc_lut[i] = NULL; 1204 } 1205 if (pool->mpc_shaper[i] != NULL) { 1206 dc_transfer_func_release(pool->mpc_shaper[i]); 1207 pool->mpc_shaper[i] = NULL; 1208 } 1209 } 1210 1211 for (i = 0; i < pool->pipe_count; i++) { 1212 if (pool->multiple_abms[i] != NULL) 1213 dce_abm_destroy(&pool->multiple_abms[i]); 1214 } 1215 1216 if (pool->dccg != NULL) 1217 dcn_dccg_destroy(&pool->dccg); 1218 } 1219 1220 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1221 { 1222 dcn302_resource_destruct(*pool); 1223 kfree(*pool); 1224 *pool = NULL; 1225 } 1226 1227 static struct resource_funcs dcn302_res_pool_funcs = { 1228 .destroy = dcn302_destroy_resource_pool, 1229 .link_enc_create = dcn302_link_encoder_create, 1230 .panel_cntl_create = dcn302_panel_cntl_create, 1231 .validate_bandwidth = dcn30_validate_bandwidth, 1232 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1233 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1234 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1235 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1236 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1237 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1238 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1239 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1240 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1241 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1242 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1243 .update_bw_bounding_box = dcn30_update_bw_bounding_box, 1244 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1245 }; 1246 1247 static struct dc_cap_funcs cap_funcs = { 1248 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1249 }; 1250 1251 static const struct bios_registers bios_regs = { 1252 NBIO_SR(BIOS_SCRATCH_3), 1253 NBIO_SR(BIOS_SCRATCH_6) 1254 }; 1255 1256 static const struct dccg_registers dccg_regs = { 1257 DCCG_REG_LIST_DCN3_02() 1258 }; 1259 1260 static const struct dccg_shift dccg_shift = { 1261 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1262 }; 1263 1264 static const struct dccg_mask dccg_mask = { 1265 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1266 }; 1267 1268 #define abm_regs(id)\ 1269 [id] = { ABM_DCN301_REG_LIST(id) } 1270 1271 static const struct dce_abm_registers abm_regs[] = { 1272 abm_regs(0), 1273 abm_regs(1), 1274 abm_regs(2), 1275 abm_regs(3), 1276 abm_regs(4) 1277 }; 1278 1279 static const struct dce_abm_shift abm_shift = { 1280 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1281 }; 1282 1283 static const struct dce_abm_mask abm_mask = { 1284 ABM_MASK_SH_LIST_DCN30(_MASK) 1285 }; 1286 1287 static bool dcn302_resource_construct( 1288 uint8_t num_virtual_links, 1289 struct dc *dc, 1290 struct resource_pool *pool) 1291 { 1292 int i; 1293 struct dc_context *ctx = dc->ctx; 1294 struct irq_service_init_data init_data; 1295 1296 ctx->dc_bios->regs = &bios_regs; 1297 1298 pool->res_cap = &res_cap_dcn302; 1299 1300 pool->funcs = &dcn302_res_pool_funcs; 1301 1302 /************************************************* 1303 * Resource + asic cap harcoding * 1304 *************************************************/ 1305 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1306 pool->pipe_count = pool->res_cap->num_timing_generator; 1307 pool->mpcc_count = pool->res_cap->num_timing_generator; 1308 dc->caps.max_downscale_ratio = 600; 1309 dc->caps.i2c_speed_in_khz = 100; 1310 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1311 dc->caps.max_cursor_size = 256; 1312 dc->caps.min_horizontal_blanking_period = 80; 1313 dc->caps.dmdata_alloc_size = 2048; 1314 1315 dc->caps.max_slave_planes = 1; 1316 dc->caps.post_blend_color_processing = true; 1317 dc->caps.force_dp_tps4_for_cp2520 = true; 1318 dc->caps.extended_aux_timeout_support = true; 1319 dc->caps.dmcub_support = true; 1320 1321 /* Color pipeline capabilities */ 1322 dc->caps.color.dpp.dcn_arch = 1; 1323 dc->caps.color.dpp.input_lut_shared = 0; 1324 dc->caps.color.dpp.icsc = 1; 1325 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1326 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1327 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1328 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1329 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1330 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1331 dc->caps.color.dpp.post_csc = 1; 1332 dc->caps.color.dpp.gamma_corr = 1; 1333 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1334 1335 dc->caps.color.dpp.hw_3d_lut = 1; 1336 dc->caps.color.dpp.ogam_ram = 1; 1337 // no OGAM ROM on DCN3 1338 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1339 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1340 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1341 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1342 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1343 dc->caps.color.dpp.ocsc = 0; 1344 1345 dc->caps.color.mpc.gamut_remap = 1; 1346 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1347 dc->caps.color.mpc.ogam_ram = 1; 1348 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1349 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1350 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1351 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1352 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1353 dc->caps.color.mpc.ocsc = 1; 1354 1355 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1356 dc->debug = debug_defaults_drv; 1357 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) 1358 dc->debug = debug_defaults_diags; 1359 else 1360 dc->debug = debug_defaults_diags; 1361 1362 // Init the vm_helper 1363 if (dc->vm_helper) 1364 vm_helper_init(dc->vm_helper, 16); 1365 1366 /************************************************* 1367 * Create resources * 1368 *************************************************/ 1369 1370 /* Clock Sources for Pixel Clock*/ 1371 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1372 dcn302_clock_source_create(ctx, ctx->dc_bios, 1373 CLOCK_SOURCE_COMBO_PHY_PLL0, 1374 &clk_src_regs[0], false); 1375 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1376 dcn302_clock_source_create(ctx, ctx->dc_bios, 1377 CLOCK_SOURCE_COMBO_PHY_PLL1, 1378 &clk_src_regs[1], false); 1379 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1380 dcn302_clock_source_create(ctx, ctx->dc_bios, 1381 CLOCK_SOURCE_COMBO_PHY_PLL2, 1382 &clk_src_regs[2], false); 1383 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1384 dcn302_clock_source_create(ctx, ctx->dc_bios, 1385 CLOCK_SOURCE_COMBO_PHY_PLL3, 1386 &clk_src_regs[3], false); 1387 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1388 dcn302_clock_source_create(ctx, ctx->dc_bios, 1389 CLOCK_SOURCE_COMBO_PHY_PLL4, 1390 &clk_src_regs[4], false); 1391 1392 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1393 1394 /* todo: not reuse phy_pll registers */ 1395 pool->dp_clock_source = 1396 dcn302_clock_source_create(ctx, ctx->dc_bios, 1397 CLOCK_SOURCE_ID_DP_DTO, 1398 &clk_src_regs[0], true); 1399 1400 for (i = 0; i < pool->clk_src_count; i++) { 1401 if (pool->clock_sources[i] == NULL) { 1402 dm_error("DC: failed to create clock sources!\n"); 1403 BREAK_TO_DEBUGGER(); 1404 goto create_fail; 1405 } 1406 } 1407 1408 /* DCCG */ 1409 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1410 if (pool->dccg == NULL) { 1411 dm_error("DC: failed to create dccg!\n"); 1412 BREAK_TO_DEBUGGER(); 1413 goto create_fail; 1414 } 1415 1416 /* PP Lib and SMU interfaces */ 1417 init_soc_bounding_box(dc, pool); 1418 1419 /* DML */ 1420 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1421 1422 /* IRQ */ 1423 init_data.ctx = dc->ctx; 1424 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1425 if (!pool->irqs) 1426 goto create_fail; 1427 1428 /* HUBBUB */ 1429 pool->hubbub = dcn302_hubbub_create(ctx); 1430 if (pool->hubbub == NULL) { 1431 BREAK_TO_DEBUGGER(); 1432 dm_error("DC: failed to create hubbub!\n"); 1433 goto create_fail; 1434 } 1435 1436 /* HUBPs, DPPs, OPPs and TGs */ 1437 for (i = 0; i < pool->pipe_count; i++) { 1438 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1439 if (pool->hubps[i] == NULL) { 1440 BREAK_TO_DEBUGGER(); 1441 dm_error("DC: failed to create hubps!\n"); 1442 goto create_fail; 1443 } 1444 1445 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1446 if (pool->dpps[i] == NULL) { 1447 BREAK_TO_DEBUGGER(); 1448 dm_error("DC: failed to create dpps!\n"); 1449 goto create_fail; 1450 } 1451 } 1452 1453 for (i = 0; i < pool->res_cap->num_opp; i++) { 1454 pool->opps[i] = dcn302_opp_create(ctx, i); 1455 if (pool->opps[i] == NULL) { 1456 BREAK_TO_DEBUGGER(); 1457 dm_error("DC: failed to create output pixel processor!\n"); 1458 goto create_fail; 1459 } 1460 } 1461 1462 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1463 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1464 if (pool->timing_generators[i] == NULL) { 1465 BREAK_TO_DEBUGGER(); 1466 dm_error("DC: failed to create tg!\n"); 1467 goto create_fail; 1468 } 1469 } 1470 pool->timing_generator_count = i; 1471 1472 /* ABMs */ 1473 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1474 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1475 if (pool->multiple_abms[i] == NULL) { 1476 dm_error("DC: failed to create abm for pipe %d!\n", i); 1477 BREAK_TO_DEBUGGER(); 1478 goto create_fail; 1479 } 1480 } 1481 1482 /* MPC and DSC */ 1483 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1484 if (pool->mpc == NULL) { 1485 BREAK_TO_DEBUGGER(); 1486 dm_error("DC: failed to create mpc!\n"); 1487 goto create_fail; 1488 } 1489 1490 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1491 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1492 if (pool->dscs[i] == NULL) { 1493 BREAK_TO_DEBUGGER(); 1494 dm_error("DC: failed to create display stream compressor %d!\n", i); 1495 goto create_fail; 1496 } 1497 } 1498 1499 /* DWB and MMHUBBUB */ 1500 if (!dcn302_dwbc_create(ctx, pool)) { 1501 BREAK_TO_DEBUGGER(); 1502 dm_error("DC: failed to create dwbc!\n"); 1503 goto create_fail; 1504 } 1505 1506 if (!dcn302_mmhubbub_create(ctx, pool)) { 1507 BREAK_TO_DEBUGGER(); 1508 dm_error("DC: failed to create mcif_wb!\n"); 1509 goto create_fail; 1510 } 1511 1512 /* AUX and I2C */ 1513 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1514 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1515 if (pool->engines[i] == NULL) { 1516 BREAK_TO_DEBUGGER(); 1517 dm_error("DC:failed to create aux engine!!\n"); 1518 goto create_fail; 1519 } 1520 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1521 if (pool->hw_i2cs[i] == NULL) { 1522 BREAK_TO_DEBUGGER(); 1523 dm_error("DC:failed to create hw i2c!!\n"); 1524 goto create_fail; 1525 } 1526 pool->sw_i2cs[i] = NULL; 1527 } 1528 1529 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1530 if (!resource_construct(num_virtual_links, dc, pool, 1531 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1532 &res_create_funcs : &res_create_maximus_funcs))) 1533 goto create_fail; 1534 1535 /* HW Sequencer and Plane caps */ 1536 dcn302_hw_sequencer_construct(dc); 1537 1538 dc->caps.max_planes = pool->pipe_count; 1539 1540 for (i = 0; i < dc->caps.max_planes; ++i) 1541 dc->caps.planes[i] = plane_cap; 1542 1543 dc->cap_funcs = cap_funcs; 1544 1545 return true; 1546 1547 create_fail: 1548 1549 dcn302_resource_destruct(pool); 1550 1551 return false; 1552 } 1553 1554 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1555 { 1556 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1557 1558 if (!pool) 1559 return NULL; 1560 1561 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1562 return pool; 1563 1564 BREAK_TO_DEBUGGER(); 1565 kfree(pool); 1566 return NULL; 1567 } 1568