1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dml/dcn30/dcn30_fpu.h" 47 48 #include "dcn10/dcn10_resource.h" 49 50 #include "link.h" 51 #include "dce/dce_abm.h" 52 #include "dce/dce_audio.h" 53 #include "dce/dce_aux.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_hwseq.h" 56 #include "dce/dce_i2c_hw.h" 57 #include "dce/dce_panel_cntl.h" 58 #include "dce/dmub_abm.h" 59 #include "dce/dmub_psr.h" 60 #include "clk_mgr.h" 61 62 #include "hw_sequencer_private.h" 63 #include "reg_helper.h" 64 #include "resource.h" 65 #include "vm_helper.h" 66 67 #include "dml/dcn302/dcn302_fpu.h" 68 69 #include "dimgrey_cavefish_ip_offset.h" 70 #include "dcn/dcn_3_0_2_offset.h" 71 #include "dcn/dcn_3_0_2_sh_mask.h" 72 #include "dpcs/dpcs_3_0_0_offset.h" 73 #include "dpcs/dpcs_3_0_0_sh_mask.h" 74 #include "nbio/nbio_7_4_offset.h" 75 #include "amdgpu_socbb.h" 76 77 #define DC_LOGGER_INIT(logger) 78 79 static const struct dc_debug_options debug_defaults_drv = { 80 .disable_dmcu = true, 81 .force_abm_enable = false, 82 .timing_trace = false, 83 .clock_trace = true, 84 .disable_pplib_clock_request = true, 85 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 86 .force_single_disp_pipe_split = false, 87 .disable_dcc = DCC_ENABLE, 88 .vsr_support = true, 89 .performance_trace = false, 90 .max_downscale_src_width = 7680,/*upto 8K*/ 91 .disable_pplib_wm_range = false, 92 .scl_reset_length10 = true, 93 .sanity_checks = false, 94 .underflow_assert_delay_us = 0xFFFFFFFF, 95 .dwb_fi_phase = -1, // -1 = disable, 96 .dmub_command_table = true, 97 .use_max_lb = true, 98 .exit_idle_opt_for_cursor_updates = true 99 }; 100 101 static const struct dc_panel_config panel_config_defaults = { 102 .psr = { 103 .disable_psr = false, 104 .disallow_psrsu = false, 105 }, 106 }; 107 108 enum dcn302_clk_src_array_id { 109 DCN302_CLK_SRC_PLL0, 110 DCN302_CLK_SRC_PLL1, 111 DCN302_CLK_SRC_PLL2, 112 DCN302_CLK_SRC_PLL3, 113 DCN302_CLK_SRC_PLL4, 114 DCN302_CLK_SRC_TOTAL 115 }; 116 117 static const struct resource_caps res_cap_dcn302 = { 118 .num_timing_generator = 5, 119 .num_opp = 5, 120 .num_video_plane = 5, 121 .num_audio = 5, 122 .num_stream_encoder = 5, 123 .num_dwb = 1, 124 .num_ddc = 5, 125 .num_vmid = 16, 126 .num_mpc_3dlut = 2, 127 .num_dsc = 5, 128 }; 129 130 static const struct dc_plane_cap plane_cap = { 131 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 132 .per_pixel_alpha = true, 133 .pixel_format_support = { 134 .argb8888 = true, 135 .nv12 = true, 136 .fp16 = true, 137 .p010 = true, 138 .ayuv = false, 139 }, 140 .max_upscale_factor = { 141 .argb8888 = 16000, 142 .nv12 = 16000, 143 .fp16 = 16000 144 }, 145 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 146 .max_downscale_factor = { 147 .argb8888 = 167, 148 .nv12 = 167, 149 .fp16 = 167 150 }, 151 16, 152 16 153 }; 154 155 /* NBIO */ 156 #define NBIO_BASE_INNER(seg) \ 157 NBIO_BASE__INST0_SEG ## seg 158 159 #define NBIO_BASE(seg) \ 160 NBIO_BASE_INNER(seg) 161 162 #define NBIO_SR(reg_name)\ 163 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 164 mm ## reg_name 165 166 /* DCN */ 167 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 168 169 #define BASE(seg) BASE_INNER(seg) 170 171 #define SR(reg_name)\ 172 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 173 174 #define SF(reg_name, field_name, post_fix)\ 175 .field_name = reg_name ## __ ## field_name ## post_fix 176 177 #define SRI(reg_name, block, id)\ 178 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 179 180 #define SRI2(reg_name, block, id)\ 181 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 182 183 #define SRII(reg_name, block, id)\ 184 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 185 mm ## block ## id ## _ ## reg_name 186 187 #define DCCG_SRII(reg_name, block, id)\ 188 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 189 mm ## block ## id ## _ ## reg_name 190 191 #define VUPDATE_SRII(reg_name, block, id)\ 192 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 193 mm ## reg_name ## _ ## block ## id 194 195 #define SRII_DWB(reg_name, temp_name, block, id)\ 196 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 197 mm ## block ## id ## _ ## temp_name 198 199 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 200 .field_name = reg_name ## __ ## field_name ## post_fix 201 202 #define SRII_MPC_RMU(reg_name, block, id)\ 203 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 204 mm ## block ## id ## _ ## reg_name 205 206 static const struct dcn_hubbub_registers hubbub_reg = { 207 HUBBUB_REG_LIST_DCN30(0) 208 }; 209 210 static const struct dcn_hubbub_shift hubbub_shift = { 211 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 212 }; 213 214 static const struct dcn_hubbub_mask hubbub_mask = { 215 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 216 }; 217 218 #define vmid_regs(id)\ 219 [id] = { DCN20_VMID_REG_LIST(id) } 220 221 static const struct dcn_vmid_registers vmid_regs[] = { 222 vmid_regs(0), 223 vmid_regs(1), 224 vmid_regs(2), 225 vmid_regs(3), 226 vmid_regs(4), 227 vmid_regs(5), 228 vmid_regs(6), 229 vmid_regs(7), 230 vmid_regs(8), 231 vmid_regs(9), 232 vmid_regs(10), 233 vmid_regs(11), 234 vmid_regs(12), 235 vmid_regs(13), 236 vmid_regs(14), 237 vmid_regs(15) 238 }; 239 240 static const struct dcn20_vmid_shift vmid_shifts = { 241 DCN20_VMID_MASK_SH_LIST(__SHIFT) 242 }; 243 244 static const struct dcn20_vmid_mask vmid_masks = { 245 DCN20_VMID_MASK_SH_LIST(_MASK) 246 }; 247 248 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 249 { 250 int i; 251 252 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 253 254 if (!hubbub3) 255 return NULL; 256 257 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 258 259 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 260 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 261 262 vmid->ctx = ctx; 263 264 vmid->regs = &vmid_regs[i]; 265 vmid->shifts = &vmid_shifts; 266 vmid->masks = &vmid_masks; 267 } 268 269 return &hubbub3->base; 270 } 271 272 #define vpg_regs(id)\ 273 [id] = { VPG_DCN3_REG_LIST(id) } 274 275 static const struct dcn30_vpg_registers vpg_regs[] = { 276 vpg_regs(0), 277 vpg_regs(1), 278 vpg_regs(2), 279 vpg_regs(3), 280 vpg_regs(4), 281 vpg_regs(5) 282 }; 283 284 static const struct dcn30_vpg_shift vpg_shift = { 285 DCN3_VPG_MASK_SH_LIST(__SHIFT) 286 }; 287 288 static const struct dcn30_vpg_mask vpg_mask = { 289 DCN3_VPG_MASK_SH_LIST(_MASK) 290 }; 291 292 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 293 { 294 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 295 296 if (!vpg3) 297 return NULL; 298 299 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 300 301 return &vpg3->base; 302 } 303 304 #define afmt_regs(id)\ 305 [id] = { AFMT_DCN3_REG_LIST(id) } 306 307 static const struct dcn30_afmt_registers afmt_regs[] = { 308 afmt_regs(0), 309 afmt_regs(1), 310 afmt_regs(2), 311 afmt_regs(3), 312 afmt_regs(4), 313 afmt_regs(5) 314 }; 315 316 static const struct dcn30_afmt_shift afmt_shift = { 317 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 318 }; 319 320 static const struct dcn30_afmt_mask afmt_mask = { 321 DCN3_AFMT_MASK_SH_LIST(_MASK) 322 }; 323 324 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 325 { 326 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 327 328 if (!afmt3) 329 return NULL; 330 331 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 332 333 return &afmt3->base; 334 } 335 336 #define audio_regs(id)\ 337 [id] = { AUD_COMMON_REG_LIST(id) } 338 339 static const struct dce_audio_registers audio_regs[] = { 340 audio_regs(0), 341 audio_regs(1), 342 audio_regs(2), 343 audio_regs(3), 344 audio_regs(4), 345 audio_regs(5), 346 audio_regs(6) 347 }; 348 349 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 350 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 351 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 352 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 353 354 static const struct dce_audio_shift audio_shift = { 355 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 356 }; 357 358 static const struct dce_audio_mask audio_mask = { 359 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 360 }; 361 362 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 363 { 364 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 365 } 366 367 #define stream_enc_regs(id)\ 368 [id] = { SE_DCN3_REG_LIST(id) } 369 370 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 371 stream_enc_regs(0), 372 stream_enc_regs(1), 373 stream_enc_regs(2), 374 stream_enc_regs(3), 375 stream_enc_regs(4) 376 }; 377 378 static const struct dcn10_stream_encoder_shift se_shift = { 379 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 380 }; 381 382 static const struct dcn10_stream_encoder_mask se_mask = { 383 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 384 }; 385 386 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 387 { 388 struct dcn10_stream_encoder *enc1; 389 struct vpg *vpg; 390 struct afmt *afmt; 391 int vpg_inst; 392 int afmt_inst; 393 394 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 395 if (eng_id <= ENGINE_ID_DIGE) { 396 vpg_inst = eng_id; 397 afmt_inst = eng_id; 398 } else 399 return NULL; 400 401 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 402 vpg = dcn302_vpg_create(ctx, vpg_inst); 403 afmt = dcn302_afmt_create(ctx, afmt_inst); 404 405 if (!enc1 || !vpg || !afmt) { 406 kfree(enc1); 407 kfree(vpg); 408 kfree(afmt); 409 return NULL; 410 } 411 412 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 413 &se_shift, &se_mask); 414 415 return &enc1->base; 416 } 417 418 #define clk_src_regs(index, pllid)\ 419 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 420 421 static const struct dce110_clk_src_regs clk_src_regs[] = { 422 clk_src_regs(0, A), 423 clk_src_regs(1, B), 424 clk_src_regs(2, C), 425 clk_src_regs(3, D), 426 clk_src_regs(4, E) 427 }; 428 429 static const struct dce110_clk_src_shift cs_shift = { 430 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 431 }; 432 433 static const struct dce110_clk_src_mask cs_mask = { 434 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 435 }; 436 437 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 438 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 439 { 440 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 441 442 if (!clk_src) 443 return NULL; 444 445 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 446 clk_src->base.dp_clk_src = dp_clk_src; 447 return &clk_src->base; 448 } 449 450 kfree(clk_src); 451 BREAK_TO_DEBUGGER(); 452 return NULL; 453 } 454 455 static const struct dce_hwseq_registers hwseq_reg = { 456 HWSEQ_DCN302_REG_LIST() 457 }; 458 459 static const struct dce_hwseq_shift hwseq_shift = { 460 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 461 }; 462 463 static const struct dce_hwseq_mask hwseq_mask = { 464 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 465 }; 466 467 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 468 { 469 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 470 471 if (hws) { 472 hws->ctx = ctx; 473 hws->regs = &hwseq_reg; 474 hws->shifts = &hwseq_shift; 475 hws->masks = &hwseq_mask; 476 } 477 return hws; 478 } 479 480 #define hubp_regs(id)\ 481 [id] = { HUBP_REG_LIST_DCN30(id) } 482 483 static const struct dcn_hubp2_registers hubp_regs[] = { 484 hubp_regs(0), 485 hubp_regs(1), 486 hubp_regs(2), 487 hubp_regs(3), 488 hubp_regs(4) 489 }; 490 491 static const struct dcn_hubp2_shift hubp_shift = { 492 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 493 }; 494 495 static const struct dcn_hubp2_mask hubp_mask = { 496 HUBP_MASK_SH_LIST_DCN30(_MASK) 497 }; 498 499 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 500 { 501 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 502 503 if (!hubp2) 504 return NULL; 505 506 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 507 return &hubp2->base; 508 509 BREAK_TO_DEBUGGER(); 510 kfree(hubp2); 511 return NULL; 512 } 513 514 #define dpp_regs(id)\ 515 [id] = { DPP_REG_LIST_DCN30(id) } 516 517 static const struct dcn3_dpp_registers dpp_regs[] = { 518 dpp_regs(0), 519 dpp_regs(1), 520 dpp_regs(2), 521 dpp_regs(3), 522 dpp_regs(4) 523 }; 524 525 static const struct dcn3_dpp_shift tf_shift = { 526 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 527 }; 528 529 static const struct dcn3_dpp_mask tf_mask = { 530 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 531 }; 532 533 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 534 { 535 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 536 537 if (!dpp) 538 return NULL; 539 540 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 541 return &dpp->base; 542 543 BREAK_TO_DEBUGGER(); 544 kfree(dpp); 545 return NULL; 546 } 547 548 #define opp_regs(id)\ 549 [id] = { OPP_REG_LIST_DCN30(id) } 550 551 static const struct dcn20_opp_registers opp_regs[] = { 552 opp_regs(0), 553 opp_regs(1), 554 opp_regs(2), 555 opp_regs(3), 556 opp_regs(4) 557 }; 558 559 static const struct dcn20_opp_shift opp_shift = { 560 OPP_MASK_SH_LIST_DCN20(__SHIFT) 561 }; 562 563 static const struct dcn20_opp_mask opp_mask = { 564 OPP_MASK_SH_LIST_DCN20(_MASK) 565 }; 566 567 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 568 { 569 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 570 571 if (!opp) { 572 BREAK_TO_DEBUGGER(); 573 return NULL; 574 } 575 576 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 577 return &opp->base; 578 } 579 580 #define optc_regs(id)\ 581 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 582 583 static const struct dcn_optc_registers optc_regs[] = { 584 optc_regs(0), 585 optc_regs(1), 586 optc_regs(2), 587 optc_regs(3), 588 optc_regs(4) 589 }; 590 591 static const struct dcn_optc_shift optc_shift = { 592 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 593 }; 594 595 static const struct dcn_optc_mask optc_mask = { 596 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 597 }; 598 599 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 600 { 601 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 602 603 if (!tgn10) 604 return NULL; 605 606 tgn10->base.inst = instance; 607 tgn10->base.ctx = ctx; 608 609 tgn10->tg_regs = &optc_regs[instance]; 610 tgn10->tg_shift = &optc_shift; 611 tgn10->tg_mask = &optc_mask; 612 613 dcn30_timing_generator_init(tgn10); 614 615 return &tgn10->base; 616 } 617 618 static const struct dcn30_mpc_registers mpc_regs = { 619 MPC_REG_LIST_DCN3_0(0), 620 MPC_REG_LIST_DCN3_0(1), 621 MPC_REG_LIST_DCN3_0(2), 622 MPC_REG_LIST_DCN3_0(3), 623 MPC_REG_LIST_DCN3_0(4), 624 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 625 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 626 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 627 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 628 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 629 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 630 MPC_RMU_REG_LIST_DCN3AG(0), 631 MPC_RMU_REG_LIST_DCN3AG(1), 632 MPC_RMU_REG_LIST_DCN3AG(2), 633 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 634 }; 635 636 static const struct dcn30_mpc_shift mpc_shift = { 637 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 638 }; 639 640 static const struct dcn30_mpc_mask mpc_mask = { 641 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 642 }; 643 644 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 645 { 646 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 647 648 if (!mpc30) 649 return NULL; 650 651 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 652 653 return &mpc30->base; 654 } 655 656 #define dsc_regsDCN20(id)\ 657 [id] = { DSC_REG_LIST_DCN20(id) } 658 659 static const struct dcn20_dsc_registers dsc_regs[] = { 660 dsc_regsDCN20(0), 661 dsc_regsDCN20(1), 662 dsc_regsDCN20(2), 663 dsc_regsDCN20(3), 664 dsc_regsDCN20(4) 665 }; 666 667 static const struct dcn20_dsc_shift dsc_shift = { 668 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 669 }; 670 671 static const struct dcn20_dsc_mask dsc_mask = { 672 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 673 }; 674 675 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 676 { 677 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 678 679 if (!dsc) { 680 BREAK_TO_DEBUGGER(); 681 return NULL; 682 } 683 684 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 685 return &dsc->base; 686 } 687 688 #define dwbc_regs_dcn3(id)\ 689 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 690 691 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 692 dwbc_regs_dcn3(0) 693 }; 694 695 static const struct dcn30_dwbc_shift dwbc30_shift = { 696 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 697 }; 698 699 static const struct dcn30_dwbc_mask dwbc30_mask = { 700 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 701 }; 702 703 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 704 { 705 int i; 706 uint32_t pipe_count = pool->res_cap->num_dwb; 707 708 for (i = 0; i < pipe_count; i++) { 709 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 710 711 if (!dwbc30) { 712 dm_error("DC: failed to create dwbc30!\n"); 713 return false; 714 } 715 716 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 717 718 pool->dwbc[i] = &dwbc30->base; 719 } 720 return true; 721 } 722 723 #define mcif_wb_regs_dcn3(id)\ 724 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 725 726 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 727 mcif_wb_regs_dcn3(0) 728 }; 729 730 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 731 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 732 }; 733 734 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 735 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 736 }; 737 738 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 739 { 740 int i; 741 uint32_t pipe_count = pool->res_cap->num_dwb; 742 743 for (i = 0; i < pipe_count; i++) { 744 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 745 746 if (!mcif_wb30) { 747 dm_error("DC: failed to create mcif_wb30!\n"); 748 return false; 749 } 750 751 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 752 753 pool->mcif_wb[i] = &mcif_wb30->base; 754 } 755 return true; 756 } 757 758 #define aux_engine_regs(id)\ 759 [id] = {\ 760 AUX_COMMON_REG_LIST0(id), \ 761 .AUXN_IMPCAL = 0, \ 762 .AUXP_IMPCAL = 0, \ 763 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 764 } 765 766 static const struct dce110_aux_registers aux_engine_regs[] = { 767 aux_engine_regs(0), 768 aux_engine_regs(1), 769 aux_engine_regs(2), 770 aux_engine_regs(3), 771 aux_engine_regs(4) 772 }; 773 774 static const struct dce110_aux_registers_shift aux_shift = { 775 DCN_AUX_MASK_SH_LIST(__SHIFT) 776 }; 777 778 static const struct dce110_aux_registers_mask aux_mask = { 779 DCN_AUX_MASK_SH_LIST(_MASK) 780 }; 781 782 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 783 { 784 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 785 786 if (!aux_engine) 787 return NULL; 788 789 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 790 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 791 792 return &aux_engine->base; 793 } 794 795 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 796 797 static const struct dce_i2c_registers i2c_hw_regs[] = { 798 i2c_inst_regs(1), 799 i2c_inst_regs(2), 800 i2c_inst_regs(3), 801 i2c_inst_regs(4), 802 i2c_inst_regs(5) 803 }; 804 805 static const struct dce_i2c_shift i2c_shifts = { 806 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 807 }; 808 809 static const struct dce_i2c_mask i2c_masks = { 810 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 811 }; 812 813 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 814 { 815 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 816 817 if (!dce_i2c_hw) 818 return NULL; 819 820 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 821 822 return dce_i2c_hw; 823 } 824 825 static const struct encoder_feature_support link_enc_feature = { 826 .max_hdmi_deep_color = COLOR_DEPTH_121212, 827 .max_hdmi_pixel_clock = 600000, 828 .hdmi_ycbcr420_supported = true, 829 .dp_ycbcr420_supported = true, 830 .fec_supported = true, 831 .flags.bits.IS_HBR2_CAPABLE = true, 832 .flags.bits.IS_HBR3_CAPABLE = true, 833 .flags.bits.IS_TPS3_CAPABLE = true, 834 .flags.bits.IS_TPS4_CAPABLE = true 835 }; 836 837 #define link_regs(id, phyid)\ 838 [id] = {\ 839 LE_DCN3_REG_LIST(id), \ 840 UNIPHY_DCN2_REG_LIST(phyid), \ 841 DPCS_DCN2_REG_LIST(id), \ 842 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 843 } 844 845 static const struct dcn10_link_enc_registers link_enc_regs[] = { 846 link_regs(0, A), 847 link_regs(1, B), 848 link_regs(2, C), 849 link_regs(3, D), 850 link_regs(4, E) 851 }; 852 853 static const struct dcn10_link_enc_shift le_shift = { 854 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 855 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 856 }; 857 858 static const struct dcn10_link_enc_mask le_mask = { 859 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 860 DPCS_DCN2_MASK_SH_LIST(_MASK) 861 }; 862 863 #define aux_regs(id)\ 864 [id] = { DCN2_AUX_REG_LIST(id) } 865 866 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 867 aux_regs(0), 868 aux_regs(1), 869 aux_regs(2), 870 aux_regs(3), 871 aux_regs(4) 872 }; 873 874 #define hpd_regs(id)\ 875 [id] = { HPD_REG_LIST(id) } 876 877 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 878 hpd_regs(0), 879 hpd_regs(1), 880 hpd_regs(2), 881 hpd_regs(3), 882 hpd_regs(4) 883 }; 884 885 static struct link_encoder *dcn302_link_encoder_create( 886 struct dc_context *ctx, 887 const struct encoder_init_data *enc_init_data) 888 { 889 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 890 891 if (!enc20) 892 return NULL; 893 894 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 895 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 896 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 897 898 return &enc20->enc10.base; 899 } 900 901 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 902 { DCN_PANEL_CNTL_REG_LIST() } 903 }; 904 905 static const struct dce_panel_cntl_shift panel_cntl_shift = { 906 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 907 }; 908 909 static const struct dce_panel_cntl_mask panel_cntl_mask = { 910 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 911 }; 912 913 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 914 { 915 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 916 917 if (!panel_cntl) 918 return NULL; 919 920 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 921 &panel_cntl_shift, &panel_cntl_mask); 922 923 return &panel_cntl->base; 924 } 925 926 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 927 { 928 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 929 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 930 } 931 932 static const struct resource_create_funcs res_create_funcs = { 933 .read_dce_straps = read_dce_straps, 934 .create_audio = dcn302_create_audio, 935 .create_stream_encoder = dcn302_stream_encoder_create, 936 .create_hwseq = dcn302_hwseq_create, 937 }; 938 939 static bool is_soc_bounding_box_valid(struct dc *dc) 940 { 941 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 942 943 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 944 return true; 945 946 return false; 947 } 948 949 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 950 { 951 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 952 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 953 954 DC_LOGGER_INIT(dc->ctx->logger); 955 956 if (!is_soc_bounding_box_valid(dc)) { 957 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 958 return false; 959 } 960 961 loaded_ip->max_num_otg = pool->pipe_count; 962 loaded_ip->max_num_dpp = pool->pipe_count; 963 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 964 DC_FP_START(); 965 dcn20_patch_bounding_box(dc, loaded_bb); 966 DC_FP_END(); 967 968 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 969 struct bp_soc_bb_info bb_info = { 0 }; 970 971 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 972 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 973 974 DC_FP_START(); 975 dcn302_fpu_init_soc_bounding_box(bb_info); 976 DC_FP_END(); 977 } 978 } 979 980 return true; 981 } 982 983 static void dcn302_resource_destruct(struct resource_pool *pool) 984 { 985 unsigned int i; 986 987 for (i = 0; i < pool->stream_enc_count; i++) { 988 if (pool->stream_enc[i] != NULL) { 989 if (pool->stream_enc[i]->vpg != NULL) { 990 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 991 pool->stream_enc[i]->vpg = NULL; 992 } 993 if (pool->stream_enc[i]->afmt != NULL) { 994 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 995 pool->stream_enc[i]->afmt = NULL; 996 } 997 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 998 pool->stream_enc[i] = NULL; 999 } 1000 } 1001 1002 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1003 if (pool->dscs[i] != NULL) 1004 dcn20_dsc_destroy(&pool->dscs[i]); 1005 } 1006 1007 if (pool->mpc != NULL) { 1008 kfree(TO_DCN20_MPC(pool->mpc)); 1009 pool->mpc = NULL; 1010 } 1011 1012 if (pool->hubbub != NULL) { 1013 kfree(pool->hubbub); 1014 pool->hubbub = NULL; 1015 } 1016 1017 for (i = 0; i < pool->pipe_count; i++) { 1018 if (pool->dpps[i] != NULL) { 1019 kfree(TO_DCN20_DPP(pool->dpps[i])); 1020 pool->dpps[i] = NULL; 1021 } 1022 1023 if (pool->hubps[i] != NULL) { 1024 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1025 pool->hubps[i] = NULL; 1026 } 1027 1028 if (pool->irqs != NULL) 1029 dal_irq_service_destroy(&pool->irqs); 1030 } 1031 1032 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1033 if (pool->engines[i] != NULL) 1034 dce110_engine_destroy(&pool->engines[i]); 1035 if (pool->hw_i2cs[i] != NULL) { 1036 kfree(pool->hw_i2cs[i]); 1037 pool->hw_i2cs[i] = NULL; 1038 } 1039 if (pool->sw_i2cs[i] != NULL) { 1040 kfree(pool->sw_i2cs[i]); 1041 pool->sw_i2cs[i] = NULL; 1042 } 1043 } 1044 1045 for (i = 0; i < pool->res_cap->num_opp; i++) { 1046 if (pool->opps[i] != NULL) 1047 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1048 } 1049 1050 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1051 if (pool->timing_generators[i] != NULL) { 1052 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1053 pool->timing_generators[i] = NULL; 1054 } 1055 } 1056 1057 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1058 if (pool->dwbc[i] != NULL) { 1059 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1060 pool->dwbc[i] = NULL; 1061 } 1062 if (pool->mcif_wb[i] != NULL) { 1063 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1064 pool->mcif_wb[i] = NULL; 1065 } 1066 } 1067 1068 for (i = 0; i < pool->audio_count; i++) { 1069 if (pool->audios[i]) 1070 dce_aud_destroy(&pool->audios[i]); 1071 } 1072 1073 for (i = 0; i < pool->clk_src_count; i++) { 1074 if (pool->clock_sources[i] != NULL) 1075 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1076 } 1077 1078 if (pool->dp_clock_source != NULL) 1079 dcn20_clock_source_destroy(&pool->dp_clock_source); 1080 1081 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1082 if (pool->mpc_lut[i] != NULL) { 1083 dc_3dlut_func_release(pool->mpc_lut[i]); 1084 pool->mpc_lut[i] = NULL; 1085 } 1086 if (pool->mpc_shaper[i] != NULL) { 1087 dc_transfer_func_release(pool->mpc_shaper[i]); 1088 pool->mpc_shaper[i] = NULL; 1089 } 1090 } 1091 1092 for (i = 0; i < pool->pipe_count; i++) { 1093 if (pool->multiple_abms[i] != NULL) 1094 dce_abm_destroy(&pool->multiple_abms[i]); 1095 } 1096 1097 if (pool->psr != NULL) 1098 dmub_psr_destroy(&pool->psr); 1099 1100 if (pool->dccg != NULL) 1101 dcn_dccg_destroy(&pool->dccg); 1102 1103 if (pool->oem_device != NULL) { 1104 struct dc *dc = pool->oem_device->ctx->dc; 1105 1106 dc->link_srv->destroy_ddc_service(&pool->oem_device); 1107 } 1108 } 1109 1110 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1111 { 1112 dcn302_resource_destruct(*pool); 1113 kfree(*pool); 1114 *pool = NULL; 1115 } 1116 1117 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1118 { 1119 DC_FP_START(); 1120 dcn302_fpu_update_bw_bounding_box(dc, bw_params); 1121 DC_FP_END(); 1122 } 1123 1124 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config) 1125 { 1126 *panel_config = panel_config_defaults; 1127 } 1128 1129 static struct resource_funcs dcn302_res_pool_funcs = { 1130 .destroy = dcn302_destroy_resource_pool, 1131 .link_enc_create = dcn302_link_encoder_create, 1132 .panel_cntl_create = dcn302_panel_cntl_create, 1133 .validate_bandwidth = dcn30_validate_bandwidth, 1134 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1135 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1136 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1137 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1138 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1139 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1140 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1141 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1142 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1143 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1144 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1145 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1146 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1147 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1148 .get_panel_config_defaults = dcn302_get_panel_config_defaults, 1149 }; 1150 1151 static struct dc_cap_funcs cap_funcs = { 1152 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1153 }; 1154 1155 static const struct bios_registers bios_regs = { 1156 NBIO_SR(BIOS_SCRATCH_3), 1157 NBIO_SR(BIOS_SCRATCH_6) 1158 }; 1159 1160 static const struct dccg_registers dccg_regs = { 1161 DCCG_REG_LIST_DCN3_02() 1162 }; 1163 1164 static const struct dccg_shift dccg_shift = { 1165 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1166 }; 1167 1168 static const struct dccg_mask dccg_mask = { 1169 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1170 }; 1171 1172 #define abm_regs(id)\ 1173 [id] = { ABM_DCN302_REG_LIST(id) } 1174 1175 static const struct dce_abm_registers abm_regs[] = { 1176 abm_regs(0), 1177 abm_regs(1), 1178 abm_regs(2), 1179 abm_regs(3), 1180 abm_regs(4) 1181 }; 1182 1183 static const struct dce_abm_shift abm_shift = { 1184 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1185 }; 1186 1187 static const struct dce_abm_mask abm_mask = { 1188 ABM_MASK_SH_LIST_DCN30(_MASK) 1189 }; 1190 1191 static bool dcn302_resource_construct( 1192 uint8_t num_virtual_links, 1193 struct dc *dc, 1194 struct resource_pool *pool) 1195 { 1196 int i; 1197 struct dc_context *ctx = dc->ctx; 1198 struct irq_service_init_data init_data; 1199 struct ddc_service_init_data ddc_init_data = {0}; 1200 1201 ctx->dc_bios->regs = &bios_regs; 1202 1203 pool->res_cap = &res_cap_dcn302; 1204 1205 pool->funcs = &dcn302_res_pool_funcs; 1206 1207 /************************************************* 1208 * Resource + asic cap harcoding * 1209 *************************************************/ 1210 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1211 pool->pipe_count = pool->res_cap->num_timing_generator; 1212 pool->mpcc_count = pool->res_cap->num_timing_generator; 1213 dc->caps.max_downscale_ratio = 600; 1214 dc->caps.i2c_speed_in_khz = 100; 1215 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1216 dc->caps.max_cursor_size = 256; 1217 dc->caps.min_horizontal_blanking_period = 80; 1218 dc->caps.dmdata_alloc_size = 2048; 1219 dc->caps.mall_size_per_mem_channel = 4; 1220 /* total size = mall per channel * num channels * 1024 * 1024 */ 1221 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1222 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1223 dc->caps.max_slave_planes = 2; 1224 dc->caps.max_slave_yuv_planes = 2; 1225 dc->caps.max_slave_rgb_planes = 2; 1226 dc->caps.post_blend_color_processing = true; 1227 dc->caps.force_dp_tps4_for_cp2520 = true; 1228 dc->caps.extended_aux_timeout_support = true; 1229 dc->caps.dmcub_support = true; 1230 dc->caps.max_v_total = (1 << 15) - 1; 1231 1232 /* Color pipeline capabilities */ 1233 dc->caps.color.dpp.dcn_arch = 1; 1234 dc->caps.color.dpp.input_lut_shared = 0; 1235 dc->caps.color.dpp.icsc = 1; 1236 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1237 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1238 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1239 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1240 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1241 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1242 dc->caps.color.dpp.post_csc = 1; 1243 dc->caps.color.dpp.gamma_corr = 1; 1244 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1245 1246 dc->caps.color.dpp.hw_3d_lut = 1; 1247 dc->caps.color.dpp.ogam_ram = 1; 1248 // no OGAM ROM on DCN3 1249 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1250 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1251 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1252 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1253 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1254 dc->caps.color.dpp.ocsc = 0; 1255 1256 dc->caps.color.mpc.gamut_remap = 1; 1257 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1258 dc->caps.color.mpc.ogam_ram = 1; 1259 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1260 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1261 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1262 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1263 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1264 dc->caps.color.mpc.ocsc = 1; 1265 1266 dc->caps.dp_hdmi21_pcon_support = true; 1267 1268 /* read VBIOS LTTPR caps */ 1269 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1270 enum bp_result bp_query_result; 1271 uint8_t is_vbios_lttpr_enable = 0; 1272 1273 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1274 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1275 } 1276 1277 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1278 enum bp_result bp_query_result; 1279 uint8_t is_vbios_interop_enabled = 0; 1280 1281 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 1282 &is_vbios_interop_enabled); 1283 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1284 } 1285 1286 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1287 dc->debug = debug_defaults_drv; 1288 1289 // Init the vm_helper 1290 if (dc->vm_helper) 1291 vm_helper_init(dc->vm_helper, 16); 1292 1293 /************************************************* 1294 * Create resources * 1295 *************************************************/ 1296 1297 /* Clock Sources for Pixel Clock*/ 1298 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1299 dcn302_clock_source_create(ctx, ctx->dc_bios, 1300 CLOCK_SOURCE_COMBO_PHY_PLL0, 1301 &clk_src_regs[0], false); 1302 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1303 dcn302_clock_source_create(ctx, ctx->dc_bios, 1304 CLOCK_SOURCE_COMBO_PHY_PLL1, 1305 &clk_src_regs[1], false); 1306 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1307 dcn302_clock_source_create(ctx, ctx->dc_bios, 1308 CLOCK_SOURCE_COMBO_PHY_PLL2, 1309 &clk_src_regs[2], false); 1310 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1311 dcn302_clock_source_create(ctx, ctx->dc_bios, 1312 CLOCK_SOURCE_COMBO_PHY_PLL3, 1313 &clk_src_regs[3], false); 1314 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1315 dcn302_clock_source_create(ctx, ctx->dc_bios, 1316 CLOCK_SOURCE_COMBO_PHY_PLL4, 1317 &clk_src_regs[4], false); 1318 1319 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1320 1321 /* todo: not reuse phy_pll registers */ 1322 pool->dp_clock_source = 1323 dcn302_clock_source_create(ctx, ctx->dc_bios, 1324 CLOCK_SOURCE_ID_DP_DTO, 1325 &clk_src_regs[0], true); 1326 1327 for (i = 0; i < pool->clk_src_count; i++) { 1328 if (pool->clock_sources[i] == NULL) { 1329 dm_error("DC: failed to create clock sources!\n"); 1330 BREAK_TO_DEBUGGER(); 1331 goto create_fail; 1332 } 1333 } 1334 1335 /* DCCG */ 1336 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1337 if (pool->dccg == NULL) { 1338 dm_error("DC: failed to create dccg!\n"); 1339 BREAK_TO_DEBUGGER(); 1340 goto create_fail; 1341 } 1342 1343 /* PP Lib and SMU interfaces */ 1344 init_soc_bounding_box(dc, pool); 1345 1346 /* DML */ 1347 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1348 1349 /* IRQ */ 1350 init_data.ctx = dc->ctx; 1351 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1352 if (!pool->irqs) 1353 goto create_fail; 1354 1355 /* HUBBUB */ 1356 pool->hubbub = dcn302_hubbub_create(ctx); 1357 if (pool->hubbub == NULL) { 1358 BREAK_TO_DEBUGGER(); 1359 dm_error("DC: failed to create hubbub!\n"); 1360 goto create_fail; 1361 } 1362 1363 /* HUBPs, DPPs, OPPs and TGs */ 1364 for (i = 0; i < pool->pipe_count; i++) { 1365 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1366 if (pool->hubps[i] == NULL) { 1367 BREAK_TO_DEBUGGER(); 1368 dm_error("DC: failed to create hubps!\n"); 1369 goto create_fail; 1370 } 1371 1372 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1373 if (pool->dpps[i] == NULL) { 1374 BREAK_TO_DEBUGGER(); 1375 dm_error("DC: failed to create dpps!\n"); 1376 goto create_fail; 1377 } 1378 } 1379 1380 for (i = 0; i < pool->res_cap->num_opp; i++) { 1381 pool->opps[i] = dcn302_opp_create(ctx, i); 1382 if (pool->opps[i] == NULL) { 1383 BREAK_TO_DEBUGGER(); 1384 dm_error("DC: failed to create output pixel processor!\n"); 1385 goto create_fail; 1386 } 1387 } 1388 1389 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1390 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1391 if (pool->timing_generators[i] == NULL) { 1392 BREAK_TO_DEBUGGER(); 1393 dm_error("DC: failed to create tg!\n"); 1394 goto create_fail; 1395 } 1396 } 1397 pool->timing_generator_count = i; 1398 1399 /* PSR */ 1400 pool->psr = dmub_psr_create(ctx); 1401 if (pool->psr == NULL) { 1402 dm_error("DC: failed to create psr!\n"); 1403 BREAK_TO_DEBUGGER(); 1404 goto create_fail; 1405 } 1406 1407 /* ABMs */ 1408 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1409 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1410 if (pool->multiple_abms[i] == NULL) { 1411 dm_error("DC: failed to create abm for pipe %d!\n", i); 1412 BREAK_TO_DEBUGGER(); 1413 goto create_fail; 1414 } 1415 } 1416 1417 /* MPC and DSC */ 1418 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1419 if (pool->mpc == NULL) { 1420 BREAK_TO_DEBUGGER(); 1421 dm_error("DC: failed to create mpc!\n"); 1422 goto create_fail; 1423 } 1424 1425 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1426 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1427 if (pool->dscs[i] == NULL) { 1428 BREAK_TO_DEBUGGER(); 1429 dm_error("DC: failed to create display stream compressor %d!\n", i); 1430 goto create_fail; 1431 } 1432 } 1433 1434 /* DWB and MMHUBBUB */ 1435 if (!dcn302_dwbc_create(ctx, pool)) { 1436 BREAK_TO_DEBUGGER(); 1437 dm_error("DC: failed to create dwbc!\n"); 1438 goto create_fail; 1439 } 1440 1441 if (!dcn302_mmhubbub_create(ctx, pool)) { 1442 BREAK_TO_DEBUGGER(); 1443 dm_error("DC: failed to create mcif_wb!\n"); 1444 goto create_fail; 1445 } 1446 1447 /* AUX and I2C */ 1448 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1449 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1450 if (pool->engines[i] == NULL) { 1451 BREAK_TO_DEBUGGER(); 1452 dm_error("DC:failed to create aux engine!!\n"); 1453 goto create_fail; 1454 } 1455 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1456 if (pool->hw_i2cs[i] == NULL) { 1457 BREAK_TO_DEBUGGER(); 1458 dm_error("DC:failed to create hw i2c!!\n"); 1459 goto create_fail; 1460 } 1461 pool->sw_i2cs[i] = NULL; 1462 } 1463 1464 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1465 if (!resource_construct(num_virtual_links, dc, pool, 1466 &res_create_funcs)) 1467 goto create_fail; 1468 1469 /* HW Sequencer and Plane caps */ 1470 dcn302_hw_sequencer_construct(dc); 1471 1472 dc->caps.max_planes = pool->pipe_count; 1473 1474 for (i = 0; i < dc->caps.max_planes; ++i) 1475 dc->caps.planes[i] = plane_cap; 1476 1477 dc->cap_funcs = cap_funcs; 1478 1479 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1480 ddc_init_data.ctx = dc->ctx; 1481 ddc_init_data.link = NULL; 1482 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1483 ddc_init_data.id.enum_id = 0; 1484 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1485 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 1486 } else { 1487 pool->oem_device = NULL; 1488 } 1489 1490 return true; 1491 1492 create_fail: 1493 1494 dcn302_resource_destruct(pool); 1495 1496 return false; 1497 } 1498 1499 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1500 { 1501 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1502 1503 if (!pool) 1504 return NULL; 1505 1506 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1507 return pool; 1508 1509 BREAK_TO_DEBUGGER(); 1510 kfree(pool); 1511 return NULL; 1512 } 1513