1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dcn10/dcn10_resource.h" 47 48 #include "dce/dce_abm.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_clock_source.h" 52 #include "dce/dce_hwseq.h" 53 #include "dce/dce_i2c_hw.h" 54 #include "dce/dce_panel_cntl.h" 55 #include "dce/dmub_abm.h" 56 #include "dce/dmub_psr.h" 57 #include "clk_mgr.h" 58 59 #include "hw_sequencer_private.h" 60 #include "reg_helper.h" 61 #include "resource.h" 62 #include "vm_helper.h" 63 64 #include "dimgrey_cavefish_ip_offset.h" 65 #include "dcn/dcn_3_0_2_offset.h" 66 #include "dcn/dcn_3_0_2_sh_mask.h" 67 #include "dcn/dpcs_3_0_0_offset.h" 68 #include "dcn/dpcs_3_0_0_sh_mask.h" 69 #include "nbio/nbio_7_4_offset.h" 70 #include "amdgpu_socbb.h" 71 72 #define DC_LOGGER_INIT(logger) 73 74 struct _vcs_dpi_ip_params_st dcn3_02_ip = { 75 .use_min_dcfclk = 0, 76 .clamp_min_dcfclk = 0, 77 .odm_capable = 1, 78 .gpuvm_enable = 1, 79 .hostvm_enable = 0, 80 .gpuvm_max_page_table_levels = 4, 81 .hostvm_max_page_table_levels = 4, 82 .hostvm_cached_page_table_levels = 0, 83 .pte_group_size_bytes = 2048, 84 .num_dsc = 5, 85 .rob_buffer_size_kbytes = 184, 86 .det_buffer_size_kbytes = 184, 87 .dpte_buffer_size_in_pte_reqs_luma = 64, 88 .dpte_buffer_size_in_pte_reqs_chroma = 34, 89 .pde_proc_buffer_size_64k_reqs = 48, 90 .dpp_output_buffer_pixels = 2560, 91 .opp_output_buffer_lines = 1, 92 .pixel_chunk_size_kbytes = 8, 93 .pte_enable = 1, 94 .max_page_table_levels = 2, 95 .pte_chunk_size_kbytes = 2, // ? 96 .meta_chunk_size_kbytes = 2, 97 .writeback_chunk_size_kbytes = 8, 98 .line_buffer_size_bits = 789504, 99 .is_line_buffer_bpp_fixed = 0, // ? 100 .line_buffer_fixed_bpp = 0, // ? 101 .dcc_supported = true, 102 .writeback_interface_buffer_size_kbytes = 90, 103 .writeback_line_buffer_buffer_size = 0, 104 .max_line_buffer_lines = 12, 105 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 106 .writeback_chroma_buffer_size_kbytes = 8, 107 .writeback_chroma_line_buffer_width_pixels = 4, 108 .writeback_max_hscl_ratio = 1, 109 .writeback_max_vscl_ratio = 1, 110 .writeback_min_hscl_ratio = 1, 111 .writeback_min_vscl_ratio = 1, 112 .writeback_max_hscl_taps = 1, 113 .writeback_max_vscl_taps = 1, 114 .writeback_line_buffer_luma_buffer_size = 0, 115 .writeback_line_buffer_chroma_buffer_size = 14643, 116 .cursor_buffer_size = 8, 117 .cursor_chunk_size = 2, 118 .max_num_otg = 5, 119 .max_num_dpp = 5, 120 .max_num_wb = 1, 121 .max_dchub_pscl_bw_pix_per_clk = 4, 122 .max_pscl_lb_bw_pix_per_clk = 2, 123 .max_lb_vscl_bw_pix_per_clk = 4, 124 .max_vscl_hscl_bw_pix_per_clk = 4, 125 .max_hscl_ratio = 6, 126 .max_vscl_ratio = 6, 127 .hscl_mults = 4, 128 .vscl_mults = 4, 129 .max_hscl_taps = 8, 130 .max_vscl_taps = 8, 131 .dispclk_ramp_margin_percent = 1, 132 .underscan_factor = 1.11, 133 .min_vblank_lines = 32, 134 .dppclk_delay_subtotal = 46, 135 .dynamic_metadata_vm_enabled = true, 136 .dppclk_delay_scl_lb_only = 16, 137 .dppclk_delay_scl = 50, 138 .dppclk_delay_cnvc_formatter = 27, 139 .dppclk_delay_cnvc_cursor = 6, 140 .dispclk_delay_subtotal = 119, 141 .dcfclk_cstate_latency = 5.2, // SRExitTime 142 .max_inter_dcn_tile_repeaters = 8, 143 .max_num_hdmi_frl_outputs = 1, 144 .odm_combine_4to1_supported = true, 145 146 .xfc_supported = false, 147 .xfc_fill_bw_overhead_percent = 10.0, 148 .xfc_fill_constant_bytes = 0, 149 .gfx7_compat_tiling_supported = 0, 150 .number_of_cursors = 1, 151 }; 152 153 struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = { 154 .clock_limits = { 155 { 156 .state = 0, 157 .dispclk_mhz = 562.0, 158 .dppclk_mhz = 300.0, 159 .phyclk_mhz = 300.0, 160 .phyclk_d18_mhz = 667.0, 161 .dscclk_mhz = 405.6, 162 }, 163 }, 164 165 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 166 .num_states = 1, 167 .sr_exit_time_us = 15.5, 168 .sr_enter_plus_exit_time_us = 20, 169 .urgent_latency_us = 4.0, 170 .urgent_latency_pixel_data_only_us = 4.0, 171 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 172 .urgent_latency_vm_data_only_us = 4.0, 173 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 174 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 175 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 176 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 177 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 178 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 179 .max_avg_sdp_bw_use_normal_percent = 60.0, 180 .max_avg_dram_bw_use_normal_percent = 40.0, 181 .writeback_latency_us = 12.0, 182 .max_request_size_bytes = 256, 183 .fabric_datapath_to_dcn_data_return_bytes = 64, 184 .dcn_downspread_percent = 0.5, 185 .downspread_percent = 0.38, 186 .dram_page_open_time_ns = 50.0, 187 .dram_rw_turnaround_time_ns = 17.5, 188 .dram_return_buffer_per_channel_bytes = 8192, 189 .round_trip_ping_latency_dcfclk_cycles = 156, 190 .urgent_out_of_order_return_per_channel_bytes = 4096, 191 .channel_interleave_bytes = 256, 192 .num_banks = 8, 193 .gpuvm_min_page_size_bytes = 4096, 194 .hostvm_min_page_size_bytes = 4096, 195 .dram_clock_change_latency_us = 404, 196 .dummy_pstate_latency_us = 5, 197 .writeback_dram_clock_change_latency_us = 23.0, 198 .return_bus_width_bytes = 64, 199 .dispclk_dppclk_vco_speed_mhz = 3650, 200 .xfc_bus_transport_time_us = 20, // ? 201 .xfc_xbuf_latency_tolerance_us = 4, // ? 202 .use_urgent_burst_bw = 1, // ? 203 .do_urgent_latency_adjustment = true, 204 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 205 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 206 }; 207 208 static const struct dc_debug_options debug_defaults_drv = { 209 .disable_dmcu = true, 210 .force_abm_enable = false, 211 .timing_trace = false, 212 .clock_trace = true, 213 .disable_pplib_clock_request = true, 214 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 215 .force_single_disp_pipe_split = false, 216 .disable_dcc = DCC_ENABLE, 217 .vsr_support = true, 218 .performance_trace = false, 219 .max_downscale_src_width = 7680,/*upto 8K*/ 220 .disable_pplib_wm_range = false, 221 .scl_reset_length10 = true, 222 .sanity_checks = false, 223 .underflow_assert_delay_us = 0xFFFFFFFF, 224 .dwb_fi_phase = -1, // -1 = disable, 225 .dmub_command_table = true, 226 .use_max_lb = true 227 }; 228 229 static const struct dc_debug_options debug_defaults_diags = { 230 .disable_dmcu = true, 231 .force_abm_enable = false, 232 .timing_trace = true, 233 .clock_trace = true, 234 .disable_dpp_power_gate = true, 235 .disable_hubp_power_gate = true, 236 .disable_clock_gate = true, 237 .disable_pplib_clock_request = true, 238 .disable_pplib_wm_range = true, 239 .disable_stutter = false, 240 .scl_reset_length10 = true, 241 .dwb_fi_phase = -1, // -1 = disable 242 .dmub_command_table = true, 243 .enable_tri_buf = true, 244 .disable_psr = true, 245 .use_max_lb = true 246 }; 247 248 enum dcn302_clk_src_array_id { 249 DCN302_CLK_SRC_PLL0, 250 DCN302_CLK_SRC_PLL1, 251 DCN302_CLK_SRC_PLL2, 252 DCN302_CLK_SRC_PLL3, 253 DCN302_CLK_SRC_PLL4, 254 DCN302_CLK_SRC_TOTAL 255 }; 256 257 static const struct resource_caps res_cap_dcn302 = { 258 .num_timing_generator = 5, 259 .num_opp = 5, 260 .num_video_plane = 5, 261 .num_audio = 5, 262 .num_stream_encoder = 5, 263 .num_dwb = 1, 264 .num_ddc = 5, 265 .num_vmid = 16, 266 .num_mpc_3dlut = 2, 267 .num_dsc = 5, 268 }; 269 270 static const struct dc_plane_cap plane_cap = { 271 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 272 .blends_with_above = true, 273 .blends_with_below = true, 274 .per_pixel_alpha = true, 275 .pixel_format_support = { 276 .argb8888 = true, 277 .nv12 = true, 278 .fp16 = true, 279 .p010 = false, 280 .ayuv = false, 281 }, 282 .max_upscale_factor = { 283 .argb8888 = 16000, 284 .nv12 = 16000, 285 .fp16 = 16000 286 }, 287 .max_downscale_factor = { 288 .argb8888 = 600, 289 .nv12 = 600, 290 .fp16 = 600 291 }, 292 16, 293 16 294 }; 295 296 /* NBIO */ 297 #define NBIO_BASE_INNER(seg) \ 298 NBIO_BASE__INST0_SEG ## seg 299 300 #define NBIO_BASE(seg) \ 301 NBIO_BASE_INNER(seg) 302 303 #define NBIO_SR(reg_name)\ 304 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 305 mm ## reg_name 306 307 /* DCN */ 308 #undef BASE_INNER 309 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 310 311 #define BASE(seg) BASE_INNER(seg) 312 313 #define SR(reg_name)\ 314 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 315 316 #define SF(reg_name, field_name, post_fix)\ 317 .field_name = reg_name ## __ ## field_name ## post_fix 318 319 #define SRI(reg_name, block, id)\ 320 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 321 322 #define SRI2(reg_name, block, id)\ 323 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 324 325 #define SRII(reg_name, block, id)\ 326 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 327 mm ## block ## id ## _ ## reg_name 328 329 #define DCCG_SRII(reg_name, block, id)\ 330 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 331 mm ## block ## id ## _ ## reg_name 332 333 #define VUPDATE_SRII(reg_name, block, id)\ 334 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 335 mm ## reg_name ## _ ## block ## id 336 337 #define SRII_DWB(reg_name, temp_name, block, id)\ 338 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 339 mm ## block ## id ## _ ## temp_name 340 341 #define SRII_MPC_RMU(reg_name, block, id)\ 342 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 343 mm ## block ## id ## _ ## reg_name 344 345 static const struct dcn_hubbub_registers hubbub_reg = { 346 HUBBUB_REG_LIST_DCN30(0) 347 }; 348 349 static const struct dcn_hubbub_shift hubbub_shift = { 350 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 351 }; 352 353 static const struct dcn_hubbub_mask hubbub_mask = { 354 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 355 }; 356 357 #define vmid_regs(id)\ 358 [id] = { DCN20_VMID_REG_LIST(id) } 359 360 static const struct dcn_vmid_registers vmid_regs[] = { 361 vmid_regs(0), 362 vmid_regs(1), 363 vmid_regs(2), 364 vmid_regs(3), 365 vmid_regs(4), 366 vmid_regs(5), 367 vmid_regs(6), 368 vmid_regs(7), 369 vmid_regs(8), 370 vmid_regs(9), 371 vmid_regs(10), 372 vmid_regs(11), 373 vmid_regs(12), 374 vmid_regs(13), 375 vmid_regs(14), 376 vmid_regs(15) 377 }; 378 379 static const struct dcn20_vmid_shift vmid_shifts = { 380 DCN20_VMID_MASK_SH_LIST(__SHIFT) 381 }; 382 383 static const struct dcn20_vmid_mask vmid_masks = { 384 DCN20_VMID_MASK_SH_LIST(_MASK) 385 }; 386 387 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 388 { 389 int i; 390 391 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 392 393 if (!hubbub3) 394 return NULL; 395 396 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 397 398 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 399 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 400 401 vmid->ctx = ctx; 402 403 vmid->regs = &vmid_regs[i]; 404 vmid->shifts = &vmid_shifts; 405 vmid->masks = &vmid_masks; 406 } 407 408 return &hubbub3->base; 409 } 410 411 #define vpg_regs(id)\ 412 [id] = { VPG_DCN3_REG_LIST(id) } 413 414 static const struct dcn30_vpg_registers vpg_regs[] = { 415 vpg_regs(0), 416 vpg_regs(1), 417 vpg_regs(2), 418 vpg_regs(3), 419 vpg_regs(4), 420 vpg_regs(5) 421 }; 422 423 static const struct dcn30_vpg_shift vpg_shift = { 424 DCN3_VPG_MASK_SH_LIST(__SHIFT) 425 }; 426 427 static const struct dcn30_vpg_mask vpg_mask = { 428 DCN3_VPG_MASK_SH_LIST(_MASK) 429 }; 430 431 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 432 { 433 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 434 435 if (!vpg3) 436 return NULL; 437 438 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 439 440 return &vpg3->base; 441 } 442 443 #define afmt_regs(id)\ 444 [id] = { AFMT_DCN3_REG_LIST(id) } 445 446 static const struct dcn30_afmt_registers afmt_regs[] = { 447 afmt_regs(0), 448 afmt_regs(1), 449 afmt_regs(2), 450 afmt_regs(3), 451 afmt_regs(4), 452 afmt_regs(5) 453 }; 454 455 static const struct dcn30_afmt_shift afmt_shift = { 456 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 457 }; 458 459 static const struct dcn30_afmt_mask afmt_mask = { 460 DCN3_AFMT_MASK_SH_LIST(_MASK) 461 }; 462 463 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 464 { 465 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 466 467 if (!afmt3) 468 return NULL; 469 470 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 471 472 return &afmt3->base; 473 } 474 475 #define audio_regs(id)\ 476 [id] = { AUD_COMMON_REG_LIST(id) } 477 478 static const struct dce_audio_registers audio_regs[] = { 479 audio_regs(0), 480 audio_regs(1), 481 audio_regs(2), 482 audio_regs(3), 483 audio_regs(4), 484 audio_regs(5), 485 audio_regs(6) 486 }; 487 488 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 489 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 490 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 491 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 492 493 static const struct dce_audio_shift audio_shift = { 494 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 495 }; 496 497 static const struct dce_audio_mask audio_mask = { 498 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 499 }; 500 501 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 502 { 503 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 504 } 505 506 #define stream_enc_regs(id)\ 507 [id] = { SE_DCN3_REG_LIST(id) } 508 509 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 510 stream_enc_regs(0), 511 stream_enc_regs(1), 512 stream_enc_regs(2), 513 stream_enc_regs(3), 514 stream_enc_regs(4) 515 }; 516 517 static const struct dcn10_stream_encoder_shift se_shift = { 518 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 519 }; 520 521 static const struct dcn10_stream_encoder_mask se_mask = { 522 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 523 }; 524 525 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 526 { 527 struct dcn10_stream_encoder *enc1; 528 struct vpg *vpg; 529 struct afmt *afmt; 530 int vpg_inst; 531 int afmt_inst; 532 533 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 534 if (eng_id <= ENGINE_ID_DIGE) { 535 vpg_inst = eng_id; 536 afmt_inst = eng_id; 537 } else 538 return NULL; 539 540 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 541 vpg = dcn302_vpg_create(ctx, vpg_inst); 542 afmt = dcn302_afmt_create(ctx, afmt_inst); 543 544 if (!enc1 || !vpg || !afmt) 545 return NULL; 546 547 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 548 &se_shift, &se_mask); 549 550 return &enc1->base; 551 } 552 553 #define clk_src_regs(index, pllid)\ 554 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 555 556 static const struct dce110_clk_src_regs clk_src_regs[] = { 557 clk_src_regs(0, A), 558 clk_src_regs(1, B), 559 clk_src_regs(2, C), 560 clk_src_regs(3, D), 561 clk_src_regs(4, E) 562 }; 563 564 static const struct dce110_clk_src_shift cs_shift = { 565 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 566 }; 567 568 static const struct dce110_clk_src_mask cs_mask = { 569 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 570 }; 571 572 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 573 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 574 { 575 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 576 577 if (!clk_src) 578 return NULL; 579 580 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 581 clk_src->base.dp_clk_src = dp_clk_src; 582 return &clk_src->base; 583 } 584 585 BREAK_TO_DEBUGGER(); 586 return NULL; 587 } 588 589 static const struct dce_hwseq_registers hwseq_reg = { 590 HWSEQ_DCN302_REG_LIST() 591 }; 592 593 static const struct dce_hwseq_shift hwseq_shift = { 594 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 595 }; 596 597 static const struct dce_hwseq_mask hwseq_mask = { 598 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 599 }; 600 601 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 602 { 603 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 604 605 if (hws) { 606 hws->ctx = ctx; 607 hws->regs = &hwseq_reg; 608 hws->shifts = &hwseq_shift; 609 hws->masks = &hwseq_mask; 610 } 611 return hws; 612 } 613 614 #define hubp_regs(id)\ 615 [id] = { HUBP_REG_LIST_DCN30(id) } 616 617 static const struct dcn_hubp2_registers hubp_regs[] = { 618 hubp_regs(0), 619 hubp_regs(1), 620 hubp_regs(2), 621 hubp_regs(3), 622 hubp_regs(4) 623 }; 624 625 static const struct dcn_hubp2_shift hubp_shift = { 626 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 627 }; 628 629 static const struct dcn_hubp2_mask hubp_mask = { 630 HUBP_MASK_SH_LIST_DCN30(_MASK) 631 }; 632 633 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 634 { 635 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 636 637 if (!hubp2) 638 return NULL; 639 640 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 641 return &hubp2->base; 642 643 BREAK_TO_DEBUGGER(); 644 kfree(hubp2); 645 return NULL; 646 } 647 648 #define dpp_regs(id)\ 649 [id] = { DPP_REG_LIST_DCN30(id) } 650 651 static const struct dcn3_dpp_registers dpp_regs[] = { 652 dpp_regs(0), 653 dpp_regs(1), 654 dpp_regs(2), 655 dpp_regs(3), 656 dpp_regs(4) 657 }; 658 659 static const struct dcn3_dpp_shift tf_shift = { 660 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 661 }; 662 663 static const struct dcn3_dpp_mask tf_mask = { 664 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 665 }; 666 667 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 668 { 669 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 670 671 if (!dpp) 672 return NULL; 673 674 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 675 return &dpp->base; 676 677 BREAK_TO_DEBUGGER(); 678 kfree(dpp); 679 return NULL; 680 } 681 682 #define opp_regs(id)\ 683 [id] = { OPP_REG_LIST_DCN30(id) } 684 685 static const struct dcn20_opp_registers opp_regs[] = { 686 opp_regs(0), 687 opp_regs(1), 688 opp_regs(2), 689 opp_regs(3), 690 opp_regs(4) 691 }; 692 693 static const struct dcn20_opp_shift opp_shift = { 694 OPP_MASK_SH_LIST_DCN20(__SHIFT) 695 }; 696 697 static const struct dcn20_opp_mask opp_mask = { 698 OPP_MASK_SH_LIST_DCN20(_MASK) 699 }; 700 701 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 702 { 703 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 704 705 if (!opp) { 706 BREAK_TO_DEBUGGER(); 707 return NULL; 708 } 709 710 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 711 return &opp->base; 712 } 713 714 #define optc_regs(id)\ 715 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 716 717 static const struct dcn_optc_registers optc_regs[] = { 718 optc_regs(0), 719 optc_regs(1), 720 optc_regs(2), 721 optc_regs(3), 722 optc_regs(4) 723 }; 724 725 static const struct dcn_optc_shift optc_shift = { 726 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 727 }; 728 729 static const struct dcn_optc_mask optc_mask = { 730 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 731 }; 732 733 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 734 { 735 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 736 737 if (!tgn10) 738 return NULL; 739 740 tgn10->base.inst = instance; 741 tgn10->base.ctx = ctx; 742 743 tgn10->tg_regs = &optc_regs[instance]; 744 tgn10->tg_shift = &optc_shift; 745 tgn10->tg_mask = &optc_mask; 746 747 dcn30_timing_generator_init(tgn10); 748 749 return &tgn10->base; 750 } 751 752 static const struct dcn30_mpc_registers mpc_regs = { 753 MPC_REG_LIST_DCN3_0(0), 754 MPC_REG_LIST_DCN3_0(1), 755 MPC_REG_LIST_DCN3_0(2), 756 MPC_REG_LIST_DCN3_0(3), 757 MPC_REG_LIST_DCN3_0(4), 758 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 759 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 760 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 761 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 762 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 763 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 764 MPC_RMU_REG_LIST_DCN3AG(0), 765 MPC_RMU_REG_LIST_DCN3AG(1), 766 MPC_RMU_REG_LIST_DCN3AG(2), 767 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 768 }; 769 770 static const struct dcn30_mpc_shift mpc_shift = { 771 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 772 }; 773 774 static const struct dcn30_mpc_mask mpc_mask = { 775 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 776 }; 777 778 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 779 { 780 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 781 782 if (!mpc30) 783 return NULL; 784 785 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 786 787 return &mpc30->base; 788 } 789 790 #define dsc_regsDCN20(id)\ 791 [id] = { DSC_REG_LIST_DCN20(id) } 792 793 static const struct dcn20_dsc_registers dsc_regs[] = { 794 dsc_regsDCN20(0), 795 dsc_regsDCN20(1), 796 dsc_regsDCN20(2), 797 dsc_regsDCN20(3), 798 dsc_regsDCN20(4) 799 }; 800 801 static const struct dcn20_dsc_shift dsc_shift = { 802 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 803 }; 804 805 static const struct dcn20_dsc_mask dsc_mask = { 806 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 807 }; 808 809 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 810 { 811 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 812 813 if (!dsc) { 814 BREAK_TO_DEBUGGER(); 815 return NULL; 816 } 817 818 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 819 return &dsc->base; 820 } 821 822 #define dwbc_regs_dcn3(id)\ 823 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 824 825 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 826 dwbc_regs_dcn3(0) 827 }; 828 829 static const struct dcn30_dwbc_shift dwbc30_shift = { 830 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 831 }; 832 833 static const struct dcn30_dwbc_mask dwbc30_mask = { 834 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 835 }; 836 837 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 838 { 839 int i; 840 uint32_t pipe_count = pool->res_cap->num_dwb; 841 842 for (i = 0; i < pipe_count; i++) { 843 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 844 845 if (!dwbc30) { 846 dm_error("DC: failed to create dwbc30!\n"); 847 return false; 848 } 849 850 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 851 852 pool->dwbc[i] = &dwbc30->base; 853 } 854 return true; 855 } 856 857 #define mcif_wb_regs_dcn3(id)\ 858 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 859 860 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 861 mcif_wb_regs_dcn3(0) 862 }; 863 864 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 865 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 866 }; 867 868 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 869 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 870 }; 871 872 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 873 { 874 int i; 875 uint32_t pipe_count = pool->res_cap->num_dwb; 876 877 for (i = 0; i < pipe_count; i++) { 878 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 879 880 if (!mcif_wb30) { 881 dm_error("DC: failed to create mcif_wb30!\n"); 882 return false; 883 } 884 885 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 886 887 pool->mcif_wb[i] = &mcif_wb30->base; 888 } 889 return true; 890 } 891 892 #define aux_engine_regs(id)\ 893 [id] = {\ 894 AUX_COMMON_REG_LIST0(id), \ 895 .AUXN_IMPCAL = 0, \ 896 .AUXP_IMPCAL = 0, \ 897 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 898 } 899 900 static const struct dce110_aux_registers aux_engine_regs[] = { 901 aux_engine_regs(0), 902 aux_engine_regs(1), 903 aux_engine_regs(2), 904 aux_engine_regs(3), 905 aux_engine_regs(4) 906 }; 907 908 static const struct dce110_aux_registers_shift aux_shift = { 909 DCN_AUX_MASK_SH_LIST(__SHIFT) 910 }; 911 912 static const struct dce110_aux_registers_mask aux_mask = { 913 DCN_AUX_MASK_SH_LIST(_MASK) 914 }; 915 916 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 917 { 918 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 919 920 if (!aux_engine) 921 return NULL; 922 923 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 924 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 925 926 return &aux_engine->base; 927 } 928 929 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 930 931 static const struct dce_i2c_registers i2c_hw_regs[] = { 932 i2c_inst_regs(1), 933 i2c_inst_regs(2), 934 i2c_inst_regs(3), 935 i2c_inst_regs(4), 936 i2c_inst_regs(5) 937 }; 938 939 static const struct dce_i2c_shift i2c_shifts = { 940 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 941 }; 942 943 static const struct dce_i2c_mask i2c_masks = { 944 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 945 }; 946 947 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 948 { 949 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 950 951 if (!dce_i2c_hw) 952 return NULL; 953 954 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 955 956 return dce_i2c_hw; 957 } 958 959 static const struct encoder_feature_support link_enc_feature = { 960 .max_hdmi_deep_color = COLOR_DEPTH_121212, 961 .max_hdmi_pixel_clock = 600000, 962 .hdmi_ycbcr420_supported = true, 963 .dp_ycbcr420_supported = true, 964 .fec_supported = true, 965 .flags.bits.IS_HBR2_CAPABLE = true, 966 .flags.bits.IS_HBR3_CAPABLE = true, 967 .flags.bits.IS_TPS3_CAPABLE = true, 968 .flags.bits.IS_TPS4_CAPABLE = true 969 }; 970 971 #define link_regs(id, phyid)\ 972 [id] = {\ 973 LE_DCN3_REG_LIST(id), \ 974 UNIPHY_DCN2_REG_LIST(phyid), \ 975 DPCS_DCN2_REG_LIST(id), \ 976 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 977 } 978 979 static const struct dcn10_link_enc_registers link_enc_regs[] = { 980 link_regs(0, A), 981 link_regs(1, B), 982 link_regs(2, C), 983 link_regs(3, D), 984 link_regs(4, E) 985 }; 986 987 static const struct dcn10_link_enc_shift le_shift = { 988 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 989 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 990 }; 991 992 static const struct dcn10_link_enc_mask le_mask = { 993 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 994 DPCS_DCN2_MASK_SH_LIST(_MASK) 995 }; 996 997 #define aux_regs(id)\ 998 [id] = { DCN2_AUX_REG_LIST(id) } 999 1000 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1001 aux_regs(0), 1002 aux_regs(1), 1003 aux_regs(2), 1004 aux_regs(3), 1005 aux_regs(4) 1006 }; 1007 1008 #define hpd_regs(id)\ 1009 [id] = { HPD_REG_LIST(id) } 1010 1011 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1012 hpd_regs(0), 1013 hpd_regs(1), 1014 hpd_regs(2), 1015 hpd_regs(3), 1016 hpd_regs(4) 1017 }; 1018 1019 static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data) 1020 { 1021 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1022 1023 if (!enc20) 1024 return NULL; 1025 1026 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 1027 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 1028 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 1029 1030 return &enc20->enc10.base; 1031 } 1032 1033 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1034 { DCN_PANEL_CNTL_REG_LIST() } 1035 }; 1036 1037 static const struct dce_panel_cntl_shift panel_cntl_shift = { 1038 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1039 }; 1040 1041 static const struct dce_panel_cntl_mask panel_cntl_mask = { 1042 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1043 }; 1044 1045 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1046 { 1047 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1048 1049 if (!panel_cntl) 1050 return NULL; 1051 1052 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 1053 &panel_cntl_shift, &panel_cntl_mask); 1054 1055 return &panel_cntl->base; 1056 } 1057 1058 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 1059 { 1060 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1061 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1062 } 1063 1064 static const struct resource_create_funcs res_create_funcs = { 1065 .read_dce_straps = read_dce_straps, 1066 .create_audio = dcn302_create_audio, 1067 .create_stream_encoder = dcn302_stream_encoder_create, 1068 .create_hwseq = dcn302_hwseq_create, 1069 }; 1070 1071 static const struct resource_create_funcs res_create_maximus_funcs = { 1072 .read_dce_straps = NULL, 1073 .create_audio = NULL, 1074 .create_stream_encoder = NULL, 1075 .create_hwseq = dcn302_hwseq_create, 1076 }; 1077 1078 static bool is_soc_bounding_box_valid(struct dc *dc) 1079 { 1080 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1081 1082 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 1083 return true; 1084 1085 return false; 1086 } 1087 1088 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 1089 { 1090 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 1091 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 1092 1093 DC_LOGGER_INIT(dc->ctx->logger); 1094 1095 if (!is_soc_bounding_box_valid(dc)) { 1096 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1097 return false; 1098 } 1099 1100 loaded_ip->max_num_otg = pool->pipe_count; 1101 loaded_ip->max_num_dpp = pool->pipe_count; 1102 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1103 dcn20_patch_bounding_box(dc, loaded_bb); 1104 return true; 1105 } 1106 1107 static void dcn302_resource_destruct(struct resource_pool *pool) 1108 { 1109 unsigned int i; 1110 1111 for (i = 0; i < pool->stream_enc_count; i++) { 1112 if (pool->stream_enc[i] != NULL) { 1113 if (pool->stream_enc[i]->vpg != NULL) { 1114 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1115 pool->stream_enc[i]->vpg = NULL; 1116 } 1117 if (pool->stream_enc[i]->afmt != NULL) { 1118 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1119 pool->stream_enc[i]->afmt = NULL; 1120 } 1121 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1122 pool->stream_enc[i] = NULL; 1123 } 1124 } 1125 1126 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1127 if (pool->dscs[i] != NULL) 1128 dcn20_dsc_destroy(&pool->dscs[i]); 1129 } 1130 1131 if (pool->mpc != NULL) { 1132 kfree(TO_DCN20_MPC(pool->mpc)); 1133 pool->mpc = NULL; 1134 } 1135 1136 if (pool->hubbub != NULL) { 1137 kfree(pool->hubbub); 1138 pool->hubbub = NULL; 1139 } 1140 1141 for (i = 0; i < pool->pipe_count; i++) { 1142 if (pool->dpps[i] != NULL) { 1143 kfree(TO_DCN20_DPP(pool->dpps[i])); 1144 pool->dpps[i] = NULL; 1145 } 1146 1147 if (pool->hubps[i] != NULL) { 1148 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1149 pool->hubps[i] = NULL; 1150 } 1151 1152 if (pool->irqs != NULL) 1153 dal_irq_service_destroy(&pool->irqs); 1154 } 1155 1156 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1157 if (pool->engines[i] != NULL) 1158 dce110_engine_destroy(&pool->engines[i]); 1159 if (pool->hw_i2cs[i] != NULL) { 1160 kfree(pool->hw_i2cs[i]); 1161 pool->hw_i2cs[i] = NULL; 1162 } 1163 if (pool->sw_i2cs[i] != NULL) { 1164 kfree(pool->sw_i2cs[i]); 1165 pool->sw_i2cs[i] = NULL; 1166 } 1167 } 1168 1169 for (i = 0; i < pool->res_cap->num_opp; i++) { 1170 if (pool->opps[i] != NULL) 1171 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1172 } 1173 1174 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1175 if (pool->timing_generators[i] != NULL) { 1176 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1177 pool->timing_generators[i] = NULL; 1178 } 1179 } 1180 1181 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1182 if (pool->dwbc[i] != NULL) { 1183 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1184 pool->dwbc[i] = NULL; 1185 } 1186 if (pool->mcif_wb[i] != NULL) { 1187 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1188 pool->mcif_wb[i] = NULL; 1189 } 1190 } 1191 1192 for (i = 0; i < pool->audio_count; i++) { 1193 if (pool->audios[i]) 1194 dce_aud_destroy(&pool->audios[i]); 1195 } 1196 1197 for (i = 0; i < pool->clk_src_count; i++) { 1198 if (pool->clock_sources[i] != NULL) 1199 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1200 } 1201 1202 if (pool->dp_clock_source != NULL) 1203 dcn20_clock_source_destroy(&pool->dp_clock_source); 1204 1205 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1206 if (pool->mpc_lut[i] != NULL) { 1207 dc_3dlut_func_release(pool->mpc_lut[i]); 1208 pool->mpc_lut[i] = NULL; 1209 } 1210 if (pool->mpc_shaper[i] != NULL) { 1211 dc_transfer_func_release(pool->mpc_shaper[i]); 1212 pool->mpc_shaper[i] = NULL; 1213 } 1214 } 1215 1216 for (i = 0; i < pool->pipe_count; i++) { 1217 if (pool->multiple_abms[i] != NULL) 1218 dce_abm_destroy(&pool->multiple_abms[i]); 1219 } 1220 1221 if (pool->psr != NULL) 1222 dmub_psr_destroy(&pool->psr); 1223 1224 if (pool->dccg != NULL) 1225 dcn_dccg_destroy(&pool->dccg); 1226 } 1227 1228 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1229 { 1230 dcn302_resource_destruct(*pool); 1231 kfree(*pool); 1232 *pool = NULL; 1233 } 1234 1235 static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1236 unsigned int *optimal_dcfclk, 1237 unsigned int *optimal_fclk) 1238 { 1239 double bw_from_dram, bw_from_dram1, bw_from_dram2; 1240 1241 bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans * 1242 dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_dram_bw_use_normal_percent / 100); 1243 bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans * 1244 dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100); 1245 1246 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1247 1248 if (optimal_fclk) 1249 *optimal_fclk = bw_from_dram / 1250 (dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1251 1252 if (optimal_dcfclk) 1253 *optimal_dcfclk = bw_from_dram / 1254 (dcn3_02_soc.return_bus_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1255 } 1256 1257 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1258 { 1259 unsigned int i, j; 1260 unsigned int num_states = 0; 1261 1262 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 1263 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 1264 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 1265 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 1266 1267 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; 1268 unsigned int num_dcfclk_sta_targets = 4; 1269 unsigned int num_uclk_states; 1270 1271 1272 if (dc->ctx->dc_bios->vram_info.num_chans) 1273 dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 1274 1275 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 1276 dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 1277 1278 dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1279 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1280 1281 if (bw_params->clk_table.entries[0].memclk_mhz) { 1282 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 1283 1284 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 1285 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 1286 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 1287 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 1288 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 1289 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 1290 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 1291 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 1292 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 1293 } 1294 if (!max_dcfclk_mhz) 1295 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; 1296 if (!max_dispclk_mhz) 1297 max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; 1298 if (!max_dppclk_mhz) 1299 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; 1300 if (!max_phyclk_mhz) 1301 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; 1302 1303 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1304 /* If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array */ 1305 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 1306 num_dcfclk_sta_targets++; 1307 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1308 /* If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates */ 1309 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1310 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 1311 dcfclk_sta_targets[i] = max_dcfclk_mhz; 1312 break; 1313 } 1314 } 1315 /* Update size of array since we "removed" duplicates */ 1316 num_dcfclk_sta_targets = i + 1; 1317 } 1318 1319 num_uclk_states = bw_params->clk_table.num_entries; 1320 1321 /* Calculate optimal dcfclk for each uclk */ 1322 for (i = 0; i < num_uclk_states; i++) { 1323 dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 1324 &optimal_dcfclk_for_uclk[i], NULL); 1325 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 1326 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 1327 } 1328 } 1329 1330 /* Calculate optimal uclk for each dcfclk sta target */ 1331 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1332 for (j = 0; j < num_uclk_states; j++) { 1333 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 1334 optimal_uclk_for_dcfclk_sta_targets[i] = 1335 bw_params->clk_table.entries[j].memclk_mhz * 16; 1336 break; 1337 } 1338 } 1339 } 1340 1341 i = 0; 1342 j = 0; 1343 /* create the final dcfclk and uclk table */ 1344 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 1345 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 1346 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1347 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1348 } else { 1349 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1350 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1351 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1352 } else { 1353 j = num_uclk_states; 1354 } 1355 } 1356 } 1357 1358 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 1359 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1360 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1361 } 1362 1363 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 1364 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1365 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1366 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1367 } 1368 1369 dcn3_02_soc.num_states = num_states; 1370 for (i = 0; i < dcn3_02_soc.num_states; i++) { 1371 dcn3_02_soc.clock_limits[i].state = i; 1372 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 1373 dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 1374 dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 1375 1376 /* Fill all states with max values of all other clocks */ 1377 dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1378 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1379 dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1380 dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz; 1381 /* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */ 1382 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 1383 dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz; 1384 dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[0].socclk_mhz; 1385 dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz; 1386 } 1387 /* re-init DML with updated bb */ 1388 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1389 if (dc->current_state) 1390 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1391 } 1392 } 1393 1394 static struct resource_funcs dcn302_res_pool_funcs = { 1395 .destroy = dcn302_destroy_resource_pool, 1396 .link_enc_create = dcn302_link_encoder_create, 1397 .panel_cntl_create = dcn302_panel_cntl_create, 1398 .validate_bandwidth = dcn30_validate_bandwidth, 1399 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1400 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1401 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1402 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1403 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1404 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1405 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1406 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1407 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1408 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1409 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1410 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1411 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1412 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1413 }; 1414 1415 static struct dc_cap_funcs cap_funcs = { 1416 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1417 }; 1418 1419 static const struct bios_registers bios_regs = { 1420 NBIO_SR(BIOS_SCRATCH_3), 1421 NBIO_SR(BIOS_SCRATCH_6) 1422 }; 1423 1424 static const struct dccg_registers dccg_regs = { 1425 DCCG_REG_LIST_DCN3_02() 1426 }; 1427 1428 static const struct dccg_shift dccg_shift = { 1429 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1430 }; 1431 1432 static const struct dccg_mask dccg_mask = { 1433 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1434 }; 1435 1436 #define abm_regs(id)\ 1437 [id] = { ABM_DCN301_REG_LIST(id) } 1438 1439 static const struct dce_abm_registers abm_regs[] = { 1440 abm_regs(0), 1441 abm_regs(1), 1442 abm_regs(2), 1443 abm_regs(3), 1444 abm_regs(4) 1445 }; 1446 1447 static const struct dce_abm_shift abm_shift = { 1448 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1449 }; 1450 1451 static const struct dce_abm_mask abm_mask = { 1452 ABM_MASK_SH_LIST_DCN30(_MASK) 1453 }; 1454 1455 static bool dcn302_resource_construct( 1456 uint8_t num_virtual_links, 1457 struct dc *dc, 1458 struct resource_pool *pool) 1459 { 1460 int i; 1461 struct dc_context *ctx = dc->ctx; 1462 struct irq_service_init_data init_data; 1463 1464 ctx->dc_bios->regs = &bios_regs; 1465 1466 pool->res_cap = &res_cap_dcn302; 1467 1468 pool->funcs = &dcn302_res_pool_funcs; 1469 1470 /************************************************* 1471 * Resource + asic cap harcoding * 1472 *************************************************/ 1473 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1474 pool->pipe_count = pool->res_cap->num_timing_generator; 1475 pool->mpcc_count = pool->res_cap->num_timing_generator; 1476 dc->caps.max_downscale_ratio = 600; 1477 dc->caps.i2c_speed_in_khz = 100; 1478 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1479 dc->caps.max_cursor_size = 256; 1480 dc->caps.min_horizontal_blanking_period = 80; 1481 dc->caps.dmdata_alloc_size = 2048; 1482 dc->caps.mall_size_per_mem_channel = 4; 1483 /* total size = mall per channel * num channels * 1024 * 1024 */ 1484 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1485 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1486 dc->caps.max_slave_planes = 1; 1487 dc->caps.max_slave_yuv_planes = 1; 1488 dc->caps.max_slave_rgb_planes = 1; 1489 dc->caps.post_blend_color_processing = true; 1490 dc->caps.force_dp_tps4_for_cp2520 = true; 1491 dc->caps.extended_aux_timeout_support = true; 1492 dc->caps.dmcub_support = true; 1493 1494 /* Color pipeline capabilities */ 1495 dc->caps.color.dpp.dcn_arch = 1; 1496 dc->caps.color.dpp.input_lut_shared = 0; 1497 dc->caps.color.dpp.icsc = 1; 1498 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1499 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1500 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1501 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1502 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1503 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1504 dc->caps.color.dpp.post_csc = 1; 1505 dc->caps.color.dpp.gamma_corr = 1; 1506 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1507 1508 dc->caps.color.dpp.hw_3d_lut = 1; 1509 dc->caps.color.dpp.ogam_ram = 1; 1510 // no OGAM ROM on DCN3 1511 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1512 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1513 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1514 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1515 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1516 dc->caps.color.dpp.ocsc = 0; 1517 1518 dc->caps.color.mpc.gamut_remap = 1; 1519 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1520 dc->caps.color.mpc.ogam_ram = 1; 1521 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1522 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1523 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1524 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1525 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1526 dc->caps.color.mpc.ocsc = 1; 1527 1528 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1529 dc->debug = debug_defaults_drv; 1530 else 1531 dc->debug = debug_defaults_diags; 1532 1533 // Init the vm_helper 1534 if (dc->vm_helper) 1535 vm_helper_init(dc->vm_helper, 16); 1536 1537 /************************************************* 1538 * Create resources * 1539 *************************************************/ 1540 1541 /* Clock Sources for Pixel Clock*/ 1542 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1543 dcn302_clock_source_create(ctx, ctx->dc_bios, 1544 CLOCK_SOURCE_COMBO_PHY_PLL0, 1545 &clk_src_regs[0], false); 1546 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1547 dcn302_clock_source_create(ctx, ctx->dc_bios, 1548 CLOCK_SOURCE_COMBO_PHY_PLL1, 1549 &clk_src_regs[1], false); 1550 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1551 dcn302_clock_source_create(ctx, ctx->dc_bios, 1552 CLOCK_SOURCE_COMBO_PHY_PLL2, 1553 &clk_src_regs[2], false); 1554 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1555 dcn302_clock_source_create(ctx, ctx->dc_bios, 1556 CLOCK_SOURCE_COMBO_PHY_PLL3, 1557 &clk_src_regs[3], false); 1558 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1559 dcn302_clock_source_create(ctx, ctx->dc_bios, 1560 CLOCK_SOURCE_COMBO_PHY_PLL4, 1561 &clk_src_regs[4], false); 1562 1563 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1564 1565 /* todo: not reuse phy_pll registers */ 1566 pool->dp_clock_source = 1567 dcn302_clock_source_create(ctx, ctx->dc_bios, 1568 CLOCK_SOURCE_ID_DP_DTO, 1569 &clk_src_regs[0], true); 1570 1571 for (i = 0; i < pool->clk_src_count; i++) { 1572 if (pool->clock_sources[i] == NULL) { 1573 dm_error("DC: failed to create clock sources!\n"); 1574 BREAK_TO_DEBUGGER(); 1575 goto create_fail; 1576 } 1577 } 1578 1579 /* DCCG */ 1580 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1581 if (pool->dccg == NULL) { 1582 dm_error("DC: failed to create dccg!\n"); 1583 BREAK_TO_DEBUGGER(); 1584 goto create_fail; 1585 } 1586 1587 /* PP Lib and SMU interfaces */ 1588 init_soc_bounding_box(dc, pool); 1589 1590 /* DML */ 1591 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1592 1593 /* IRQ */ 1594 init_data.ctx = dc->ctx; 1595 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1596 if (!pool->irqs) 1597 goto create_fail; 1598 1599 /* HUBBUB */ 1600 pool->hubbub = dcn302_hubbub_create(ctx); 1601 if (pool->hubbub == NULL) { 1602 BREAK_TO_DEBUGGER(); 1603 dm_error("DC: failed to create hubbub!\n"); 1604 goto create_fail; 1605 } 1606 1607 /* HUBPs, DPPs, OPPs and TGs */ 1608 for (i = 0; i < pool->pipe_count; i++) { 1609 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1610 if (pool->hubps[i] == NULL) { 1611 BREAK_TO_DEBUGGER(); 1612 dm_error("DC: failed to create hubps!\n"); 1613 goto create_fail; 1614 } 1615 1616 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1617 if (pool->dpps[i] == NULL) { 1618 BREAK_TO_DEBUGGER(); 1619 dm_error("DC: failed to create dpps!\n"); 1620 goto create_fail; 1621 } 1622 } 1623 1624 for (i = 0; i < pool->res_cap->num_opp; i++) { 1625 pool->opps[i] = dcn302_opp_create(ctx, i); 1626 if (pool->opps[i] == NULL) { 1627 BREAK_TO_DEBUGGER(); 1628 dm_error("DC: failed to create output pixel processor!\n"); 1629 goto create_fail; 1630 } 1631 } 1632 1633 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1634 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1635 if (pool->timing_generators[i] == NULL) { 1636 BREAK_TO_DEBUGGER(); 1637 dm_error("DC: failed to create tg!\n"); 1638 goto create_fail; 1639 } 1640 } 1641 pool->timing_generator_count = i; 1642 1643 /* PSR */ 1644 pool->psr = dmub_psr_create(ctx); 1645 if (pool->psr == NULL) { 1646 dm_error("DC: failed to create psr!\n"); 1647 BREAK_TO_DEBUGGER(); 1648 goto create_fail; 1649 } 1650 1651 /* ABMs */ 1652 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1653 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1654 if (pool->multiple_abms[i] == NULL) { 1655 dm_error("DC: failed to create abm for pipe %d!\n", i); 1656 BREAK_TO_DEBUGGER(); 1657 goto create_fail; 1658 } 1659 } 1660 1661 /* MPC and DSC */ 1662 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1663 if (pool->mpc == NULL) { 1664 BREAK_TO_DEBUGGER(); 1665 dm_error("DC: failed to create mpc!\n"); 1666 goto create_fail; 1667 } 1668 1669 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1670 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1671 if (pool->dscs[i] == NULL) { 1672 BREAK_TO_DEBUGGER(); 1673 dm_error("DC: failed to create display stream compressor %d!\n", i); 1674 goto create_fail; 1675 } 1676 } 1677 1678 /* DWB and MMHUBBUB */ 1679 if (!dcn302_dwbc_create(ctx, pool)) { 1680 BREAK_TO_DEBUGGER(); 1681 dm_error("DC: failed to create dwbc!\n"); 1682 goto create_fail; 1683 } 1684 1685 if (!dcn302_mmhubbub_create(ctx, pool)) { 1686 BREAK_TO_DEBUGGER(); 1687 dm_error("DC: failed to create mcif_wb!\n"); 1688 goto create_fail; 1689 } 1690 1691 /* AUX and I2C */ 1692 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1693 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1694 if (pool->engines[i] == NULL) { 1695 BREAK_TO_DEBUGGER(); 1696 dm_error("DC:failed to create aux engine!!\n"); 1697 goto create_fail; 1698 } 1699 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1700 if (pool->hw_i2cs[i] == NULL) { 1701 BREAK_TO_DEBUGGER(); 1702 dm_error("DC:failed to create hw i2c!!\n"); 1703 goto create_fail; 1704 } 1705 pool->sw_i2cs[i] = NULL; 1706 } 1707 1708 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1709 if (!resource_construct(num_virtual_links, dc, pool, 1710 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1711 &res_create_funcs : &res_create_maximus_funcs))) 1712 goto create_fail; 1713 1714 /* HW Sequencer and Plane caps */ 1715 dcn302_hw_sequencer_construct(dc); 1716 1717 dc->caps.max_planes = pool->pipe_count; 1718 1719 for (i = 0; i < dc->caps.max_planes; ++i) 1720 dc->caps.planes[i] = plane_cap; 1721 1722 dc->cap_funcs = cap_funcs; 1723 1724 return true; 1725 1726 create_fail: 1727 1728 dcn302_resource_destruct(pool); 1729 1730 return false; 1731 } 1732 1733 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1734 { 1735 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1736 1737 if (!pool) 1738 return NULL; 1739 1740 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1741 return pool; 1742 1743 BREAK_TO_DEBUGGER(); 1744 kfree(pool); 1745 return NULL; 1746 } 1747