1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dml/dcn30/dcn30_fpu.h" 47 48 #include "dcn10/dcn10_resource.h" 49 50 #include "dce/dce_abm.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_clock_source.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_i2c_hw.h" 56 #include "dce/dce_panel_cntl.h" 57 #include "dce/dmub_abm.h" 58 #include "dce/dmub_psr.h" 59 #include "clk_mgr.h" 60 61 #include "hw_sequencer_private.h" 62 #include "reg_helper.h" 63 #include "resource.h" 64 #include "vm_helper.h" 65 66 #include "dml/dcn302/dcn302_fpu.h" 67 68 #include "dimgrey_cavefish_ip_offset.h" 69 #include "dcn/dcn_3_0_2_offset.h" 70 #include "dcn/dcn_3_0_2_sh_mask.h" 71 #include "dpcs/dpcs_3_0_0_offset.h" 72 #include "dpcs/dpcs_3_0_0_sh_mask.h" 73 #include "nbio/nbio_7_4_offset.h" 74 #include "amdgpu_socbb.h" 75 76 #define DC_LOGGER_INIT(logger) 77 78 static const struct dc_debug_options debug_defaults_drv = { 79 .disable_dmcu = true, 80 .force_abm_enable = false, 81 .timing_trace = false, 82 .clock_trace = true, 83 .disable_pplib_clock_request = true, 84 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 85 .force_single_disp_pipe_split = false, 86 .disable_dcc = DCC_ENABLE, 87 .vsr_support = true, 88 .performance_trace = false, 89 .max_downscale_src_width = 7680,/*upto 8K*/ 90 .disable_pplib_wm_range = false, 91 .scl_reset_length10 = true, 92 .sanity_checks = false, 93 .underflow_assert_delay_us = 0xFFFFFFFF, 94 .dwb_fi_phase = -1, // -1 = disable, 95 .dmub_command_table = true, 96 .use_max_lb = true, 97 .exit_idle_opt_for_cursor_updates = true 98 }; 99 100 static const struct dc_debug_options debug_defaults_diags = { 101 .disable_dmcu = true, 102 .force_abm_enable = false, 103 .timing_trace = true, 104 .clock_trace = true, 105 .disable_dpp_power_gate = true, 106 .disable_hubp_power_gate = true, 107 .disable_clock_gate = true, 108 .disable_pplib_clock_request = true, 109 .disable_pplib_wm_range = true, 110 .disable_stutter = false, 111 .scl_reset_length10 = true, 112 .dwb_fi_phase = -1, // -1 = disable 113 .dmub_command_table = true, 114 .enable_tri_buf = true, 115 .disable_psr = true, 116 .use_max_lb = true 117 }; 118 119 enum dcn302_clk_src_array_id { 120 DCN302_CLK_SRC_PLL0, 121 DCN302_CLK_SRC_PLL1, 122 DCN302_CLK_SRC_PLL2, 123 DCN302_CLK_SRC_PLL3, 124 DCN302_CLK_SRC_PLL4, 125 DCN302_CLK_SRC_TOTAL 126 }; 127 128 static const struct resource_caps res_cap_dcn302 = { 129 .num_timing_generator = 5, 130 .num_opp = 5, 131 .num_video_plane = 5, 132 .num_audio = 5, 133 .num_stream_encoder = 5, 134 .num_dwb = 1, 135 .num_ddc = 5, 136 .num_vmid = 16, 137 .num_mpc_3dlut = 2, 138 .num_dsc = 5, 139 }; 140 141 static const struct dc_plane_cap plane_cap = { 142 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 143 .blends_with_above = true, 144 .blends_with_below = true, 145 .per_pixel_alpha = true, 146 .pixel_format_support = { 147 .argb8888 = true, 148 .nv12 = true, 149 .fp16 = true, 150 .p010 = true, 151 .ayuv = false, 152 }, 153 .max_upscale_factor = { 154 .argb8888 = 16000, 155 .nv12 = 16000, 156 .fp16 = 16000 157 }, 158 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 159 .max_downscale_factor = { 160 .argb8888 = 167, 161 .nv12 = 167, 162 .fp16 = 167 163 }, 164 16, 165 16 166 }; 167 168 /* NBIO */ 169 #define NBIO_BASE_INNER(seg) \ 170 NBIO_BASE__INST0_SEG ## seg 171 172 #define NBIO_BASE(seg) \ 173 NBIO_BASE_INNER(seg) 174 175 #define NBIO_SR(reg_name)\ 176 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 177 mm ## reg_name 178 179 /* DCN */ 180 #undef BASE_INNER 181 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 182 183 #define BASE(seg) BASE_INNER(seg) 184 185 #define SR(reg_name)\ 186 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 187 188 #define SF(reg_name, field_name, post_fix)\ 189 .field_name = reg_name ## __ ## field_name ## post_fix 190 191 #define SRI(reg_name, block, id)\ 192 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 193 194 #define SRI2(reg_name, block, id)\ 195 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 196 197 #define SRII(reg_name, block, id)\ 198 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 199 mm ## block ## id ## _ ## reg_name 200 201 #define DCCG_SRII(reg_name, block, id)\ 202 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 203 mm ## block ## id ## _ ## reg_name 204 205 #define VUPDATE_SRII(reg_name, block, id)\ 206 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 207 mm ## reg_name ## _ ## block ## id 208 209 #define SRII_DWB(reg_name, temp_name, block, id)\ 210 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 211 mm ## block ## id ## _ ## temp_name 212 213 #define SRII_MPC_RMU(reg_name, block, id)\ 214 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 215 mm ## block ## id ## _ ## reg_name 216 217 static const struct dcn_hubbub_registers hubbub_reg = { 218 HUBBUB_REG_LIST_DCN30(0) 219 }; 220 221 static const struct dcn_hubbub_shift hubbub_shift = { 222 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 223 }; 224 225 static const struct dcn_hubbub_mask hubbub_mask = { 226 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 227 }; 228 229 #define vmid_regs(id)\ 230 [id] = { DCN20_VMID_REG_LIST(id) } 231 232 static const struct dcn_vmid_registers vmid_regs[] = { 233 vmid_regs(0), 234 vmid_regs(1), 235 vmid_regs(2), 236 vmid_regs(3), 237 vmid_regs(4), 238 vmid_regs(5), 239 vmid_regs(6), 240 vmid_regs(7), 241 vmid_regs(8), 242 vmid_regs(9), 243 vmid_regs(10), 244 vmid_regs(11), 245 vmid_regs(12), 246 vmid_regs(13), 247 vmid_regs(14), 248 vmid_regs(15) 249 }; 250 251 static const struct dcn20_vmid_shift vmid_shifts = { 252 DCN20_VMID_MASK_SH_LIST(__SHIFT) 253 }; 254 255 static const struct dcn20_vmid_mask vmid_masks = { 256 DCN20_VMID_MASK_SH_LIST(_MASK) 257 }; 258 259 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 260 { 261 int i; 262 263 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 264 265 if (!hubbub3) 266 return NULL; 267 268 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 269 270 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 271 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 272 273 vmid->ctx = ctx; 274 275 vmid->regs = &vmid_regs[i]; 276 vmid->shifts = &vmid_shifts; 277 vmid->masks = &vmid_masks; 278 } 279 280 return &hubbub3->base; 281 } 282 283 #define vpg_regs(id)\ 284 [id] = { VPG_DCN3_REG_LIST(id) } 285 286 static const struct dcn30_vpg_registers vpg_regs[] = { 287 vpg_regs(0), 288 vpg_regs(1), 289 vpg_regs(2), 290 vpg_regs(3), 291 vpg_regs(4), 292 vpg_regs(5) 293 }; 294 295 static const struct dcn30_vpg_shift vpg_shift = { 296 DCN3_VPG_MASK_SH_LIST(__SHIFT) 297 }; 298 299 static const struct dcn30_vpg_mask vpg_mask = { 300 DCN3_VPG_MASK_SH_LIST(_MASK) 301 }; 302 303 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 304 { 305 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 306 307 if (!vpg3) 308 return NULL; 309 310 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 311 312 return &vpg3->base; 313 } 314 315 #define afmt_regs(id)\ 316 [id] = { AFMT_DCN3_REG_LIST(id) } 317 318 static const struct dcn30_afmt_registers afmt_regs[] = { 319 afmt_regs(0), 320 afmt_regs(1), 321 afmt_regs(2), 322 afmt_regs(3), 323 afmt_regs(4), 324 afmt_regs(5) 325 }; 326 327 static const struct dcn30_afmt_shift afmt_shift = { 328 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 329 }; 330 331 static const struct dcn30_afmt_mask afmt_mask = { 332 DCN3_AFMT_MASK_SH_LIST(_MASK) 333 }; 334 335 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 336 { 337 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 338 339 if (!afmt3) 340 return NULL; 341 342 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 343 344 return &afmt3->base; 345 } 346 347 #define audio_regs(id)\ 348 [id] = { AUD_COMMON_REG_LIST(id) } 349 350 static const struct dce_audio_registers audio_regs[] = { 351 audio_regs(0), 352 audio_regs(1), 353 audio_regs(2), 354 audio_regs(3), 355 audio_regs(4), 356 audio_regs(5), 357 audio_regs(6) 358 }; 359 360 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 361 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 362 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 363 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 364 365 static const struct dce_audio_shift audio_shift = { 366 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 367 }; 368 369 static const struct dce_audio_mask audio_mask = { 370 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 371 }; 372 373 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 374 { 375 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 376 } 377 378 #define stream_enc_regs(id)\ 379 [id] = { SE_DCN3_REG_LIST(id) } 380 381 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 382 stream_enc_regs(0), 383 stream_enc_regs(1), 384 stream_enc_regs(2), 385 stream_enc_regs(3), 386 stream_enc_regs(4) 387 }; 388 389 static const struct dcn10_stream_encoder_shift se_shift = { 390 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 391 }; 392 393 static const struct dcn10_stream_encoder_mask se_mask = { 394 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 395 }; 396 397 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 398 { 399 struct dcn10_stream_encoder *enc1; 400 struct vpg *vpg; 401 struct afmt *afmt; 402 int vpg_inst; 403 int afmt_inst; 404 405 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 406 if (eng_id <= ENGINE_ID_DIGE) { 407 vpg_inst = eng_id; 408 afmt_inst = eng_id; 409 } else 410 return NULL; 411 412 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 413 vpg = dcn302_vpg_create(ctx, vpg_inst); 414 afmt = dcn302_afmt_create(ctx, afmt_inst); 415 416 if (!enc1 || !vpg || !afmt) { 417 kfree(enc1); 418 kfree(vpg); 419 kfree(afmt); 420 return NULL; 421 } 422 423 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 424 &se_shift, &se_mask); 425 426 return &enc1->base; 427 } 428 429 #define clk_src_regs(index, pllid)\ 430 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 431 432 static const struct dce110_clk_src_regs clk_src_regs[] = { 433 clk_src_regs(0, A), 434 clk_src_regs(1, B), 435 clk_src_regs(2, C), 436 clk_src_regs(3, D), 437 clk_src_regs(4, E) 438 }; 439 440 static const struct dce110_clk_src_shift cs_shift = { 441 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 442 }; 443 444 static const struct dce110_clk_src_mask cs_mask = { 445 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 446 }; 447 448 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 449 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 450 { 451 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 452 453 if (!clk_src) 454 return NULL; 455 456 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 457 clk_src->base.dp_clk_src = dp_clk_src; 458 return &clk_src->base; 459 } 460 461 BREAK_TO_DEBUGGER(); 462 return NULL; 463 } 464 465 static const struct dce_hwseq_registers hwseq_reg = { 466 HWSEQ_DCN302_REG_LIST() 467 }; 468 469 static const struct dce_hwseq_shift hwseq_shift = { 470 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 471 }; 472 473 static const struct dce_hwseq_mask hwseq_mask = { 474 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 475 }; 476 477 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 478 { 479 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 480 481 if (hws) { 482 hws->ctx = ctx; 483 hws->regs = &hwseq_reg; 484 hws->shifts = &hwseq_shift; 485 hws->masks = &hwseq_mask; 486 } 487 return hws; 488 } 489 490 #define hubp_regs(id)\ 491 [id] = { HUBP_REG_LIST_DCN30(id) } 492 493 static const struct dcn_hubp2_registers hubp_regs[] = { 494 hubp_regs(0), 495 hubp_regs(1), 496 hubp_regs(2), 497 hubp_regs(3), 498 hubp_regs(4) 499 }; 500 501 static const struct dcn_hubp2_shift hubp_shift = { 502 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 503 }; 504 505 static const struct dcn_hubp2_mask hubp_mask = { 506 HUBP_MASK_SH_LIST_DCN30(_MASK) 507 }; 508 509 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 510 { 511 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 512 513 if (!hubp2) 514 return NULL; 515 516 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 517 return &hubp2->base; 518 519 BREAK_TO_DEBUGGER(); 520 kfree(hubp2); 521 return NULL; 522 } 523 524 #define dpp_regs(id)\ 525 [id] = { DPP_REG_LIST_DCN30(id) } 526 527 static const struct dcn3_dpp_registers dpp_regs[] = { 528 dpp_regs(0), 529 dpp_regs(1), 530 dpp_regs(2), 531 dpp_regs(3), 532 dpp_regs(4) 533 }; 534 535 static const struct dcn3_dpp_shift tf_shift = { 536 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 537 }; 538 539 static const struct dcn3_dpp_mask tf_mask = { 540 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 541 }; 542 543 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 544 { 545 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 546 547 if (!dpp) 548 return NULL; 549 550 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 551 return &dpp->base; 552 553 BREAK_TO_DEBUGGER(); 554 kfree(dpp); 555 return NULL; 556 } 557 558 #define opp_regs(id)\ 559 [id] = { OPP_REG_LIST_DCN30(id) } 560 561 static const struct dcn20_opp_registers opp_regs[] = { 562 opp_regs(0), 563 opp_regs(1), 564 opp_regs(2), 565 opp_regs(3), 566 opp_regs(4) 567 }; 568 569 static const struct dcn20_opp_shift opp_shift = { 570 OPP_MASK_SH_LIST_DCN20(__SHIFT) 571 }; 572 573 static const struct dcn20_opp_mask opp_mask = { 574 OPP_MASK_SH_LIST_DCN20(_MASK) 575 }; 576 577 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 578 { 579 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 580 581 if (!opp) { 582 BREAK_TO_DEBUGGER(); 583 return NULL; 584 } 585 586 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 587 return &opp->base; 588 } 589 590 #define optc_regs(id)\ 591 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 592 593 static const struct dcn_optc_registers optc_regs[] = { 594 optc_regs(0), 595 optc_regs(1), 596 optc_regs(2), 597 optc_regs(3), 598 optc_regs(4) 599 }; 600 601 static const struct dcn_optc_shift optc_shift = { 602 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 603 }; 604 605 static const struct dcn_optc_mask optc_mask = { 606 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 607 }; 608 609 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 610 { 611 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 612 613 if (!tgn10) 614 return NULL; 615 616 tgn10->base.inst = instance; 617 tgn10->base.ctx = ctx; 618 619 tgn10->tg_regs = &optc_regs[instance]; 620 tgn10->tg_shift = &optc_shift; 621 tgn10->tg_mask = &optc_mask; 622 623 dcn30_timing_generator_init(tgn10); 624 625 return &tgn10->base; 626 } 627 628 static const struct dcn30_mpc_registers mpc_regs = { 629 MPC_REG_LIST_DCN3_0(0), 630 MPC_REG_LIST_DCN3_0(1), 631 MPC_REG_LIST_DCN3_0(2), 632 MPC_REG_LIST_DCN3_0(3), 633 MPC_REG_LIST_DCN3_0(4), 634 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 635 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 636 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 637 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 638 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 639 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 640 MPC_RMU_REG_LIST_DCN3AG(0), 641 MPC_RMU_REG_LIST_DCN3AG(1), 642 MPC_RMU_REG_LIST_DCN3AG(2), 643 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 644 }; 645 646 static const struct dcn30_mpc_shift mpc_shift = { 647 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 648 }; 649 650 static const struct dcn30_mpc_mask mpc_mask = { 651 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 652 }; 653 654 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 655 { 656 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 657 658 if (!mpc30) 659 return NULL; 660 661 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 662 663 return &mpc30->base; 664 } 665 666 #define dsc_regsDCN20(id)\ 667 [id] = { DSC_REG_LIST_DCN20(id) } 668 669 static const struct dcn20_dsc_registers dsc_regs[] = { 670 dsc_regsDCN20(0), 671 dsc_regsDCN20(1), 672 dsc_regsDCN20(2), 673 dsc_regsDCN20(3), 674 dsc_regsDCN20(4) 675 }; 676 677 static const struct dcn20_dsc_shift dsc_shift = { 678 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 679 }; 680 681 static const struct dcn20_dsc_mask dsc_mask = { 682 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 683 }; 684 685 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 686 { 687 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 688 689 if (!dsc) { 690 BREAK_TO_DEBUGGER(); 691 return NULL; 692 } 693 694 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 695 return &dsc->base; 696 } 697 698 #define dwbc_regs_dcn3(id)\ 699 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 700 701 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 702 dwbc_regs_dcn3(0) 703 }; 704 705 static const struct dcn30_dwbc_shift dwbc30_shift = { 706 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 707 }; 708 709 static const struct dcn30_dwbc_mask dwbc30_mask = { 710 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 711 }; 712 713 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 714 { 715 int i; 716 uint32_t pipe_count = pool->res_cap->num_dwb; 717 718 for (i = 0; i < pipe_count; i++) { 719 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 720 721 if (!dwbc30) { 722 dm_error("DC: failed to create dwbc30!\n"); 723 return false; 724 } 725 726 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 727 728 pool->dwbc[i] = &dwbc30->base; 729 } 730 return true; 731 } 732 733 #define mcif_wb_regs_dcn3(id)\ 734 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 735 736 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 737 mcif_wb_regs_dcn3(0) 738 }; 739 740 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 741 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 742 }; 743 744 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 745 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 746 }; 747 748 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 749 { 750 int i; 751 uint32_t pipe_count = pool->res_cap->num_dwb; 752 753 for (i = 0; i < pipe_count; i++) { 754 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 755 756 if (!mcif_wb30) { 757 dm_error("DC: failed to create mcif_wb30!\n"); 758 return false; 759 } 760 761 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 762 763 pool->mcif_wb[i] = &mcif_wb30->base; 764 } 765 return true; 766 } 767 768 #define aux_engine_regs(id)\ 769 [id] = {\ 770 AUX_COMMON_REG_LIST0(id), \ 771 .AUXN_IMPCAL = 0, \ 772 .AUXP_IMPCAL = 0, \ 773 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 774 } 775 776 static const struct dce110_aux_registers aux_engine_regs[] = { 777 aux_engine_regs(0), 778 aux_engine_regs(1), 779 aux_engine_regs(2), 780 aux_engine_regs(3), 781 aux_engine_regs(4) 782 }; 783 784 static const struct dce110_aux_registers_shift aux_shift = { 785 DCN_AUX_MASK_SH_LIST(__SHIFT) 786 }; 787 788 static const struct dce110_aux_registers_mask aux_mask = { 789 DCN_AUX_MASK_SH_LIST(_MASK) 790 }; 791 792 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 793 { 794 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 795 796 if (!aux_engine) 797 return NULL; 798 799 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 800 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 801 802 return &aux_engine->base; 803 } 804 805 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 806 807 static const struct dce_i2c_registers i2c_hw_regs[] = { 808 i2c_inst_regs(1), 809 i2c_inst_regs(2), 810 i2c_inst_regs(3), 811 i2c_inst_regs(4), 812 i2c_inst_regs(5) 813 }; 814 815 static const struct dce_i2c_shift i2c_shifts = { 816 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 817 }; 818 819 static const struct dce_i2c_mask i2c_masks = { 820 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 821 }; 822 823 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 824 { 825 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 826 827 if (!dce_i2c_hw) 828 return NULL; 829 830 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 831 832 return dce_i2c_hw; 833 } 834 835 static const struct encoder_feature_support link_enc_feature = { 836 .max_hdmi_deep_color = COLOR_DEPTH_121212, 837 .max_hdmi_pixel_clock = 600000, 838 .hdmi_ycbcr420_supported = true, 839 .dp_ycbcr420_supported = true, 840 .fec_supported = true, 841 .flags.bits.IS_HBR2_CAPABLE = true, 842 .flags.bits.IS_HBR3_CAPABLE = true, 843 .flags.bits.IS_TPS3_CAPABLE = true, 844 .flags.bits.IS_TPS4_CAPABLE = true 845 }; 846 847 #define link_regs(id, phyid)\ 848 [id] = {\ 849 LE_DCN3_REG_LIST(id), \ 850 UNIPHY_DCN2_REG_LIST(phyid), \ 851 DPCS_DCN2_REG_LIST(id), \ 852 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 853 } 854 855 static const struct dcn10_link_enc_registers link_enc_regs[] = { 856 link_regs(0, A), 857 link_regs(1, B), 858 link_regs(2, C), 859 link_regs(3, D), 860 link_regs(4, E) 861 }; 862 863 static const struct dcn10_link_enc_shift le_shift = { 864 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 865 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 866 }; 867 868 static const struct dcn10_link_enc_mask le_mask = { 869 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 870 DPCS_DCN2_MASK_SH_LIST(_MASK) 871 }; 872 873 #define aux_regs(id)\ 874 [id] = { DCN2_AUX_REG_LIST(id) } 875 876 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 877 aux_regs(0), 878 aux_regs(1), 879 aux_regs(2), 880 aux_regs(3), 881 aux_regs(4) 882 }; 883 884 #define hpd_regs(id)\ 885 [id] = { HPD_REG_LIST(id) } 886 887 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 888 hpd_regs(0), 889 hpd_regs(1), 890 hpd_regs(2), 891 hpd_regs(3), 892 hpd_regs(4) 893 }; 894 895 static struct link_encoder *dcn302_link_encoder_create( 896 struct dc_context *ctx, 897 const struct encoder_init_data *enc_init_data) 898 { 899 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 900 901 if (!enc20) 902 return NULL; 903 904 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 905 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 906 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 907 908 return &enc20->enc10.base; 909 } 910 911 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 912 { DCN_PANEL_CNTL_REG_LIST() } 913 }; 914 915 static const struct dce_panel_cntl_shift panel_cntl_shift = { 916 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 917 }; 918 919 static const struct dce_panel_cntl_mask panel_cntl_mask = { 920 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 921 }; 922 923 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 924 { 925 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 926 927 if (!panel_cntl) 928 return NULL; 929 930 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 931 &panel_cntl_shift, &panel_cntl_mask); 932 933 return &panel_cntl->base; 934 } 935 936 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 937 { 938 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 939 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 940 } 941 942 static const struct resource_create_funcs res_create_funcs = { 943 .read_dce_straps = read_dce_straps, 944 .create_audio = dcn302_create_audio, 945 .create_stream_encoder = dcn302_stream_encoder_create, 946 .create_hwseq = dcn302_hwseq_create, 947 }; 948 949 static const struct resource_create_funcs res_create_maximus_funcs = { 950 .read_dce_straps = NULL, 951 .create_audio = NULL, 952 .create_stream_encoder = NULL, 953 .create_hwseq = dcn302_hwseq_create, 954 }; 955 956 static bool is_soc_bounding_box_valid(struct dc *dc) 957 { 958 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 959 960 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 961 return true; 962 963 return false; 964 } 965 966 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 967 { 968 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 969 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 970 971 DC_LOGGER_INIT(dc->ctx->logger); 972 973 if (!is_soc_bounding_box_valid(dc)) { 974 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 975 return false; 976 } 977 978 loaded_ip->max_num_otg = pool->pipe_count; 979 loaded_ip->max_num_dpp = pool->pipe_count; 980 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 981 DC_FP_START(); 982 dcn20_patch_bounding_box(dc, loaded_bb); 983 DC_FP_END(); 984 985 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 986 struct bp_soc_bb_info bb_info = { 0 }; 987 988 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 989 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 990 991 DC_FP_START(); 992 dcn302_fpu_init_soc_bounding_box(bb_info); 993 DC_FP_END(); 994 } 995 } 996 997 return true; 998 } 999 1000 static void dcn302_resource_destruct(struct resource_pool *pool) 1001 { 1002 unsigned int i; 1003 1004 for (i = 0; i < pool->stream_enc_count; i++) { 1005 if (pool->stream_enc[i] != NULL) { 1006 if (pool->stream_enc[i]->vpg != NULL) { 1007 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1008 pool->stream_enc[i]->vpg = NULL; 1009 } 1010 if (pool->stream_enc[i]->afmt != NULL) { 1011 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1012 pool->stream_enc[i]->afmt = NULL; 1013 } 1014 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1015 pool->stream_enc[i] = NULL; 1016 } 1017 } 1018 1019 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1020 if (pool->dscs[i] != NULL) 1021 dcn20_dsc_destroy(&pool->dscs[i]); 1022 } 1023 1024 if (pool->mpc != NULL) { 1025 kfree(TO_DCN20_MPC(pool->mpc)); 1026 pool->mpc = NULL; 1027 } 1028 1029 if (pool->hubbub != NULL) { 1030 kfree(pool->hubbub); 1031 pool->hubbub = NULL; 1032 } 1033 1034 for (i = 0; i < pool->pipe_count; i++) { 1035 if (pool->dpps[i] != NULL) { 1036 kfree(TO_DCN20_DPP(pool->dpps[i])); 1037 pool->dpps[i] = NULL; 1038 } 1039 1040 if (pool->hubps[i] != NULL) { 1041 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1042 pool->hubps[i] = NULL; 1043 } 1044 1045 if (pool->irqs != NULL) 1046 dal_irq_service_destroy(&pool->irqs); 1047 } 1048 1049 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1050 if (pool->engines[i] != NULL) 1051 dce110_engine_destroy(&pool->engines[i]); 1052 if (pool->hw_i2cs[i] != NULL) { 1053 kfree(pool->hw_i2cs[i]); 1054 pool->hw_i2cs[i] = NULL; 1055 } 1056 if (pool->sw_i2cs[i] != NULL) { 1057 kfree(pool->sw_i2cs[i]); 1058 pool->sw_i2cs[i] = NULL; 1059 } 1060 } 1061 1062 for (i = 0; i < pool->res_cap->num_opp; i++) { 1063 if (pool->opps[i] != NULL) 1064 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1065 } 1066 1067 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1068 if (pool->timing_generators[i] != NULL) { 1069 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1070 pool->timing_generators[i] = NULL; 1071 } 1072 } 1073 1074 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1075 if (pool->dwbc[i] != NULL) { 1076 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1077 pool->dwbc[i] = NULL; 1078 } 1079 if (pool->mcif_wb[i] != NULL) { 1080 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1081 pool->mcif_wb[i] = NULL; 1082 } 1083 } 1084 1085 for (i = 0; i < pool->audio_count; i++) { 1086 if (pool->audios[i]) 1087 dce_aud_destroy(&pool->audios[i]); 1088 } 1089 1090 for (i = 0; i < pool->clk_src_count; i++) { 1091 if (pool->clock_sources[i] != NULL) 1092 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1093 } 1094 1095 if (pool->dp_clock_source != NULL) 1096 dcn20_clock_source_destroy(&pool->dp_clock_source); 1097 1098 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1099 if (pool->mpc_lut[i] != NULL) { 1100 dc_3dlut_func_release(pool->mpc_lut[i]); 1101 pool->mpc_lut[i] = NULL; 1102 } 1103 if (pool->mpc_shaper[i] != NULL) { 1104 dc_transfer_func_release(pool->mpc_shaper[i]); 1105 pool->mpc_shaper[i] = NULL; 1106 } 1107 } 1108 1109 for (i = 0; i < pool->pipe_count; i++) { 1110 if (pool->multiple_abms[i] != NULL) 1111 dce_abm_destroy(&pool->multiple_abms[i]); 1112 } 1113 1114 if (pool->psr != NULL) 1115 dmub_psr_destroy(&pool->psr); 1116 1117 if (pool->dccg != NULL) 1118 dcn_dccg_destroy(&pool->dccg); 1119 } 1120 1121 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1122 { 1123 dcn302_resource_destruct(*pool); 1124 kfree(*pool); 1125 *pool = NULL; 1126 } 1127 1128 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1129 { 1130 DC_FP_START(); 1131 dcn302_fpu_update_bw_bounding_box(dc, bw_params); 1132 DC_FP_END(); 1133 } 1134 1135 static struct resource_funcs dcn302_res_pool_funcs = { 1136 .destroy = dcn302_destroy_resource_pool, 1137 .link_enc_create = dcn302_link_encoder_create, 1138 .panel_cntl_create = dcn302_panel_cntl_create, 1139 .validate_bandwidth = dcn30_validate_bandwidth, 1140 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1141 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1142 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1143 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1144 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1145 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1146 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1147 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1148 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1149 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1150 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1151 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1152 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1153 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1154 }; 1155 1156 static struct dc_cap_funcs cap_funcs = { 1157 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1158 }; 1159 1160 static const struct bios_registers bios_regs = { 1161 NBIO_SR(BIOS_SCRATCH_3), 1162 NBIO_SR(BIOS_SCRATCH_6) 1163 }; 1164 1165 static const struct dccg_registers dccg_regs = { 1166 DCCG_REG_LIST_DCN3_02() 1167 }; 1168 1169 static const struct dccg_shift dccg_shift = { 1170 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1171 }; 1172 1173 static const struct dccg_mask dccg_mask = { 1174 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1175 }; 1176 1177 #define abm_regs(id)\ 1178 [id] = { ABM_DCN302_REG_LIST(id) } 1179 1180 static const struct dce_abm_registers abm_regs[] = { 1181 abm_regs(0), 1182 abm_regs(1), 1183 abm_regs(2), 1184 abm_regs(3), 1185 abm_regs(4) 1186 }; 1187 1188 static const struct dce_abm_shift abm_shift = { 1189 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1190 }; 1191 1192 static const struct dce_abm_mask abm_mask = { 1193 ABM_MASK_SH_LIST_DCN30(_MASK) 1194 }; 1195 1196 static bool dcn302_resource_construct( 1197 uint8_t num_virtual_links, 1198 struct dc *dc, 1199 struct resource_pool *pool) 1200 { 1201 int i; 1202 struct dc_context *ctx = dc->ctx; 1203 struct irq_service_init_data init_data; 1204 1205 ctx->dc_bios->regs = &bios_regs; 1206 1207 pool->res_cap = &res_cap_dcn302; 1208 1209 pool->funcs = &dcn302_res_pool_funcs; 1210 1211 /************************************************* 1212 * Resource + asic cap harcoding * 1213 *************************************************/ 1214 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1215 pool->pipe_count = pool->res_cap->num_timing_generator; 1216 pool->mpcc_count = pool->res_cap->num_timing_generator; 1217 dc->caps.max_downscale_ratio = 600; 1218 dc->caps.i2c_speed_in_khz = 100; 1219 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1220 dc->caps.max_cursor_size = 256; 1221 dc->caps.min_horizontal_blanking_period = 80; 1222 dc->caps.dmdata_alloc_size = 2048; 1223 dc->caps.mall_size_per_mem_channel = 4; 1224 /* total size = mall per channel * num channels * 1024 * 1024 */ 1225 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1226 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1227 dc->caps.max_slave_planes = 2; 1228 dc->caps.max_slave_yuv_planes = 2; 1229 dc->caps.max_slave_rgb_planes = 2; 1230 dc->caps.post_blend_color_processing = true; 1231 dc->caps.force_dp_tps4_for_cp2520 = true; 1232 dc->caps.extended_aux_timeout_support = true; 1233 dc->caps.dmcub_support = true; 1234 1235 /* Color pipeline capabilities */ 1236 dc->caps.color.dpp.dcn_arch = 1; 1237 dc->caps.color.dpp.input_lut_shared = 0; 1238 dc->caps.color.dpp.icsc = 1; 1239 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1240 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1241 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1242 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1243 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1244 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1245 dc->caps.color.dpp.post_csc = 1; 1246 dc->caps.color.dpp.gamma_corr = 1; 1247 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1248 1249 dc->caps.color.dpp.hw_3d_lut = 1; 1250 dc->caps.color.dpp.ogam_ram = 1; 1251 // no OGAM ROM on DCN3 1252 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1253 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1254 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1255 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1256 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1257 dc->caps.color.dpp.ocsc = 0; 1258 1259 dc->caps.color.mpc.gamut_remap = 1; 1260 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1261 dc->caps.color.mpc.ogam_ram = 1; 1262 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1263 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1264 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1265 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1266 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1267 dc->caps.color.mpc.ocsc = 1; 1268 1269 /* read VBIOS LTTPR caps */ 1270 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1271 enum bp_result bp_query_result; 1272 uint8_t is_vbios_lttpr_enable = 0; 1273 1274 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1275 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1276 } 1277 1278 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1279 enum bp_result bp_query_result; 1280 uint8_t is_vbios_interop_enabled = 0; 1281 1282 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 1283 &is_vbios_interop_enabled); 1284 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1285 } 1286 1287 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1288 dc->debug = debug_defaults_drv; 1289 else 1290 dc->debug = debug_defaults_diags; 1291 1292 // Init the vm_helper 1293 if (dc->vm_helper) 1294 vm_helper_init(dc->vm_helper, 16); 1295 1296 /************************************************* 1297 * Create resources * 1298 *************************************************/ 1299 1300 /* Clock Sources for Pixel Clock*/ 1301 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1302 dcn302_clock_source_create(ctx, ctx->dc_bios, 1303 CLOCK_SOURCE_COMBO_PHY_PLL0, 1304 &clk_src_regs[0], false); 1305 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1306 dcn302_clock_source_create(ctx, ctx->dc_bios, 1307 CLOCK_SOURCE_COMBO_PHY_PLL1, 1308 &clk_src_regs[1], false); 1309 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1310 dcn302_clock_source_create(ctx, ctx->dc_bios, 1311 CLOCK_SOURCE_COMBO_PHY_PLL2, 1312 &clk_src_regs[2], false); 1313 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1314 dcn302_clock_source_create(ctx, ctx->dc_bios, 1315 CLOCK_SOURCE_COMBO_PHY_PLL3, 1316 &clk_src_regs[3], false); 1317 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1318 dcn302_clock_source_create(ctx, ctx->dc_bios, 1319 CLOCK_SOURCE_COMBO_PHY_PLL4, 1320 &clk_src_regs[4], false); 1321 1322 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1323 1324 /* todo: not reuse phy_pll registers */ 1325 pool->dp_clock_source = 1326 dcn302_clock_source_create(ctx, ctx->dc_bios, 1327 CLOCK_SOURCE_ID_DP_DTO, 1328 &clk_src_regs[0], true); 1329 1330 for (i = 0; i < pool->clk_src_count; i++) { 1331 if (pool->clock_sources[i] == NULL) { 1332 dm_error("DC: failed to create clock sources!\n"); 1333 BREAK_TO_DEBUGGER(); 1334 goto create_fail; 1335 } 1336 } 1337 1338 /* DCCG */ 1339 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1340 if (pool->dccg == NULL) { 1341 dm_error("DC: failed to create dccg!\n"); 1342 BREAK_TO_DEBUGGER(); 1343 goto create_fail; 1344 } 1345 1346 /* PP Lib and SMU interfaces */ 1347 init_soc_bounding_box(dc, pool); 1348 1349 /* DML */ 1350 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1351 1352 /* IRQ */ 1353 init_data.ctx = dc->ctx; 1354 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1355 if (!pool->irqs) 1356 goto create_fail; 1357 1358 /* HUBBUB */ 1359 pool->hubbub = dcn302_hubbub_create(ctx); 1360 if (pool->hubbub == NULL) { 1361 BREAK_TO_DEBUGGER(); 1362 dm_error("DC: failed to create hubbub!\n"); 1363 goto create_fail; 1364 } 1365 1366 /* HUBPs, DPPs, OPPs and TGs */ 1367 for (i = 0; i < pool->pipe_count; i++) { 1368 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1369 if (pool->hubps[i] == NULL) { 1370 BREAK_TO_DEBUGGER(); 1371 dm_error("DC: failed to create hubps!\n"); 1372 goto create_fail; 1373 } 1374 1375 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1376 if (pool->dpps[i] == NULL) { 1377 BREAK_TO_DEBUGGER(); 1378 dm_error("DC: failed to create dpps!\n"); 1379 goto create_fail; 1380 } 1381 } 1382 1383 for (i = 0; i < pool->res_cap->num_opp; i++) { 1384 pool->opps[i] = dcn302_opp_create(ctx, i); 1385 if (pool->opps[i] == NULL) { 1386 BREAK_TO_DEBUGGER(); 1387 dm_error("DC: failed to create output pixel processor!\n"); 1388 goto create_fail; 1389 } 1390 } 1391 1392 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1393 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1394 if (pool->timing_generators[i] == NULL) { 1395 BREAK_TO_DEBUGGER(); 1396 dm_error("DC: failed to create tg!\n"); 1397 goto create_fail; 1398 } 1399 } 1400 pool->timing_generator_count = i; 1401 1402 /* PSR */ 1403 pool->psr = dmub_psr_create(ctx); 1404 if (pool->psr == NULL) { 1405 dm_error("DC: failed to create psr!\n"); 1406 BREAK_TO_DEBUGGER(); 1407 goto create_fail; 1408 } 1409 1410 /* ABMs */ 1411 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1412 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1413 if (pool->multiple_abms[i] == NULL) { 1414 dm_error("DC: failed to create abm for pipe %d!\n", i); 1415 BREAK_TO_DEBUGGER(); 1416 goto create_fail; 1417 } 1418 } 1419 1420 /* MPC and DSC */ 1421 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1422 if (pool->mpc == NULL) { 1423 BREAK_TO_DEBUGGER(); 1424 dm_error("DC: failed to create mpc!\n"); 1425 goto create_fail; 1426 } 1427 1428 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1429 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1430 if (pool->dscs[i] == NULL) { 1431 BREAK_TO_DEBUGGER(); 1432 dm_error("DC: failed to create display stream compressor %d!\n", i); 1433 goto create_fail; 1434 } 1435 } 1436 1437 /* DWB and MMHUBBUB */ 1438 if (!dcn302_dwbc_create(ctx, pool)) { 1439 BREAK_TO_DEBUGGER(); 1440 dm_error("DC: failed to create dwbc!\n"); 1441 goto create_fail; 1442 } 1443 1444 if (!dcn302_mmhubbub_create(ctx, pool)) { 1445 BREAK_TO_DEBUGGER(); 1446 dm_error("DC: failed to create mcif_wb!\n"); 1447 goto create_fail; 1448 } 1449 1450 /* AUX and I2C */ 1451 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1452 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1453 if (pool->engines[i] == NULL) { 1454 BREAK_TO_DEBUGGER(); 1455 dm_error("DC:failed to create aux engine!!\n"); 1456 goto create_fail; 1457 } 1458 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1459 if (pool->hw_i2cs[i] == NULL) { 1460 BREAK_TO_DEBUGGER(); 1461 dm_error("DC:failed to create hw i2c!!\n"); 1462 goto create_fail; 1463 } 1464 pool->sw_i2cs[i] = NULL; 1465 } 1466 1467 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1468 if (!resource_construct(num_virtual_links, dc, pool, 1469 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1470 &res_create_funcs : &res_create_maximus_funcs))) 1471 goto create_fail; 1472 1473 /* HW Sequencer and Plane caps */ 1474 dcn302_hw_sequencer_construct(dc); 1475 1476 dc->caps.max_planes = pool->pipe_count; 1477 1478 for (i = 0; i < dc->caps.max_planes; ++i) 1479 dc->caps.planes[i] = plane_cap; 1480 1481 dc->cap_funcs = cap_funcs; 1482 1483 return true; 1484 1485 create_fail: 1486 1487 dcn302_resource_destruct(pool); 1488 1489 return false; 1490 } 1491 1492 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1493 { 1494 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1495 1496 if (!pool) 1497 return NULL; 1498 1499 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1500 return pool; 1501 1502 BREAK_TO_DEBUGGER(); 1503 kfree(pool); 1504 return NULL; 1505 } 1506