1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dml/dcn30/dcn30_fpu.h" 47 48 #include "dcn10/dcn10_resource.h" 49 50 #include "link.h" 51 #include "dce/dce_abm.h" 52 #include "dce/dce_audio.h" 53 #include "dce/dce_aux.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_hwseq.h" 56 #include "dce/dce_i2c_hw.h" 57 #include "dce/dce_panel_cntl.h" 58 #include "dce/dmub_abm.h" 59 #include "dce/dmub_psr.h" 60 #include "clk_mgr.h" 61 62 #include "hw_sequencer_private.h" 63 #include "reg_helper.h" 64 #include "resource.h" 65 #include "vm_helper.h" 66 67 #include "dml/dcn302/dcn302_fpu.h" 68 69 #include "dimgrey_cavefish_ip_offset.h" 70 #include "dcn/dcn_3_0_2_offset.h" 71 #include "dcn/dcn_3_0_2_sh_mask.h" 72 #include "dpcs/dpcs_3_0_0_offset.h" 73 #include "dpcs/dpcs_3_0_0_sh_mask.h" 74 #include "nbio/nbio_7_4_offset.h" 75 #include "amdgpu_socbb.h" 76 77 #define DC_LOGGER_INIT(logger) 78 79 static const struct dc_debug_options debug_defaults_drv = { 80 .disable_dmcu = true, 81 .force_abm_enable = false, 82 .timing_trace = false, 83 .clock_trace = true, 84 .disable_pplib_clock_request = true, 85 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 86 .force_single_disp_pipe_split = false, 87 .disable_dcc = DCC_ENABLE, 88 .vsr_support = true, 89 .performance_trace = false, 90 .max_downscale_src_width = 7680,/*upto 8K*/ 91 .disable_pplib_wm_range = false, 92 .scl_reset_length10 = true, 93 .sanity_checks = false, 94 .underflow_assert_delay_us = 0xFFFFFFFF, 95 .dwb_fi_phase = -1, // -1 = disable, 96 .dmub_command_table = true, 97 .use_max_lb = true, 98 .exit_idle_opt_for_cursor_updates = true 99 }; 100 101 static const struct dc_debug_options debug_defaults_diags = { 102 .disable_dmcu = true, 103 .force_abm_enable = false, 104 .timing_trace = true, 105 .clock_trace = true, 106 .disable_dpp_power_gate = true, 107 .disable_hubp_power_gate = true, 108 .disable_clock_gate = true, 109 .disable_pplib_clock_request = true, 110 .disable_pplib_wm_range = true, 111 .disable_stutter = false, 112 .scl_reset_length10 = true, 113 .dwb_fi_phase = -1, // -1 = disable 114 .dmub_command_table = true, 115 .enable_tri_buf = true, 116 .use_max_lb = true 117 }; 118 119 static const struct dc_panel_config panel_config_defaults = { 120 .psr = { 121 .disable_psr = false, 122 .disallow_psrsu = false, 123 }, 124 }; 125 126 enum dcn302_clk_src_array_id { 127 DCN302_CLK_SRC_PLL0, 128 DCN302_CLK_SRC_PLL1, 129 DCN302_CLK_SRC_PLL2, 130 DCN302_CLK_SRC_PLL3, 131 DCN302_CLK_SRC_PLL4, 132 DCN302_CLK_SRC_TOTAL 133 }; 134 135 static const struct resource_caps res_cap_dcn302 = { 136 .num_timing_generator = 5, 137 .num_opp = 5, 138 .num_video_plane = 5, 139 .num_audio = 5, 140 .num_stream_encoder = 5, 141 .num_dwb = 1, 142 .num_ddc = 5, 143 .num_vmid = 16, 144 .num_mpc_3dlut = 2, 145 .num_dsc = 5, 146 }; 147 148 static const struct dc_plane_cap plane_cap = { 149 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 150 .blends_with_above = true, 151 .blends_with_below = true, 152 .per_pixel_alpha = true, 153 .pixel_format_support = { 154 .argb8888 = true, 155 .nv12 = true, 156 .fp16 = true, 157 .p010 = true, 158 .ayuv = false, 159 }, 160 .max_upscale_factor = { 161 .argb8888 = 16000, 162 .nv12 = 16000, 163 .fp16 = 16000 164 }, 165 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 166 .max_downscale_factor = { 167 .argb8888 = 167, 168 .nv12 = 167, 169 .fp16 = 167 170 }, 171 16, 172 16 173 }; 174 175 /* NBIO */ 176 #define NBIO_BASE_INNER(seg) \ 177 NBIO_BASE__INST0_SEG ## seg 178 179 #define NBIO_BASE(seg) \ 180 NBIO_BASE_INNER(seg) 181 182 #define NBIO_SR(reg_name)\ 183 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 184 mm ## reg_name 185 186 /* DCN */ 187 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 188 189 #define BASE(seg) BASE_INNER(seg) 190 191 #define SR(reg_name)\ 192 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 193 194 #define SF(reg_name, field_name, post_fix)\ 195 .field_name = reg_name ## __ ## field_name ## post_fix 196 197 #define SRI(reg_name, block, id)\ 198 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 199 200 #define SRI2(reg_name, block, id)\ 201 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 202 203 #define SRII(reg_name, block, id)\ 204 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 205 mm ## block ## id ## _ ## reg_name 206 207 #define DCCG_SRII(reg_name, block, id)\ 208 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 209 mm ## block ## id ## _ ## reg_name 210 211 #define VUPDATE_SRII(reg_name, block, id)\ 212 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 213 mm ## reg_name ## _ ## block ## id 214 215 #define SRII_DWB(reg_name, temp_name, block, id)\ 216 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 217 mm ## block ## id ## _ ## temp_name 218 219 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 220 .field_name = reg_name ## __ ## field_name ## post_fix 221 222 #define SRII_MPC_RMU(reg_name, block, id)\ 223 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 224 mm ## block ## id ## _ ## reg_name 225 226 static const struct dcn_hubbub_registers hubbub_reg = { 227 HUBBUB_REG_LIST_DCN30(0) 228 }; 229 230 static const struct dcn_hubbub_shift hubbub_shift = { 231 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 232 }; 233 234 static const struct dcn_hubbub_mask hubbub_mask = { 235 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 236 }; 237 238 #define vmid_regs(id)\ 239 [id] = { DCN20_VMID_REG_LIST(id) } 240 241 static const struct dcn_vmid_registers vmid_regs[] = { 242 vmid_regs(0), 243 vmid_regs(1), 244 vmid_regs(2), 245 vmid_regs(3), 246 vmid_regs(4), 247 vmid_regs(5), 248 vmid_regs(6), 249 vmid_regs(7), 250 vmid_regs(8), 251 vmid_regs(9), 252 vmid_regs(10), 253 vmid_regs(11), 254 vmid_regs(12), 255 vmid_regs(13), 256 vmid_regs(14), 257 vmid_regs(15) 258 }; 259 260 static const struct dcn20_vmid_shift vmid_shifts = { 261 DCN20_VMID_MASK_SH_LIST(__SHIFT) 262 }; 263 264 static const struct dcn20_vmid_mask vmid_masks = { 265 DCN20_VMID_MASK_SH_LIST(_MASK) 266 }; 267 268 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 269 { 270 int i; 271 272 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 273 274 if (!hubbub3) 275 return NULL; 276 277 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 278 279 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 280 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 281 282 vmid->ctx = ctx; 283 284 vmid->regs = &vmid_regs[i]; 285 vmid->shifts = &vmid_shifts; 286 vmid->masks = &vmid_masks; 287 } 288 289 return &hubbub3->base; 290 } 291 292 #define vpg_regs(id)\ 293 [id] = { VPG_DCN3_REG_LIST(id) } 294 295 static const struct dcn30_vpg_registers vpg_regs[] = { 296 vpg_regs(0), 297 vpg_regs(1), 298 vpg_regs(2), 299 vpg_regs(3), 300 vpg_regs(4), 301 vpg_regs(5) 302 }; 303 304 static const struct dcn30_vpg_shift vpg_shift = { 305 DCN3_VPG_MASK_SH_LIST(__SHIFT) 306 }; 307 308 static const struct dcn30_vpg_mask vpg_mask = { 309 DCN3_VPG_MASK_SH_LIST(_MASK) 310 }; 311 312 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 313 { 314 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 315 316 if (!vpg3) 317 return NULL; 318 319 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 320 321 return &vpg3->base; 322 } 323 324 #define afmt_regs(id)\ 325 [id] = { AFMT_DCN3_REG_LIST(id) } 326 327 static const struct dcn30_afmt_registers afmt_regs[] = { 328 afmt_regs(0), 329 afmt_regs(1), 330 afmt_regs(2), 331 afmt_regs(3), 332 afmt_regs(4), 333 afmt_regs(5) 334 }; 335 336 static const struct dcn30_afmt_shift afmt_shift = { 337 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 338 }; 339 340 static const struct dcn30_afmt_mask afmt_mask = { 341 DCN3_AFMT_MASK_SH_LIST(_MASK) 342 }; 343 344 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 345 { 346 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 347 348 if (!afmt3) 349 return NULL; 350 351 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 352 353 return &afmt3->base; 354 } 355 356 #define audio_regs(id)\ 357 [id] = { AUD_COMMON_REG_LIST(id) } 358 359 static const struct dce_audio_registers audio_regs[] = { 360 audio_regs(0), 361 audio_regs(1), 362 audio_regs(2), 363 audio_regs(3), 364 audio_regs(4), 365 audio_regs(5), 366 audio_regs(6) 367 }; 368 369 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 370 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 371 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 372 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 373 374 static const struct dce_audio_shift audio_shift = { 375 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 376 }; 377 378 static const struct dce_audio_mask audio_mask = { 379 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 380 }; 381 382 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 383 { 384 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 385 } 386 387 #define stream_enc_regs(id)\ 388 [id] = { SE_DCN3_REG_LIST(id) } 389 390 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 391 stream_enc_regs(0), 392 stream_enc_regs(1), 393 stream_enc_regs(2), 394 stream_enc_regs(3), 395 stream_enc_regs(4) 396 }; 397 398 static const struct dcn10_stream_encoder_shift se_shift = { 399 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 400 }; 401 402 static const struct dcn10_stream_encoder_mask se_mask = { 403 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 404 }; 405 406 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 407 { 408 struct dcn10_stream_encoder *enc1; 409 struct vpg *vpg; 410 struct afmt *afmt; 411 int vpg_inst; 412 int afmt_inst; 413 414 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 415 if (eng_id <= ENGINE_ID_DIGE) { 416 vpg_inst = eng_id; 417 afmt_inst = eng_id; 418 } else 419 return NULL; 420 421 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 422 vpg = dcn302_vpg_create(ctx, vpg_inst); 423 afmt = dcn302_afmt_create(ctx, afmt_inst); 424 425 if (!enc1 || !vpg || !afmt) { 426 kfree(enc1); 427 kfree(vpg); 428 kfree(afmt); 429 return NULL; 430 } 431 432 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 433 &se_shift, &se_mask); 434 435 return &enc1->base; 436 } 437 438 #define clk_src_regs(index, pllid)\ 439 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 440 441 static const struct dce110_clk_src_regs clk_src_regs[] = { 442 clk_src_regs(0, A), 443 clk_src_regs(1, B), 444 clk_src_regs(2, C), 445 clk_src_regs(3, D), 446 clk_src_regs(4, E) 447 }; 448 449 static const struct dce110_clk_src_shift cs_shift = { 450 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 451 }; 452 453 static const struct dce110_clk_src_mask cs_mask = { 454 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 455 }; 456 457 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 458 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 459 { 460 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 461 462 if (!clk_src) 463 return NULL; 464 465 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 466 clk_src->base.dp_clk_src = dp_clk_src; 467 return &clk_src->base; 468 } 469 470 kfree(clk_src); 471 BREAK_TO_DEBUGGER(); 472 return NULL; 473 } 474 475 static const struct dce_hwseq_registers hwseq_reg = { 476 HWSEQ_DCN302_REG_LIST() 477 }; 478 479 static const struct dce_hwseq_shift hwseq_shift = { 480 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 481 }; 482 483 static const struct dce_hwseq_mask hwseq_mask = { 484 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 485 }; 486 487 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 488 { 489 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 490 491 if (hws) { 492 hws->ctx = ctx; 493 hws->regs = &hwseq_reg; 494 hws->shifts = &hwseq_shift; 495 hws->masks = &hwseq_mask; 496 } 497 return hws; 498 } 499 500 #define hubp_regs(id)\ 501 [id] = { HUBP_REG_LIST_DCN30(id) } 502 503 static const struct dcn_hubp2_registers hubp_regs[] = { 504 hubp_regs(0), 505 hubp_regs(1), 506 hubp_regs(2), 507 hubp_regs(3), 508 hubp_regs(4) 509 }; 510 511 static const struct dcn_hubp2_shift hubp_shift = { 512 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 513 }; 514 515 static const struct dcn_hubp2_mask hubp_mask = { 516 HUBP_MASK_SH_LIST_DCN30(_MASK) 517 }; 518 519 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 520 { 521 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 522 523 if (!hubp2) 524 return NULL; 525 526 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 527 return &hubp2->base; 528 529 BREAK_TO_DEBUGGER(); 530 kfree(hubp2); 531 return NULL; 532 } 533 534 #define dpp_regs(id)\ 535 [id] = { DPP_REG_LIST_DCN30(id) } 536 537 static const struct dcn3_dpp_registers dpp_regs[] = { 538 dpp_regs(0), 539 dpp_regs(1), 540 dpp_regs(2), 541 dpp_regs(3), 542 dpp_regs(4) 543 }; 544 545 static const struct dcn3_dpp_shift tf_shift = { 546 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 547 }; 548 549 static const struct dcn3_dpp_mask tf_mask = { 550 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 551 }; 552 553 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 554 { 555 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 556 557 if (!dpp) 558 return NULL; 559 560 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 561 return &dpp->base; 562 563 BREAK_TO_DEBUGGER(); 564 kfree(dpp); 565 return NULL; 566 } 567 568 #define opp_regs(id)\ 569 [id] = { OPP_REG_LIST_DCN30(id) } 570 571 static const struct dcn20_opp_registers opp_regs[] = { 572 opp_regs(0), 573 opp_regs(1), 574 opp_regs(2), 575 opp_regs(3), 576 opp_regs(4) 577 }; 578 579 static const struct dcn20_opp_shift opp_shift = { 580 OPP_MASK_SH_LIST_DCN20(__SHIFT) 581 }; 582 583 static const struct dcn20_opp_mask opp_mask = { 584 OPP_MASK_SH_LIST_DCN20(_MASK) 585 }; 586 587 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 588 { 589 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 590 591 if (!opp) { 592 BREAK_TO_DEBUGGER(); 593 return NULL; 594 } 595 596 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 597 return &opp->base; 598 } 599 600 #define optc_regs(id)\ 601 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 602 603 static const struct dcn_optc_registers optc_regs[] = { 604 optc_regs(0), 605 optc_regs(1), 606 optc_regs(2), 607 optc_regs(3), 608 optc_regs(4) 609 }; 610 611 static const struct dcn_optc_shift optc_shift = { 612 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 613 }; 614 615 static const struct dcn_optc_mask optc_mask = { 616 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 617 }; 618 619 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 620 { 621 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 622 623 if (!tgn10) 624 return NULL; 625 626 tgn10->base.inst = instance; 627 tgn10->base.ctx = ctx; 628 629 tgn10->tg_regs = &optc_regs[instance]; 630 tgn10->tg_shift = &optc_shift; 631 tgn10->tg_mask = &optc_mask; 632 633 dcn30_timing_generator_init(tgn10); 634 635 return &tgn10->base; 636 } 637 638 static const struct dcn30_mpc_registers mpc_regs = { 639 MPC_REG_LIST_DCN3_0(0), 640 MPC_REG_LIST_DCN3_0(1), 641 MPC_REG_LIST_DCN3_0(2), 642 MPC_REG_LIST_DCN3_0(3), 643 MPC_REG_LIST_DCN3_0(4), 644 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 645 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 646 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 647 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 648 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 649 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 650 MPC_RMU_REG_LIST_DCN3AG(0), 651 MPC_RMU_REG_LIST_DCN3AG(1), 652 MPC_RMU_REG_LIST_DCN3AG(2), 653 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 654 }; 655 656 static const struct dcn30_mpc_shift mpc_shift = { 657 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 658 }; 659 660 static const struct dcn30_mpc_mask mpc_mask = { 661 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 662 }; 663 664 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 665 { 666 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 667 668 if (!mpc30) 669 return NULL; 670 671 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 672 673 return &mpc30->base; 674 } 675 676 #define dsc_regsDCN20(id)\ 677 [id] = { DSC_REG_LIST_DCN20(id) } 678 679 static const struct dcn20_dsc_registers dsc_regs[] = { 680 dsc_regsDCN20(0), 681 dsc_regsDCN20(1), 682 dsc_regsDCN20(2), 683 dsc_regsDCN20(3), 684 dsc_regsDCN20(4) 685 }; 686 687 static const struct dcn20_dsc_shift dsc_shift = { 688 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 689 }; 690 691 static const struct dcn20_dsc_mask dsc_mask = { 692 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 693 }; 694 695 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 696 { 697 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 698 699 if (!dsc) { 700 BREAK_TO_DEBUGGER(); 701 return NULL; 702 } 703 704 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 705 return &dsc->base; 706 } 707 708 #define dwbc_regs_dcn3(id)\ 709 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 710 711 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 712 dwbc_regs_dcn3(0) 713 }; 714 715 static const struct dcn30_dwbc_shift dwbc30_shift = { 716 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 717 }; 718 719 static const struct dcn30_dwbc_mask dwbc30_mask = { 720 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 721 }; 722 723 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 724 { 725 int i; 726 uint32_t pipe_count = pool->res_cap->num_dwb; 727 728 for (i = 0; i < pipe_count; i++) { 729 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 730 731 if (!dwbc30) { 732 dm_error("DC: failed to create dwbc30!\n"); 733 return false; 734 } 735 736 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 737 738 pool->dwbc[i] = &dwbc30->base; 739 } 740 return true; 741 } 742 743 #define mcif_wb_regs_dcn3(id)\ 744 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 745 746 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 747 mcif_wb_regs_dcn3(0) 748 }; 749 750 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 751 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 752 }; 753 754 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 755 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 756 }; 757 758 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 759 { 760 int i; 761 uint32_t pipe_count = pool->res_cap->num_dwb; 762 763 for (i = 0; i < pipe_count; i++) { 764 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 765 766 if (!mcif_wb30) { 767 dm_error("DC: failed to create mcif_wb30!\n"); 768 return false; 769 } 770 771 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 772 773 pool->mcif_wb[i] = &mcif_wb30->base; 774 } 775 return true; 776 } 777 778 #define aux_engine_regs(id)\ 779 [id] = {\ 780 AUX_COMMON_REG_LIST0(id), \ 781 .AUXN_IMPCAL = 0, \ 782 .AUXP_IMPCAL = 0, \ 783 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 784 } 785 786 static const struct dce110_aux_registers aux_engine_regs[] = { 787 aux_engine_regs(0), 788 aux_engine_regs(1), 789 aux_engine_regs(2), 790 aux_engine_regs(3), 791 aux_engine_regs(4) 792 }; 793 794 static const struct dce110_aux_registers_shift aux_shift = { 795 DCN_AUX_MASK_SH_LIST(__SHIFT) 796 }; 797 798 static const struct dce110_aux_registers_mask aux_mask = { 799 DCN_AUX_MASK_SH_LIST(_MASK) 800 }; 801 802 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 803 { 804 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 805 806 if (!aux_engine) 807 return NULL; 808 809 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 810 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 811 812 return &aux_engine->base; 813 } 814 815 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 816 817 static const struct dce_i2c_registers i2c_hw_regs[] = { 818 i2c_inst_regs(1), 819 i2c_inst_regs(2), 820 i2c_inst_regs(3), 821 i2c_inst_regs(4), 822 i2c_inst_regs(5) 823 }; 824 825 static const struct dce_i2c_shift i2c_shifts = { 826 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 827 }; 828 829 static const struct dce_i2c_mask i2c_masks = { 830 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 831 }; 832 833 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 834 { 835 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 836 837 if (!dce_i2c_hw) 838 return NULL; 839 840 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 841 842 return dce_i2c_hw; 843 } 844 845 static const struct encoder_feature_support link_enc_feature = { 846 .max_hdmi_deep_color = COLOR_DEPTH_121212, 847 .max_hdmi_pixel_clock = 600000, 848 .hdmi_ycbcr420_supported = true, 849 .dp_ycbcr420_supported = true, 850 .fec_supported = true, 851 .flags.bits.IS_HBR2_CAPABLE = true, 852 .flags.bits.IS_HBR3_CAPABLE = true, 853 .flags.bits.IS_TPS3_CAPABLE = true, 854 .flags.bits.IS_TPS4_CAPABLE = true 855 }; 856 857 #define link_regs(id, phyid)\ 858 [id] = {\ 859 LE_DCN3_REG_LIST(id), \ 860 UNIPHY_DCN2_REG_LIST(phyid), \ 861 DPCS_DCN2_REG_LIST(id), \ 862 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 863 } 864 865 static const struct dcn10_link_enc_registers link_enc_regs[] = { 866 link_regs(0, A), 867 link_regs(1, B), 868 link_regs(2, C), 869 link_regs(3, D), 870 link_regs(4, E) 871 }; 872 873 static const struct dcn10_link_enc_shift le_shift = { 874 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 875 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 876 }; 877 878 static const struct dcn10_link_enc_mask le_mask = { 879 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 880 DPCS_DCN2_MASK_SH_LIST(_MASK) 881 }; 882 883 #define aux_regs(id)\ 884 [id] = { DCN2_AUX_REG_LIST(id) } 885 886 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 887 aux_regs(0), 888 aux_regs(1), 889 aux_regs(2), 890 aux_regs(3), 891 aux_regs(4) 892 }; 893 894 #define hpd_regs(id)\ 895 [id] = { HPD_REG_LIST(id) } 896 897 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 898 hpd_regs(0), 899 hpd_regs(1), 900 hpd_regs(2), 901 hpd_regs(3), 902 hpd_regs(4) 903 }; 904 905 static struct link_encoder *dcn302_link_encoder_create( 906 struct dc_context *ctx, 907 const struct encoder_init_data *enc_init_data) 908 { 909 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 910 911 if (!enc20) 912 return NULL; 913 914 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 915 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 916 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 917 918 return &enc20->enc10.base; 919 } 920 921 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 922 { DCN_PANEL_CNTL_REG_LIST() } 923 }; 924 925 static const struct dce_panel_cntl_shift panel_cntl_shift = { 926 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 927 }; 928 929 static const struct dce_panel_cntl_mask panel_cntl_mask = { 930 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 931 }; 932 933 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 934 { 935 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 936 937 if (!panel_cntl) 938 return NULL; 939 940 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 941 &panel_cntl_shift, &panel_cntl_mask); 942 943 return &panel_cntl->base; 944 } 945 946 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 947 { 948 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 949 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 950 } 951 952 static const struct resource_create_funcs res_create_funcs = { 953 .read_dce_straps = read_dce_straps, 954 .create_audio = dcn302_create_audio, 955 .create_stream_encoder = dcn302_stream_encoder_create, 956 .create_hwseq = dcn302_hwseq_create, 957 }; 958 959 static const struct resource_create_funcs res_create_maximus_funcs = { 960 .read_dce_straps = NULL, 961 .create_audio = NULL, 962 .create_stream_encoder = NULL, 963 .create_hwseq = dcn302_hwseq_create, 964 }; 965 966 static bool is_soc_bounding_box_valid(struct dc *dc) 967 { 968 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 969 970 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 971 return true; 972 973 return false; 974 } 975 976 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 977 { 978 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 979 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 980 981 DC_LOGGER_INIT(dc->ctx->logger); 982 983 if (!is_soc_bounding_box_valid(dc)) { 984 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 985 return false; 986 } 987 988 loaded_ip->max_num_otg = pool->pipe_count; 989 loaded_ip->max_num_dpp = pool->pipe_count; 990 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 991 DC_FP_START(); 992 dcn20_patch_bounding_box(dc, loaded_bb); 993 DC_FP_END(); 994 995 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 996 struct bp_soc_bb_info bb_info = { 0 }; 997 998 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 999 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1000 1001 DC_FP_START(); 1002 dcn302_fpu_init_soc_bounding_box(bb_info); 1003 DC_FP_END(); 1004 } 1005 } 1006 1007 return true; 1008 } 1009 1010 static void dcn302_resource_destruct(struct resource_pool *pool) 1011 { 1012 unsigned int i; 1013 1014 for (i = 0; i < pool->stream_enc_count; i++) { 1015 if (pool->stream_enc[i] != NULL) { 1016 if (pool->stream_enc[i]->vpg != NULL) { 1017 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1018 pool->stream_enc[i]->vpg = NULL; 1019 } 1020 if (pool->stream_enc[i]->afmt != NULL) { 1021 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1022 pool->stream_enc[i]->afmt = NULL; 1023 } 1024 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1025 pool->stream_enc[i] = NULL; 1026 } 1027 } 1028 1029 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1030 if (pool->dscs[i] != NULL) 1031 dcn20_dsc_destroy(&pool->dscs[i]); 1032 } 1033 1034 if (pool->mpc != NULL) { 1035 kfree(TO_DCN20_MPC(pool->mpc)); 1036 pool->mpc = NULL; 1037 } 1038 1039 if (pool->hubbub != NULL) { 1040 kfree(pool->hubbub); 1041 pool->hubbub = NULL; 1042 } 1043 1044 for (i = 0; i < pool->pipe_count; i++) { 1045 if (pool->dpps[i] != NULL) { 1046 kfree(TO_DCN20_DPP(pool->dpps[i])); 1047 pool->dpps[i] = NULL; 1048 } 1049 1050 if (pool->hubps[i] != NULL) { 1051 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1052 pool->hubps[i] = NULL; 1053 } 1054 1055 if (pool->irqs != NULL) 1056 dal_irq_service_destroy(&pool->irqs); 1057 } 1058 1059 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1060 if (pool->engines[i] != NULL) 1061 dce110_engine_destroy(&pool->engines[i]); 1062 if (pool->hw_i2cs[i] != NULL) { 1063 kfree(pool->hw_i2cs[i]); 1064 pool->hw_i2cs[i] = NULL; 1065 } 1066 if (pool->sw_i2cs[i] != NULL) { 1067 kfree(pool->sw_i2cs[i]); 1068 pool->sw_i2cs[i] = NULL; 1069 } 1070 } 1071 1072 for (i = 0; i < pool->res_cap->num_opp; i++) { 1073 if (pool->opps[i] != NULL) 1074 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1075 } 1076 1077 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1078 if (pool->timing_generators[i] != NULL) { 1079 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1080 pool->timing_generators[i] = NULL; 1081 } 1082 } 1083 1084 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1085 if (pool->dwbc[i] != NULL) { 1086 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1087 pool->dwbc[i] = NULL; 1088 } 1089 if (pool->mcif_wb[i] != NULL) { 1090 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1091 pool->mcif_wb[i] = NULL; 1092 } 1093 } 1094 1095 for (i = 0; i < pool->audio_count; i++) { 1096 if (pool->audios[i]) 1097 dce_aud_destroy(&pool->audios[i]); 1098 } 1099 1100 for (i = 0; i < pool->clk_src_count; i++) { 1101 if (pool->clock_sources[i] != NULL) 1102 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1103 } 1104 1105 if (pool->dp_clock_source != NULL) 1106 dcn20_clock_source_destroy(&pool->dp_clock_source); 1107 1108 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1109 if (pool->mpc_lut[i] != NULL) { 1110 dc_3dlut_func_release(pool->mpc_lut[i]); 1111 pool->mpc_lut[i] = NULL; 1112 } 1113 if (pool->mpc_shaper[i] != NULL) { 1114 dc_transfer_func_release(pool->mpc_shaper[i]); 1115 pool->mpc_shaper[i] = NULL; 1116 } 1117 } 1118 1119 for (i = 0; i < pool->pipe_count; i++) { 1120 if (pool->multiple_abms[i] != NULL) 1121 dce_abm_destroy(&pool->multiple_abms[i]); 1122 } 1123 1124 if (pool->psr != NULL) 1125 dmub_psr_destroy(&pool->psr); 1126 1127 if (pool->dccg != NULL) 1128 dcn_dccg_destroy(&pool->dccg); 1129 1130 if (pool->oem_device != NULL) 1131 link_destroy_ddc_service(&pool->oem_device); 1132 } 1133 1134 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1135 { 1136 dcn302_resource_destruct(*pool); 1137 kfree(*pool); 1138 *pool = NULL; 1139 } 1140 1141 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1142 { 1143 DC_FP_START(); 1144 dcn302_fpu_update_bw_bounding_box(dc, bw_params); 1145 DC_FP_END(); 1146 } 1147 1148 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config) 1149 { 1150 *panel_config = panel_config_defaults; 1151 } 1152 1153 static struct resource_funcs dcn302_res_pool_funcs = { 1154 .destroy = dcn302_destroy_resource_pool, 1155 .link_enc_create = dcn302_link_encoder_create, 1156 .panel_cntl_create = dcn302_panel_cntl_create, 1157 .validate_bandwidth = dcn30_validate_bandwidth, 1158 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1159 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1160 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1161 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1162 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1163 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1164 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1165 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1166 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1167 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1168 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1169 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1170 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1171 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1172 .get_panel_config_defaults = dcn302_get_panel_config_defaults, 1173 }; 1174 1175 static struct dc_cap_funcs cap_funcs = { 1176 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1177 }; 1178 1179 static const struct bios_registers bios_regs = { 1180 NBIO_SR(BIOS_SCRATCH_3), 1181 NBIO_SR(BIOS_SCRATCH_6) 1182 }; 1183 1184 static const struct dccg_registers dccg_regs = { 1185 DCCG_REG_LIST_DCN3_02() 1186 }; 1187 1188 static const struct dccg_shift dccg_shift = { 1189 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1190 }; 1191 1192 static const struct dccg_mask dccg_mask = { 1193 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1194 }; 1195 1196 #define abm_regs(id)\ 1197 [id] = { ABM_DCN302_REG_LIST(id) } 1198 1199 static const struct dce_abm_registers abm_regs[] = { 1200 abm_regs(0), 1201 abm_regs(1), 1202 abm_regs(2), 1203 abm_regs(3), 1204 abm_regs(4) 1205 }; 1206 1207 static const struct dce_abm_shift abm_shift = { 1208 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1209 }; 1210 1211 static const struct dce_abm_mask abm_mask = { 1212 ABM_MASK_SH_LIST_DCN30(_MASK) 1213 }; 1214 1215 static bool dcn302_resource_construct( 1216 uint8_t num_virtual_links, 1217 struct dc *dc, 1218 struct resource_pool *pool) 1219 { 1220 int i; 1221 struct dc_context *ctx = dc->ctx; 1222 struct irq_service_init_data init_data; 1223 struct ddc_service_init_data ddc_init_data = {0}; 1224 1225 ctx->dc_bios->regs = &bios_regs; 1226 1227 pool->res_cap = &res_cap_dcn302; 1228 1229 pool->funcs = &dcn302_res_pool_funcs; 1230 1231 /************************************************* 1232 * Resource + asic cap harcoding * 1233 *************************************************/ 1234 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1235 pool->pipe_count = pool->res_cap->num_timing_generator; 1236 pool->mpcc_count = pool->res_cap->num_timing_generator; 1237 dc->caps.max_downscale_ratio = 600; 1238 dc->caps.i2c_speed_in_khz = 100; 1239 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1240 dc->caps.max_cursor_size = 256; 1241 dc->caps.min_horizontal_blanking_period = 80; 1242 dc->caps.dmdata_alloc_size = 2048; 1243 dc->caps.mall_size_per_mem_channel = 4; 1244 /* total size = mall per channel * num channels * 1024 * 1024 */ 1245 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1246 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1247 dc->caps.max_slave_planes = 2; 1248 dc->caps.max_slave_yuv_planes = 2; 1249 dc->caps.max_slave_rgb_planes = 2; 1250 dc->caps.post_blend_color_processing = true; 1251 dc->caps.force_dp_tps4_for_cp2520 = true; 1252 dc->caps.extended_aux_timeout_support = true; 1253 dc->caps.dmcub_support = true; 1254 1255 /* Color pipeline capabilities */ 1256 dc->caps.color.dpp.dcn_arch = 1; 1257 dc->caps.color.dpp.input_lut_shared = 0; 1258 dc->caps.color.dpp.icsc = 1; 1259 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1260 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1261 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1262 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1263 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1264 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1265 dc->caps.color.dpp.post_csc = 1; 1266 dc->caps.color.dpp.gamma_corr = 1; 1267 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1268 1269 dc->caps.color.dpp.hw_3d_lut = 1; 1270 dc->caps.color.dpp.ogam_ram = 1; 1271 // no OGAM ROM on DCN3 1272 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1273 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1274 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1275 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1276 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1277 dc->caps.color.dpp.ocsc = 0; 1278 1279 dc->caps.color.mpc.gamut_remap = 1; 1280 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1281 dc->caps.color.mpc.ogam_ram = 1; 1282 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1283 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1284 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1285 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1286 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1287 dc->caps.color.mpc.ocsc = 1; 1288 1289 dc->caps.dp_hdmi21_pcon_support = true; 1290 1291 /* read VBIOS LTTPR caps */ 1292 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1293 enum bp_result bp_query_result; 1294 uint8_t is_vbios_lttpr_enable = 0; 1295 1296 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1297 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1298 } 1299 1300 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1301 enum bp_result bp_query_result; 1302 uint8_t is_vbios_interop_enabled = 0; 1303 1304 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 1305 &is_vbios_interop_enabled); 1306 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1307 } 1308 1309 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1310 dc->debug = debug_defaults_drv; 1311 else 1312 dc->debug = debug_defaults_diags; 1313 1314 // Init the vm_helper 1315 if (dc->vm_helper) 1316 vm_helper_init(dc->vm_helper, 16); 1317 1318 /************************************************* 1319 * Create resources * 1320 *************************************************/ 1321 1322 /* Clock Sources for Pixel Clock*/ 1323 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1324 dcn302_clock_source_create(ctx, ctx->dc_bios, 1325 CLOCK_SOURCE_COMBO_PHY_PLL0, 1326 &clk_src_regs[0], false); 1327 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1328 dcn302_clock_source_create(ctx, ctx->dc_bios, 1329 CLOCK_SOURCE_COMBO_PHY_PLL1, 1330 &clk_src_regs[1], false); 1331 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1332 dcn302_clock_source_create(ctx, ctx->dc_bios, 1333 CLOCK_SOURCE_COMBO_PHY_PLL2, 1334 &clk_src_regs[2], false); 1335 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1336 dcn302_clock_source_create(ctx, ctx->dc_bios, 1337 CLOCK_SOURCE_COMBO_PHY_PLL3, 1338 &clk_src_regs[3], false); 1339 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1340 dcn302_clock_source_create(ctx, ctx->dc_bios, 1341 CLOCK_SOURCE_COMBO_PHY_PLL4, 1342 &clk_src_regs[4], false); 1343 1344 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1345 1346 /* todo: not reuse phy_pll registers */ 1347 pool->dp_clock_source = 1348 dcn302_clock_source_create(ctx, ctx->dc_bios, 1349 CLOCK_SOURCE_ID_DP_DTO, 1350 &clk_src_regs[0], true); 1351 1352 for (i = 0; i < pool->clk_src_count; i++) { 1353 if (pool->clock_sources[i] == NULL) { 1354 dm_error("DC: failed to create clock sources!\n"); 1355 BREAK_TO_DEBUGGER(); 1356 goto create_fail; 1357 } 1358 } 1359 1360 /* DCCG */ 1361 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1362 if (pool->dccg == NULL) { 1363 dm_error("DC: failed to create dccg!\n"); 1364 BREAK_TO_DEBUGGER(); 1365 goto create_fail; 1366 } 1367 1368 /* PP Lib and SMU interfaces */ 1369 init_soc_bounding_box(dc, pool); 1370 1371 /* DML */ 1372 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1373 1374 /* IRQ */ 1375 init_data.ctx = dc->ctx; 1376 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1377 if (!pool->irqs) 1378 goto create_fail; 1379 1380 /* HUBBUB */ 1381 pool->hubbub = dcn302_hubbub_create(ctx); 1382 if (pool->hubbub == NULL) { 1383 BREAK_TO_DEBUGGER(); 1384 dm_error("DC: failed to create hubbub!\n"); 1385 goto create_fail; 1386 } 1387 1388 /* HUBPs, DPPs, OPPs and TGs */ 1389 for (i = 0; i < pool->pipe_count; i++) { 1390 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1391 if (pool->hubps[i] == NULL) { 1392 BREAK_TO_DEBUGGER(); 1393 dm_error("DC: failed to create hubps!\n"); 1394 goto create_fail; 1395 } 1396 1397 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1398 if (pool->dpps[i] == NULL) { 1399 BREAK_TO_DEBUGGER(); 1400 dm_error("DC: failed to create dpps!\n"); 1401 goto create_fail; 1402 } 1403 } 1404 1405 for (i = 0; i < pool->res_cap->num_opp; i++) { 1406 pool->opps[i] = dcn302_opp_create(ctx, i); 1407 if (pool->opps[i] == NULL) { 1408 BREAK_TO_DEBUGGER(); 1409 dm_error("DC: failed to create output pixel processor!\n"); 1410 goto create_fail; 1411 } 1412 } 1413 1414 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1415 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1416 if (pool->timing_generators[i] == NULL) { 1417 BREAK_TO_DEBUGGER(); 1418 dm_error("DC: failed to create tg!\n"); 1419 goto create_fail; 1420 } 1421 } 1422 pool->timing_generator_count = i; 1423 1424 /* PSR */ 1425 pool->psr = dmub_psr_create(ctx); 1426 if (pool->psr == NULL) { 1427 dm_error("DC: failed to create psr!\n"); 1428 BREAK_TO_DEBUGGER(); 1429 goto create_fail; 1430 } 1431 1432 /* ABMs */ 1433 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1434 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1435 if (pool->multiple_abms[i] == NULL) { 1436 dm_error("DC: failed to create abm for pipe %d!\n", i); 1437 BREAK_TO_DEBUGGER(); 1438 goto create_fail; 1439 } 1440 } 1441 1442 /* MPC and DSC */ 1443 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1444 if (pool->mpc == NULL) { 1445 BREAK_TO_DEBUGGER(); 1446 dm_error("DC: failed to create mpc!\n"); 1447 goto create_fail; 1448 } 1449 1450 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1451 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1452 if (pool->dscs[i] == NULL) { 1453 BREAK_TO_DEBUGGER(); 1454 dm_error("DC: failed to create display stream compressor %d!\n", i); 1455 goto create_fail; 1456 } 1457 } 1458 1459 /* DWB and MMHUBBUB */ 1460 if (!dcn302_dwbc_create(ctx, pool)) { 1461 BREAK_TO_DEBUGGER(); 1462 dm_error("DC: failed to create dwbc!\n"); 1463 goto create_fail; 1464 } 1465 1466 if (!dcn302_mmhubbub_create(ctx, pool)) { 1467 BREAK_TO_DEBUGGER(); 1468 dm_error("DC: failed to create mcif_wb!\n"); 1469 goto create_fail; 1470 } 1471 1472 /* AUX and I2C */ 1473 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1474 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1475 if (pool->engines[i] == NULL) { 1476 BREAK_TO_DEBUGGER(); 1477 dm_error("DC:failed to create aux engine!!\n"); 1478 goto create_fail; 1479 } 1480 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1481 if (pool->hw_i2cs[i] == NULL) { 1482 BREAK_TO_DEBUGGER(); 1483 dm_error("DC:failed to create hw i2c!!\n"); 1484 goto create_fail; 1485 } 1486 pool->sw_i2cs[i] = NULL; 1487 } 1488 1489 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1490 if (!resource_construct(num_virtual_links, dc, pool, 1491 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1492 &res_create_funcs : &res_create_maximus_funcs))) 1493 goto create_fail; 1494 1495 /* HW Sequencer and Plane caps */ 1496 dcn302_hw_sequencer_construct(dc); 1497 1498 dc->caps.max_planes = pool->pipe_count; 1499 1500 for (i = 0; i < dc->caps.max_planes; ++i) 1501 dc->caps.planes[i] = plane_cap; 1502 1503 dc->cap_funcs = cap_funcs; 1504 1505 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1506 ddc_init_data.ctx = dc->ctx; 1507 ddc_init_data.link = NULL; 1508 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1509 ddc_init_data.id.enum_id = 0; 1510 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1511 pool->oem_device = link_create_ddc_service(&ddc_init_data); 1512 } else { 1513 pool->oem_device = NULL; 1514 } 1515 1516 return true; 1517 1518 create_fail: 1519 1520 dcn302_resource_destruct(pool); 1521 1522 return false; 1523 } 1524 1525 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1526 { 1527 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1528 1529 if (!pool) 1530 return NULL; 1531 1532 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1533 return pool; 1534 1535 BREAK_TO_DEBUGGER(); 1536 kfree(pool); 1537 return NULL; 1538 } 1539