1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dcn10/dcn10_resource.h" 47 48 #include "dce/dce_abm.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_clock_source.h" 52 #include "dce/dce_hwseq.h" 53 #include "dce/dce_i2c_hw.h" 54 #include "dce/dce_panel_cntl.h" 55 #include "dce/dmub_abm.h" 56 #include "dce/dmub_psr.h" 57 #include "clk_mgr.h" 58 59 #include "hw_sequencer_private.h" 60 #include "reg_helper.h" 61 #include "resource.h" 62 #include "vm_helper.h" 63 64 #include "dimgrey_cavefish_ip_offset.h" 65 #include "dcn/dcn_3_0_2_offset.h" 66 #include "dcn/dcn_3_0_2_sh_mask.h" 67 #include "dcn/dpcs_3_0_0_offset.h" 68 #include "dcn/dpcs_3_0_0_sh_mask.h" 69 #include "nbio/nbio_7_4_offset.h" 70 #include "amdgpu_socbb.h" 71 72 #define DC_LOGGER_INIT(logger) 73 74 struct _vcs_dpi_ip_params_st dcn3_02_ip = { 75 .use_min_dcfclk = 0, 76 .clamp_min_dcfclk = 0, 77 .odm_capable = 1, 78 .gpuvm_enable = 1, 79 .hostvm_enable = 0, 80 .gpuvm_max_page_table_levels = 4, 81 .hostvm_max_page_table_levels = 4, 82 .hostvm_cached_page_table_levels = 0, 83 .pte_group_size_bytes = 2048, 84 .num_dsc = 5, 85 .rob_buffer_size_kbytes = 184, 86 .det_buffer_size_kbytes = 184, 87 .dpte_buffer_size_in_pte_reqs_luma = 64, 88 .dpte_buffer_size_in_pte_reqs_chroma = 34, 89 .pde_proc_buffer_size_64k_reqs = 48, 90 .dpp_output_buffer_pixels = 2560, 91 .opp_output_buffer_lines = 1, 92 .pixel_chunk_size_kbytes = 8, 93 .pte_enable = 1, 94 .max_page_table_levels = 2, 95 .pte_chunk_size_kbytes = 2, // ? 96 .meta_chunk_size_kbytes = 2, 97 .writeback_chunk_size_kbytes = 8, 98 .line_buffer_size_bits = 789504, 99 .is_line_buffer_bpp_fixed = 0, // ? 100 .line_buffer_fixed_bpp = 0, // ? 101 .dcc_supported = true, 102 .writeback_interface_buffer_size_kbytes = 90, 103 .writeback_line_buffer_buffer_size = 0, 104 .max_line_buffer_lines = 12, 105 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 106 .writeback_chroma_buffer_size_kbytes = 8, 107 .writeback_chroma_line_buffer_width_pixels = 4, 108 .writeback_max_hscl_ratio = 1, 109 .writeback_max_vscl_ratio = 1, 110 .writeback_min_hscl_ratio = 1, 111 .writeback_min_vscl_ratio = 1, 112 .writeback_max_hscl_taps = 1, 113 .writeback_max_vscl_taps = 1, 114 .writeback_line_buffer_luma_buffer_size = 0, 115 .writeback_line_buffer_chroma_buffer_size = 14643, 116 .cursor_buffer_size = 8, 117 .cursor_chunk_size = 2, 118 .max_num_otg = 5, 119 .max_num_dpp = 5, 120 .max_num_wb = 1, 121 .max_dchub_pscl_bw_pix_per_clk = 4, 122 .max_pscl_lb_bw_pix_per_clk = 2, 123 .max_lb_vscl_bw_pix_per_clk = 4, 124 .max_vscl_hscl_bw_pix_per_clk = 4, 125 .max_hscl_ratio = 6, 126 .max_vscl_ratio = 6, 127 .hscl_mults = 4, 128 .vscl_mults = 4, 129 .max_hscl_taps = 8, 130 .max_vscl_taps = 8, 131 .dispclk_ramp_margin_percent = 1, 132 .underscan_factor = 1.11, 133 .min_vblank_lines = 32, 134 .dppclk_delay_subtotal = 46, 135 .dynamic_metadata_vm_enabled = true, 136 .dppclk_delay_scl_lb_only = 16, 137 .dppclk_delay_scl = 50, 138 .dppclk_delay_cnvc_formatter = 27, 139 .dppclk_delay_cnvc_cursor = 6, 140 .dispclk_delay_subtotal = 119, 141 .dcfclk_cstate_latency = 5.2, // SRExitTime 142 .max_inter_dcn_tile_repeaters = 8, 143 .max_num_hdmi_frl_outputs = 1, 144 .odm_combine_4to1_supported = true, 145 146 .xfc_supported = false, 147 .xfc_fill_bw_overhead_percent = 10.0, 148 .xfc_fill_constant_bytes = 0, 149 .gfx7_compat_tiling_supported = 0, 150 .number_of_cursors = 1, 151 }; 152 153 struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = { 154 .clock_limits = { 155 { 156 .state = 0, 157 .dispclk_mhz = 562.0, 158 .dppclk_mhz = 300.0, 159 .phyclk_mhz = 300.0, 160 .phyclk_d18_mhz = 667.0, 161 .dscclk_mhz = 405.6, 162 }, 163 }, 164 165 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 166 .num_states = 1, 167 .sr_exit_time_us = 15.5, 168 .sr_enter_plus_exit_time_us = 20, 169 .urgent_latency_us = 4.0, 170 .urgent_latency_pixel_data_only_us = 4.0, 171 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 172 .urgent_latency_vm_data_only_us = 4.0, 173 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 174 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 175 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 176 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 177 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 178 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 179 .max_avg_sdp_bw_use_normal_percent = 60.0, 180 .max_avg_dram_bw_use_normal_percent = 40.0, 181 .writeback_latency_us = 12.0, 182 .max_request_size_bytes = 256, 183 .fabric_datapath_to_dcn_data_return_bytes = 64, 184 .dcn_downspread_percent = 0.5, 185 .downspread_percent = 0.38, 186 .dram_page_open_time_ns = 50.0, 187 .dram_rw_turnaround_time_ns = 17.5, 188 .dram_return_buffer_per_channel_bytes = 8192, 189 .round_trip_ping_latency_dcfclk_cycles = 156, 190 .urgent_out_of_order_return_per_channel_bytes = 4096, 191 .channel_interleave_bytes = 256, 192 .num_banks = 8, 193 .gpuvm_min_page_size_bytes = 4096, 194 .hostvm_min_page_size_bytes = 4096, 195 .dram_clock_change_latency_us = 404, 196 .dummy_pstate_latency_us = 5, 197 .writeback_dram_clock_change_latency_us = 23.0, 198 .return_bus_width_bytes = 64, 199 .dispclk_dppclk_vco_speed_mhz = 3650, 200 .xfc_bus_transport_time_us = 20, // ? 201 .xfc_xbuf_latency_tolerance_us = 4, // ? 202 .use_urgent_burst_bw = 1, // ? 203 .do_urgent_latency_adjustment = true, 204 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 205 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 206 }; 207 208 static const struct dc_debug_options debug_defaults_drv = { 209 .disable_dmcu = true, 210 .force_abm_enable = false, 211 .timing_trace = false, 212 .clock_trace = true, 213 .disable_pplib_clock_request = true, 214 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 215 .force_single_disp_pipe_split = false, 216 .disable_dcc = DCC_ENABLE, 217 .vsr_support = true, 218 .performance_trace = false, 219 .max_downscale_src_width = 7680,/*upto 8K*/ 220 .disable_pplib_wm_range = false, 221 .scl_reset_length10 = true, 222 .sanity_checks = false, 223 .underflow_assert_delay_us = 0xFFFFFFFF, 224 .dwb_fi_phase = -1, // -1 = disable, 225 .dmub_command_table = true, 226 .use_max_lb = true 227 }; 228 229 static const struct dc_debug_options debug_defaults_diags = { 230 .disable_dmcu = true, 231 .force_abm_enable = false, 232 .timing_trace = true, 233 .clock_trace = true, 234 .disable_dpp_power_gate = true, 235 .disable_hubp_power_gate = true, 236 .disable_clock_gate = true, 237 .disable_pplib_clock_request = true, 238 .disable_pplib_wm_range = true, 239 .disable_stutter = false, 240 .scl_reset_length10 = true, 241 .dwb_fi_phase = -1, // -1 = disable 242 .dmub_command_table = true, 243 .enable_tri_buf = true, 244 .disable_psr = true, 245 .use_max_lb = true 246 }; 247 248 enum dcn302_clk_src_array_id { 249 DCN302_CLK_SRC_PLL0, 250 DCN302_CLK_SRC_PLL1, 251 DCN302_CLK_SRC_PLL2, 252 DCN302_CLK_SRC_PLL3, 253 DCN302_CLK_SRC_PLL4, 254 DCN302_CLK_SRC_TOTAL 255 }; 256 257 static const struct resource_caps res_cap_dcn302 = { 258 .num_timing_generator = 5, 259 .num_opp = 5, 260 .num_video_plane = 5, 261 .num_audio = 5, 262 .num_stream_encoder = 5, 263 .num_dwb = 1, 264 .num_ddc = 5, 265 .num_vmid = 16, 266 .num_mpc_3dlut = 2, 267 .num_dsc = 5, 268 }; 269 270 static const struct dc_plane_cap plane_cap = { 271 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 272 .blends_with_above = true, 273 .blends_with_below = true, 274 .per_pixel_alpha = true, 275 .pixel_format_support = { 276 .argb8888 = true, 277 .nv12 = true, 278 .fp16 = true, 279 .p010 = false, 280 .ayuv = false, 281 }, 282 .max_upscale_factor = { 283 .argb8888 = 16000, 284 .nv12 = 16000, 285 .fp16 = 16000 286 }, 287 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 288 .max_downscale_factor = { 289 .argb8888 = 167, 290 .nv12 = 167, 291 .fp16 = 167 292 }, 293 16, 294 16 295 }; 296 297 /* NBIO */ 298 #define NBIO_BASE_INNER(seg) \ 299 NBIO_BASE__INST0_SEG ## seg 300 301 #define NBIO_BASE(seg) \ 302 NBIO_BASE_INNER(seg) 303 304 #define NBIO_SR(reg_name)\ 305 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 306 mm ## reg_name 307 308 /* DCN */ 309 #undef BASE_INNER 310 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 311 312 #define BASE(seg) BASE_INNER(seg) 313 314 #define SR(reg_name)\ 315 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 316 317 #define SF(reg_name, field_name, post_fix)\ 318 .field_name = reg_name ## __ ## field_name ## post_fix 319 320 #define SRI(reg_name, block, id)\ 321 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 322 323 #define SRI2(reg_name, block, id)\ 324 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 325 326 #define SRII(reg_name, block, id)\ 327 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 328 mm ## block ## id ## _ ## reg_name 329 330 #define DCCG_SRII(reg_name, block, id)\ 331 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 332 mm ## block ## id ## _ ## reg_name 333 334 #define VUPDATE_SRII(reg_name, block, id)\ 335 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 336 mm ## reg_name ## _ ## block ## id 337 338 #define SRII_DWB(reg_name, temp_name, block, id)\ 339 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 340 mm ## block ## id ## _ ## temp_name 341 342 #define SRII_MPC_RMU(reg_name, block, id)\ 343 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 344 mm ## block ## id ## _ ## reg_name 345 346 static const struct dcn_hubbub_registers hubbub_reg = { 347 HUBBUB_REG_LIST_DCN30(0) 348 }; 349 350 static const struct dcn_hubbub_shift hubbub_shift = { 351 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 352 }; 353 354 static const struct dcn_hubbub_mask hubbub_mask = { 355 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 356 }; 357 358 #define vmid_regs(id)\ 359 [id] = { DCN20_VMID_REG_LIST(id) } 360 361 static const struct dcn_vmid_registers vmid_regs[] = { 362 vmid_regs(0), 363 vmid_regs(1), 364 vmid_regs(2), 365 vmid_regs(3), 366 vmid_regs(4), 367 vmid_regs(5), 368 vmid_regs(6), 369 vmid_regs(7), 370 vmid_regs(8), 371 vmid_regs(9), 372 vmid_regs(10), 373 vmid_regs(11), 374 vmid_regs(12), 375 vmid_regs(13), 376 vmid_regs(14), 377 vmid_regs(15) 378 }; 379 380 static const struct dcn20_vmid_shift vmid_shifts = { 381 DCN20_VMID_MASK_SH_LIST(__SHIFT) 382 }; 383 384 static const struct dcn20_vmid_mask vmid_masks = { 385 DCN20_VMID_MASK_SH_LIST(_MASK) 386 }; 387 388 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 389 { 390 int i; 391 392 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 393 394 if (!hubbub3) 395 return NULL; 396 397 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 398 399 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 400 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 401 402 vmid->ctx = ctx; 403 404 vmid->regs = &vmid_regs[i]; 405 vmid->shifts = &vmid_shifts; 406 vmid->masks = &vmid_masks; 407 } 408 409 return &hubbub3->base; 410 } 411 412 #define vpg_regs(id)\ 413 [id] = { VPG_DCN3_REG_LIST(id) } 414 415 static const struct dcn30_vpg_registers vpg_regs[] = { 416 vpg_regs(0), 417 vpg_regs(1), 418 vpg_regs(2), 419 vpg_regs(3), 420 vpg_regs(4), 421 vpg_regs(5) 422 }; 423 424 static const struct dcn30_vpg_shift vpg_shift = { 425 DCN3_VPG_MASK_SH_LIST(__SHIFT) 426 }; 427 428 static const struct dcn30_vpg_mask vpg_mask = { 429 DCN3_VPG_MASK_SH_LIST(_MASK) 430 }; 431 432 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 433 { 434 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 435 436 if (!vpg3) 437 return NULL; 438 439 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 440 441 return &vpg3->base; 442 } 443 444 #define afmt_regs(id)\ 445 [id] = { AFMT_DCN3_REG_LIST(id) } 446 447 static const struct dcn30_afmt_registers afmt_regs[] = { 448 afmt_regs(0), 449 afmt_regs(1), 450 afmt_regs(2), 451 afmt_regs(3), 452 afmt_regs(4), 453 afmt_regs(5) 454 }; 455 456 static const struct dcn30_afmt_shift afmt_shift = { 457 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 458 }; 459 460 static const struct dcn30_afmt_mask afmt_mask = { 461 DCN3_AFMT_MASK_SH_LIST(_MASK) 462 }; 463 464 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 465 { 466 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 467 468 if (!afmt3) 469 return NULL; 470 471 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 472 473 return &afmt3->base; 474 } 475 476 #define audio_regs(id)\ 477 [id] = { AUD_COMMON_REG_LIST(id) } 478 479 static const struct dce_audio_registers audio_regs[] = { 480 audio_regs(0), 481 audio_regs(1), 482 audio_regs(2), 483 audio_regs(3), 484 audio_regs(4), 485 audio_regs(5), 486 audio_regs(6) 487 }; 488 489 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 490 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 491 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 492 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 493 494 static const struct dce_audio_shift audio_shift = { 495 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 496 }; 497 498 static const struct dce_audio_mask audio_mask = { 499 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 500 }; 501 502 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 503 { 504 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 505 } 506 507 #define stream_enc_regs(id)\ 508 [id] = { SE_DCN3_REG_LIST(id) } 509 510 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 511 stream_enc_regs(0), 512 stream_enc_regs(1), 513 stream_enc_regs(2), 514 stream_enc_regs(3), 515 stream_enc_regs(4) 516 }; 517 518 static const struct dcn10_stream_encoder_shift se_shift = { 519 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 520 }; 521 522 static const struct dcn10_stream_encoder_mask se_mask = { 523 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 524 }; 525 526 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 527 { 528 struct dcn10_stream_encoder *enc1; 529 struct vpg *vpg; 530 struct afmt *afmt; 531 int vpg_inst; 532 int afmt_inst; 533 534 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 535 if (eng_id <= ENGINE_ID_DIGE) { 536 vpg_inst = eng_id; 537 afmt_inst = eng_id; 538 } else 539 return NULL; 540 541 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 542 vpg = dcn302_vpg_create(ctx, vpg_inst); 543 afmt = dcn302_afmt_create(ctx, afmt_inst); 544 545 if (!enc1 || !vpg || !afmt) 546 return NULL; 547 548 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 549 &se_shift, &se_mask); 550 551 return &enc1->base; 552 } 553 554 #define clk_src_regs(index, pllid)\ 555 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 556 557 static const struct dce110_clk_src_regs clk_src_regs[] = { 558 clk_src_regs(0, A), 559 clk_src_regs(1, B), 560 clk_src_regs(2, C), 561 clk_src_regs(3, D), 562 clk_src_regs(4, E) 563 }; 564 565 static const struct dce110_clk_src_shift cs_shift = { 566 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 567 }; 568 569 static const struct dce110_clk_src_mask cs_mask = { 570 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 571 }; 572 573 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 574 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 575 { 576 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 577 578 if (!clk_src) 579 return NULL; 580 581 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 582 clk_src->base.dp_clk_src = dp_clk_src; 583 return &clk_src->base; 584 } 585 586 BREAK_TO_DEBUGGER(); 587 return NULL; 588 } 589 590 static const struct dce_hwseq_registers hwseq_reg = { 591 HWSEQ_DCN302_REG_LIST() 592 }; 593 594 static const struct dce_hwseq_shift hwseq_shift = { 595 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 596 }; 597 598 static const struct dce_hwseq_mask hwseq_mask = { 599 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 600 }; 601 602 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 603 { 604 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 605 606 if (hws) { 607 hws->ctx = ctx; 608 hws->regs = &hwseq_reg; 609 hws->shifts = &hwseq_shift; 610 hws->masks = &hwseq_mask; 611 } 612 return hws; 613 } 614 615 #define hubp_regs(id)\ 616 [id] = { HUBP_REG_LIST_DCN30(id) } 617 618 static const struct dcn_hubp2_registers hubp_regs[] = { 619 hubp_regs(0), 620 hubp_regs(1), 621 hubp_regs(2), 622 hubp_regs(3), 623 hubp_regs(4) 624 }; 625 626 static const struct dcn_hubp2_shift hubp_shift = { 627 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 628 }; 629 630 static const struct dcn_hubp2_mask hubp_mask = { 631 HUBP_MASK_SH_LIST_DCN30(_MASK) 632 }; 633 634 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 635 { 636 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 637 638 if (!hubp2) 639 return NULL; 640 641 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 642 return &hubp2->base; 643 644 BREAK_TO_DEBUGGER(); 645 kfree(hubp2); 646 return NULL; 647 } 648 649 #define dpp_regs(id)\ 650 [id] = { DPP_REG_LIST_DCN30(id) } 651 652 static const struct dcn3_dpp_registers dpp_regs[] = { 653 dpp_regs(0), 654 dpp_regs(1), 655 dpp_regs(2), 656 dpp_regs(3), 657 dpp_regs(4) 658 }; 659 660 static const struct dcn3_dpp_shift tf_shift = { 661 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 662 }; 663 664 static const struct dcn3_dpp_mask tf_mask = { 665 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 666 }; 667 668 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 669 { 670 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 671 672 if (!dpp) 673 return NULL; 674 675 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 676 return &dpp->base; 677 678 BREAK_TO_DEBUGGER(); 679 kfree(dpp); 680 return NULL; 681 } 682 683 #define opp_regs(id)\ 684 [id] = { OPP_REG_LIST_DCN30(id) } 685 686 static const struct dcn20_opp_registers opp_regs[] = { 687 opp_regs(0), 688 opp_regs(1), 689 opp_regs(2), 690 opp_regs(3), 691 opp_regs(4) 692 }; 693 694 static const struct dcn20_opp_shift opp_shift = { 695 OPP_MASK_SH_LIST_DCN20(__SHIFT) 696 }; 697 698 static const struct dcn20_opp_mask opp_mask = { 699 OPP_MASK_SH_LIST_DCN20(_MASK) 700 }; 701 702 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 703 { 704 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 705 706 if (!opp) { 707 BREAK_TO_DEBUGGER(); 708 return NULL; 709 } 710 711 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 712 return &opp->base; 713 } 714 715 #define optc_regs(id)\ 716 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 717 718 static const struct dcn_optc_registers optc_regs[] = { 719 optc_regs(0), 720 optc_regs(1), 721 optc_regs(2), 722 optc_regs(3), 723 optc_regs(4) 724 }; 725 726 static const struct dcn_optc_shift optc_shift = { 727 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 728 }; 729 730 static const struct dcn_optc_mask optc_mask = { 731 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 732 }; 733 734 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 735 { 736 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 737 738 if (!tgn10) 739 return NULL; 740 741 tgn10->base.inst = instance; 742 tgn10->base.ctx = ctx; 743 744 tgn10->tg_regs = &optc_regs[instance]; 745 tgn10->tg_shift = &optc_shift; 746 tgn10->tg_mask = &optc_mask; 747 748 dcn30_timing_generator_init(tgn10); 749 750 return &tgn10->base; 751 } 752 753 static const struct dcn30_mpc_registers mpc_regs = { 754 MPC_REG_LIST_DCN3_0(0), 755 MPC_REG_LIST_DCN3_0(1), 756 MPC_REG_LIST_DCN3_0(2), 757 MPC_REG_LIST_DCN3_0(3), 758 MPC_REG_LIST_DCN3_0(4), 759 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 760 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 761 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 762 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 763 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 764 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 765 MPC_RMU_REG_LIST_DCN3AG(0), 766 MPC_RMU_REG_LIST_DCN3AG(1), 767 MPC_RMU_REG_LIST_DCN3AG(2), 768 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 769 }; 770 771 static const struct dcn30_mpc_shift mpc_shift = { 772 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 773 }; 774 775 static const struct dcn30_mpc_mask mpc_mask = { 776 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 777 }; 778 779 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 780 { 781 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 782 783 if (!mpc30) 784 return NULL; 785 786 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 787 788 return &mpc30->base; 789 } 790 791 #define dsc_regsDCN20(id)\ 792 [id] = { DSC_REG_LIST_DCN20(id) } 793 794 static const struct dcn20_dsc_registers dsc_regs[] = { 795 dsc_regsDCN20(0), 796 dsc_regsDCN20(1), 797 dsc_regsDCN20(2), 798 dsc_regsDCN20(3), 799 dsc_regsDCN20(4) 800 }; 801 802 static const struct dcn20_dsc_shift dsc_shift = { 803 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 804 }; 805 806 static const struct dcn20_dsc_mask dsc_mask = { 807 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 808 }; 809 810 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 811 { 812 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 813 814 if (!dsc) { 815 BREAK_TO_DEBUGGER(); 816 return NULL; 817 } 818 819 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 820 return &dsc->base; 821 } 822 823 #define dwbc_regs_dcn3(id)\ 824 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 825 826 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 827 dwbc_regs_dcn3(0) 828 }; 829 830 static const struct dcn30_dwbc_shift dwbc30_shift = { 831 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 832 }; 833 834 static const struct dcn30_dwbc_mask dwbc30_mask = { 835 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 836 }; 837 838 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 839 { 840 int i; 841 uint32_t pipe_count = pool->res_cap->num_dwb; 842 843 for (i = 0; i < pipe_count; i++) { 844 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 845 846 if (!dwbc30) { 847 dm_error("DC: failed to create dwbc30!\n"); 848 return false; 849 } 850 851 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 852 853 pool->dwbc[i] = &dwbc30->base; 854 } 855 return true; 856 } 857 858 #define mcif_wb_regs_dcn3(id)\ 859 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 860 861 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 862 mcif_wb_regs_dcn3(0) 863 }; 864 865 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 866 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 867 }; 868 869 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 870 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 871 }; 872 873 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 874 { 875 int i; 876 uint32_t pipe_count = pool->res_cap->num_dwb; 877 878 for (i = 0; i < pipe_count; i++) { 879 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 880 881 if (!mcif_wb30) { 882 dm_error("DC: failed to create mcif_wb30!\n"); 883 return false; 884 } 885 886 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 887 888 pool->mcif_wb[i] = &mcif_wb30->base; 889 } 890 return true; 891 } 892 893 #define aux_engine_regs(id)\ 894 [id] = {\ 895 AUX_COMMON_REG_LIST0(id), \ 896 .AUXN_IMPCAL = 0, \ 897 .AUXP_IMPCAL = 0, \ 898 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 899 } 900 901 static const struct dce110_aux_registers aux_engine_regs[] = { 902 aux_engine_regs(0), 903 aux_engine_regs(1), 904 aux_engine_regs(2), 905 aux_engine_regs(3), 906 aux_engine_regs(4) 907 }; 908 909 static const struct dce110_aux_registers_shift aux_shift = { 910 DCN_AUX_MASK_SH_LIST(__SHIFT) 911 }; 912 913 static const struct dce110_aux_registers_mask aux_mask = { 914 DCN_AUX_MASK_SH_LIST(_MASK) 915 }; 916 917 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 918 { 919 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 920 921 if (!aux_engine) 922 return NULL; 923 924 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 925 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 926 927 return &aux_engine->base; 928 } 929 930 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 931 932 static const struct dce_i2c_registers i2c_hw_regs[] = { 933 i2c_inst_regs(1), 934 i2c_inst_regs(2), 935 i2c_inst_regs(3), 936 i2c_inst_regs(4), 937 i2c_inst_regs(5) 938 }; 939 940 static const struct dce_i2c_shift i2c_shifts = { 941 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 942 }; 943 944 static const struct dce_i2c_mask i2c_masks = { 945 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 946 }; 947 948 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 949 { 950 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 951 952 if (!dce_i2c_hw) 953 return NULL; 954 955 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 956 957 return dce_i2c_hw; 958 } 959 960 static const struct encoder_feature_support link_enc_feature = { 961 .max_hdmi_deep_color = COLOR_DEPTH_121212, 962 .max_hdmi_pixel_clock = 600000, 963 .hdmi_ycbcr420_supported = true, 964 .dp_ycbcr420_supported = true, 965 .fec_supported = true, 966 .flags.bits.IS_HBR2_CAPABLE = true, 967 .flags.bits.IS_HBR3_CAPABLE = true, 968 .flags.bits.IS_TPS3_CAPABLE = true, 969 .flags.bits.IS_TPS4_CAPABLE = true 970 }; 971 972 #define link_regs(id, phyid)\ 973 [id] = {\ 974 LE_DCN3_REG_LIST(id), \ 975 UNIPHY_DCN2_REG_LIST(phyid), \ 976 DPCS_DCN2_REG_LIST(id), \ 977 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 978 } 979 980 static const struct dcn10_link_enc_registers link_enc_regs[] = { 981 link_regs(0, A), 982 link_regs(1, B), 983 link_regs(2, C), 984 link_regs(3, D), 985 link_regs(4, E) 986 }; 987 988 static const struct dcn10_link_enc_shift le_shift = { 989 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 990 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 991 }; 992 993 static const struct dcn10_link_enc_mask le_mask = { 994 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 995 DPCS_DCN2_MASK_SH_LIST(_MASK) 996 }; 997 998 #define aux_regs(id)\ 999 [id] = { DCN2_AUX_REG_LIST(id) } 1000 1001 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1002 aux_regs(0), 1003 aux_regs(1), 1004 aux_regs(2), 1005 aux_regs(3), 1006 aux_regs(4) 1007 }; 1008 1009 #define hpd_regs(id)\ 1010 [id] = { HPD_REG_LIST(id) } 1011 1012 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1013 hpd_regs(0), 1014 hpd_regs(1), 1015 hpd_regs(2), 1016 hpd_regs(3), 1017 hpd_regs(4) 1018 }; 1019 1020 static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data) 1021 { 1022 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1023 1024 if (!enc20) 1025 return NULL; 1026 1027 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 1028 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 1029 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 1030 1031 return &enc20->enc10.base; 1032 } 1033 1034 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1035 { DCN_PANEL_CNTL_REG_LIST() } 1036 }; 1037 1038 static const struct dce_panel_cntl_shift panel_cntl_shift = { 1039 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1040 }; 1041 1042 static const struct dce_panel_cntl_mask panel_cntl_mask = { 1043 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1044 }; 1045 1046 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1047 { 1048 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1049 1050 if (!panel_cntl) 1051 return NULL; 1052 1053 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 1054 &panel_cntl_shift, &panel_cntl_mask); 1055 1056 return &panel_cntl->base; 1057 } 1058 1059 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 1060 { 1061 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1062 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1063 } 1064 1065 static const struct resource_create_funcs res_create_funcs = { 1066 .read_dce_straps = read_dce_straps, 1067 .create_audio = dcn302_create_audio, 1068 .create_stream_encoder = dcn302_stream_encoder_create, 1069 .create_hwseq = dcn302_hwseq_create, 1070 }; 1071 1072 static const struct resource_create_funcs res_create_maximus_funcs = { 1073 .read_dce_straps = NULL, 1074 .create_audio = NULL, 1075 .create_stream_encoder = NULL, 1076 .create_hwseq = dcn302_hwseq_create, 1077 }; 1078 1079 static bool is_soc_bounding_box_valid(struct dc *dc) 1080 { 1081 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1082 1083 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 1084 return true; 1085 1086 return false; 1087 } 1088 1089 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 1090 { 1091 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 1092 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 1093 1094 DC_LOGGER_INIT(dc->ctx->logger); 1095 1096 if (!is_soc_bounding_box_valid(dc)) { 1097 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1098 return false; 1099 } 1100 1101 loaded_ip->max_num_otg = pool->pipe_count; 1102 loaded_ip->max_num_dpp = pool->pipe_count; 1103 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1104 dcn20_patch_bounding_box(dc, loaded_bb); 1105 return true; 1106 } 1107 1108 static void dcn302_resource_destruct(struct resource_pool *pool) 1109 { 1110 unsigned int i; 1111 1112 for (i = 0; i < pool->stream_enc_count; i++) { 1113 if (pool->stream_enc[i] != NULL) { 1114 if (pool->stream_enc[i]->vpg != NULL) { 1115 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1116 pool->stream_enc[i]->vpg = NULL; 1117 } 1118 if (pool->stream_enc[i]->afmt != NULL) { 1119 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1120 pool->stream_enc[i]->afmt = NULL; 1121 } 1122 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1123 pool->stream_enc[i] = NULL; 1124 } 1125 } 1126 1127 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1128 if (pool->dscs[i] != NULL) 1129 dcn20_dsc_destroy(&pool->dscs[i]); 1130 } 1131 1132 if (pool->mpc != NULL) { 1133 kfree(TO_DCN20_MPC(pool->mpc)); 1134 pool->mpc = NULL; 1135 } 1136 1137 if (pool->hubbub != NULL) { 1138 kfree(pool->hubbub); 1139 pool->hubbub = NULL; 1140 } 1141 1142 for (i = 0; i < pool->pipe_count; i++) { 1143 if (pool->dpps[i] != NULL) { 1144 kfree(TO_DCN20_DPP(pool->dpps[i])); 1145 pool->dpps[i] = NULL; 1146 } 1147 1148 if (pool->hubps[i] != NULL) { 1149 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1150 pool->hubps[i] = NULL; 1151 } 1152 1153 if (pool->irqs != NULL) 1154 dal_irq_service_destroy(&pool->irqs); 1155 } 1156 1157 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1158 if (pool->engines[i] != NULL) 1159 dce110_engine_destroy(&pool->engines[i]); 1160 if (pool->hw_i2cs[i] != NULL) { 1161 kfree(pool->hw_i2cs[i]); 1162 pool->hw_i2cs[i] = NULL; 1163 } 1164 if (pool->sw_i2cs[i] != NULL) { 1165 kfree(pool->sw_i2cs[i]); 1166 pool->sw_i2cs[i] = NULL; 1167 } 1168 } 1169 1170 for (i = 0; i < pool->res_cap->num_opp; i++) { 1171 if (pool->opps[i] != NULL) 1172 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1173 } 1174 1175 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1176 if (pool->timing_generators[i] != NULL) { 1177 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1178 pool->timing_generators[i] = NULL; 1179 } 1180 } 1181 1182 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1183 if (pool->dwbc[i] != NULL) { 1184 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1185 pool->dwbc[i] = NULL; 1186 } 1187 if (pool->mcif_wb[i] != NULL) { 1188 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1189 pool->mcif_wb[i] = NULL; 1190 } 1191 } 1192 1193 for (i = 0; i < pool->audio_count; i++) { 1194 if (pool->audios[i]) 1195 dce_aud_destroy(&pool->audios[i]); 1196 } 1197 1198 for (i = 0; i < pool->clk_src_count; i++) { 1199 if (pool->clock_sources[i] != NULL) 1200 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1201 } 1202 1203 if (pool->dp_clock_source != NULL) 1204 dcn20_clock_source_destroy(&pool->dp_clock_source); 1205 1206 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1207 if (pool->mpc_lut[i] != NULL) { 1208 dc_3dlut_func_release(pool->mpc_lut[i]); 1209 pool->mpc_lut[i] = NULL; 1210 } 1211 if (pool->mpc_shaper[i] != NULL) { 1212 dc_transfer_func_release(pool->mpc_shaper[i]); 1213 pool->mpc_shaper[i] = NULL; 1214 } 1215 } 1216 1217 for (i = 0; i < pool->pipe_count; i++) { 1218 if (pool->multiple_abms[i] != NULL) 1219 dce_abm_destroy(&pool->multiple_abms[i]); 1220 } 1221 1222 if (pool->psr != NULL) 1223 dmub_psr_destroy(&pool->psr); 1224 1225 if (pool->dccg != NULL) 1226 dcn_dccg_destroy(&pool->dccg); 1227 } 1228 1229 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1230 { 1231 dcn302_resource_destruct(*pool); 1232 kfree(*pool); 1233 *pool = NULL; 1234 } 1235 1236 static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1237 unsigned int *optimal_dcfclk, 1238 unsigned int *optimal_fclk) 1239 { 1240 double bw_from_dram, bw_from_dram1, bw_from_dram2; 1241 1242 bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans * 1243 dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_dram_bw_use_normal_percent / 100); 1244 bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans * 1245 dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100); 1246 1247 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1248 1249 if (optimal_fclk) 1250 *optimal_fclk = bw_from_dram / 1251 (dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1252 1253 if (optimal_dcfclk) 1254 *optimal_dcfclk = bw_from_dram / 1255 (dcn3_02_soc.return_bus_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1256 } 1257 1258 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1259 { 1260 unsigned int i, j; 1261 unsigned int num_states = 0; 1262 1263 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 1264 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 1265 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 1266 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 1267 1268 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; 1269 unsigned int num_dcfclk_sta_targets = 4; 1270 unsigned int num_uclk_states; 1271 1272 1273 if (dc->ctx->dc_bios->vram_info.num_chans) 1274 dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 1275 1276 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 1277 dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 1278 1279 dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1280 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1281 1282 if (bw_params->clk_table.entries[0].memclk_mhz) { 1283 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 1284 1285 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 1286 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 1287 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 1288 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 1289 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 1290 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 1291 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 1292 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 1293 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 1294 } 1295 if (!max_dcfclk_mhz) 1296 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; 1297 if (!max_dispclk_mhz) 1298 max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; 1299 if (!max_dppclk_mhz) 1300 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; 1301 if (!max_phyclk_mhz) 1302 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; 1303 1304 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1305 /* If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array */ 1306 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 1307 num_dcfclk_sta_targets++; 1308 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1309 /* If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates */ 1310 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1311 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 1312 dcfclk_sta_targets[i] = max_dcfclk_mhz; 1313 break; 1314 } 1315 } 1316 /* Update size of array since we "removed" duplicates */ 1317 num_dcfclk_sta_targets = i + 1; 1318 } 1319 1320 num_uclk_states = bw_params->clk_table.num_entries; 1321 1322 /* Calculate optimal dcfclk for each uclk */ 1323 for (i = 0; i < num_uclk_states; i++) { 1324 dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 1325 &optimal_dcfclk_for_uclk[i], NULL); 1326 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 1327 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 1328 } 1329 } 1330 1331 /* Calculate optimal uclk for each dcfclk sta target */ 1332 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1333 for (j = 0; j < num_uclk_states; j++) { 1334 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 1335 optimal_uclk_for_dcfclk_sta_targets[i] = 1336 bw_params->clk_table.entries[j].memclk_mhz * 16; 1337 break; 1338 } 1339 } 1340 } 1341 1342 i = 0; 1343 j = 0; 1344 /* create the final dcfclk and uclk table */ 1345 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 1346 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 1347 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1348 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1349 } else { 1350 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1351 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1352 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1353 } else { 1354 j = num_uclk_states; 1355 } 1356 } 1357 } 1358 1359 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 1360 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1361 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1362 } 1363 1364 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 1365 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1366 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1367 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1368 } 1369 1370 dcn3_02_soc.num_states = num_states; 1371 for (i = 0; i < dcn3_02_soc.num_states; i++) { 1372 dcn3_02_soc.clock_limits[i].state = i; 1373 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 1374 dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 1375 dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 1376 1377 /* Fill all states with max values of all other clocks */ 1378 dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1379 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1380 dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1381 dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz; 1382 /* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */ 1383 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 1384 dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz; 1385 dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[0].socclk_mhz; 1386 dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz; 1387 } 1388 /* re-init DML with updated bb */ 1389 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1390 if (dc->current_state) 1391 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1392 } 1393 } 1394 1395 static struct resource_funcs dcn302_res_pool_funcs = { 1396 .destroy = dcn302_destroy_resource_pool, 1397 .link_enc_create = dcn302_link_encoder_create, 1398 .panel_cntl_create = dcn302_panel_cntl_create, 1399 .validate_bandwidth = dcn30_validate_bandwidth, 1400 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1401 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1402 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1403 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1404 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1405 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1406 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1407 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1408 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1409 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1410 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1411 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1412 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1413 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1414 }; 1415 1416 static struct dc_cap_funcs cap_funcs = { 1417 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1418 }; 1419 1420 static const struct bios_registers bios_regs = { 1421 NBIO_SR(BIOS_SCRATCH_3), 1422 NBIO_SR(BIOS_SCRATCH_6) 1423 }; 1424 1425 static const struct dccg_registers dccg_regs = { 1426 DCCG_REG_LIST_DCN3_02() 1427 }; 1428 1429 static const struct dccg_shift dccg_shift = { 1430 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1431 }; 1432 1433 static const struct dccg_mask dccg_mask = { 1434 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1435 }; 1436 1437 #define abm_regs(id)\ 1438 [id] = { ABM_DCN301_REG_LIST(id) } 1439 1440 static const struct dce_abm_registers abm_regs[] = { 1441 abm_regs(0), 1442 abm_regs(1), 1443 abm_regs(2), 1444 abm_regs(3), 1445 abm_regs(4) 1446 }; 1447 1448 static const struct dce_abm_shift abm_shift = { 1449 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1450 }; 1451 1452 static const struct dce_abm_mask abm_mask = { 1453 ABM_MASK_SH_LIST_DCN30(_MASK) 1454 }; 1455 1456 static bool dcn302_resource_construct( 1457 uint8_t num_virtual_links, 1458 struct dc *dc, 1459 struct resource_pool *pool) 1460 { 1461 int i; 1462 struct dc_context *ctx = dc->ctx; 1463 struct irq_service_init_data init_data; 1464 1465 ctx->dc_bios->regs = &bios_regs; 1466 1467 pool->res_cap = &res_cap_dcn302; 1468 1469 pool->funcs = &dcn302_res_pool_funcs; 1470 1471 /************************************************* 1472 * Resource + asic cap harcoding * 1473 *************************************************/ 1474 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1475 pool->pipe_count = pool->res_cap->num_timing_generator; 1476 pool->mpcc_count = pool->res_cap->num_timing_generator; 1477 dc->caps.max_downscale_ratio = 600; 1478 dc->caps.i2c_speed_in_khz = 100; 1479 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1480 dc->caps.max_cursor_size = 256; 1481 dc->caps.min_horizontal_blanking_period = 80; 1482 dc->caps.dmdata_alloc_size = 2048; 1483 dc->caps.mall_size_per_mem_channel = 4; 1484 /* total size = mall per channel * num channels * 1024 * 1024 */ 1485 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1486 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1487 dc->caps.max_slave_planes = 1; 1488 dc->caps.max_slave_yuv_planes = 1; 1489 dc->caps.max_slave_rgb_planes = 1; 1490 dc->caps.post_blend_color_processing = true; 1491 dc->caps.force_dp_tps4_for_cp2520 = true; 1492 dc->caps.extended_aux_timeout_support = true; 1493 dc->caps.dmcub_support = true; 1494 1495 /* Color pipeline capabilities */ 1496 dc->caps.color.dpp.dcn_arch = 1; 1497 dc->caps.color.dpp.input_lut_shared = 0; 1498 dc->caps.color.dpp.icsc = 1; 1499 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1500 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1501 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1502 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1503 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1504 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1505 dc->caps.color.dpp.post_csc = 1; 1506 dc->caps.color.dpp.gamma_corr = 1; 1507 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1508 1509 dc->caps.color.dpp.hw_3d_lut = 1; 1510 dc->caps.color.dpp.ogam_ram = 1; 1511 // no OGAM ROM on DCN3 1512 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1513 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1514 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1515 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1516 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1517 dc->caps.color.dpp.ocsc = 0; 1518 1519 dc->caps.color.mpc.gamut_remap = 1; 1520 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1521 dc->caps.color.mpc.ogam_ram = 1; 1522 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1523 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1524 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1525 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1526 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1527 dc->caps.color.mpc.ocsc = 1; 1528 1529 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1530 dc->debug = debug_defaults_drv; 1531 else 1532 dc->debug = debug_defaults_diags; 1533 1534 // Init the vm_helper 1535 if (dc->vm_helper) 1536 vm_helper_init(dc->vm_helper, 16); 1537 1538 /************************************************* 1539 * Create resources * 1540 *************************************************/ 1541 1542 /* Clock Sources for Pixel Clock*/ 1543 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1544 dcn302_clock_source_create(ctx, ctx->dc_bios, 1545 CLOCK_SOURCE_COMBO_PHY_PLL0, 1546 &clk_src_regs[0], false); 1547 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1548 dcn302_clock_source_create(ctx, ctx->dc_bios, 1549 CLOCK_SOURCE_COMBO_PHY_PLL1, 1550 &clk_src_regs[1], false); 1551 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1552 dcn302_clock_source_create(ctx, ctx->dc_bios, 1553 CLOCK_SOURCE_COMBO_PHY_PLL2, 1554 &clk_src_regs[2], false); 1555 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1556 dcn302_clock_source_create(ctx, ctx->dc_bios, 1557 CLOCK_SOURCE_COMBO_PHY_PLL3, 1558 &clk_src_regs[3], false); 1559 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1560 dcn302_clock_source_create(ctx, ctx->dc_bios, 1561 CLOCK_SOURCE_COMBO_PHY_PLL4, 1562 &clk_src_regs[4], false); 1563 1564 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1565 1566 /* todo: not reuse phy_pll registers */ 1567 pool->dp_clock_source = 1568 dcn302_clock_source_create(ctx, ctx->dc_bios, 1569 CLOCK_SOURCE_ID_DP_DTO, 1570 &clk_src_regs[0], true); 1571 1572 for (i = 0; i < pool->clk_src_count; i++) { 1573 if (pool->clock_sources[i] == NULL) { 1574 dm_error("DC: failed to create clock sources!\n"); 1575 BREAK_TO_DEBUGGER(); 1576 goto create_fail; 1577 } 1578 } 1579 1580 /* DCCG */ 1581 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1582 if (pool->dccg == NULL) { 1583 dm_error("DC: failed to create dccg!\n"); 1584 BREAK_TO_DEBUGGER(); 1585 goto create_fail; 1586 } 1587 1588 /* PP Lib and SMU interfaces */ 1589 init_soc_bounding_box(dc, pool); 1590 1591 /* DML */ 1592 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1593 1594 /* IRQ */ 1595 init_data.ctx = dc->ctx; 1596 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1597 if (!pool->irqs) 1598 goto create_fail; 1599 1600 /* HUBBUB */ 1601 pool->hubbub = dcn302_hubbub_create(ctx); 1602 if (pool->hubbub == NULL) { 1603 BREAK_TO_DEBUGGER(); 1604 dm_error("DC: failed to create hubbub!\n"); 1605 goto create_fail; 1606 } 1607 1608 /* HUBPs, DPPs, OPPs and TGs */ 1609 for (i = 0; i < pool->pipe_count; i++) { 1610 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1611 if (pool->hubps[i] == NULL) { 1612 BREAK_TO_DEBUGGER(); 1613 dm_error("DC: failed to create hubps!\n"); 1614 goto create_fail; 1615 } 1616 1617 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1618 if (pool->dpps[i] == NULL) { 1619 BREAK_TO_DEBUGGER(); 1620 dm_error("DC: failed to create dpps!\n"); 1621 goto create_fail; 1622 } 1623 } 1624 1625 for (i = 0; i < pool->res_cap->num_opp; i++) { 1626 pool->opps[i] = dcn302_opp_create(ctx, i); 1627 if (pool->opps[i] == NULL) { 1628 BREAK_TO_DEBUGGER(); 1629 dm_error("DC: failed to create output pixel processor!\n"); 1630 goto create_fail; 1631 } 1632 } 1633 1634 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1635 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1636 if (pool->timing_generators[i] == NULL) { 1637 BREAK_TO_DEBUGGER(); 1638 dm_error("DC: failed to create tg!\n"); 1639 goto create_fail; 1640 } 1641 } 1642 pool->timing_generator_count = i; 1643 1644 /* PSR */ 1645 pool->psr = dmub_psr_create(ctx); 1646 if (pool->psr == NULL) { 1647 dm_error("DC: failed to create psr!\n"); 1648 BREAK_TO_DEBUGGER(); 1649 goto create_fail; 1650 } 1651 1652 /* ABMs */ 1653 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1654 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1655 if (pool->multiple_abms[i] == NULL) { 1656 dm_error("DC: failed to create abm for pipe %d!\n", i); 1657 BREAK_TO_DEBUGGER(); 1658 goto create_fail; 1659 } 1660 } 1661 1662 /* MPC and DSC */ 1663 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1664 if (pool->mpc == NULL) { 1665 BREAK_TO_DEBUGGER(); 1666 dm_error("DC: failed to create mpc!\n"); 1667 goto create_fail; 1668 } 1669 1670 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1671 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1672 if (pool->dscs[i] == NULL) { 1673 BREAK_TO_DEBUGGER(); 1674 dm_error("DC: failed to create display stream compressor %d!\n", i); 1675 goto create_fail; 1676 } 1677 } 1678 1679 /* DWB and MMHUBBUB */ 1680 if (!dcn302_dwbc_create(ctx, pool)) { 1681 BREAK_TO_DEBUGGER(); 1682 dm_error("DC: failed to create dwbc!\n"); 1683 goto create_fail; 1684 } 1685 1686 if (!dcn302_mmhubbub_create(ctx, pool)) { 1687 BREAK_TO_DEBUGGER(); 1688 dm_error("DC: failed to create mcif_wb!\n"); 1689 goto create_fail; 1690 } 1691 1692 /* AUX and I2C */ 1693 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1694 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1695 if (pool->engines[i] == NULL) { 1696 BREAK_TO_DEBUGGER(); 1697 dm_error("DC:failed to create aux engine!!\n"); 1698 goto create_fail; 1699 } 1700 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1701 if (pool->hw_i2cs[i] == NULL) { 1702 BREAK_TO_DEBUGGER(); 1703 dm_error("DC:failed to create hw i2c!!\n"); 1704 goto create_fail; 1705 } 1706 pool->sw_i2cs[i] = NULL; 1707 } 1708 1709 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1710 if (!resource_construct(num_virtual_links, dc, pool, 1711 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1712 &res_create_funcs : &res_create_maximus_funcs))) 1713 goto create_fail; 1714 1715 /* HW Sequencer and Plane caps */ 1716 dcn302_hw_sequencer_construct(dc); 1717 1718 dc->caps.max_planes = pool->pipe_count; 1719 1720 for (i = 0; i < dc->caps.max_planes; ++i) 1721 dc->caps.planes[i] = plane_cap; 1722 1723 dc->cap_funcs = cap_funcs; 1724 1725 return true; 1726 1727 create_fail: 1728 1729 dcn302_resource_destruct(pool); 1730 1731 return false; 1732 } 1733 1734 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1735 { 1736 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1737 1738 if (!pool) 1739 return NULL; 1740 1741 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1742 return pool; 1743 1744 BREAK_TO_DEBUGGER(); 1745 kfree(pool); 1746 return NULL; 1747 } 1748