1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dcn302_init.h"
27 #include "dcn302_resource.h"
28 #include "dcn302_dccg.h"
29 #include "irq/dcn302/irq_service_dcn302.h"
30 
31 #include "dcn30/dcn30_dio_link_encoder.h"
32 #include "dcn30/dcn30_dio_stream_encoder.h"
33 #include "dcn30/dcn30_dwb.h"
34 #include "dcn30/dcn30_dpp.h"
35 #include "dcn30/dcn30_hubbub.h"
36 #include "dcn30/dcn30_hubp.h"
37 #include "dcn30/dcn30_mmhubbub.h"
38 #include "dcn30/dcn30_mpc.h"
39 #include "dcn30/dcn30_opp.h"
40 #include "dcn30/dcn30_optc.h"
41 #include "dcn30/dcn30_resource.h"
42 
43 #include "dcn20/dcn20_dsc.h"
44 #include "dcn20/dcn20_resource.h"
45 
46 #include "dcn10/dcn10_resource.h"
47 
48 #include "dce/dce_abm.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_aux.h"
51 #include "dce/dce_clock_source.h"
52 #include "dce/dce_hwseq.h"
53 #include "dce/dce_i2c_hw.h"
54 #include "dce/dce_panel_cntl.h"
55 #include "dce/dmub_abm.h"
56 #include "dce/dmub_psr.h"
57 #include "clk_mgr.h"
58 
59 #include "hw_sequencer_private.h"
60 #include "reg_helper.h"
61 #include "resource.h"
62 #include "vm_helper.h"
63 
64 #include "dimgrey_cavefish_ip_offset.h"
65 #include "dcn/dcn_3_0_2_offset.h"
66 #include "dcn/dcn_3_0_2_sh_mask.h"
67 #include "dcn/dpcs_3_0_0_offset.h"
68 #include "dcn/dpcs_3_0_0_sh_mask.h"
69 #include "nbio/nbio_7_4_offset.h"
70 #include "amdgpu_socbb.h"
71 
72 #define DC_LOGGER_INIT(logger)
73 
74 struct _vcs_dpi_ip_params_st dcn3_02_ip = {
75 		.use_min_dcfclk = 0,
76 		.clamp_min_dcfclk = 0,
77 		.odm_capable = 1,
78 		.gpuvm_enable = 1,
79 		.hostvm_enable = 0,
80 		.gpuvm_max_page_table_levels = 4,
81 		.hostvm_max_page_table_levels = 4,
82 		.hostvm_cached_page_table_levels = 0,
83 		.pte_group_size_bytes = 2048,
84 		.num_dsc = 5,
85 		.rob_buffer_size_kbytes = 184,
86 		.det_buffer_size_kbytes = 184,
87 		.dpte_buffer_size_in_pte_reqs_luma = 64,
88 		.dpte_buffer_size_in_pte_reqs_chroma = 34,
89 		.pde_proc_buffer_size_64k_reqs = 48,
90 		.dpp_output_buffer_pixels = 2560,
91 		.opp_output_buffer_lines = 1,
92 		.pixel_chunk_size_kbytes = 8,
93 		.pte_enable = 1,
94 		.max_page_table_levels = 2,
95 		.pte_chunk_size_kbytes = 2,  // ?
96 		.meta_chunk_size_kbytes = 2,
97 		.writeback_chunk_size_kbytes = 8,
98 		.line_buffer_size_bits = 789504,
99 		.is_line_buffer_bpp_fixed = 0,  // ?
100 		.line_buffer_fixed_bpp = 0,     // ?
101 		.dcc_supported = true,
102 		.writeback_interface_buffer_size_kbytes = 90,
103 		.writeback_line_buffer_buffer_size = 0,
104 		.max_line_buffer_lines = 12,
105 		.writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
106 		.writeback_chroma_buffer_size_kbytes = 8,
107 		.writeback_chroma_line_buffer_width_pixels = 4,
108 		.writeback_max_hscl_ratio = 1,
109 		.writeback_max_vscl_ratio = 1,
110 		.writeback_min_hscl_ratio = 1,
111 		.writeback_min_vscl_ratio = 1,
112 		.writeback_max_hscl_taps = 1,
113 		.writeback_max_vscl_taps = 1,
114 		.writeback_line_buffer_luma_buffer_size = 0,
115 		.writeback_line_buffer_chroma_buffer_size = 14643,
116 		.cursor_buffer_size = 8,
117 		.cursor_chunk_size = 2,
118 		.max_num_otg = 5,
119 		.max_num_dpp = 5,
120 		.max_num_wb = 1,
121 		.max_dchub_pscl_bw_pix_per_clk = 4,
122 		.max_pscl_lb_bw_pix_per_clk = 2,
123 		.max_lb_vscl_bw_pix_per_clk = 4,
124 		.max_vscl_hscl_bw_pix_per_clk = 4,
125 		.max_hscl_ratio = 6,
126 		.max_vscl_ratio = 6,
127 		.hscl_mults = 4,
128 		.vscl_mults = 4,
129 		.max_hscl_taps = 8,
130 		.max_vscl_taps = 8,
131 		.dispclk_ramp_margin_percent = 1,
132 		.underscan_factor = 1.11,
133 		.min_vblank_lines = 32,
134 		.dppclk_delay_subtotal = 46,
135 		.dynamic_metadata_vm_enabled = true,
136 		.dppclk_delay_scl_lb_only = 16,
137 		.dppclk_delay_scl = 50,
138 		.dppclk_delay_cnvc_formatter = 27,
139 		.dppclk_delay_cnvc_cursor = 6,
140 		.dispclk_delay_subtotal = 119,
141 		.dcfclk_cstate_latency = 5.2, // SRExitTime
142 		.max_inter_dcn_tile_repeaters = 8,
143 		.max_num_hdmi_frl_outputs = 1,
144 		.odm_combine_4to1_supported = true,
145 
146 		.xfc_supported = false,
147 		.xfc_fill_bw_overhead_percent = 10.0,
148 		.xfc_fill_constant_bytes = 0,
149 		.gfx7_compat_tiling_supported = 0,
150 		.number_of_cursors = 1,
151 };
152 
153 struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = {
154 		.clock_limits = {
155 				{
156 						.state = 0,
157 						.dispclk_mhz = 562.0,
158 						.dppclk_mhz = 300.0,
159 						.phyclk_mhz = 300.0,
160 						.phyclk_d18_mhz = 667.0,
161 						.dscclk_mhz = 405.6,
162 				},
163 		},
164 
165 		.min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
166 		.num_states = 1,
167 		.sr_exit_time_us = 26.5,
168 		.sr_enter_plus_exit_time_us = 31,
169 		.urgent_latency_us = 4.0,
170 		.urgent_latency_pixel_data_only_us = 4.0,
171 		.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
172 		.urgent_latency_vm_data_only_us = 4.0,
173 		.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
174 		.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
175 		.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
176 		.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
177 		.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
178 		.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
179 		.max_avg_sdp_bw_use_normal_percent = 60.0,
180 		.max_avg_dram_bw_use_normal_percent = 40.0,
181 		.writeback_latency_us = 12.0,
182 		.max_request_size_bytes = 256,
183 		.fabric_datapath_to_dcn_data_return_bytes = 64,
184 		.dcn_downspread_percent = 0.5,
185 		.downspread_percent = 0.38,
186 		.dram_page_open_time_ns = 50.0,
187 		.dram_rw_turnaround_time_ns = 17.5,
188 		.dram_return_buffer_per_channel_bytes = 8192,
189 		.round_trip_ping_latency_dcfclk_cycles = 156,
190 		.urgent_out_of_order_return_per_channel_bytes = 4096,
191 		.channel_interleave_bytes = 256,
192 		.num_banks = 8,
193 		.gpuvm_min_page_size_bytes = 4096,
194 		.hostvm_min_page_size_bytes = 4096,
195 		.dram_clock_change_latency_us = 404,
196 		.dummy_pstate_latency_us = 5,
197 		.writeback_dram_clock_change_latency_us = 23.0,
198 		.return_bus_width_bytes = 64,
199 		.dispclk_dppclk_vco_speed_mhz = 3650,
200 		.xfc_bus_transport_time_us = 20,      // ?
201 		.xfc_xbuf_latency_tolerance_us = 4,  // ?
202 		.use_urgent_burst_bw = 1,            // ?
203 		.do_urgent_latency_adjustment = true,
204 		.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
205 		.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
206 };
207 
208 static const struct dc_debug_options debug_defaults_drv = {
209 		.disable_dmcu = true,
210 		.force_abm_enable = false,
211 		.timing_trace = false,
212 		.clock_trace = true,
213 		.disable_pplib_clock_request = true,
214 		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
215 		.force_single_disp_pipe_split = false,
216 		.disable_dcc = DCC_ENABLE,
217 		.vsr_support = true,
218 		.performance_trace = false,
219 		.max_downscale_src_width = 7680,/*upto 8K*/
220 		.disable_pplib_wm_range = false,
221 		.scl_reset_length10 = true,
222 		.sanity_checks = false,
223 		.underflow_assert_delay_us = 0xFFFFFFFF,
224 		.dwb_fi_phase = -1, // -1 = disable,
225 		.dmub_command_table = true,
226 		.use_max_lb = true
227 };
228 
229 static const struct dc_debug_options debug_defaults_diags = {
230 		.disable_dmcu = true,
231 		.force_abm_enable = false,
232 		.timing_trace = true,
233 		.clock_trace = true,
234 		.disable_dpp_power_gate = true,
235 		.disable_hubp_power_gate = true,
236 		.disable_clock_gate = true,
237 		.disable_pplib_clock_request = true,
238 		.disable_pplib_wm_range = true,
239 		.disable_stutter = false,
240 		.scl_reset_length10 = true,
241 		.dwb_fi_phase = -1, // -1 = disable
242 		.dmub_command_table = true,
243 		.enable_tri_buf = true,
244 		.disable_psr = true,
245 		.use_max_lb = true
246 };
247 
248 enum dcn302_clk_src_array_id {
249 	DCN302_CLK_SRC_PLL0,
250 	DCN302_CLK_SRC_PLL1,
251 	DCN302_CLK_SRC_PLL2,
252 	DCN302_CLK_SRC_PLL3,
253 	DCN302_CLK_SRC_PLL4,
254 	DCN302_CLK_SRC_TOTAL
255 };
256 
257 static const struct resource_caps res_cap_dcn302 = {
258 		.num_timing_generator = 5,
259 		.num_opp = 5,
260 		.num_video_plane = 5,
261 		.num_audio = 5,
262 		.num_stream_encoder = 5,
263 		.num_dwb = 1,
264 		.num_ddc = 5,
265 		.num_vmid = 16,
266 		.num_mpc_3dlut = 2,
267 		.num_dsc = 5,
268 };
269 
270 static const struct dc_plane_cap plane_cap = {
271 		.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
272 		.blends_with_above = true,
273 		.blends_with_below = true,
274 		.per_pixel_alpha = true,
275 		.pixel_format_support = {
276 				.argb8888 = true,
277 				.nv12 = true,
278 				.fp16 = true,
279 				.p010 = false,
280 				.ayuv = false,
281 		},
282 		.max_upscale_factor = {
283 				.argb8888 = 16000,
284 				.nv12 = 16000,
285 				.fp16 = 16000
286 		},
287 		/* 6:1 downscaling ratio: 1000/6 = 166.666 */
288 		.max_downscale_factor = {
289 				.argb8888 = 167,
290 				.nv12 = 167,
291 				.fp16 = 167
292 		},
293 		16,
294 		16
295 };
296 
297 /* NBIO */
298 #define NBIO_BASE_INNER(seg) \
299 		NBIO_BASE__INST0_SEG ## seg
300 
301 #define NBIO_BASE(seg) \
302 		NBIO_BASE_INNER(seg)
303 
304 #define NBIO_SR(reg_name)\
305 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
306 		mm ## reg_name
307 
308 /* DCN */
309 #undef BASE_INNER
310 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
311 
312 #define BASE(seg) BASE_INNER(seg)
313 
314 #define SR(reg_name)\
315 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
316 
317 #define SF(reg_name, field_name, post_fix)\
318 		.field_name = reg_name ## __ ## field_name ## post_fix
319 
320 #define SRI(reg_name, block, id)\
321 		.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
322 
323 #define SRI2(reg_name, block, id)\
324 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
325 
326 #define SRII(reg_name, block, id)\
327 		.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
328 		mm ## block ## id ## _ ## reg_name
329 
330 #define DCCG_SRII(reg_name, block, id)\
331 		.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
332 		mm ## block ## id ## _ ## reg_name
333 
334 #define VUPDATE_SRII(reg_name, block, id)\
335 		.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
336 		mm ## reg_name ## _ ## block ## id
337 
338 #define SRII_DWB(reg_name, temp_name, block, id)\
339 		.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
340 		mm ## block ## id ## _ ## temp_name
341 
342 #define SRII_MPC_RMU(reg_name, block, id)\
343 		.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
344 		mm ## block ## id ## _ ## reg_name
345 
346 static const struct dcn_hubbub_registers hubbub_reg = {
347 		HUBBUB_REG_LIST_DCN30(0)
348 };
349 
350 static const struct dcn_hubbub_shift hubbub_shift = {
351 		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
352 };
353 
354 static const struct dcn_hubbub_mask hubbub_mask = {
355 		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
356 };
357 
358 #define vmid_regs(id)\
359 		[id] = { DCN20_VMID_REG_LIST(id) }
360 
361 static const struct dcn_vmid_registers vmid_regs[] = {
362 		vmid_regs(0),
363 		vmid_regs(1),
364 		vmid_regs(2),
365 		vmid_regs(3),
366 		vmid_regs(4),
367 		vmid_regs(5),
368 		vmid_regs(6),
369 		vmid_regs(7),
370 		vmid_regs(8),
371 		vmid_regs(9),
372 		vmid_regs(10),
373 		vmid_regs(11),
374 		vmid_regs(12),
375 		vmid_regs(13),
376 		vmid_regs(14),
377 		vmid_regs(15)
378 };
379 
380 static const struct dcn20_vmid_shift vmid_shifts = {
381 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
382 };
383 
384 static const struct dcn20_vmid_mask vmid_masks = {
385 		DCN20_VMID_MASK_SH_LIST(_MASK)
386 };
387 
388 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
389 {
390 	int i;
391 
392 	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
393 
394 	if (!hubbub3)
395 		return NULL;
396 
397 	hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
398 
399 	for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
400 		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
401 
402 		vmid->ctx = ctx;
403 
404 		vmid->regs = &vmid_regs[i];
405 		vmid->shifts = &vmid_shifts;
406 		vmid->masks = &vmid_masks;
407 	}
408 
409 	return &hubbub3->base;
410 }
411 
412 #define vpg_regs(id)\
413 		[id] = { VPG_DCN3_REG_LIST(id) }
414 
415 static const struct dcn30_vpg_registers vpg_regs[] = {
416 		vpg_regs(0),
417 		vpg_regs(1),
418 		vpg_regs(2),
419 		vpg_regs(3),
420 		vpg_regs(4),
421 		vpg_regs(5)
422 };
423 
424 static const struct dcn30_vpg_shift vpg_shift = {
425 		DCN3_VPG_MASK_SH_LIST(__SHIFT)
426 };
427 
428 static const struct dcn30_vpg_mask vpg_mask = {
429 		DCN3_VPG_MASK_SH_LIST(_MASK)
430 };
431 
432 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
433 {
434 	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
435 
436 	if (!vpg3)
437 		return NULL;
438 
439 	vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
440 
441 	return &vpg3->base;
442 }
443 
444 #define afmt_regs(id)\
445 		[id] = { AFMT_DCN3_REG_LIST(id) }
446 
447 static const struct dcn30_afmt_registers afmt_regs[] = {
448 		afmt_regs(0),
449 		afmt_regs(1),
450 		afmt_regs(2),
451 		afmt_regs(3),
452 		afmt_regs(4),
453 		afmt_regs(5)
454 };
455 
456 static const struct dcn30_afmt_shift afmt_shift = {
457 		DCN3_AFMT_MASK_SH_LIST(__SHIFT)
458 };
459 
460 static const struct dcn30_afmt_mask afmt_mask = {
461 		DCN3_AFMT_MASK_SH_LIST(_MASK)
462 };
463 
464 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
465 {
466 	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
467 
468 	if (!afmt3)
469 		return NULL;
470 
471 	afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
472 
473 	return &afmt3->base;
474 }
475 
476 #define audio_regs(id)\
477 		[id] = { AUD_COMMON_REG_LIST(id) }
478 
479 static const struct dce_audio_registers audio_regs[] = {
480 		audio_regs(0),
481 		audio_regs(1),
482 		audio_regs(2),
483 		audio_regs(3),
484 		audio_regs(4),
485 		audio_regs(5),
486 		audio_regs(6)
487 };
488 
489 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
490 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
491 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
492 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
493 
494 static const struct dce_audio_shift audio_shift = {
495 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
496 };
497 
498 static const struct dce_audio_mask audio_mask = {
499 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
500 };
501 
502 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
503 {
504 	return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
505 }
506 
507 #define stream_enc_regs(id)\
508 		[id] = { SE_DCN3_REG_LIST(id) }
509 
510 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
511 		stream_enc_regs(0),
512 		stream_enc_regs(1),
513 		stream_enc_regs(2),
514 		stream_enc_regs(3),
515 		stream_enc_regs(4)
516 };
517 
518 static const struct dcn10_stream_encoder_shift se_shift = {
519 		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
520 };
521 
522 static const struct dcn10_stream_encoder_mask se_mask = {
523 		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
524 };
525 
526 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
527 {
528 	struct dcn10_stream_encoder *enc1;
529 	struct vpg *vpg;
530 	struct afmt *afmt;
531 	int vpg_inst;
532 	int afmt_inst;
533 
534 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
535 	if (eng_id <= ENGINE_ID_DIGE) {
536 		vpg_inst = eng_id;
537 		afmt_inst = eng_id;
538 	} else
539 		return NULL;
540 
541 	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
542 	vpg = dcn302_vpg_create(ctx, vpg_inst);
543 	afmt = dcn302_afmt_create(ctx, afmt_inst);
544 
545 	if (!enc1 || !vpg || !afmt) {
546 		kfree(enc1);
547 		kfree(vpg);
548 		kfree(afmt);
549 		return NULL;
550 	}
551 
552 	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
553 			&se_shift, &se_mask);
554 
555 	return &enc1->base;
556 }
557 
558 #define clk_src_regs(index, pllid)\
559 		[index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
560 
561 static const struct dce110_clk_src_regs clk_src_regs[] = {
562 		clk_src_regs(0, A),
563 		clk_src_regs(1, B),
564 		clk_src_regs(2, C),
565 		clk_src_regs(3, D),
566 		clk_src_regs(4, E)
567 };
568 
569 static const struct dce110_clk_src_shift cs_shift = {
570 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
571 };
572 
573 static const struct dce110_clk_src_mask cs_mask = {
574 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
575 };
576 
577 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
578 		enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
579 {
580 	struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
581 
582 	if (!clk_src)
583 		return NULL;
584 
585 	if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
586 		clk_src->base.dp_clk_src = dp_clk_src;
587 		return &clk_src->base;
588 	}
589 
590 	BREAK_TO_DEBUGGER();
591 	return NULL;
592 }
593 
594 static const struct dce_hwseq_registers hwseq_reg = {
595 		HWSEQ_DCN302_REG_LIST()
596 };
597 
598 static const struct dce_hwseq_shift hwseq_shift = {
599 		HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
600 };
601 
602 static const struct dce_hwseq_mask hwseq_mask = {
603 		HWSEQ_DCN302_MASK_SH_LIST(_MASK)
604 };
605 
606 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
607 {
608 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
609 
610 	if (hws) {
611 		hws->ctx = ctx;
612 		hws->regs = &hwseq_reg;
613 		hws->shifts = &hwseq_shift;
614 		hws->masks = &hwseq_mask;
615 	}
616 	return hws;
617 }
618 
619 #define hubp_regs(id)\
620 		[id] = { HUBP_REG_LIST_DCN30(id) }
621 
622 static const struct dcn_hubp2_registers hubp_regs[] = {
623 		hubp_regs(0),
624 		hubp_regs(1),
625 		hubp_regs(2),
626 		hubp_regs(3),
627 		hubp_regs(4)
628 };
629 
630 static const struct dcn_hubp2_shift hubp_shift = {
631 		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
632 };
633 
634 static const struct dcn_hubp2_mask hubp_mask = {
635 		HUBP_MASK_SH_LIST_DCN30(_MASK)
636 };
637 
638 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
639 {
640 	struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
641 
642 	if (!hubp2)
643 		return NULL;
644 
645 	if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
646 		return &hubp2->base;
647 
648 	BREAK_TO_DEBUGGER();
649 	kfree(hubp2);
650 	return NULL;
651 }
652 
653 #define dpp_regs(id)\
654 		[id] = { DPP_REG_LIST_DCN30(id) }
655 
656 static const struct dcn3_dpp_registers dpp_regs[] = {
657 		dpp_regs(0),
658 		dpp_regs(1),
659 		dpp_regs(2),
660 		dpp_regs(3),
661 		dpp_regs(4)
662 };
663 
664 static const struct dcn3_dpp_shift tf_shift = {
665 		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
666 };
667 
668 static const struct dcn3_dpp_mask tf_mask = {
669 		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
670 };
671 
672 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
673 {
674 	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
675 
676 	if (!dpp)
677 		return NULL;
678 
679 	if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
680 		return &dpp->base;
681 
682 	BREAK_TO_DEBUGGER();
683 	kfree(dpp);
684 	return NULL;
685 }
686 
687 #define opp_regs(id)\
688 		[id] = { OPP_REG_LIST_DCN30(id) }
689 
690 static const struct dcn20_opp_registers opp_regs[] = {
691 		opp_regs(0),
692 		opp_regs(1),
693 		opp_regs(2),
694 		opp_regs(3),
695 		opp_regs(4)
696 };
697 
698 static const struct dcn20_opp_shift opp_shift = {
699 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
700 };
701 
702 static const struct dcn20_opp_mask opp_mask = {
703 		OPP_MASK_SH_LIST_DCN20(_MASK)
704 };
705 
706 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
707 {
708 	struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
709 
710 	if (!opp) {
711 		BREAK_TO_DEBUGGER();
712 		return NULL;
713 	}
714 
715 	dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
716 	return &opp->base;
717 }
718 
719 #define optc_regs(id)\
720 		[id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
721 
722 static const struct dcn_optc_registers optc_regs[] = {
723 		optc_regs(0),
724 		optc_regs(1),
725 		optc_regs(2),
726 		optc_regs(3),
727 		optc_regs(4)
728 };
729 
730 static const struct dcn_optc_shift optc_shift = {
731 		OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
732 };
733 
734 static const struct dcn_optc_mask optc_mask = {
735 		OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
736 };
737 
738 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
739 {
740 	struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
741 
742 	if (!tgn10)
743 		return NULL;
744 
745 	tgn10->base.inst = instance;
746 	tgn10->base.ctx = ctx;
747 
748 	tgn10->tg_regs = &optc_regs[instance];
749 	tgn10->tg_shift = &optc_shift;
750 	tgn10->tg_mask = &optc_mask;
751 
752 	dcn30_timing_generator_init(tgn10);
753 
754 	return &tgn10->base;
755 }
756 
757 static const struct dcn30_mpc_registers mpc_regs = {
758 		MPC_REG_LIST_DCN3_0(0),
759 		MPC_REG_LIST_DCN3_0(1),
760 		MPC_REG_LIST_DCN3_0(2),
761 		MPC_REG_LIST_DCN3_0(3),
762 		MPC_REG_LIST_DCN3_0(4),
763 		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
764 		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
765 		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
766 		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
767 		MPC_OUT_MUX_REG_LIST_DCN3_0(4),
768 		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
769 		MPC_RMU_REG_LIST_DCN3AG(0),
770 		MPC_RMU_REG_LIST_DCN3AG(1),
771 		MPC_RMU_REG_LIST_DCN3AG(2),
772 		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
773 };
774 
775 static const struct dcn30_mpc_shift mpc_shift = {
776 		MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
777 };
778 
779 static const struct dcn30_mpc_mask mpc_mask = {
780 		MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
781 };
782 
783 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
784 {
785 	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
786 
787 	if (!mpc30)
788 		return NULL;
789 
790 	dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
791 
792 	return &mpc30->base;
793 }
794 
795 #define dsc_regsDCN20(id)\
796 [id] = { DSC_REG_LIST_DCN20(id) }
797 
798 static const struct dcn20_dsc_registers dsc_regs[] = {
799 		dsc_regsDCN20(0),
800 		dsc_regsDCN20(1),
801 		dsc_regsDCN20(2),
802 		dsc_regsDCN20(3),
803 		dsc_regsDCN20(4)
804 };
805 
806 static const struct dcn20_dsc_shift dsc_shift = {
807 		DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
808 };
809 
810 static const struct dcn20_dsc_mask dsc_mask = {
811 		DSC_REG_LIST_SH_MASK_DCN20(_MASK)
812 };
813 
814 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
815 {
816 	struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
817 
818 	if (!dsc) {
819 		BREAK_TO_DEBUGGER();
820 		return NULL;
821 	}
822 
823 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
824 	return &dsc->base;
825 }
826 
827 #define dwbc_regs_dcn3(id)\
828 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
829 
830 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
831 		dwbc_regs_dcn3(0)
832 };
833 
834 static const struct dcn30_dwbc_shift dwbc30_shift = {
835 		DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
836 };
837 
838 static const struct dcn30_dwbc_mask dwbc30_mask = {
839 		DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
840 };
841 
842 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
843 {
844 	int i;
845 	uint32_t pipe_count = pool->res_cap->num_dwb;
846 
847 	for (i = 0; i < pipe_count; i++) {
848 		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
849 
850 		if (!dwbc30) {
851 			dm_error("DC: failed to create dwbc30!\n");
852 			return false;
853 		}
854 
855 		dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
856 
857 		pool->dwbc[i] = &dwbc30->base;
858 	}
859 	return true;
860 }
861 
862 #define mcif_wb_regs_dcn3(id)\
863 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
864 
865 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
866 		mcif_wb_regs_dcn3(0)
867 };
868 
869 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
870 		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
871 };
872 
873 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
874 		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
875 };
876 
877 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
878 {
879 	int i;
880 	uint32_t pipe_count = pool->res_cap->num_dwb;
881 
882 	for (i = 0; i < pipe_count; i++) {
883 		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
884 
885 		if (!mcif_wb30) {
886 			dm_error("DC: failed to create mcif_wb30!\n");
887 			return false;
888 		}
889 
890 		dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
891 
892 		pool->mcif_wb[i] = &mcif_wb30->base;
893 	}
894 	return true;
895 }
896 
897 #define aux_engine_regs(id)\
898 [id] = {\
899 		AUX_COMMON_REG_LIST0(id), \
900 		.AUXN_IMPCAL = 0, \
901 		.AUXP_IMPCAL = 0, \
902 		.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
903 }
904 
905 static const struct dce110_aux_registers aux_engine_regs[] = {
906 		aux_engine_regs(0),
907 		aux_engine_regs(1),
908 		aux_engine_regs(2),
909 		aux_engine_regs(3),
910 		aux_engine_regs(4)
911 };
912 
913 static const struct dce110_aux_registers_shift aux_shift = {
914 		DCN_AUX_MASK_SH_LIST(__SHIFT)
915 };
916 
917 static const struct dce110_aux_registers_mask aux_mask = {
918 		DCN_AUX_MASK_SH_LIST(_MASK)
919 };
920 
921 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
922 {
923 	struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
924 
925 	if (!aux_engine)
926 		return NULL;
927 
928 	dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
929 			&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
930 
931 	return &aux_engine->base;
932 }
933 
934 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
935 
936 static const struct dce_i2c_registers i2c_hw_regs[] = {
937 		i2c_inst_regs(1),
938 		i2c_inst_regs(2),
939 		i2c_inst_regs(3),
940 		i2c_inst_regs(4),
941 		i2c_inst_regs(5)
942 };
943 
944 static const struct dce_i2c_shift i2c_shifts = {
945 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
946 };
947 
948 static const struct dce_i2c_mask i2c_masks = {
949 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
950 };
951 
952 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
953 {
954 	struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
955 
956 	if (!dce_i2c_hw)
957 		return NULL;
958 
959 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
960 
961 	return dce_i2c_hw;
962 }
963 
964 static const struct encoder_feature_support link_enc_feature = {
965 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
966 		.max_hdmi_pixel_clock = 600000,
967 		.hdmi_ycbcr420_supported = true,
968 		.dp_ycbcr420_supported = true,
969 		.fec_supported = true,
970 		.flags.bits.IS_HBR2_CAPABLE = true,
971 		.flags.bits.IS_HBR3_CAPABLE = true,
972 		.flags.bits.IS_TPS3_CAPABLE = true,
973 		.flags.bits.IS_TPS4_CAPABLE = true
974 };
975 
976 #define link_regs(id, phyid)\
977 		[id] = {\
978 				LE_DCN3_REG_LIST(id), \
979 				UNIPHY_DCN2_REG_LIST(phyid), \
980 				DPCS_DCN2_REG_LIST(id), \
981 				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
982 		}
983 
984 static const struct dcn10_link_enc_registers link_enc_regs[] = {
985 		link_regs(0, A),
986 		link_regs(1, B),
987 		link_regs(2, C),
988 		link_regs(3, D),
989 		link_regs(4, E)
990 };
991 
992 static const struct dcn10_link_enc_shift le_shift = {
993 		LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
994 		DPCS_DCN2_MASK_SH_LIST(__SHIFT)
995 };
996 
997 static const struct dcn10_link_enc_mask le_mask = {
998 		LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
999 		DPCS_DCN2_MASK_SH_LIST(_MASK)
1000 };
1001 
1002 #define aux_regs(id)\
1003 		[id] = { DCN2_AUX_REG_LIST(id) }
1004 
1005 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1006 		aux_regs(0),
1007 		aux_regs(1),
1008 		aux_regs(2),
1009 		aux_regs(3),
1010 		aux_regs(4)
1011 };
1012 
1013 #define hpd_regs(id)\
1014 		[id] = { HPD_REG_LIST(id) }
1015 
1016 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1017 		hpd_regs(0),
1018 		hpd_regs(1),
1019 		hpd_regs(2),
1020 		hpd_regs(3),
1021 		hpd_regs(4)
1022 };
1023 
1024 static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data)
1025 {
1026 	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1027 
1028 	if (!enc20)
1029 		return NULL;
1030 
1031 	dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
1032 			&link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
1033 			&link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
1034 
1035 	return &enc20->enc10.base;
1036 }
1037 
1038 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1039 		{ DCN_PANEL_CNTL_REG_LIST() }
1040 };
1041 
1042 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1043 		DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1044 };
1045 
1046 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1047 		DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1048 };
1049 
1050 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1051 {
1052 	struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1053 
1054 	if (!panel_cntl)
1055 		return NULL;
1056 
1057 	dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
1058 			&panel_cntl_shift, &panel_cntl_mask);
1059 
1060 	return &panel_cntl->base;
1061 }
1062 
1063 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
1064 {
1065 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1066 			FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1067 }
1068 
1069 static const struct resource_create_funcs res_create_funcs = {
1070 		.read_dce_straps = read_dce_straps,
1071 		.create_audio = dcn302_create_audio,
1072 		.create_stream_encoder = dcn302_stream_encoder_create,
1073 		.create_hwseq = dcn302_hwseq_create,
1074 };
1075 
1076 static const struct resource_create_funcs res_create_maximus_funcs = {
1077 		.read_dce_straps = NULL,
1078 		.create_audio = NULL,
1079 		.create_stream_encoder = NULL,
1080 		.create_hwseq = dcn302_hwseq_create,
1081 };
1082 
1083 static bool is_soc_bounding_box_valid(struct dc *dc)
1084 {
1085 	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1086 
1087 	if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
1088 		return true;
1089 
1090 	return false;
1091 }
1092 
1093 static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
1094 {
1095 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
1096 	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
1097 
1098 	DC_LOGGER_INIT(dc->ctx->logger);
1099 
1100 	if (!is_soc_bounding_box_valid(dc)) {
1101 		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1102 		return false;
1103 	}
1104 
1105 	loaded_ip->max_num_otg = pool->pipe_count;
1106 	loaded_ip->max_num_dpp = pool->pipe_count;
1107 	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1108 	dcn20_patch_bounding_box(dc, loaded_bb);
1109 
1110 	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1111 		struct bp_soc_bb_info bb_info = { 0 };
1112 
1113 		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
1114 			    dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1115 			if (bb_info.dram_clock_change_latency_100ns > 0)
1116 				dcn3_02_soc.dram_clock_change_latency_us =
1117 					bb_info.dram_clock_change_latency_100ns * 10;
1118 
1119 			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1120 				dcn3_02_soc.sr_enter_plus_exit_time_us =
1121 					bb_info.dram_sr_enter_exit_latency_100ns * 10;
1122 
1123 			if (bb_info.dram_sr_exit_latency_100ns > 0)
1124 				dcn3_02_soc.sr_exit_time_us =
1125 					bb_info.dram_sr_exit_latency_100ns * 10;
1126 		}
1127 	}
1128 
1129 	return true;
1130 }
1131 
1132 static void dcn302_resource_destruct(struct resource_pool *pool)
1133 {
1134 	unsigned int i;
1135 
1136 	for (i = 0; i < pool->stream_enc_count; i++) {
1137 		if (pool->stream_enc[i] != NULL) {
1138 			if (pool->stream_enc[i]->vpg != NULL) {
1139 				kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
1140 				pool->stream_enc[i]->vpg = NULL;
1141 			}
1142 			if (pool->stream_enc[i]->afmt != NULL) {
1143 				kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1144 				pool->stream_enc[i]->afmt = NULL;
1145 			}
1146 			kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1147 			pool->stream_enc[i] = NULL;
1148 		}
1149 	}
1150 
1151 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
1152 		if (pool->dscs[i] != NULL)
1153 			dcn20_dsc_destroy(&pool->dscs[i]);
1154 	}
1155 
1156 	if (pool->mpc != NULL) {
1157 		kfree(TO_DCN20_MPC(pool->mpc));
1158 		pool->mpc = NULL;
1159 	}
1160 
1161 	if (pool->hubbub != NULL) {
1162 		kfree(pool->hubbub);
1163 		pool->hubbub = NULL;
1164 	}
1165 
1166 	for (i = 0; i < pool->pipe_count; i++) {
1167 		if (pool->dpps[i] != NULL) {
1168 			kfree(TO_DCN20_DPP(pool->dpps[i]));
1169 			pool->dpps[i] = NULL;
1170 		}
1171 
1172 		if (pool->hubps[i] != NULL) {
1173 			kfree(TO_DCN20_HUBP(pool->hubps[i]));
1174 			pool->hubps[i] = NULL;
1175 		}
1176 
1177 		if (pool->irqs != NULL)
1178 			dal_irq_service_destroy(&pool->irqs);
1179 	}
1180 
1181 	for (i = 0; i < pool->res_cap->num_ddc; i++) {
1182 		if (pool->engines[i] != NULL)
1183 			dce110_engine_destroy(&pool->engines[i]);
1184 		if (pool->hw_i2cs[i] != NULL) {
1185 			kfree(pool->hw_i2cs[i]);
1186 			pool->hw_i2cs[i] = NULL;
1187 		}
1188 		if (pool->sw_i2cs[i] != NULL) {
1189 			kfree(pool->sw_i2cs[i]);
1190 			pool->sw_i2cs[i] = NULL;
1191 		}
1192 	}
1193 
1194 	for (i = 0; i < pool->res_cap->num_opp; i++) {
1195 		if (pool->opps[i] != NULL)
1196 			pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1197 	}
1198 
1199 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1200 		if (pool->timing_generators[i] != NULL)	{
1201 			kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1202 			pool->timing_generators[i] = NULL;
1203 		}
1204 	}
1205 
1206 	for (i = 0; i < pool->res_cap->num_dwb; i++) {
1207 		if (pool->dwbc[i] != NULL) {
1208 			kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1209 			pool->dwbc[i] = NULL;
1210 		}
1211 		if (pool->mcif_wb[i] != NULL) {
1212 			kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1213 			pool->mcif_wb[i] = NULL;
1214 		}
1215 	}
1216 
1217 	for (i = 0; i < pool->audio_count; i++) {
1218 		if (pool->audios[i])
1219 			dce_aud_destroy(&pool->audios[i]);
1220 	}
1221 
1222 	for (i = 0; i < pool->clk_src_count; i++) {
1223 		if (pool->clock_sources[i] != NULL)
1224 			dcn20_clock_source_destroy(&pool->clock_sources[i]);
1225 	}
1226 
1227 	if (pool->dp_clock_source != NULL)
1228 		dcn20_clock_source_destroy(&pool->dp_clock_source);
1229 
1230 	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1231 		if (pool->mpc_lut[i] != NULL) {
1232 			dc_3dlut_func_release(pool->mpc_lut[i]);
1233 			pool->mpc_lut[i] = NULL;
1234 		}
1235 		if (pool->mpc_shaper[i] != NULL) {
1236 			dc_transfer_func_release(pool->mpc_shaper[i]);
1237 			pool->mpc_shaper[i] = NULL;
1238 		}
1239 	}
1240 
1241 	for (i = 0; i < pool->pipe_count; i++) {
1242 		if (pool->multiple_abms[i] != NULL)
1243 			dce_abm_destroy(&pool->multiple_abms[i]);
1244 	}
1245 
1246 	if (pool->psr != NULL)
1247 		dmub_psr_destroy(&pool->psr);
1248 
1249 	if (pool->dccg != NULL)
1250 		dcn_dccg_destroy(&pool->dccg);
1251 }
1252 
1253 static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1254 {
1255 	dcn302_resource_destruct(*pool);
1256 	kfree(*pool);
1257 	*pool = NULL;
1258 }
1259 
1260 static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
1261 		unsigned int *optimal_dcfclk,
1262 		unsigned int *optimal_fclk)
1263 {
1264 	double bw_from_dram, bw_from_dram1, bw_from_dram2;
1265 
1266 	bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans *
1267 		dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_dram_bw_use_normal_percent / 100);
1268 	bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans *
1269 		dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100);
1270 
1271 	bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
1272 
1273 	if (optimal_fclk)
1274 		*optimal_fclk = bw_from_dram /
1275 		(dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100));
1276 
1277 	if (optimal_dcfclk)
1278 		*optimal_dcfclk =  bw_from_dram /
1279 		(dcn3_02_soc.return_bus_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100));
1280 }
1281 
1282 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1283 {
1284 	unsigned int i, j;
1285 	unsigned int num_states = 0;
1286 
1287 	unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
1288 	unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
1289 	unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
1290 	unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
1291 
1292 	unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
1293 	unsigned int num_dcfclk_sta_targets = 4;
1294 	unsigned int num_uclk_states;
1295 
1296 
1297 	if (dc->ctx->dc_bios->vram_info.num_chans)
1298 		dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
1299 
1300 	if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
1301 		dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
1302 
1303 	dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1304 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1305 
1306 	if (bw_params->clk_table.entries[0].memclk_mhz) {
1307 		int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
1308 
1309 		for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
1310 			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
1311 				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
1312 			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
1313 				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
1314 			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
1315 				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
1316 			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
1317 				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
1318 		}
1319 		if (!max_dcfclk_mhz)
1320 			max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz;
1321 		if (!max_dispclk_mhz)
1322 			max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz;
1323 		if (!max_dppclk_mhz)
1324 			max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz;
1325 		if (!max_phyclk_mhz)
1326 			max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz;
1327 
1328 		if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1329 			/* If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array */
1330 			dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
1331 			num_dcfclk_sta_targets++;
1332 		} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1333 			/* If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates */
1334 			for (i = 0; i < num_dcfclk_sta_targets; i++) {
1335 				if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
1336 					dcfclk_sta_targets[i] = max_dcfclk_mhz;
1337 					break;
1338 				}
1339 			}
1340 			/* Update size of array since we "removed" duplicates */
1341 			num_dcfclk_sta_targets = i + 1;
1342 		}
1343 
1344 		num_uclk_states = bw_params->clk_table.num_entries;
1345 
1346 		/* Calculate optimal dcfclk for each uclk */
1347 		for (i = 0; i < num_uclk_states; i++) {
1348 			dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
1349 					&optimal_dcfclk_for_uclk[i], NULL);
1350 			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
1351 				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
1352 			}
1353 		}
1354 
1355 		/* Calculate optimal uclk for each dcfclk sta target */
1356 		for (i = 0; i < num_dcfclk_sta_targets; i++) {
1357 			for (j = 0; j < num_uclk_states; j++) {
1358 				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
1359 					optimal_uclk_for_dcfclk_sta_targets[i] =
1360 							bw_params->clk_table.entries[j].memclk_mhz * 16;
1361 					break;
1362 				}
1363 			}
1364 		}
1365 
1366 		i = 0;
1367 		j = 0;
1368 		/* create the final dcfclk and uclk table */
1369 		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
1370 			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
1371 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1372 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1373 			} else {
1374 				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1375 					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1376 					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
1377 				} else {
1378 					j = num_uclk_states;
1379 				}
1380 			}
1381 		}
1382 
1383 		while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
1384 			dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1385 			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1386 		}
1387 
1388 		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
1389 				optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1390 			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1391 			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
1392 		}
1393 
1394 		dcn3_02_soc.num_states = num_states;
1395 		for (i = 0; i < dcn3_02_soc.num_states; i++) {
1396 			dcn3_02_soc.clock_limits[i].state = i;
1397 			dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
1398 			dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
1399 			dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
1400 
1401 			/* Fill all states with max values of all other clocks */
1402 			dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
1403 			dcn3_02_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
1404 			dcn3_02_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
1405 			/* Populate from bw_params for DTBCLK, SOCCLK */
1406 			if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
1407 				dcn3_02_soc.clock_limits[i].dtbclk_mhz  = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz;
1408 			else
1409 				dcn3_02_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
1410 			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
1411 				dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz;
1412 			else
1413 				dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
1414 			/* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */
1415 			/* FCLK, PHYCLK_D18, DSCCLK */
1416 			dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz;
1417 			dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz;
1418 		}
1419 		/* re-init DML with updated bb */
1420 		dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1421 		if (dc->current_state)
1422 			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1423 	}
1424 }
1425 
1426 static struct resource_funcs dcn302_res_pool_funcs = {
1427 		.destroy = dcn302_destroy_resource_pool,
1428 		.link_enc_create = dcn302_link_encoder_create,
1429 		.panel_cntl_create = dcn302_panel_cntl_create,
1430 		.validate_bandwidth = dcn30_validate_bandwidth,
1431 		.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1432 		.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1433 		.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1434 		.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1435 		.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1436 		.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1437 		.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1438 		.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1439 		.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1440 		.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1441 		.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1442 		.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1443 		.update_bw_bounding_box = dcn302_update_bw_bounding_box,
1444 		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1445 };
1446 
1447 static struct dc_cap_funcs cap_funcs = {
1448 		.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1449 };
1450 
1451 static const struct bios_registers bios_regs = {
1452 		NBIO_SR(BIOS_SCRATCH_3),
1453 		NBIO_SR(BIOS_SCRATCH_6)
1454 };
1455 
1456 static const struct dccg_registers dccg_regs = {
1457 		DCCG_REG_LIST_DCN3_02()
1458 };
1459 
1460 static const struct dccg_shift dccg_shift = {
1461 		DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1462 };
1463 
1464 static const struct dccg_mask dccg_mask = {
1465 		DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1466 };
1467 
1468 #define abm_regs(id)\
1469 		[id] = { ABM_DCN302_REG_LIST(id) }
1470 
1471 static const struct dce_abm_registers abm_regs[] = {
1472 		abm_regs(0),
1473 		abm_regs(1),
1474 		abm_regs(2),
1475 		abm_regs(3),
1476 		abm_regs(4)
1477 };
1478 
1479 static const struct dce_abm_shift abm_shift = {
1480 		ABM_MASK_SH_LIST_DCN30(__SHIFT)
1481 };
1482 
1483 static const struct dce_abm_mask abm_mask = {
1484 		ABM_MASK_SH_LIST_DCN30(_MASK)
1485 };
1486 
1487 static bool dcn302_resource_construct(
1488 		uint8_t num_virtual_links,
1489 		struct dc *dc,
1490 		struct resource_pool *pool)
1491 {
1492 	int i;
1493 	struct dc_context *ctx = dc->ctx;
1494 	struct irq_service_init_data init_data;
1495 
1496 	ctx->dc_bios->regs = &bios_regs;
1497 
1498 	pool->res_cap = &res_cap_dcn302;
1499 
1500 	pool->funcs = &dcn302_res_pool_funcs;
1501 
1502 	/*************************************************
1503 	 *  Resource + asic cap harcoding                *
1504 	 *************************************************/
1505 	pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1506 	pool->pipe_count = pool->res_cap->num_timing_generator;
1507 	pool->mpcc_count = pool->res_cap->num_timing_generator;
1508 	dc->caps.max_downscale_ratio = 600;
1509 	dc->caps.i2c_speed_in_khz = 100;
1510 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1511 	dc->caps.max_cursor_size = 256;
1512 	dc->caps.min_horizontal_blanking_period = 80;
1513 	dc->caps.dmdata_alloc_size = 2048;
1514 	dc->caps.mall_size_per_mem_channel = 4;
1515 	/* total size = mall per channel * num channels * 1024 * 1024 */
1516 	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1517 	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1518 	dc->caps.max_slave_planes = 1;
1519 	dc->caps.max_slave_yuv_planes = 1;
1520 	dc->caps.max_slave_rgb_planes = 1;
1521 	dc->caps.post_blend_color_processing = true;
1522 	dc->caps.force_dp_tps4_for_cp2520 = true;
1523 	dc->caps.extended_aux_timeout_support = true;
1524 	dc->caps.dmcub_support = true;
1525 
1526 	/* Color pipeline capabilities */
1527 	dc->caps.color.dpp.dcn_arch = 1;
1528 	dc->caps.color.dpp.input_lut_shared = 0;
1529 	dc->caps.color.dpp.icsc = 1;
1530 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1531 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1532 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1533 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1534 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1535 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1536 	dc->caps.color.dpp.post_csc = 1;
1537 	dc->caps.color.dpp.gamma_corr = 1;
1538 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1539 
1540 	dc->caps.color.dpp.hw_3d_lut = 1;
1541 	dc->caps.color.dpp.ogam_ram = 1;
1542 	// no OGAM ROM on DCN3
1543 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1544 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1545 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1546 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1547 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1548 	dc->caps.color.dpp.ocsc = 0;
1549 
1550 	dc->caps.color.mpc.gamut_remap = 1;
1551 	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1552 	dc->caps.color.mpc.ogam_ram = 1;
1553 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1554 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1555 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1556 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1557 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1558 	dc->caps.color.mpc.ocsc = 1;
1559 
1560 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1561 		dc->debug = debug_defaults_drv;
1562 	else
1563 		dc->debug = debug_defaults_diags;
1564 
1565 	// Init the vm_helper
1566 	if (dc->vm_helper)
1567 		vm_helper_init(dc->vm_helper, 16);
1568 
1569 	/*************************************************
1570 	 *  Create resources                             *
1571 	 *************************************************/
1572 
1573 	/* Clock Sources for Pixel Clock*/
1574 	pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1575 			dcn302_clock_source_create(ctx, ctx->dc_bios,
1576 					CLOCK_SOURCE_COMBO_PHY_PLL0,
1577 					&clk_src_regs[0], false);
1578 	pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1579 			dcn302_clock_source_create(ctx, ctx->dc_bios,
1580 					CLOCK_SOURCE_COMBO_PHY_PLL1,
1581 					&clk_src_regs[1], false);
1582 	pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1583 			dcn302_clock_source_create(ctx, ctx->dc_bios,
1584 					CLOCK_SOURCE_COMBO_PHY_PLL2,
1585 					&clk_src_regs[2], false);
1586 	pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1587 			dcn302_clock_source_create(ctx, ctx->dc_bios,
1588 					CLOCK_SOURCE_COMBO_PHY_PLL3,
1589 					&clk_src_regs[3], false);
1590 	pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1591 			dcn302_clock_source_create(ctx, ctx->dc_bios,
1592 					CLOCK_SOURCE_COMBO_PHY_PLL4,
1593 					&clk_src_regs[4], false);
1594 
1595 	pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1596 
1597 	/* todo: not reuse phy_pll registers */
1598 	pool->dp_clock_source =
1599 			dcn302_clock_source_create(ctx, ctx->dc_bios,
1600 					CLOCK_SOURCE_ID_DP_DTO,
1601 					&clk_src_regs[0], true);
1602 
1603 	for (i = 0; i < pool->clk_src_count; i++) {
1604 		if (pool->clock_sources[i] == NULL) {
1605 			dm_error("DC: failed to create clock sources!\n");
1606 			BREAK_TO_DEBUGGER();
1607 			goto create_fail;
1608 		}
1609 	}
1610 
1611 	/* DCCG */
1612 	pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1613 	if (pool->dccg == NULL) {
1614 		dm_error("DC: failed to create dccg!\n");
1615 		BREAK_TO_DEBUGGER();
1616 		goto create_fail;
1617 	}
1618 
1619 	/* PP Lib and SMU interfaces */
1620 	init_soc_bounding_box(dc, pool);
1621 
1622 	/* DML */
1623 	dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1624 
1625 	/* IRQ */
1626 	init_data.ctx = dc->ctx;
1627 	pool->irqs = dal_irq_service_dcn302_create(&init_data);
1628 	if (!pool->irqs)
1629 		goto create_fail;
1630 
1631 	/* HUBBUB */
1632 	pool->hubbub = dcn302_hubbub_create(ctx);
1633 	if (pool->hubbub == NULL) {
1634 		BREAK_TO_DEBUGGER();
1635 		dm_error("DC: failed to create hubbub!\n");
1636 		goto create_fail;
1637 	}
1638 
1639 	/* HUBPs, DPPs, OPPs and TGs */
1640 	for (i = 0; i < pool->pipe_count; i++) {
1641 		pool->hubps[i] = dcn302_hubp_create(ctx, i);
1642 		if (pool->hubps[i] == NULL) {
1643 			BREAK_TO_DEBUGGER();
1644 			dm_error("DC: failed to create hubps!\n");
1645 			goto create_fail;
1646 		}
1647 
1648 		pool->dpps[i] = dcn302_dpp_create(ctx, i);
1649 		if (pool->dpps[i] == NULL) {
1650 			BREAK_TO_DEBUGGER();
1651 			dm_error("DC: failed to create dpps!\n");
1652 			goto create_fail;
1653 		}
1654 	}
1655 
1656 	for (i = 0; i < pool->res_cap->num_opp; i++) {
1657 		pool->opps[i] = dcn302_opp_create(ctx, i);
1658 		if (pool->opps[i] == NULL) {
1659 			BREAK_TO_DEBUGGER();
1660 			dm_error("DC: failed to create output pixel processor!\n");
1661 			goto create_fail;
1662 		}
1663 	}
1664 
1665 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1666 		pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1667 		if (pool->timing_generators[i] == NULL) {
1668 			BREAK_TO_DEBUGGER();
1669 			dm_error("DC: failed to create tg!\n");
1670 			goto create_fail;
1671 		}
1672 	}
1673 	pool->timing_generator_count = i;
1674 
1675 	/* PSR */
1676 	pool->psr = dmub_psr_create(ctx);
1677 	if (pool->psr == NULL) {
1678 		dm_error("DC: failed to create psr!\n");
1679 		BREAK_TO_DEBUGGER();
1680 		goto create_fail;
1681 	}
1682 
1683 	/* ABMs */
1684 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1685 		pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1686 		if (pool->multiple_abms[i] == NULL) {
1687 			dm_error("DC: failed to create abm for pipe %d!\n", i);
1688 			BREAK_TO_DEBUGGER();
1689 			goto create_fail;
1690 		}
1691 	}
1692 
1693 	/* MPC and DSC */
1694 	pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1695 	if (pool->mpc == NULL) {
1696 		BREAK_TO_DEBUGGER();
1697 		dm_error("DC: failed to create mpc!\n");
1698 		goto create_fail;
1699 	}
1700 
1701 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
1702 		pool->dscs[i] = dcn302_dsc_create(ctx, i);
1703 		if (pool->dscs[i] == NULL) {
1704 			BREAK_TO_DEBUGGER();
1705 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1706 			goto create_fail;
1707 		}
1708 	}
1709 
1710 	/* DWB and MMHUBBUB */
1711 	if (!dcn302_dwbc_create(ctx, pool)) {
1712 		BREAK_TO_DEBUGGER();
1713 		dm_error("DC: failed to create dwbc!\n");
1714 		goto create_fail;
1715 	}
1716 
1717 	if (!dcn302_mmhubbub_create(ctx, pool)) {
1718 		BREAK_TO_DEBUGGER();
1719 		dm_error("DC: failed to create mcif_wb!\n");
1720 		goto create_fail;
1721 	}
1722 
1723 	/* AUX and I2C */
1724 	for (i = 0; i < pool->res_cap->num_ddc; i++) {
1725 		pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1726 		if (pool->engines[i] == NULL) {
1727 			BREAK_TO_DEBUGGER();
1728 			dm_error("DC:failed to create aux engine!!\n");
1729 			goto create_fail;
1730 		}
1731 		pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1732 		if (pool->hw_i2cs[i] == NULL) {
1733 			BREAK_TO_DEBUGGER();
1734 			dm_error("DC:failed to create hw i2c!!\n");
1735 			goto create_fail;
1736 		}
1737 		pool->sw_i2cs[i] = NULL;
1738 	}
1739 
1740 	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1741 	if (!resource_construct(num_virtual_links, dc, pool,
1742 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1743 					&res_create_funcs : &res_create_maximus_funcs)))
1744 		goto create_fail;
1745 
1746 	/* HW Sequencer and Plane caps */
1747 	dcn302_hw_sequencer_construct(dc);
1748 
1749 	dc->caps.max_planes =  pool->pipe_count;
1750 
1751 	for (i = 0; i < dc->caps.max_planes; ++i)
1752 		dc->caps.planes[i] = plane_cap;
1753 
1754 	dc->cap_funcs = cap_funcs;
1755 
1756 	return true;
1757 
1758 create_fail:
1759 
1760 	dcn302_resource_destruct(pool);
1761 
1762 	return false;
1763 }
1764 
1765 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1766 {
1767 	struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1768 
1769 	if (!pool)
1770 		return NULL;
1771 
1772 	if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
1773 		return pool;
1774 
1775 	BREAK_TO_DEBUGGER();
1776 	kfree(pool);
1777 	return NULL;
1778 }
1779