1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dml/dcn30/dcn30_fpu.h" 47 48 #include "dcn10/dcn10_resource.h" 49 50 #include "dce/dce_abm.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_clock_source.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_i2c_hw.h" 56 #include "dce/dce_panel_cntl.h" 57 #include "dce/dmub_abm.h" 58 #include "dce/dmub_psr.h" 59 #include "clk_mgr.h" 60 61 #include "hw_sequencer_private.h" 62 #include "reg_helper.h" 63 #include "resource.h" 64 #include "vm_helper.h" 65 66 #include "dml/dcn302/dcn302_fpu.h" 67 68 #include "dimgrey_cavefish_ip_offset.h" 69 #include "dcn/dcn_3_0_2_offset.h" 70 #include "dcn/dcn_3_0_2_sh_mask.h" 71 #include "dpcs/dpcs_3_0_0_offset.h" 72 #include "dpcs/dpcs_3_0_0_sh_mask.h" 73 #include "nbio/nbio_7_4_offset.h" 74 #include "amdgpu_socbb.h" 75 76 #define DC_LOGGER_INIT(logger) 77 78 static const struct dc_debug_options debug_defaults_drv = { 79 .disable_dmcu = true, 80 .force_abm_enable = false, 81 .timing_trace = false, 82 .clock_trace = true, 83 .disable_pplib_clock_request = true, 84 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 85 .force_single_disp_pipe_split = false, 86 .disable_dcc = DCC_ENABLE, 87 .vsr_support = true, 88 .performance_trace = false, 89 .max_downscale_src_width = 7680,/*upto 8K*/ 90 .disable_pplib_wm_range = false, 91 .scl_reset_length10 = true, 92 .sanity_checks = false, 93 .underflow_assert_delay_us = 0xFFFFFFFF, 94 .dwb_fi_phase = -1, // -1 = disable, 95 .dmub_command_table = true, 96 .use_max_lb = true, 97 .exit_idle_opt_for_cursor_updates = true 98 }; 99 100 static const struct dc_debug_options debug_defaults_diags = { 101 .disable_dmcu = true, 102 .force_abm_enable = false, 103 .timing_trace = true, 104 .clock_trace = true, 105 .disable_dpp_power_gate = true, 106 .disable_hubp_power_gate = true, 107 .disable_clock_gate = true, 108 .disable_pplib_clock_request = true, 109 .disable_pplib_wm_range = true, 110 .disable_stutter = false, 111 .scl_reset_length10 = true, 112 .dwb_fi_phase = -1, // -1 = disable 113 .dmub_command_table = true, 114 .enable_tri_buf = true, 115 .use_max_lb = true 116 }; 117 118 static const struct dc_panel_config panel_config_defaults = { 119 .psr = { 120 .disable_psr = false, 121 .disallow_psrsu = false, 122 }, 123 }; 124 125 enum dcn302_clk_src_array_id { 126 DCN302_CLK_SRC_PLL0, 127 DCN302_CLK_SRC_PLL1, 128 DCN302_CLK_SRC_PLL2, 129 DCN302_CLK_SRC_PLL3, 130 DCN302_CLK_SRC_PLL4, 131 DCN302_CLK_SRC_TOTAL 132 }; 133 134 static const struct resource_caps res_cap_dcn302 = { 135 .num_timing_generator = 5, 136 .num_opp = 5, 137 .num_video_plane = 5, 138 .num_audio = 5, 139 .num_stream_encoder = 5, 140 .num_dwb = 1, 141 .num_ddc = 5, 142 .num_vmid = 16, 143 .num_mpc_3dlut = 2, 144 .num_dsc = 5, 145 }; 146 147 static const struct dc_plane_cap plane_cap = { 148 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 149 .blends_with_above = true, 150 .blends_with_below = true, 151 .per_pixel_alpha = true, 152 .pixel_format_support = { 153 .argb8888 = true, 154 .nv12 = true, 155 .fp16 = true, 156 .p010 = true, 157 .ayuv = false, 158 }, 159 .max_upscale_factor = { 160 .argb8888 = 16000, 161 .nv12 = 16000, 162 .fp16 = 16000 163 }, 164 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 165 .max_downscale_factor = { 166 .argb8888 = 167, 167 .nv12 = 167, 168 .fp16 = 167 169 }, 170 16, 171 16 172 }; 173 174 /* NBIO */ 175 #define NBIO_BASE_INNER(seg) \ 176 NBIO_BASE__INST0_SEG ## seg 177 178 #define NBIO_BASE(seg) \ 179 NBIO_BASE_INNER(seg) 180 181 #define NBIO_SR(reg_name)\ 182 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 183 mm ## reg_name 184 185 /* DCN */ 186 #undef BASE_INNER 187 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 188 189 #define BASE(seg) BASE_INNER(seg) 190 191 #define SR(reg_name)\ 192 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 193 194 #define SF(reg_name, field_name, post_fix)\ 195 .field_name = reg_name ## __ ## field_name ## post_fix 196 197 #define SRI(reg_name, block, id)\ 198 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 199 200 #define SRI2(reg_name, block, id)\ 201 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 202 203 #define SRII(reg_name, block, id)\ 204 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 205 mm ## block ## id ## _ ## reg_name 206 207 #define DCCG_SRII(reg_name, block, id)\ 208 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 209 mm ## block ## id ## _ ## reg_name 210 211 #define VUPDATE_SRII(reg_name, block, id)\ 212 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 213 mm ## reg_name ## _ ## block ## id 214 215 #define SRII_DWB(reg_name, temp_name, block, id)\ 216 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 217 mm ## block ## id ## _ ## temp_name 218 219 #define SRII_MPC_RMU(reg_name, block, id)\ 220 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 221 mm ## block ## id ## _ ## reg_name 222 223 static const struct dcn_hubbub_registers hubbub_reg = { 224 HUBBUB_REG_LIST_DCN30(0) 225 }; 226 227 static const struct dcn_hubbub_shift hubbub_shift = { 228 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 229 }; 230 231 static const struct dcn_hubbub_mask hubbub_mask = { 232 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 233 }; 234 235 #define vmid_regs(id)\ 236 [id] = { DCN20_VMID_REG_LIST(id) } 237 238 static const struct dcn_vmid_registers vmid_regs[] = { 239 vmid_regs(0), 240 vmid_regs(1), 241 vmid_regs(2), 242 vmid_regs(3), 243 vmid_regs(4), 244 vmid_regs(5), 245 vmid_regs(6), 246 vmid_regs(7), 247 vmid_regs(8), 248 vmid_regs(9), 249 vmid_regs(10), 250 vmid_regs(11), 251 vmid_regs(12), 252 vmid_regs(13), 253 vmid_regs(14), 254 vmid_regs(15) 255 }; 256 257 static const struct dcn20_vmid_shift vmid_shifts = { 258 DCN20_VMID_MASK_SH_LIST(__SHIFT) 259 }; 260 261 static const struct dcn20_vmid_mask vmid_masks = { 262 DCN20_VMID_MASK_SH_LIST(_MASK) 263 }; 264 265 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 266 { 267 int i; 268 269 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 270 271 if (!hubbub3) 272 return NULL; 273 274 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 275 276 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 277 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 278 279 vmid->ctx = ctx; 280 281 vmid->regs = &vmid_regs[i]; 282 vmid->shifts = &vmid_shifts; 283 vmid->masks = &vmid_masks; 284 } 285 286 return &hubbub3->base; 287 } 288 289 #define vpg_regs(id)\ 290 [id] = { VPG_DCN3_REG_LIST(id) } 291 292 static const struct dcn30_vpg_registers vpg_regs[] = { 293 vpg_regs(0), 294 vpg_regs(1), 295 vpg_regs(2), 296 vpg_regs(3), 297 vpg_regs(4), 298 vpg_regs(5) 299 }; 300 301 static const struct dcn30_vpg_shift vpg_shift = { 302 DCN3_VPG_MASK_SH_LIST(__SHIFT) 303 }; 304 305 static const struct dcn30_vpg_mask vpg_mask = { 306 DCN3_VPG_MASK_SH_LIST(_MASK) 307 }; 308 309 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 310 { 311 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 312 313 if (!vpg3) 314 return NULL; 315 316 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 317 318 return &vpg3->base; 319 } 320 321 #define afmt_regs(id)\ 322 [id] = { AFMT_DCN3_REG_LIST(id) } 323 324 static const struct dcn30_afmt_registers afmt_regs[] = { 325 afmt_regs(0), 326 afmt_regs(1), 327 afmt_regs(2), 328 afmt_regs(3), 329 afmt_regs(4), 330 afmt_regs(5) 331 }; 332 333 static const struct dcn30_afmt_shift afmt_shift = { 334 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 335 }; 336 337 static const struct dcn30_afmt_mask afmt_mask = { 338 DCN3_AFMT_MASK_SH_LIST(_MASK) 339 }; 340 341 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 342 { 343 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 344 345 if (!afmt3) 346 return NULL; 347 348 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 349 350 return &afmt3->base; 351 } 352 353 #define audio_regs(id)\ 354 [id] = { AUD_COMMON_REG_LIST(id) } 355 356 static const struct dce_audio_registers audio_regs[] = { 357 audio_regs(0), 358 audio_regs(1), 359 audio_regs(2), 360 audio_regs(3), 361 audio_regs(4), 362 audio_regs(5), 363 audio_regs(6) 364 }; 365 366 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 367 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 368 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 369 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 370 371 static const struct dce_audio_shift audio_shift = { 372 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 373 }; 374 375 static const struct dce_audio_mask audio_mask = { 376 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 377 }; 378 379 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 380 { 381 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 382 } 383 384 #define stream_enc_regs(id)\ 385 [id] = { SE_DCN3_REG_LIST(id) } 386 387 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 388 stream_enc_regs(0), 389 stream_enc_regs(1), 390 stream_enc_regs(2), 391 stream_enc_regs(3), 392 stream_enc_regs(4) 393 }; 394 395 static const struct dcn10_stream_encoder_shift se_shift = { 396 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 397 }; 398 399 static const struct dcn10_stream_encoder_mask se_mask = { 400 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 401 }; 402 403 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 404 { 405 struct dcn10_stream_encoder *enc1; 406 struct vpg *vpg; 407 struct afmt *afmt; 408 int vpg_inst; 409 int afmt_inst; 410 411 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 412 if (eng_id <= ENGINE_ID_DIGE) { 413 vpg_inst = eng_id; 414 afmt_inst = eng_id; 415 } else 416 return NULL; 417 418 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 419 vpg = dcn302_vpg_create(ctx, vpg_inst); 420 afmt = dcn302_afmt_create(ctx, afmt_inst); 421 422 if (!enc1 || !vpg || !afmt) { 423 kfree(enc1); 424 kfree(vpg); 425 kfree(afmt); 426 return NULL; 427 } 428 429 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 430 &se_shift, &se_mask); 431 432 return &enc1->base; 433 } 434 435 #define clk_src_regs(index, pllid)\ 436 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 437 438 static const struct dce110_clk_src_regs clk_src_regs[] = { 439 clk_src_regs(0, A), 440 clk_src_regs(1, B), 441 clk_src_regs(2, C), 442 clk_src_regs(3, D), 443 clk_src_regs(4, E) 444 }; 445 446 static const struct dce110_clk_src_shift cs_shift = { 447 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 448 }; 449 450 static const struct dce110_clk_src_mask cs_mask = { 451 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 452 }; 453 454 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 455 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 456 { 457 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 458 459 if (!clk_src) 460 return NULL; 461 462 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 463 clk_src->base.dp_clk_src = dp_clk_src; 464 return &clk_src->base; 465 } 466 467 BREAK_TO_DEBUGGER(); 468 return NULL; 469 } 470 471 static const struct dce_hwseq_registers hwseq_reg = { 472 HWSEQ_DCN302_REG_LIST() 473 }; 474 475 static const struct dce_hwseq_shift hwseq_shift = { 476 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 477 }; 478 479 static const struct dce_hwseq_mask hwseq_mask = { 480 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 481 }; 482 483 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 484 { 485 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 486 487 if (hws) { 488 hws->ctx = ctx; 489 hws->regs = &hwseq_reg; 490 hws->shifts = &hwseq_shift; 491 hws->masks = &hwseq_mask; 492 } 493 return hws; 494 } 495 496 #define hubp_regs(id)\ 497 [id] = { HUBP_REG_LIST_DCN30(id) } 498 499 static const struct dcn_hubp2_registers hubp_regs[] = { 500 hubp_regs(0), 501 hubp_regs(1), 502 hubp_regs(2), 503 hubp_regs(3), 504 hubp_regs(4) 505 }; 506 507 static const struct dcn_hubp2_shift hubp_shift = { 508 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 509 }; 510 511 static const struct dcn_hubp2_mask hubp_mask = { 512 HUBP_MASK_SH_LIST_DCN30(_MASK) 513 }; 514 515 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 516 { 517 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 518 519 if (!hubp2) 520 return NULL; 521 522 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 523 return &hubp2->base; 524 525 BREAK_TO_DEBUGGER(); 526 kfree(hubp2); 527 return NULL; 528 } 529 530 #define dpp_regs(id)\ 531 [id] = { DPP_REG_LIST_DCN30(id) } 532 533 static const struct dcn3_dpp_registers dpp_regs[] = { 534 dpp_regs(0), 535 dpp_regs(1), 536 dpp_regs(2), 537 dpp_regs(3), 538 dpp_regs(4) 539 }; 540 541 static const struct dcn3_dpp_shift tf_shift = { 542 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 543 }; 544 545 static const struct dcn3_dpp_mask tf_mask = { 546 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 547 }; 548 549 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 550 { 551 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 552 553 if (!dpp) 554 return NULL; 555 556 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 557 return &dpp->base; 558 559 BREAK_TO_DEBUGGER(); 560 kfree(dpp); 561 return NULL; 562 } 563 564 #define opp_regs(id)\ 565 [id] = { OPP_REG_LIST_DCN30(id) } 566 567 static const struct dcn20_opp_registers opp_regs[] = { 568 opp_regs(0), 569 opp_regs(1), 570 opp_regs(2), 571 opp_regs(3), 572 opp_regs(4) 573 }; 574 575 static const struct dcn20_opp_shift opp_shift = { 576 OPP_MASK_SH_LIST_DCN20(__SHIFT) 577 }; 578 579 static const struct dcn20_opp_mask opp_mask = { 580 OPP_MASK_SH_LIST_DCN20(_MASK) 581 }; 582 583 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 584 { 585 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 586 587 if (!opp) { 588 BREAK_TO_DEBUGGER(); 589 return NULL; 590 } 591 592 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 593 return &opp->base; 594 } 595 596 #define optc_regs(id)\ 597 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 598 599 static const struct dcn_optc_registers optc_regs[] = { 600 optc_regs(0), 601 optc_regs(1), 602 optc_regs(2), 603 optc_regs(3), 604 optc_regs(4) 605 }; 606 607 static const struct dcn_optc_shift optc_shift = { 608 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 609 }; 610 611 static const struct dcn_optc_mask optc_mask = { 612 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 613 }; 614 615 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 616 { 617 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 618 619 if (!tgn10) 620 return NULL; 621 622 tgn10->base.inst = instance; 623 tgn10->base.ctx = ctx; 624 625 tgn10->tg_regs = &optc_regs[instance]; 626 tgn10->tg_shift = &optc_shift; 627 tgn10->tg_mask = &optc_mask; 628 629 dcn30_timing_generator_init(tgn10); 630 631 return &tgn10->base; 632 } 633 634 static const struct dcn30_mpc_registers mpc_regs = { 635 MPC_REG_LIST_DCN3_0(0), 636 MPC_REG_LIST_DCN3_0(1), 637 MPC_REG_LIST_DCN3_0(2), 638 MPC_REG_LIST_DCN3_0(3), 639 MPC_REG_LIST_DCN3_0(4), 640 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 641 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 642 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 643 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 644 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 645 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 646 MPC_RMU_REG_LIST_DCN3AG(0), 647 MPC_RMU_REG_LIST_DCN3AG(1), 648 MPC_RMU_REG_LIST_DCN3AG(2), 649 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 650 }; 651 652 static const struct dcn30_mpc_shift mpc_shift = { 653 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 654 }; 655 656 static const struct dcn30_mpc_mask mpc_mask = { 657 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 658 }; 659 660 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 661 { 662 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 663 664 if (!mpc30) 665 return NULL; 666 667 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 668 669 return &mpc30->base; 670 } 671 672 #define dsc_regsDCN20(id)\ 673 [id] = { DSC_REG_LIST_DCN20(id) } 674 675 static const struct dcn20_dsc_registers dsc_regs[] = { 676 dsc_regsDCN20(0), 677 dsc_regsDCN20(1), 678 dsc_regsDCN20(2), 679 dsc_regsDCN20(3), 680 dsc_regsDCN20(4) 681 }; 682 683 static const struct dcn20_dsc_shift dsc_shift = { 684 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 685 }; 686 687 static const struct dcn20_dsc_mask dsc_mask = { 688 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 689 }; 690 691 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 692 { 693 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 694 695 if (!dsc) { 696 BREAK_TO_DEBUGGER(); 697 return NULL; 698 } 699 700 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 701 return &dsc->base; 702 } 703 704 #define dwbc_regs_dcn3(id)\ 705 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 706 707 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 708 dwbc_regs_dcn3(0) 709 }; 710 711 static const struct dcn30_dwbc_shift dwbc30_shift = { 712 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 713 }; 714 715 static const struct dcn30_dwbc_mask dwbc30_mask = { 716 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 717 }; 718 719 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 720 { 721 int i; 722 uint32_t pipe_count = pool->res_cap->num_dwb; 723 724 for (i = 0; i < pipe_count; i++) { 725 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 726 727 if (!dwbc30) { 728 dm_error("DC: failed to create dwbc30!\n"); 729 return false; 730 } 731 732 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 733 734 pool->dwbc[i] = &dwbc30->base; 735 } 736 return true; 737 } 738 739 #define mcif_wb_regs_dcn3(id)\ 740 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 741 742 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 743 mcif_wb_regs_dcn3(0) 744 }; 745 746 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 747 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 748 }; 749 750 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 751 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 752 }; 753 754 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 755 { 756 int i; 757 uint32_t pipe_count = pool->res_cap->num_dwb; 758 759 for (i = 0; i < pipe_count; i++) { 760 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 761 762 if (!mcif_wb30) { 763 dm_error("DC: failed to create mcif_wb30!\n"); 764 return false; 765 } 766 767 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 768 769 pool->mcif_wb[i] = &mcif_wb30->base; 770 } 771 return true; 772 } 773 774 #define aux_engine_regs(id)\ 775 [id] = {\ 776 AUX_COMMON_REG_LIST0(id), \ 777 .AUXN_IMPCAL = 0, \ 778 .AUXP_IMPCAL = 0, \ 779 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 780 } 781 782 static const struct dce110_aux_registers aux_engine_regs[] = { 783 aux_engine_regs(0), 784 aux_engine_regs(1), 785 aux_engine_regs(2), 786 aux_engine_regs(3), 787 aux_engine_regs(4) 788 }; 789 790 static const struct dce110_aux_registers_shift aux_shift = { 791 DCN_AUX_MASK_SH_LIST(__SHIFT) 792 }; 793 794 static const struct dce110_aux_registers_mask aux_mask = { 795 DCN_AUX_MASK_SH_LIST(_MASK) 796 }; 797 798 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 799 { 800 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 801 802 if (!aux_engine) 803 return NULL; 804 805 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 806 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 807 808 return &aux_engine->base; 809 } 810 811 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 812 813 static const struct dce_i2c_registers i2c_hw_regs[] = { 814 i2c_inst_regs(1), 815 i2c_inst_regs(2), 816 i2c_inst_regs(3), 817 i2c_inst_regs(4), 818 i2c_inst_regs(5) 819 }; 820 821 static const struct dce_i2c_shift i2c_shifts = { 822 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 823 }; 824 825 static const struct dce_i2c_mask i2c_masks = { 826 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 827 }; 828 829 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 830 { 831 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 832 833 if (!dce_i2c_hw) 834 return NULL; 835 836 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 837 838 return dce_i2c_hw; 839 } 840 841 static const struct encoder_feature_support link_enc_feature = { 842 .max_hdmi_deep_color = COLOR_DEPTH_121212, 843 .max_hdmi_pixel_clock = 600000, 844 .hdmi_ycbcr420_supported = true, 845 .dp_ycbcr420_supported = true, 846 .fec_supported = true, 847 .flags.bits.IS_HBR2_CAPABLE = true, 848 .flags.bits.IS_HBR3_CAPABLE = true, 849 .flags.bits.IS_TPS3_CAPABLE = true, 850 .flags.bits.IS_TPS4_CAPABLE = true 851 }; 852 853 #define link_regs(id, phyid)\ 854 [id] = {\ 855 LE_DCN3_REG_LIST(id), \ 856 UNIPHY_DCN2_REG_LIST(phyid), \ 857 DPCS_DCN2_REG_LIST(id), \ 858 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 859 } 860 861 static const struct dcn10_link_enc_registers link_enc_regs[] = { 862 link_regs(0, A), 863 link_regs(1, B), 864 link_regs(2, C), 865 link_regs(3, D), 866 link_regs(4, E) 867 }; 868 869 static const struct dcn10_link_enc_shift le_shift = { 870 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 871 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 872 }; 873 874 static const struct dcn10_link_enc_mask le_mask = { 875 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 876 DPCS_DCN2_MASK_SH_LIST(_MASK) 877 }; 878 879 #define aux_regs(id)\ 880 [id] = { DCN2_AUX_REG_LIST(id) } 881 882 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 883 aux_regs(0), 884 aux_regs(1), 885 aux_regs(2), 886 aux_regs(3), 887 aux_regs(4) 888 }; 889 890 #define hpd_regs(id)\ 891 [id] = { HPD_REG_LIST(id) } 892 893 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 894 hpd_regs(0), 895 hpd_regs(1), 896 hpd_regs(2), 897 hpd_regs(3), 898 hpd_regs(4) 899 }; 900 901 static struct link_encoder *dcn302_link_encoder_create( 902 struct dc_context *ctx, 903 const struct encoder_init_data *enc_init_data) 904 { 905 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 906 907 if (!enc20) 908 return NULL; 909 910 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 911 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 912 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 913 914 return &enc20->enc10.base; 915 } 916 917 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 918 { DCN_PANEL_CNTL_REG_LIST() } 919 }; 920 921 static const struct dce_panel_cntl_shift panel_cntl_shift = { 922 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 923 }; 924 925 static const struct dce_panel_cntl_mask panel_cntl_mask = { 926 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 927 }; 928 929 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 930 { 931 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 932 933 if (!panel_cntl) 934 return NULL; 935 936 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 937 &panel_cntl_shift, &panel_cntl_mask); 938 939 return &panel_cntl->base; 940 } 941 942 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 943 { 944 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 945 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 946 } 947 948 static const struct resource_create_funcs res_create_funcs = { 949 .read_dce_straps = read_dce_straps, 950 .create_audio = dcn302_create_audio, 951 .create_stream_encoder = dcn302_stream_encoder_create, 952 .create_hwseq = dcn302_hwseq_create, 953 }; 954 955 static const struct resource_create_funcs res_create_maximus_funcs = { 956 .read_dce_straps = NULL, 957 .create_audio = NULL, 958 .create_stream_encoder = NULL, 959 .create_hwseq = dcn302_hwseq_create, 960 }; 961 962 static bool is_soc_bounding_box_valid(struct dc *dc) 963 { 964 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 965 966 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 967 return true; 968 969 return false; 970 } 971 972 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 973 { 974 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 975 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 976 977 DC_LOGGER_INIT(dc->ctx->logger); 978 979 if (!is_soc_bounding_box_valid(dc)) { 980 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 981 return false; 982 } 983 984 loaded_ip->max_num_otg = pool->pipe_count; 985 loaded_ip->max_num_dpp = pool->pipe_count; 986 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 987 DC_FP_START(); 988 dcn20_patch_bounding_box(dc, loaded_bb); 989 DC_FP_END(); 990 991 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 992 struct bp_soc_bb_info bb_info = { 0 }; 993 994 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 995 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 996 997 DC_FP_START(); 998 dcn302_fpu_init_soc_bounding_box(bb_info); 999 DC_FP_END(); 1000 } 1001 } 1002 1003 return true; 1004 } 1005 1006 static void dcn302_resource_destruct(struct resource_pool *pool) 1007 { 1008 unsigned int i; 1009 1010 for (i = 0; i < pool->stream_enc_count; i++) { 1011 if (pool->stream_enc[i] != NULL) { 1012 if (pool->stream_enc[i]->vpg != NULL) { 1013 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1014 pool->stream_enc[i]->vpg = NULL; 1015 } 1016 if (pool->stream_enc[i]->afmt != NULL) { 1017 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1018 pool->stream_enc[i]->afmt = NULL; 1019 } 1020 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1021 pool->stream_enc[i] = NULL; 1022 } 1023 } 1024 1025 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1026 if (pool->dscs[i] != NULL) 1027 dcn20_dsc_destroy(&pool->dscs[i]); 1028 } 1029 1030 if (pool->mpc != NULL) { 1031 kfree(TO_DCN20_MPC(pool->mpc)); 1032 pool->mpc = NULL; 1033 } 1034 1035 if (pool->hubbub != NULL) { 1036 kfree(pool->hubbub); 1037 pool->hubbub = NULL; 1038 } 1039 1040 for (i = 0; i < pool->pipe_count; i++) { 1041 if (pool->dpps[i] != NULL) { 1042 kfree(TO_DCN20_DPP(pool->dpps[i])); 1043 pool->dpps[i] = NULL; 1044 } 1045 1046 if (pool->hubps[i] != NULL) { 1047 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1048 pool->hubps[i] = NULL; 1049 } 1050 1051 if (pool->irqs != NULL) 1052 dal_irq_service_destroy(&pool->irqs); 1053 } 1054 1055 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1056 if (pool->engines[i] != NULL) 1057 dce110_engine_destroy(&pool->engines[i]); 1058 if (pool->hw_i2cs[i] != NULL) { 1059 kfree(pool->hw_i2cs[i]); 1060 pool->hw_i2cs[i] = NULL; 1061 } 1062 if (pool->sw_i2cs[i] != NULL) { 1063 kfree(pool->sw_i2cs[i]); 1064 pool->sw_i2cs[i] = NULL; 1065 } 1066 } 1067 1068 for (i = 0; i < pool->res_cap->num_opp; i++) { 1069 if (pool->opps[i] != NULL) 1070 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1071 } 1072 1073 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1074 if (pool->timing_generators[i] != NULL) { 1075 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1076 pool->timing_generators[i] = NULL; 1077 } 1078 } 1079 1080 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1081 if (pool->dwbc[i] != NULL) { 1082 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1083 pool->dwbc[i] = NULL; 1084 } 1085 if (pool->mcif_wb[i] != NULL) { 1086 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1087 pool->mcif_wb[i] = NULL; 1088 } 1089 } 1090 1091 for (i = 0; i < pool->audio_count; i++) { 1092 if (pool->audios[i]) 1093 dce_aud_destroy(&pool->audios[i]); 1094 } 1095 1096 for (i = 0; i < pool->clk_src_count; i++) { 1097 if (pool->clock_sources[i] != NULL) 1098 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1099 } 1100 1101 if (pool->dp_clock_source != NULL) 1102 dcn20_clock_source_destroy(&pool->dp_clock_source); 1103 1104 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1105 if (pool->mpc_lut[i] != NULL) { 1106 dc_3dlut_func_release(pool->mpc_lut[i]); 1107 pool->mpc_lut[i] = NULL; 1108 } 1109 if (pool->mpc_shaper[i] != NULL) { 1110 dc_transfer_func_release(pool->mpc_shaper[i]); 1111 pool->mpc_shaper[i] = NULL; 1112 } 1113 } 1114 1115 for (i = 0; i < pool->pipe_count; i++) { 1116 if (pool->multiple_abms[i] != NULL) 1117 dce_abm_destroy(&pool->multiple_abms[i]); 1118 } 1119 1120 if (pool->psr != NULL) 1121 dmub_psr_destroy(&pool->psr); 1122 1123 if (pool->dccg != NULL) 1124 dcn_dccg_destroy(&pool->dccg); 1125 } 1126 1127 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1128 { 1129 dcn302_resource_destruct(*pool); 1130 kfree(*pool); 1131 *pool = NULL; 1132 } 1133 1134 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1135 { 1136 DC_FP_START(); 1137 dcn302_fpu_update_bw_bounding_box(dc, bw_params); 1138 DC_FP_END(); 1139 } 1140 1141 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config) 1142 { 1143 *panel_config = panel_config_defaults; 1144 } 1145 1146 static struct resource_funcs dcn302_res_pool_funcs = { 1147 .destroy = dcn302_destroy_resource_pool, 1148 .link_enc_create = dcn302_link_encoder_create, 1149 .panel_cntl_create = dcn302_panel_cntl_create, 1150 .validate_bandwidth = dcn30_validate_bandwidth, 1151 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1152 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1153 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1154 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1155 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1156 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1157 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1158 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1159 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1160 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1161 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1162 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1163 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1164 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1165 .get_panel_config_defaults = dcn302_get_panel_config_defaults, 1166 }; 1167 1168 static struct dc_cap_funcs cap_funcs = { 1169 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1170 }; 1171 1172 static const struct bios_registers bios_regs = { 1173 NBIO_SR(BIOS_SCRATCH_3), 1174 NBIO_SR(BIOS_SCRATCH_6) 1175 }; 1176 1177 static const struct dccg_registers dccg_regs = { 1178 DCCG_REG_LIST_DCN3_02() 1179 }; 1180 1181 static const struct dccg_shift dccg_shift = { 1182 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1183 }; 1184 1185 static const struct dccg_mask dccg_mask = { 1186 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1187 }; 1188 1189 #define abm_regs(id)\ 1190 [id] = { ABM_DCN302_REG_LIST(id) } 1191 1192 static const struct dce_abm_registers abm_regs[] = { 1193 abm_regs(0), 1194 abm_regs(1), 1195 abm_regs(2), 1196 abm_regs(3), 1197 abm_regs(4) 1198 }; 1199 1200 static const struct dce_abm_shift abm_shift = { 1201 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1202 }; 1203 1204 static const struct dce_abm_mask abm_mask = { 1205 ABM_MASK_SH_LIST_DCN30(_MASK) 1206 }; 1207 1208 static bool dcn302_resource_construct( 1209 uint8_t num_virtual_links, 1210 struct dc *dc, 1211 struct resource_pool *pool) 1212 { 1213 int i; 1214 struct dc_context *ctx = dc->ctx; 1215 struct irq_service_init_data init_data; 1216 1217 ctx->dc_bios->regs = &bios_regs; 1218 1219 pool->res_cap = &res_cap_dcn302; 1220 1221 pool->funcs = &dcn302_res_pool_funcs; 1222 1223 /************************************************* 1224 * Resource + asic cap harcoding * 1225 *************************************************/ 1226 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1227 pool->pipe_count = pool->res_cap->num_timing_generator; 1228 pool->mpcc_count = pool->res_cap->num_timing_generator; 1229 dc->caps.max_downscale_ratio = 600; 1230 dc->caps.i2c_speed_in_khz = 100; 1231 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1232 dc->caps.max_cursor_size = 256; 1233 dc->caps.min_horizontal_blanking_period = 80; 1234 dc->caps.dmdata_alloc_size = 2048; 1235 dc->caps.mall_size_per_mem_channel = 4; 1236 /* total size = mall per channel * num channels * 1024 * 1024 */ 1237 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1238 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1239 dc->caps.max_slave_planes = 2; 1240 dc->caps.max_slave_yuv_planes = 2; 1241 dc->caps.max_slave_rgb_planes = 2; 1242 dc->caps.post_blend_color_processing = true; 1243 dc->caps.force_dp_tps4_for_cp2520 = true; 1244 dc->caps.extended_aux_timeout_support = true; 1245 dc->caps.dmcub_support = true; 1246 1247 /* Color pipeline capabilities */ 1248 dc->caps.color.dpp.dcn_arch = 1; 1249 dc->caps.color.dpp.input_lut_shared = 0; 1250 dc->caps.color.dpp.icsc = 1; 1251 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1252 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1253 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1254 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1255 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1256 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1257 dc->caps.color.dpp.post_csc = 1; 1258 dc->caps.color.dpp.gamma_corr = 1; 1259 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1260 1261 dc->caps.color.dpp.hw_3d_lut = 1; 1262 dc->caps.color.dpp.ogam_ram = 1; 1263 // no OGAM ROM on DCN3 1264 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1265 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1266 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1267 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1268 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1269 dc->caps.color.dpp.ocsc = 0; 1270 1271 dc->caps.color.mpc.gamut_remap = 1; 1272 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1273 dc->caps.color.mpc.ogam_ram = 1; 1274 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1275 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1276 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1277 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1278 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1279 dc->caps.color.mpc.ocsc = 1; 1280 1281 /* read VBIOS LTTPR caps */ 1282 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1283 enum bp_result bp_query_result; 1284 uint8_t is_vbios_lttpr_enable = 0; 1285 1286 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1287 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1288 } 1289 1290 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1291 enum bp_result bp_query_result; 1292 uint8_t is_vbios_interop_enabled = 0; 1293 1294 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 1295 &is_vbios_interop_enabled); 1296 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1297 } 1298 1299 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1300 dc->debug = debug_defaults_drv; 1301 else 1302 dc->debug = debug_defaults_diags; 1303 1304 // Init the vm_helper 1305 if (dc->vm_helper) 1306 vm_helper_init(dc->vm_helper, 16); 1307 1308 /************************************************* 1309 * Create resources * 1310 *************************************************/ 1311 1312 /* Clock Sources for Pixel Clock*/ 1313 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1314 dcn302_clock_source_create(ctx, ctx->dc_bios, 1315 CLOCK_SOURCE_COMBO_PHY_PLL0, 1316 &clk_src_regs[0], false); 1317 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1318 dcn302_clock_source_create(ctx, ctx->dc_bios, 1319 CLOCK_SOURCE_COMBO_PHY_PLL1, 1320 &clk_src_regs[1], false); 1321 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1322 dcn302_clock_source_create(ctx, ctx->dc_bios, 1323 CLOCK_SOURCE_COMBO_PHY_PLL2, 1324 &clk_src_regs[2], false); 1325 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1326 dcn302_clock_source_create(ctx, ctx->dc_bios, 1327 CLOCK_SOURCE_COMBO_PHY_PLL3, 1328 &clk_src_regs[3], false); 1329 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1330 dcn302_clock_source_create(ctx, ctx->dc_bios, 1331 CLOCK_SOURCE_COMBO_PHY_PLL4, 1332 &clk_src_regs[4], false); 1333 1334 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1335 1336 /* todo: not reuse phy_pll registers */ 1337 pool->dp_clock_source = 1338 dcn302_clock_source_create(ctx, ctx->dc_bios, 1339 CLOCK_SOURCE_ID_DP_DTO, 1340 &clk_src_regs[0], true); 1341 1342 for (i = 0; i < pool->clk_src_count; i++) { 1343 if (pool->clock_sources[i] == NULL) { 1344 dm_error("DC: failed to create clock sources!\n"); 1345 BREAK_TO_DEBUGGER(); 1346 goto create_fail; 1347 } 1348 } 1349 1350 /* DCCG */ 1351 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1352 if (pool->dccg == NULL) { 1353 dm_error("DC: failed to create dccg!\n"); 1354 BREAK_TO_DEBUGGER(); 1355 goto create_fail; 1356 } 1357 1358 /* PP Lib and SMU interfaces */ 1359 init_soc_bounding_box(dc, pool); 1360 1361 /* DML */ 1362 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1363 1364 /* IRQ */ 1365 init_data.ctx = dc->ctx; 1366 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1367 if (!pool->irqs) 1368 goto create_fail; 1369 1370 /* HUBBUB */ 1371 pool->hubbub = dcn302_hubbub_create(ctx); 1372 if (pool->hubbub == NULL) { 1373 BREAK_TO_DEBUGGER(); 1374 dm_error("DC: failed to create hubbub!\n"); 1375 goto create_fail; 1376 } 1377 1378 /* HUBPs, DPPs, OPPs and TGs */ 1379 for (i = 0; i < pool->pipe_count; i++) { 1380 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1381 if (pool->hubps[i] == NULL) { 1382 BREAK_TO_DEBUGGER(); 1383 dm_error("DC: failed to create hubps!\n"); 1384 goto create_fail; 1385 } 1386 1387 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1388 if (pool->dpps[i] == NULL) { 1389 BREAK_TO_DEBUGGER(); 1390 dm_error("DC: failed to create dpps!\n"); 1391 goto create_fail; 1392 } 1393 } 1394 1395 for (i = 0; i < pool->res_cap->num_opp; i++) { 1396 pool->opps[i] = dcn302_opp_create(ctx, i); 1397 if (pool->opps[i] == NULL) { 1398 BREAK_TO_DEBUGGER(); 1399 dm_error("DC: failed to create output pixel processor!\n"); 1400 goto create_fail; 1401 } 1402 } 1403 1404 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1405 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1406 if (pool->timing_generators[i] == NULL) { 1407 BREAK_TO_DEBUGGER(); 1408 dm_error("DC: failed to create tg!\n"); 1409 goto create_fail; 1410 } 1411 } 1412 pool->timing_generator_count = i; 1413 1414 /* PSR */ 1415 pool->psr = dmub_psr_create(ctx); 1416 if (pool->psr == NULL) { 1417 dm_error("DC: failed to create psr!\n"); 1418 BREAK_TO_DEBUGGER(); 1419 goto create_fail; 1420 } 1421 1422 /* ABMs */ 1423 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1424 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1425 if (pool->multiple_abms[i] == NULL) { 1426 dm_error("DC: failed to create abm for pipe %d!\n", i); 1427 BREAK_TO_DEBUGGER(); 1428 goto create_fail; 1429 } 1430 } 1431 1432 /* MPC and DSC */ 1433 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1434 if (pool->mpc == NULL) { 1435 BREAK_TO_DEBUGGER(); 1436 dm_error("DC: failed to create mpc!\n"); 1437 goto create_fail; 1438 } 1439 1440 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1441 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1442 if (pool->dscs[i] == NULL) { 1443 BREAK_TO_DEBUGGER(); 1444 dm_error("DC: failed to create display stream compressor %d!\n", i); 1445 goto create_fail; 1446 } 1447 } 1448 1449 /* DWB and MMHUBBUB */ 1450 if (!dcn302_dwbc_create(ctx, pool)) { 1451 BREAK_TO_DEBUGGER(); 1452 dm_error("DC: failed to create dwbc!\n"); 1453 goto create_fail; 1454 } 1455 1456 if (!dcn302_mmhubbub_create(ctx, pool)) { 1457 BREAK_TO_DEBUGGER(); 1458 dm_error("DC: failed to create mcif_wb!\n"); 1459 goto create_fail; 1460 } 1461 1462 /* AUX and I2C */ 1463 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1464 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1465 if (pool->engines[i] == NULL) { 1466 BREAK_TO_DEBUGGER(); 1467 dm_error("DC:failed to create aux engine!!\n"); 1468 goto create_fail; 1469 } 1470 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1471 if (pool->hw_i2cs[i] == NULL) { 1472 BREAK_TO_DEBUGGER(); 1473 dm_error("DC:failed to create hw i2c!!\n"); 1474 goto create_fail; 1475 } 1476 pool->sw_i2cs[i] = NULL; 1477 } 1478 1479 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1480 if (!resource_construct(num_virtual_links, dc, pool, 1481 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1482 &res_create_funcs : &res_create_maximus_funcs))) 1483 goto create_fail; 1484 1485 /* HW Sequencer and Plane caps */ 1486 dcn302_hw_sequencer_construct(dc); 1487 1488 dc->caps.max_planes = pool->pipe_count; 1489 1490 for (i = 0; i < dc->caps.max_planes; ++i) 1491 dc->caps.planes[i] = plane_cap; 1492 1493 dc->cap_funcs = cap_funcs; 1494 1495 return true; 1496 1497 create_fail: 1498 1499 dcn302_resource_destruct(pool); 1500 1501 return false; 1502 } 1503 1504 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1505 { 1506 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1507 1508 if (!pool) 1509 return NULL; 1510 1511 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1512 return pool; 1513 1514 BREAK_TO_DEBUGGER(); 1515 kfree(pool); 1516 return NULL; 1517 } 1518