1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dcn10/dcn10_resource.h" 47 48 #include "dce/dce_abm.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_clock_source.h" 52 #include "dce/dce_hwseq.h" 53 #include "dce/dce_i2c_hw.h" 54 #include "dce/dce_panel_cntl.h" 55 #include "dce/dmub_abm.h" 56 #include "dce/dmub_psr.h" 57 #include "clk_mgr.h" 58 59 #include "hw_sequencer_private.h" 60 #include "reg_helper.h" 61 #include "resource.h" 62 #include "vm_helper.h" 63 64 #include "dimgrey_cavefish_ip_offset.h" 65 #include "dcn/dcn_3_0_2_offset.h" 66 #include "dcn/dcn_3_0_2_sh_mask.h" 67 #include "dcn/dpcs_3_0_0_offset.h" 68 #include "dcn/dpcs_3_0_0_sh_mask.h" 69 #include "nbio/nbio_7_4_offset.h" 70 #include "amdgpu_socbb.h" 71 72 #define DC_LOGGER_INIT(logger) 73 74 struct _vcs_dpi_ip_params_st dcn3_02_ip = { 75 .use_min_dcfclk = 0, 76 .clamp_min_dcfclk = 0, 77 .odm_capable = 1, 78 .gpuvm_enable = 1, 79 .hostvm_enable = 0, 80 .gpuvm_max_page_table_levels = 4, 81 .hostvm_max_page_table_levels = 4, 82 .hostvm_cached_page_table_levels = 0, 83 .pte_group_size_bytes = 2048, 84 .num_dsc = 5, 85 .rob_buffer_size_kbytes = 184, 86 .det_buffer_size_kbytes = 184, 87 .dpte_buffer_size_in_pte_reqs_luma = 64, 88 .dpte_buffer_size_in_pte_reqs_chroma = 34, 89 .pde_proc_buffer_size_64k_reqs = 48, 90 .dpp_output_buffer_pixels = 2560, 91 .opp_output_buffer_lines = 1, 92 .pixel_chunk_size_kbytes = 8, 93 .pte_enable = 1, 94 .max_page_table_levels = 2, 95 .pte_chunk_size_kbytes = 2, // ? 96 .meta_chunk_size_kbytes = 2, 97 .writeback_chunk_size_kbytes = 8, 98 .line_buffer_size_bits = 789504, 99 .is_line_buffer_bpp_fixed = 0, // ? 100 .line_buffer_fixed_bpp = 0, // ? 101 .dcc_supported = true, 102 .writeback_interface_buffer_size_kbytes = 90, 103 .writeback_line_buffer_buffer_size = 0, 104 .max_line_buffer_lines = 12, 105 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 106 .writeback_chroma_buffer_size_kbytes = 8, 107 .writeback_chroma_line_buffer_width_pixels = 4, 108 .writeback_max_hscl_ratio = 1, 109 .writeback_max_vscl_ratio = 1, 110 .writeback_min_hscl_ratio = 1, 111 .writeback_min_vscl_ratio = 1, 112 .writeback_max_hscl_taps = 1, 113 .writeback_max_vscl_taps = 1, 114 .writeback_line_buffer_luma_buffer_size = 0, 115 .writeback_line_buffer_chroma_buffer_size = 14643, 116 .cursor_buffer_size = 8, 117 .cursor_chunk_size = 2, 118 .max_num_otg = 5, 119 .max_num_dpp = 5, 120 .max_num_wb = 1, 121 .max_dchub_pscl_bw_pix_per_clk = 4, 122 .max_pscl_lb_bw_pix_per_clk = 2, 123 .max_lb_vscl_bw_pix_per_clk = 4, 124 .max_vscl_hscl_bw_pix_per_clk = 4, 125 .max_hscl_ratio = 6, 126 .max_vscl_ratio = 6, 127 .hscl_mults = 4, 128 .vscl_mults = 4, 129 .max_hscl_taps = 8, 130 .max_vscl_taps = 8, 131 .dispclk_ramp_margin_percent = 1, 132 .underscan_factor = 1.11, 133 .min_vblank_lines = 32, 134 .dppclk_delay_subtotal = 46, 135 .dynamic_metadata_vm_enabled = true, 136 .dppclk_delay_scl_lb_only = 16, 137 .dppclk_delay_scl = 50, 138 .dppclk_delay_cnvc_formatter = 27, 139 .dppclk_delay_cnvc_cursor = 6, 140 .dispclk_delay_subtotal = 119, 141 .dcfclk_cstate_latency = 5.2, // SRExitTime 142 .max_inter_dcn_tile_repeaters = 8, 143 .max_num_hdmi_frl_outputs = 1, 144 .odm_combine_4to1_supported = true, 145 146 .xfc_supported = false, 147 .xfc_fill_bw_overhead_percent = 10.0, 148 .xfc_fill_constant_bytes = 0, 149 .gfx7_compat_tiling_supported = 0, 150 .number_of_cursors = 1, 151 }; 152 153 struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = { 154 .clock_limits = { 155 { 156 .state = 0, 157 .dispclk_mhz = 562.0, 158 .dppclk_mhz = 300.0, 159 .phyclk_mhz = 300.0, 160 .phyclk_d18_mhz = 667.0, 161 .dscclk_mhz = 405.6, 162 }, 163 }, 164 165 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 166 .num_states = 1, 167 .sr_exit_time_us = 12, 168 .sr_enter_plus_exit_time_us = 20, 169 .urgent_latency_us = 4.0, 170 .urgent_latency_pixel_data_only_us = 4.0, 171 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 172 .urgent_latency_vm_data_only_us = 4.0, 173 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 174 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 175 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 176 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 177 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 178 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 179 .max_avg_sdp_bw_use_normal_percent = 60.0, 180 .max_avg_dram_bw_use_normal_percent = 40.0, 181 .writeback_latency_us = 12.0, 182 .max_request_size_bytes = 256, 183 .fabric_datapath_to_dcn_data_return_bytes = 64, 184 .dcn_downspread_percent = 0.5, 185 .downspread_percent = 0.38, 186 .dram_page_open_time_ns = 50.0, 187 .dram_rw_turnaround_time_ns = 17.5, 188 .dram_return_buffer_per_channel_bytes = 8192, 189 .round_trip_ping_latency_dcfclk_cycles = 156, 190 .urgent_out_of_order_return_per_channel_bytes = 4096, 191 .channel_interleave_bytes = 256, 192 .num_banks = 8, 193 .gpuvm_min_page_size_bytes = 4096, 194 .hostvm_min_page_size_bytes = 4096, 195 .dram_clock_change_latency_us = 404, 196 .dummy_pstate_latency_us = 5, 197 .writeback_dram_clock_change_latency_us = 23.0, 198 .return_bus_width_bytes = 64, 199 .dispclk_dppclk_vco_speed_mhz = 3650, 200 .xfc_bus_transport_time_us = 20, // ? 201 .xfc_xbuf_latency_tolerance_us = 4, // ? 202 .use_urgent_burst_bw = 1, // ? 203 .do_urgent_latency_adjustment = true, 204 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 205 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 206 }; 207 208 static const struct dc_debug_options debug_defaults_drv = { 209 .disable_dmcu = true, 210 .force_abm_enable = false, 211 .timing_trace = false, 212 .clock_trace = true, 213 .disable_pplib_clock_request = true, 214 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 215 .force_single_disp_pipe_split = false, 216 .disable_dcc = DCC_ENABLE, 217 .vsr_support = true, 218 .performance_trace = false, 219 .max_downscale_src_width = 7680,/*upto 8K*/ 220 .disable_pplib_wm_range = false, 221 .scl_reset_length10 = true, 222 .sanity_checks = false, 223 .underflow_assert_delay_us = 0xFFFFFFFF, 224 .dwb_fi_phase = -1, // -1 = disable, 225 .dmub_command_table = true, 226 }; 227 228 static const struct dc_debug_options debug_defaults_diags = { 229 .disable_dmcu = true, 230 .force_abm_enable = false, 231 .timing_trace = true, 232 .clock_trace = true, 233 .disable_dpp_power_gate = true, 234 .disable_hubp_power_gate = true, 235 .disable_clock_gate = true, 236 .disable_pplib_clock_request = true, 237 .disable_pplib_wm_range = true, 238 .disable_stutter = false, 239 .scl_reset_length10 = true, 240 .dwb_fi_phase = -1, // -1 = disable 241 .dmub_command_table = true, 242 .enable_tri_buf = true, 243 .disable_psr = true, 244 }; 245 246 enum dcn302_clk_src_array_id { 247 DCN302_CLK_SRC_PLL0, 248 DCN302_CLK_SRC_PLL1, 249 DCN302_CLK_SRC_PLL2, 250 DCN302_CLK_SRC_PLL3, 251 DCN302_CLK_SRC_PLL4, 252 DCN302_CLK_SRC_TOTAL 253 }; 254 255 static const struct resource_caps res_cap_dcn302 = { 256 .num_timing_generator = 5, 257 .num_opp = 5, 258 .num_video_plane = 5, 259 .num_audio = 5, 260 .num_stream_encoder = 5, 261 .num_dwb = 1, 262 .num_ddc = 5, 263 .num_vmid = 16, 264 .num_mpc_3dlut = 2, 265 .num_dsc = 5, 266 }; 267 268 static const struct dc_plane_cap plane_cap = { 269 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 270 .blends_with_above = true, 271 .blends_with_below = true, 272 .per_pixel_alpha = true, 273 .pixel_format_support = { 274 .argb8888 = true, 275 .nv12 = true, 276 .fp16 = true, 277 .p010 = false, 278 .ayuv = false, 279 }, 280 .max_upscale_factor = { 281 .argb8888 = 16000, 282 .nv12 = 16000, 283 .fp16 = 16000 284 }, 285 .max_downscale_factor = { 286 .argb8888 = 600, 287 .nv12 = 600, 288 .fp16 = 600 289 }, 290 16, 291 16 292 }; 293 294 /* NBIO */ 295 #define NBIO_BASE_INNER(seg) \ 296 NBIO_BASE__INST0_SEG ## seg 297 298 #define NBIO_BASE(seg) \ 299 NBIO_BASE_INNER(seg) 300 301 #define NBIO_SR(reg_name)\ 302 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 303 mm ## reg_name 304 305 /* DCN */ 306 #undef BASE_INNER 307 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 308 309 #define BASE(seg) BASE_INNER(seg) 310 311 #define SR(reg_name)\ 312 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 313 314 #define SF(reg_name, field_name, post_fix)\ 315 .field_name = reg_name ## __ ## field_name ## post_fix 316 317 #define SRI(reg_name, block, id)\ 318 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 319 320 #define SRI2(reg_name, block, id)\ 321 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 322 323 #define SRII(reg_name, block, id)\ 324 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 325 mm ## block ## id ## _ ## reg_name 326 327 #define DCCG_SRII(reg_name, block, id)\ 328 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 329 mm ## block ## id ## _ ## reg_name 330 331 #define VUPDATE_SRII(reg_name, block, id)\ 332 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 333 mm ## reg_name ## _ ## block ## id 334 335 #define SRII_DWB(reg_name, temp_name, block, id)\ 336 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 337 mm ## block ## id ## _ ## temp_name 338 339 #define SRII_MPC_RMU(reg_name, block, id)\ 340 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 341 mm ## block ## id ## _ ## reg_name 342 343 static const struct dcn_hubbub_registers hubbub_reg = { 344 HUBBUB_REG_LIST_DCN30(0) 345 }; 346 347 static const struct dcn_hubbub_shift hubbub_shift = { 348 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 349 }; 350 351 static const struct dcn_hubbub_mask hubbub_mask = { 352 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 353 }; 354 355 #define vmid_regs(id)\ 356 [id] = { DCN20_VMID_REG_LIST(id) } 357 358 static const struct dcn_vmid_registers vmid_regs[] = { 359 vmid_regs(0), 360 vmid_regs(1), 361 vmid_regs(2), 362 vmid_regs(3), 363 vmid_regs(4), 364 vmid_regs(5), 365 vmid_regs(6), 366 vmid_regs(7), 367 vmid_regs(8), 368 vmid_regs(9), 369 vmid_regs(10), 370 vmid_regs(11), 371 vmid_regs(12), 372 vmid_regs(13), 373 vmid_regs(14), 374 vmid_regs(15) 375 }; 376 377 static const struct dcn20_vmid_shift vmid_shifts = { 378 DCN20_VMID_MASK_SH_LIST(__SHIFT) 379 }; 380 381 static const struct dcn20_vmid_mask vmid_masks = { 382 DCN20_VMID_MASK_SH_LIST(_MASK) 383 }; 384 385 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 386 { 387 int i; 388 389 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 390 391 if (!hubbub3) 392 return NULL; 393 394 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 395 396 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 397 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 398 399 vmid->ctx = ctx; 400 401 vmid->regs = &vmid_regs[i]; 402 vmid->shifts = &vmid_shifts; 403 vmid->masks = &vmid_masks; 404 } 405 406 return &hubbub3->base; 407 } 408 409 #define vpg_regs(id)\ 410 [id] = { VPG_DCN3_REG_LIST(id) } 411 412 static const struct dcn30_vpg_registers vpg_regs[] = { 413 vpg_regs(0), 414 vpg_regs(1), 415 vpg_regs(2), 416 vpg_regs(3), 417 vpg_regs(4), 418 vpg_regs(5) 419 }; 420 421 static const struct dcn30_vpg_shift vpg_shift = { 422 DCN3_VPG_MASK_SH_LIST(__SHIFT) 423 }; 424 425 static const struct dcn30_vpg_mask vpg_mask = { 426 DCN3_VPG_MASK_SH_LIST(_MASK) 427 }; 428 429 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 430 { 431 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 432 433 if (!vpg3) 434 return NULL; 435 436 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 437 438 return &vpg3->base; 439 } 440 441 #define afmt_regs(id)\ 442 [id] = { AFMT_DCN3_REG_LIST(id) } 443 444 static const struct dcn30_afmt_registers afmt_regs[] = { 445 afmt_regs(0), 446 afmt_regs(1), 447 afmt_regs(2), 448 afmt_regs(3), 449 afmt_regs(4), 450 afmt_regs(5) 451 }; 452 453 static const struct dcn30_afmt_shift afmt_shift = { 454 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 455 }; 456 457 static const struct dcn30_afmt_mask afmt_mask = { 458 DCN3_AFMT_MASK_SH_LIST(_MASK) 459 }; 460 461 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 462 { 463 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 464 465 if (!afmt3) 466 return NULL; 467 468 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 469 470 return &afmt3->base; 471 } 472 473 #define audio_regs(id)\ 474 [id] = { AUD_COMMON_REG_LIST(id) } 475 476 static const struct dce_audio_registers audio_regs[] = { 477 audio_regs(0), 478 audio_regs(1), 479 audio_regs(2), 480 audio_regs(3), 481 audio_regs(4), 482 audio_regs(5), 483 audio_regs(6) 484 }; 485 486 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 487 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 488 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 489 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 490 491 static const struct dce_audio_shift audio_shift = { 492 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 493 }; 494 495 static const struct dce_audio_mask audio_mask = { 496 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 497 }; 498 499 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 500 { 501 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 502 } 503 504 #define stream_enc_regs(id)\ 505 [id] = { SE_DCN3_REG_LIST(id) } 506 507 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 508 stream_enc_regs(0), 509 stream_enc_regs(1), 510 stream_enc_regs(2), 511 stream_enc_regs(3), 512 stream_enc_regs(4) 513 }; 514 515 static const struct dcn10_stream_encoder_shift se_shift = { 516 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 517 }; 518 519 static const struct dcn10_stream_encoder_mask se_mask = { 520 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 521 }; 522 523 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 524 { 525 struct dcn10_stream_encoder *enc1; 526 struct vpg *vpg; 527 struct afmt *afmt; 528 int vpg_inst; 529 int afmt_inst; 530 531 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 532 if (eng_id <= ENGINE_ID_DIGE) { 533 vpg_inst = eng_id; 534 afmt_inst = eng_id; 535 } else 536 return NULL; 537 538 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 539 vpg = dcn302_vpg_create(ctx, vpg_inst); 540 afmt = dcn302_afmt_create(ctx, afmt_inst); 541 542 if (!enc1 || !vpg || !afmt) 543 return NULL; 544 545 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 546 &se_shift, &se_mask); 547 548 return &enc1->base; 549 } 550 551 #define clk_src_regs(index, pllid)\ 552 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 553 554 static const struct dce110_clk_src_regs clk_src_regs[] = { 555 clk_src_regs(0, A), 556 clk_src_regs(1, B), 557 clk_src_regs(2, C), 558 clk_src_regs(3, D), 559 clk_src_regs(4, E) 560 }; 561 562 static const struct dce110_clk_src_shift cs_shift = { 563 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 564 }; 565 566 static const struct dce110_clk_src_mask cs_mask = { 567 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 568 }; 569 570 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 571 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 572 { 573 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 574 575 if (!clk_src) 576 return NULL; 577 578 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 579 clk_src->base.dp_clk_src = dp_clk_src; 580 return &clk_src->base; 581 } 582 583 BREAK_TO_DEBUGGER(); 584 return NULL; 585 } 586 587 static const struct dce_hwseq_registers hwseq_reg = { 588 HWSEQ_DCN302_REG_LIST() 589 }; 590 591 static const struct dce_hwseq_shift hwseq_shift = { 592 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 593 }; 594 595 static const struct dce_hwseq_mask hwseq_mask = { 596 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 597 }; 598 599 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 600 { 601 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 602 603 if (hws) { 604 hws->ctx = ctx; 605 hws->regs = &hwseq_reg; 606 hws->shifts = &hwseq_shift; 607 hws->masks = &hwseq_mask; 608 } 609 return hws; 610 } 611 612 #define hubp_regs(id)\ 613 [id] = { HUBP_REG_LIST_DCN30(id) } 614 615 static const struct dcn_hubp2_registers hubp_regs[] = { 616 hubp_regs(0), 617 hubp_regs(1), 618 hubp_regs(2), 619 hubp_regs(3), 620 hubp_regs(4) 621 }; 622 623 static const struct dcn_hubp2_shift hubp_shift = { 624 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 625 }; 626 627 static const struct dcn_hubp2_mask hubp_mask = { 628 HUBP_MASK_SH_LIST_DCN30(_MASK) 629 }; 630 631 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 632 { 633 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 634 635 if (!hubp2) 636 return NULL; 637 638 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 639 return &hubp2->base; 640 641 BREAK_TO_DEBUGGER(); 642 kfree(hubp2); 643 return NULL; 644 } 645 646 #define dpp_regs(id)\ 647 [id] = { DPP_REG_LIST_DCN30(id) } 648 649 static const struct dcn3_dpp_registers dpp_regs[] = { 650 dpp_regs(0), 651 dpp_regs(1), 652 dpp_regs(2), 653 dpp_regs(3), 654 dpp_regs(4) 655 }; 656 657 static const struct dcn3_dpp_shift tf_shift = { 658 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 659 }; 660 661 static const struct dcn3_dpp_mask tf_mask = { 662 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 663 }; 664 665 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 666 { 667 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 668 669 if (!dpp) 670 return NULL; 671 672 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 673 return &dpp->base; 674 675 BREAK_TO_DEBUGGER(); 676 kfree(dpp); 677 return NULL; 678 } 679 680 #define opp_regs(id)\ 681 [id] = { OPP_REG_LIST_DCN30(id) } 682 683 static const struct dcn20_opp_registers opp_regs[] = { 684 opp_regs(0), 685 opp_regs(1), 686 opp_regs(2), 687 opp_regs(3), 688 opp_regs(4) 689 }; 690 691 static const struct dcn20_opp_shift opp_shift = { 692 OPP_MASK_SH_LIST_DCN20(__SHIFT) 693 }; 694 695 static const struct dcn20_opp_mask opp_mask = { 696 OPP_MASK_SH_LIST_DCN20(_MASK) 697 }; 698 699 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 700 { 701 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 702 703 if (!opp) { 704 BREAK_TO_DEBUGGER(); 705 return NULL; 706 } 707 708 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 709 return &opp->base; 710 } 711 712 #define optc_regs(id)\ 713 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 714 715 static const struct dcn_optc_registers optc_regs[] = { 716 optc_regs(0), 717 optc_regs(1), 718 optc_regs(2), 719 optc_regs(3), 720 optc_regs(4) 721 }; 722 723 static const struct dcn_optc_shift optc_shift = { 724 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 725 }; 726 727 static const struct dcn_optc_mask optc_mask = { 728 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 729 }; 730 731 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 732 { 733 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 734 735 if (!tgn10) 736 return NULL; 737 738 tgn10->base.inst = instance; 739 tgn10->base.ctx = ctx; 740 741 tgn10->tg_regs = &optc_regs[instance]; 742 tgn10->tg_shift = &optc_shift; 743 tgn10->tg_mask = &optc_mask; 744 745 dcn30_timing_generator_init(tgn10); 746 747 return &tgn10->base; 748 } 749 750 static const struct dcn30_mpc_registers mpc_regs = { 751 MPC_REG_LIST_DCN3_0(0), 752 MPC_REG_LIST_DCN3_0(1), 753 MPC_REG_LIST_DCN3_0(2), 754 MPC_REG_LIST_DCN3_0(3), 755 MPC_REG_LIST_DCN3_0(4), 756 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 757 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 758 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 759 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 760 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 761 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 762 MPC_RMU_REG_LIST_DCN3AG(0), 763 MPC_RMU_REG_LIST_DCN3AG(1), 764 MPC_RMU_REG_LIST_DCN3AG(2), 765 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 766 }; 767 768 static const struct dcn30_mpc_shift mpc_shift = { 769 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 770 }; 771 772 static const struct dcn30_mpc_mask mpc_mask = { 773 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 774 }; 775 776 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 777 { 778 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 779 780 if (!mpc30) 781 return NULL; 782 783 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 784 785 return &mpc30->base; 786 } 787 788 #define dsc_regsDCN20(id)\ 789 [id] = { DSC_REG_LIST_DCN20(id) } 790 791 static const struct dcn20_dsc_registers dsc_regs[] = { 792 dsc_regsDCN20(0), 793 dsc_regsDCN20(1), 794 dsc_regsDCN20(2), 795 dsc_regsDCN20(3), 796 dsc_regsDCN20(4) 797 }; 798 799 static const struct dcn20_dsc_shift dsc_shift = { 800 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 801 }; 802 803 static const struct dcn20_dsc_mask dsc_mask = { 804 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 805 }; 806 807 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 808 { 809 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 810 811 if (!dsc) { 812 BREAK_TO_DEBUGGER(); 813 return NULL; 814 } 815 816 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 817 return &dsc->base; 818 } 819 820 #define dwbc_regs_dcn3(id)\ 821 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 822 823 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 824 dwbc_regs_dcn3(0) 825 }; 826 827 static const struct dcn30_dwbc_shift dwbc30_shift = { 828 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 829 }; 830 831 static const struct dcn30_dwbc_mask dwbc30_mask = { 832 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 833 }; 834 835 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 836 { 837 int i; 838 uint32_t pipe_count = pool->res_cap->num_dwb; 839 840 for (i = 0; i < pipe_count; i++) { 841 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 842 843 if (!dwbc30) { 844 dm_error("DC: failed to create dwbc30!\n"); 845 return false; 846 } 847 848 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 849 850 pool->dwbc[i] = &dwbc30->base; 851 } 852 return true; 853 } 854 855 #define mcif_wb_regs_dcn3(id)\ 856 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 857 858 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 859 mcif_wb_regs_dcn3(0) 860 }; 861 862 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 863 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 864 }; 865 866 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 867 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 868 }; 869 870 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 871 { 872 int i; 873 uint32_t pipe_count = pool->res_cap->num_dwb; 874 875 for (i = 0; i < pipe_count; i++) { 876 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 877 878 if (!mcif_wb30) { 879 dm_error("DC: failed to create mcif_wb30!\n"); 880 return false; 881 } 882 883 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 884 885 pool->mcif_wb[i] = &mcif_wb30->base; 886 } 887 return true; 888 } 889 890 #define aux_engine_regs(id)\ 891 [id] = {\ 892 AUX_COMMON_REG_LIST0(id), \ 893 .AUXN_IMPCAL = 0, \ 894 .AUXP_IMPCAL = 0, \ 895 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 896 } 897 898 static const struct dce110_aux_registers aux_engine_regs[] = { 899 aux_engine_regs(0), 900 aux_engine_regs(1), 901 aux_engine_regs(2), 902 aux_engine_regs(3), 903 aux_engine_regs(4) 904 }; 905 906 static const struct dce110_aux_registers_shift aux_shift = { 907 DCN_AUX_MASK_SH_LIST(__SHIFT) 908 }; 909 910 static const struct dce110_aux_registers_mask aux_mask = { 911 DCN_AUX_MASK_SH_LIST(_MASK) 912 }; 913 914 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 915 { 916 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 917 918 if (!aux_engine) 919 return NULL; 920 921 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 922 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 923 924 return &aux_engine->base; 925 } 926 927 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 928 929 static const struct dce_i2c_registers i2c_hw_regs[] = { 930 i2c_inst_regs(1), 931 i2c_inst_regs(2), 932 i2c_inst_regs(3), 933 i2c_inst_regs(4), 934 i2c_inst_regs(5) 935 }; 936 937 static const struct dce_i2c_shift i2c_shifts = { 938 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 939 }; 940 941 static const struct dce_i2c_mask i2c_masks = { 942 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 943 }; 944 945 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 946 { 947 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 948 949 if (!dce_i2c_hw) 950 return NULL; 951 952 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 953 954 return dce_i2c_hw; 955 } 956 957 static const struct encoder_feature_support link_enc_feature = { 958 .max_hdmi_deep_color = COLOR_DEPTH_121212, 959 .max_hdmi_pixel_clock = 600000, 960 .hdmi_ycbcr420_supported = true, 961 .dp_ycbcr420_supported = true, 962 .fec_supported = true, 963 .flags.bits.IS_HBR2_CAPABLE = true, 964 .flags.bits.IS_HBR3_CAPABLE = true, 965 .flags.bits.IS_TPS3_CAPABLE = true, 966 .flags.bits.IS_TPS4_CAPABLE = true 967 }; 968 969 #define link_regs(id, phyid)\ 970 [id] = {\ 971 LE_DCN3_REG_LIST(id), \ 972 UNIPHY_DCN2_REG_LIST(phyid), \ 973 DPCS_DCN2_REG_LIST(id), \ 974 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 975 } 976 977 static const struct dcn10_link_enc_registers link_enc_regs[] = { 978 link_regs(0, A), 979 link_regs(1, B), 980 link_regs(2, C), 981 link_regs(3, D), 982 link_regs(4, E) 983 }; 984 985 static const struct dcn10_link_enc_shift le_shift = { 986 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 987 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 988 }; 989 990 static const struct dcn10_link_enc_mask le_mask = { 991 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 992 DPCS_DCN2_MASK_SH_LIST(_MASK) 993 }; 994 995 #define aux_regs(id)\ 996 [id] = { DCN2_AUX_REG_LIST(id) } 997 998 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 999 aux_regs(0), 1000 aux_regs(1), 1001 aux_regs(2), 1002 aux_regs(3), 1003 aux_regs(4) 1004 }; 1005 1006 #define hpd_regs(id)\ 1007 [id] = { HPD_REG_LIST(id) } 1008 1009 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1010 hpd_regs(0), 1011 hpd_regs(1), 1012 hpd_regs(2), 1013 hpd_regs(3), 1014 hpd_regs(4) 1015 }; 1016 1017 static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data) 1018 { 1019 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1020 1021 if (!enc20) 1022 return NULL; 1023 1024 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 1025 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 1026 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 1027 1028 return &enc20->enc10.base; 1029 } 1030 1031 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1032 { DCN_PANEL_CNTL_REG_LIST() } 1033 }; 1034 1035 static const struct dce_panel_cntl_shift panel_cntl_shift = { 1036 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1037 }; 1038 1039 static const struct dce_panel_cntl_mask panel_cntl_mask = { 1040 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1041 }; 1042 1043 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1044 { 1045 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1046 1047 if (!panel_cntl) 1048 return NULL; 1049 1050 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 1051 &panel_cntl_shift, &panel_cntl_mask); 1052 1053 return &panel_cntl->base; 1054 } 1055 1056 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 1057 { 1058 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1059 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1060 } 1061 1062 static const struct resource_create_funcs res_create_funcs = { 1063 .read_dce_straps = read_dce_straps, 1064 .create_audio = dcn302_create_audio, 1065 .create_stream_encoder = dcn302_stream_encoder_create, 1066 .create_hwseq = dcn302_hwseq_create, 1067 }; 1068 1069 static const struct resource_create_funcs res_create_maximus_funcs = { 1070 .read_dce_straps = NULL, 1071 .create_audio = NULL, 1072 .create_stream_encoder = NULL, 1073 .create_hwseq = dcn302_hwseq_create, 1074 }; 1075 1076 static bool is_soc_bounding_box_valid(struct dc *dc) 1077 { 1078 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1079 1080 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 1081 return true; 1082 1083 return false; 1084 } 1085 1086 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 1087 { 1088 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 1089 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 1090 1091 DC_LOGGER_INIT(dc->ctx->logger); 1092 1093 if (!is_soc_bounding_box_valid(dc)) { 1094 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1095 return false; 1096 } 1097 1098 loaded_ip->max_num_otg = pool->pipe_count; 1099 loaded_ip->max_num_dpp = pool->pipe_count; 1100 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1101 dcn20_patch_bounding_box(dc, loaded_bb); 1102 return true; 1103 } 1104 1105 static void dcn302_resource_destruct(struct resource_pool *pool) 1106 { 1107 unsigned int i; 1108 1109 for (i = 0; i < pool->stream_enc_count; i++) { 1110 if (pool->stream_enc[i] != NULL) { 1111 if (pool->stream_enc[i]->vpg != NULL) { 1112 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1113 pool->stream_enc[i]->vpg = NULL; 1114 } 1115 if (pool->stream_enc[i]->afmt != NULL) { 1116 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1117 pool->stream_enc[i]->afmt = NULL; 1118 } 1119 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1120 pool->stream_enc[i] = NULL; 1121 } 1122 } 1123 1124 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1125 if (pool->dscs[i] != NULL) 1126 dcn20_dsc_destroy(&pool->dscs[i]); 1127 } 1128 1129 if (pool->mpc != NULL) { 1130 kfree(TO_DCN20_MPC(pool->mpc)); 1131 pool->mpc = NULL; 1132 } 1133 1134 if (pool->hubbub != NULL) { 1135 kfree(pool->hubbub); 1136 pool->hubbub = NULL; 1137 } 1138 1139 for (i = 0; i < pool->pipe_count; i++) { 1140 if (pool->dpps[i] != NULL) { 1141 kfree(TO_DCN20_DPP(pool->dpps[i])); 1142 pool->dpps[i] = NULL; 1143 } 1144 1145 if (pool->hubps[i] != NULL) { 1146 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1147 pool->hubps[i] = NULL; 1148 } 1149 1150 if (pool->irqs != NULL) 1151 dal_irq_service_destroy(&pool->irqs); 1152 } 1153 1154 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1155 if (pool->engines[i] != NULL) 1156 dce110_engine_destroy(&pool->engines[i]); 1157 if (pool->hw_i2cs[i] != NULL) { 1158 kfree(pool->hw_i2cs[i]); 1159 pool->hw_i2cs[i] = NULL; 1160 } 1161 if (pool->sw_i2cs[i] != NULL) { 1162 kfree(pool->sw_i2cs[i]); 1163 pool->sw_i2cs[i] = NULL; 1164 } 1165 } 1166 1167 for (i = 0; i < pool->res_cap->num_opp; i++) { 1168 if (pool->opps[i] != NULL) 1169 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1170 } 1171 1172 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1173 if (pool->timing_generators[i] != NULL) { 1174 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1175 pool->timing_generators[i] = NULL; 1176 } 1177 } 1178 1179 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1180 if (pool->dwbc[i] != NULL) { 1181 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1182 pool->dwbc[i] = NULL; 1183 } 1184 if (pool->mcif_wb[i] != NULL) { 1185 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1186 pool->mcif_wb[i] = NULL; 1187 } 1188 } 1189 1190 for (i = 0; i < pool->audio_count; i++) { 1191 if (pool->audios[i]) 1192 dce_aud_destroy(&pool->audios[i]); 1193 } 1194 1195 for (i = 0; i < pool->clk_src_count; i++) { 1196 if (pool->clock_sources[i] != NULL) 1197 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1198 } 1199 1200 if (pool->dp_clock_source != NULL) 1201 dcn20_clock_source_destroy(&pool->dp_clock_source); 1202 1203 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1204 if (pool->mpc_lut[i] != NULL) { 1205 dc_3dlut_func_release(pool->mpc_lut[i]); 1206 pool->mpc_lut[i] = NULL; 1207 } 1208 if (pool->mpc_shaper[i] != NULL) { 1209 dc_transfer_func_release(pool->mpc_shaper[i]); 1210 pool->mpc_shaper[i] = NULL; 1211 } 1212 } 1213 1214 for (i = 0; i < pool->pipe_count; i++) { 1215 if (pool->multiple_abms[i] != NULL) 1216 dce_abm_destroy(&pool->multiple_abms[i]); 1217 } 1218 1219 if (pool->psr != NULL) 1220 dmub_psr_destroy(&pool->psr); 1221 1222 if (pool->dccg != NULL) 1223 dcn_dccg_destroy(&pool->dccg); 1224 } 1225 1226 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1227 { 1228 dcn302_resource_destruct(*pool); 1229 kfree(*pool); 1230 *pool = NULL; 1231 } 1232 1233 static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1234 unsigned int *optimal_dcfclk, 1235 unsigned int *optimal_fclk) 1236 { 1237 double bw_from_dram, bw_from_dram1, bw_from_dram2; 1238 1239 bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans * 1240 dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_dram_bw_use_normal_percent / 100); 1241 bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans * 1242 dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100); 1243 1244 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1245 1246 if (optimal_fclk) 1247 *optimal_fclk = bw_from_dram / 1248 (dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1249 1250 if (optimal_dcfclk) 1251 *optimal_dcfclk = bw_from_dram / 1252 (dcn3_02_soc.return_bus_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1253 } 1254 1255 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1256 { 1257 unsigned int i, j; 1258 unsigned int num_states = 0; 1259 1260 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 1261 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 1262 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 1263 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 1264 1265 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; 1266 unsigned int num_dcfclk_sta_targets = 4; 1267 unsigned int num_uclk_states; 1268 1269 1270 if (dc->ctx->dc_bios->vram_info.num_chans) 1271 dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 1272 1273 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 1274 dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 1275 1276 dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1277 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1278 1279 if (bw_params->clk_table.entries[0].memclk_mhz) { 1280 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 1281 1282 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 1283 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 1284 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 1285 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 1286 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 1287 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 1288 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 1289 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 1290 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 1291 } 1292 if (!max_dcfclk_mhz) 1293 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; 1294 if (!max_dispclk_mhz) 1295 max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; 1296 if (!max_dppclk_mhz) 1297 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; 1298 if (!max_phyclk_mhz) 1299 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; 1300 1301 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1302 /* If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array */ 1303 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 1304 num_dcfclk_sta_targets++; 1305 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1306 /* If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates */ 1307 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1308 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 1309 dcfclk_sta_targets[i] = max_dcfclk_mhz; 1310 break; 1311 } 1312 } 1313 /* Update size of array since we "removed" duplicates */ 1314 num_dcfclk_sta_targets = i + 1; 1315 } 1316 1317 num_uclk_states = bw_params->clk_table.num_entries; 1318 1319 /* Calculate optimal dcfclk for each uclk */ 1320 for (i = 0; i < num_uclk_states; i++) { 1321 dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 1322 &optimal_dcfclk_for_uclk[i], NULL); 1323 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 1324 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 1325 } 1326 } 1327 1328 /* Calculate optimal uclk for each dcfclk sta target */ 1329 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1330 for (j = 0; j < num_uclk_states; j++) { 1331 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 1332 optimal_uclk_for_dcfclk_sta_targets[i] = 1333 bw_params->clk_table.entries[j].memclk_mhz * 16; 1334 break; 1335 } 1336 } 1337 } 1338 1339 i = 0; 1340 j = 0; 1341 /* create the final dcfclk and uclk table */ 1342 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 1343 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 1344 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1345 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1346 } else { 1347 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1348 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1349 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1350 } else { 1351 j = num_uclk_states; 1352 } 1353 } 1354 } 1355 1356 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 1357 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1358 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1359 } 1360 1361 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 1362 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1363 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1364 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1365 } 1366 1367 dcn3_02_soc.num_states = num_states; 1368 for (i = 0; i < dcn3_02_soc.num_states; i++) { 1369 dcn3_02_soc.clock_limits[i].state = i; 1370 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 1371 dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 1372 dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 1373 1374 /* Fill all states with max values of all other clocks */ 1375 dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1376 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1377 dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1378 dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz; 1379 /* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */ 1380 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 1381 dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz; 1382 dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[0].socclk_mhz; 1383 dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz; 1384 } 1385 /* re-init DML with updated bb */ 1386 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1387 if (dc->current_state) 1388 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1389 } 1390 } 1391 1392 static struct resource_funcs dcn302_res_pool_funcs = { 1393 .destroy = dcn302_destroy_resource_pool, 1394 .link_enc_create = dcn302_link_encoder_create, 1395 .panel_cntl_create = dcn302_panel_cntl_create, 1396 .validate_bandwidth = dcn30_validate_bandwidth, 1397 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1398 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1399 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1400 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1401 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1402 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1403 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1404 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1405 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1406 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1407 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1408 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1409 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1410 }; 1411 1412 static struct dc_cap_funcs cap_funcs = { 1413 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1414 }; 1415 1416 static const struct bios_registers bios_regs = { 1417 NBIO_SR(BIOS_SCRATCH_3), 1418 NBIO_SR(BIOS_SCRATCH_6) 1419 }; 1420 1421 static const struct dccg_registers dccg_regs = { 1422 DCCG_REG_LIST_DCN3_02() 1423 }; 1424 1425 static const struct dccg_shift dccg_shift = { 1426 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1427 }; 1428 1429 static const struct dccg_mask dccg_mask = { 1430 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1431 }; 1432 1433 #define abm_regs(id)\ 1434 [id] = { ABM_DCN301_REG_LIST(id) } 1435 1436 static const struct dce_abm_registers abm_regs[] = { 1437 abm_regs(0), 1438 abm_regs(1), 1439 abm_regs(2), 1440 abm_regs(3), 1441 abm_regs(4) 1442 }; 1443 1444 static const struct dce_abm_shift abm_shift = { 1445 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1446 }; 1447 1448 static const struct dce_abm_mask abm_mask = { 1449 ABM_MASK_SH_LIST_DCN30(_MASK) 1450 }; 1451 1452 static bool dcn302_resource_construct( 1453 uint8_t num_virtual_links, 1454 struct dc *dc, 1455 struct resource_pool *pool) 1456 { 1457 int i; 1458 struct dc_context *ctx = dc->ctx; 1459 struct irq_service_init_data init_data; 1460 1461 ctx->dc_bios->regs = &bios_regs; 1462 1463 pool->res_cap = &res_cap_dcn302; 1464 1465 pool->funcs = &dcn302_res_pool_funcs; 1466 1467 /************************************************* 1468 * Resource + asic cap harcoding * 1469 *************************************************/ 1470 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1471 pool->pipe_count = pool->res_cap->num_timing_generator; 1472 pool->mpcc_count = pool->res_cap->num_timing_generator; 1473 dc->caps.max_downscale_ratio = 600; 1474 dc->caps.i2c_speed_in_khz = 100; 1475 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1476 dc->caps.max_cursor_size = 256; 1477 dc->caps.min_horizontal_blanking_period = 80; 1478 dc->caps.dmdata_alloc_size = 2048; 1479 dc->caps.mall_size_per_mem_channel = 4; 1480 /* total size = mall per channel * num channels * 1024 * 1024 */ 1481 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1482 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1483 dc->caps.max_slave_planes = 1; 1484 dc->caps.post_blend_color_processing = true; 1485 dc->caps.force_dp_tps4_for_cp2520 = true; 1486 dc->caps.extended_aux_timeout_support = true; 1487 dc->caps.dmcub_support = true; 1488 1489 /* Color pipeline capabilities */ 1490 dc->caps.color.dpp.dcn_arch = 1; 1491 dc->caps.color.dpp.input_lut_shared = 0; 1492 dc->caps.color.dpp.icsc = 1; 1493 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1494 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1495 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1496 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1497 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1498 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1499 dc->caps.color.dpp.post_csc = 1; 1500 dc->caps.color.dpp.gamma_corr = 1; 1501 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1502 1503 dc->caps.color.dpp.hw_3d_lut = 1; 1504 dc->caps.color.dpp.ogam_ram = 1; 1505 // no OGAM ROM on DCN3 1506 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1507 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1508 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1509 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1510 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1511 dc->caps.color.dpp.ocsc = 0; 1512 1513 dc->caps.color.mpc.gamut_remap = 1; 1514 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1515 dc->caps.color.mpc.ogam_ram = 1; 1516 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1517 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1518 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1519 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1520 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1521 dc->caps.color.mpc.ocsc = 1; 1522 1523 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1524 dc->debug = debug_defaults_drv; 1525 else 1526 dc->debug = debug_defaults_diags; 1527 1528 // Init the vm_helper 1529 if (dc->vm_helper) 1530 vm_helper_init(dc->vm_helper, 16); 1531 1532 /************************************************* 1533 * Create resources * 1534 *************************************************/ 1535 1536 /* Clock Sources for Pixel Clock*/ 1537 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1538 dcn302_clock_source_create(ctx, ctx->dc_bios, 1539 CLOCK_SOURCE_COMBO_PHY_PLL0, 1540 &clk_src_regs[0], false); 1541 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1542 dcn302_clock_source_create(ctx, ctx->dc_bios, 1543 CLOCK_SOURCE_COMBO_PHY_PLL1, 1544 &clk_src_regs[1], false); 1545 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1546 dcn302_clock_source_create(ctx, ctx->dc_bios, 1547 CLOCK_SOURCE_COMBO_PHY_PLL2, 1548 &clk_src_regs[2], false); 1549 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1550 dcn302_clock_source_create(ctx, ctx->dc_bios, 1551 CLOCK_SOURCE_COMBO_PHY_PLL3, 1552 &clk_src_regs[3], false); 1553 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1554 dcn302_clock_source_create(ctx, ctx->dc_bios, 1555 CLOCK_SOURCE_COMBO_PHY_PLL4, 1556 &clk_src_regs[4], false); 1557 1558 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1559 1560 /* todo: not reuse phy_pll registers */ 1561 pool->dp_clock_source = 1562 dcn302_clock_source_create(ctx, ctx->dc_bios, 1563 CLOCK_SOURCE_ID_DP_DTO, 1564 &clk_src_regs[0], true); 1565 1566 for (i = 0; i < pool->clk_src_count; i++) { 1567 if (pool->clock_sources[i] == NULL) { 1568 dm_error("DC: failed to create clock sources!\n"); 1569 BREAK_TO_DEBUGGER(); 1570 goto create_fail; 1571 } 1572 } 1573 1574 /* DCCG */ 1575 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1576 if (pool->dccg == NULL) { 1577 dm_error("DC: failed to create dccg!\n"); 1578 BREAK_TO_DEBUGGER(); 1579 goto create_fail; 1580 } 1581 1582 /* PP Lib and SMU interfaces */ 1583 init_soc_bounding_box(dc, pool); 1584 1585 /* DML */ 1586 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1587 1588 /* IRQ */ 1589 init_data.ctx = dc->ctx; 1590 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1591 if (!pool->irqs) 1592 goto create_fail; 1593 1594 /* HUBBUB */ 1595 pool->hubbub = dcn302_hubbub_create(ctx); 1596 if (pool->hubbub == NULL) { 1597 BREAK_TO_DEBUGGER(); 1598 dm_error("DC: failed to create hubbub!\n"); 1599 goto create_fail; 1600 } 1601 1602 /* HUBPs, DPPs, OPPs and TGs */ 1603 for (i = 0; i < pool->pipe_count; i++) { 1604 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1605 if (pool->hubps[i] == NULL) { 1606 BREAK_TO_DEBUGGER(); 1607 dm_error("DC: failed to create hubps!\n"); 1608 goto create_fail; 1609 } 1610 1611 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1612 if (pool->dpps[i] == NULL) { 1613 BREAK_TO_DEBUGGER(); 1614 dm_error("DC: failed to create dpps!\n"); 1615 goto create_fail; 1616 } 1617 } 1618 1619 for (i = 0; i < pool->res_cap->num_opp; i++) { 1620 pool->opps[i] = dcn302_opp_create(ctx, i); 1621 if (pool->opps[i] == NULL) { 1622 BREAK_TO_DEBUGGER(); 1623 dm_error("DC: failed to create output pixel processor!\n"); 1624 goto create_fail; 1625 } 1626 } 1627 1628 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1629 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1630 if (pool->timing_generators[i] == NULL) { 1631 BREAK_TO_DEBUGGER(); 1632 dm_error("DC: failed to create tg!\n"); 1633 goto create_fail; 1634 } 1635 } 1636 pool->timing_generator_count = i; 1637 1638 /* PSR */ 1639 pool->psr = dmub_psr_create(ctx); 1640 if (pool->psr == NULL) { 1641 dm_error("DC: failed to create psr!\n"); 1642 BREAK_TO_DEBUGGER(); 1643 goto create_fail; 1644 } 1645 1646 /* ABMs */ 1647 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1648 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1649 if (pool->multiple_abms[i] == NULL) { 1650 dm_error("DC: failed to create abm for pipe %d!\n", i); 1651 BREAK_TO_DEBUGGER(); 1652 goto create_fail; 1653 } 1654 } 1655 1656 /* MPC and DSC */ 1657 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1658 if (pool->mpc == NULL) { 1659 BREAK_TO_DEBUGGER(); 1660 dm_error("DC: failed to create mpc!\n"); 1661 goto create_fail; 1662 } 1663 1664 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1665 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1666 if (pool->dscs[i] == NULL) { 1667 BREAK_TO_DEBUGGER(); 1668 dm_error("DC: failed to create display stream compressor %d!\n", i); 1669 goto create_fail; 1670 } 1671 } 1672 1673 /* DWB and MMHUBBUB */ 1674 if (!dcn302_dwbc_create(ctx, pool)) { 1675 BREAK_TO_DEBUGGER(); 1676 dm_error("DC: failed to create dwbc!\n"); 1677 goto create_fail; 1678 } 1679 1680 if (!dcn302_mmhubbub_create(ctx, pool)) { 1681 BREAK_TO_DEBUGGER(); 1682 dm_error("DC: failed to create mcif_wb!\n"); 1683 goto create_fail; 1684 } 1685 1686 /* AUX and I2C */ 1687 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1688 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1689 if (pool->engines[i] == NULL) { 1690 BREAK_TO_DEBUGGER(); 1691 dm_error("DC:failed to create aux engine!!\n"); 1692 goto create_fail; 1693 } 1694 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1695 if (pool->hw_i2cs[i] == NULL) { 1696 BREAK_TO_DEBUGGER(); 1697 dm_error("DC:failed to create hw i2c!!\n"); 1698 goto create_fail; 1699 } 1700 pool->sw_i2cs[i] = NULL; 1701 } 1702 1703 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1704 if (!resource_construct(num_virtual_links, dc, pool, 1705 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1706 &res_create_funcs : &res_create_maximus_funcs))) 1707 goto create_fail; 1708 1709 /* HW Sequencer and Plane caps */ 1710 dcn302_hw_sequencer_construct(dc); 1711 1712 dc->caps.max_planes = pool->pipe_count; 1713 1714 for (i = 0; i < dc->caps.max_planes; ++i) 1715 dc->caps.planes[i] = plane_cap; 1716 1717 dc->cap_funcs = cap_funcs; 1718 1719 return true; 1720 1721 create_fail: 1722 1723 dcn302_resource_destruct(pool); 1724 1725 return false; 1726 } 1727 1728 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1729 { 1730 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1731 1732 if (!pool) 1733 return NULL; 1734 1735 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1736 return pool; 1737 1738 BREAK_TO_DEBUGGER(); 1739 kfree(pool); 1740 return NULL; 1741 } 1742