1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dml/dcn30/dcn30_fpu.h" 47 48 #include "dcn10/dcn10_resource.h" 49 50 #include "link.h" 51 #include "dce/dce_abm.h" 52 #include "dce/dce_audio.h" 53 #include "dce/dce_aux.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_hwseq.h" 56 #include "dce/dce_i2c_hw.h" 57 #include "dce/dce_panel_cntl.h" 58 #include "dce/dmub_abm.h" 59 #include "dce/dmub_psr.h" 60 #include "clk_mgr.h" 61 62 #include "hw_sequencer_private.h" 63 #include "reg_helper.h" 64 #include "resource.h" 65 #include "vm_helper.h" 66 67 #include "dml/dcn302/dcn302_fpu.h" 68 69 #include "dimgrey_cavefish_ip_offset.h" 70 #include "dcn/dcn_3_0_2_offset.h" 71 #include "dcn/dcn_3_0_2_sh_mask.h" 72 #include "dpcs/dpcs_3_0_0_offset.h" 73 #include "dpcs/dpcs_3_0_0_sh_mask.h" 74 #include "nbio/nbio_7_4_offset.h" 75 #include "amdgpu_socbb.h" 76 77 #define DC_LOGGER_INIT(logger) 78 79 static const struct dc_debug_options debug_defaults_drv = { 80 .disable_dmcu = true, 81 .force_abm_enable = false, 82 .timing_trace = false, 83 .clock_trace = true, 84 .disable_pplib_clock_request = true, 85 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 86 .force_single_disp_pipe_split = false, 87 .disable_dcc = DCC_ENABLE, 88 .vsr_support = true, 89 .performance_trace = false, 90 .max_downscale_src_width = 7680,/*upto 8K*/ 91 .disable_pplib_wm_range = false, 92 .scl_reset_length10 = true, 93 .sanity_checks = false, 94 .underflow_assert_delay_us = 0xFFFFFFFF, 95 .dwb_fi_phase = -1, // -1 = disable, 96 .dmub_command_table = true, 97 .use_max_lb = true, 98 .exit_idle_opt_for_cursor_updates = true, 99 .enable_legacy_fast_update = false, 100 }; 101 102 static const struct dc_panel_config panel_config_defaults = { 103 .psr = { 104 .disable_psr = false, 105 .disallow_psrsu = false, 106 }, 107 }; 108 109 enum dcn302_clk_src_array_id { 110 DCN302_CLK_SRC_PLL0, 111 DCN302_CLK_SRC_PLL1, 112 DCN302_CLK_SRC_PLL2, 113 DCN302_CLK_SRC_PLL3, 114 DCN302_CLK_SRC_PLL4, 115 DCN302_CLK_SRC_TOTAL 116 }; 117 118 static const struct resource_caps res_cap_dcn302 = { 119 .num_timing_generator = 5, 120 .num_opp = 5, 121 .num_video_plane = 5, 122 .num_audio = 5, 123 .num_stream_encoder = 5, 124 .num_dwb = 1, 125 .num_ddc = 5, 126 .num_vmid = 16, 127 .num_mpc_3dlut = 2, 128 .num_dsc = 5, 129 }; 130 131 static const struct dc_plane_cap plane_cap = { 132 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 133 .per_pixel_alpha = true, 134 .pixel_format_support = { 135 .argb8888 = true, 136 .nv12 = true, 137 .fp16 = true, 138 .p010 = true, 139 .ayuv = false, 140 }, 141 .max_upscale_factor = { 142 .argb8888 = 16000, 143 .nv12 = 16000, 144 .fp16 = 16000 145 }, 146 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 147 .max_downscale_factor = { 148 .argb8888 = 167, 149 .nv12 = 167, 150 .fp16 = 167 151 }, 152 16, 153 16 154 }; 155 156 /* NBIO */ 157 #define NBIO_BASE_INNER(seg) \ 158 NBIO_BASE__INST0_SEG ## seg 159 160 #define NBIO_BASE(seg) \ 161 NBIO_BASE_INNER(seg) 162 163 #define NBIO_SR(reg_name)\ 164 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 165 mm ## reg_name 166 167 /* DCN */ 168 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 169 170 #define BASE(seg) BASE_INNER(seg) 171 172 #define SR(reg_name)\ 173 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 174 175 #define SF(reg_name, field_name, post_fix)\ 176 .field_name = reg_name ## __ ## field_name ## post_fix 177 178 #define SRI(reg_name, block, id)\ 179 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 180 181 #define SRI2(reg_name, block, id)\ 182 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 183 184 #define SRII(reg_name, block, id)\ 185 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 186 mm ## block ## id ## _ ## reg_name 187 188 #define DCCG_SRII(reg_name, block, id)\ 189 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 190 mm ## block ## id ## _ ## reg_name 191 192 #define VUPDATE_SRII(reg_name, block, id)\ 193 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 194 mm ## reg_name ## _ ## block ## id 195 196 #define SRII_DWB(reg_name, temp_name, block, id)\ 197 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 198 mm ## block ## id ## _ ## temp_name 199 200 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 201 .field_name = reg_name ## __ ## field_name ## post_fix 202 203 #define SRII_MPC_RMU(reg_name, block, id)\ 204 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 205 mm ## block ## id ## _ ## reg_name 206 207 static const struct dcn_hubbub_registers hubbub_reg = { 208 HUBBUB_REG_LIST_DCN30(0) 209 }; 210 211 static const struct dcn_hubbub_shift hubbub_shift = { 212 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 213 }; 214 215 static const struct dcn_hubbub_mask hubbub_mask = { 216 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 217 }; 218 219 #define vmid_regs(id)\ 220 [id] = { DCN20_VMID_REG_LIST(id) } 221 222 static const struct dcn_vmid_registers vmid_regs[] = { 223 vmid_regs(0), 224 vmid_regs(1), 225 vmid_regs(2), 226 vmid_regs(3), 227 vmid_regs(4), 228 vmid_regs(5), 229 vmid_regs(6), 230 vmid_regs(7), 231 vmid_regs(8), 232 vmid_regs(9), 233 vmid_regs(10), 234 vmid_regs(11), 235 vmid_regs(12), 236 vmid_regs(13), 237 vmid_regs(14), 238 vmid_regs(15) 239 }; 240 241 static const struct dcn20_vmid_shift vmid_shifts = { 242 DCN20_VMID_MASK_SH_LIST(__SHIFT) 243 }; 244 245 static const struct dcn20_vmid_mask vmid_masks = { 246 DCN20_VMID_MASK_SH_LIST(_MASK) 247 }; 248 249 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 250 { 251 int i; 252 253 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 254 255 if (!hubbub3) 256 return NULL; 257 258 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 259 260 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 261 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 262 263 vmid->ctx = ctx; 264 265 vmid->regs = &vmid_regs[i]; 266 vmid->shifts = &vmid_shifts; 267 vmid->masks = &vmid_masks; 268 } 269 270 return &hubbub3->base; 271 } 272 273 #define vpg_regs(id)\ 274 [id] = { VPG_DCN3_REG_LIST(id) } 275 276 static const struct dcn30_vpg_registers vpg_regs[] = { 277 vpg_regs(0), 278 vpg_regs(1), 279 vpg_regs(2), 280 vpg_regs(3), 281 vpg_regs(4), 282 vpg_regs(5) 283 }; 284 285 static const struct dcn30_vpg_shift vpg_shift = { 286 DCN3_VPG_MASK_SH_LIST(__SHIFT) 287 }; 288 289 static const struct dcn30_vpg_mask vpg_mask = { 290 DCN3_VPG_MASK_SH_LIST(_MASK) 291 }; 292 293 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 294 { 295 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 296 297 if (!vpg3) 298 return NULL; 299 300 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 301 302 return &vpg3->base; 303 } 304 305 #define afmt_regs(id)\ 306 [id] = { AFMT_DCN3_REG_LIST(id) } 307 308 static const struct dcn30_afmt_registers afmt_regs[] = { 309 afmt_regs(0), 310 afmt_regs(1), 311 afmt_regs(2), 312 afmt_regs(3), 313 afmt_regs(4), 314 afmt_regs(5) 315 }; 316 317 static const struct dcn30_afmt_shift afmt_shift = { 318 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 319 }; 320 321 static const struct dcn30_afmt_mask afmt_mask = { 322 DCN3_AFMT_MASK_SH_LIST(_MASK) 323 }; 324 325 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 326 { 327 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 328 329 if (!afmt3) 330 return NULL; 331 332 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 333 334 return &afmt3->base; 335 } 336 337 #define audio_regs(id)\ 338 [id] = { AUD_COMMON_REG_LIST(id) } 339 340 static const struct dce_audio_registers audio_regs[] = { 341 audio_regs(0), 342 audio_regs(1), 343 audio_regs(2), 344 audio_regs(3), 345 audio_regs(4), 346 audio_regs(5), 347 audio_regs(6) 348 }; 349 350 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 351 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 352 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 353 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 354 355 static const struct dce_audio_shift audio_shift = { 356 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 357 }; 358 359 static const struct dce_audio_mask audio_mask = { 360 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 361 }; 362 363 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 364 { 365 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 366 } 367 368 #define stream_enc_regs(id)\ 369 [id] = { SE_DCN3_REG_LIST(id) } 370 371 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 372 stream_enc_regs(0), 373 stream_enc_regs(1), 374 stream_enc_regs(2), 375 stream_enc_regs(3), 376 stream_enc_regs(4) 377 }; 378 379 static const struct dcn10_stream_encoder_shift se_shift = { 380 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 381 }; 382 383 static const struct dcn10_stream_encoder_mask se_mask = { 384 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 385 }; 386 387 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 388 { 389 struct dcn10_stream_encoder *enc1; 390 struct vpg *vpg; 391 struct afmt *afmt; 392 int vpg_inst; 393 int afmt_inst; 394 395 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 396 if (eng_id <= ENGINE_ID_DIGE) { 397 vpg_inst = eng_id; 398 afmt_inst = eng_id; 399 } else 400 return NULL; 401 402 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 403 vpg = dcn302_vpg_create(ctx, vpg_inst); 404 afmt = dcn302_afmt_create(ctx, afmt_inst); 405 406 if (!enc1 || !vpg || !afmt) { 407 kfree(enc1); 408 kfree(vpg); 409 kfree(afmt); 410 return NULL; 411 } 412 413 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 414 &se_shift, &se_mask); 415 416 return &enc1->base; 417 } 418 419 #define clk_src_regs(index, pllid)\ 420 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 421 422 static const struct dce110_clk_src_regs clk_src_regs[] = { 423 clk_src_regs(0, A), 424 clk_src_regs(1, B), 425 clk_src_regs(2, C), 426 clk_src_regs(3, D), 427 clk_src_regs(4, E) 428 }; 429 430 static const struct dce110_clk_src_shift cs_shift = { 431 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 432 }; 433 434 static const struct dce110_clk_src_mask cs_mask = { 435 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 436 }; 437 438 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 439 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 440 { 441 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 442 443 if (!clk_src) 444 return NULL; 445 446 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 447 clk_src->base.dp_clk_src = dp_clk_src; 448 return &clk_src->base; 449 } 450 451 kfree(clk_src); 452 BREAK_TO_DEBUGGER(); 453 return NULL; 454 } 455 456 static const struct dce_hwseq_registers hwseq_reg = { 457 HWSEQ_DCN302_REG_LIST() 458 }; 459 460 static const struct dce_hwseq_shift hwseq_shift = { 461 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 462 }; 463 464 static const struct dce_hwseq_mask hwseq_mask = { 465 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 466 }; 467 468 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 469 { 470 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 471 472 if (hws) { 473 hws->ctx = ctx; 474 hws->regs = &hwseq_reg; 475 hws->shifts = &hwseq_shift; 476 hws->masks = &hwseq_mask; 477 } 478 return hws; 479 } 480 481 #define hubp_regs(id)\ 482 [id] = { HUBP_REG_LIST_DCN30(id) } 483 484 static const struct dcn_hubp2_registers hubp_regs[] = { 485 hubp_regs(0), 486 hubp_regs(1), 487 hubp_regs(2), 488 hubp_regs(3), 489 hubp_regs(4) 490 }; 491 492 static const struct dcn_hubp2_shift hubp_shift = { 493 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 494 }; 495 496 static const struct dcn_hubp2_mask hubp_mask = { 497 HUBP_MASK_SH_LIST_DCN30(_MASK) 498 }; 499 500 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 501 { 502 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 503 504 if (!hubp2) 505 return NULL; 506 507 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 508 return &hubp2->base; 509 510 BREAK_TO_DEBUGGER(); 511 kfree(hubp2); 512 return NULL; 513 } 514 515 #define dpp_regs(id)\ 516 [id] = { DPP_REG_LIST_DCN30(id) } 517 518 static const struct dcn3_dpp_registers dpp_regs[] = { 519 dpp_regs(0), 520 dpp_regs(1), 521 dpp_regs(2), 522 dpp_regs(3), 523 dpp_regs(4) 524 }; 525 526 static const struct dcn3_dpp_shift tf_shift = { 527 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 528 }; 529 530 static const struct dcn3_dpp_mask tf_mask = { 531 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 532 }; 533 534 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 535 { 536 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 537 538 if (!dpp) 539 return NULL; 540 541 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 542 return &dpp->base; 543 544 BREAK_TO_DEBUGGER(); 545 kfree(dpp); 546 return NULL; 547 } 548 549 #define opp_regs(id)\ 550 [id] = { OPP_REG_LIST_DCN30(id) } 551 552 static const struct dcn20_opp_registers opp_regs[] = { 553 opp_regs(0), 554 opp_regs(1), 555 opp_regs(2), 556 opp_regs(3), 557 opp_regs(4) 558 }; 559 560 static const struct dcn20_opp_shift opp_shift = { 561 OPP_MASK_SH_LIST_DCN20(__SHIFT) 562 }; 563 564 static const struct dcn20_opp_mask opp_mask = { 565 OPP_MASK_SH_LIST_DCN20(_MASK) 566 }; 567 568 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 569 { 570 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 571 572 if (!opp) { 573 BREAK_TO_DEBUGGER(); 574 return NULL; 575 } 576 577 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 578 return &opp->base; 579 } 580 581 #define optc_regs(id)\ 582 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 583 584 static const struct dcn_optc_registers optc_regs[] = { 585 optc_regs(0), 586 optc_regs(1), 587 optc_regs(2), 588 optc_regs(3), 589 optc_regs(4) 590 }; 591 592 static const struct dcn_optc_shift optc_shift = { 593 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 594 }; 595 596 static const struct dcn_optc_mask optc_mask = { 597 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 598 }; 599 600 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 601 { 602 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 603 604 if (!tgn10) 605 return NULL; 606 607 tgn10->base.inst = instance; 608 tgn10->base.ctx = ctx; 609 610 tgn10->tg_regs = &optc_regs[instance]; 611 tgn10->tg_shift = &optc_shift; 612 tgn10->tg_mask = &optc_mask; 613 614 dcn30_timing_generator_init(tgn10); 615 616 return &tgn10->base; 617 } 618 619 static const struct dcn30_mpc_registers mpc_regs = { 620 MPC_REG_LIST_DCN3_0(0), 621 MPC_REG_LIST_DCN3_0(1), 622 MPC_REG_LIST_DCN3_0(2), 623 MPC_REG_LIST_DCN3_0(3), 624 MPC_REG_LIST_DCN3_0(4), 625 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 626 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 627 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 628 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 629 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 630 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 631 MPC_RMU_REG_LIST_DCN3AG(0), 632 MPC_RMU_REG_LIST_DCN3AG(1), 633 MPC_RMU_REG_LIST_DCN3AG(2), 634 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 635 }; 636 637 static const struct dcn30_mpc_shift mpc_shift = { 638 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 639 }; 640 641 static const struct dcn30_mpc_mask mpc_mask = { 642 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 643 }; 644 645 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 646 { 647 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 648 649 if (!mpc30) 650 return NULL; 651 652 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 653 654 return &mpc30->base; 655 } 656 657 #define dsc_regsDCN20(id)\ 658 [id] = { DSC_REG_LIST_DCN20(id) } 659 660 static const struct dcn20_dsc_registers dsc_regs[] = { 661 dsc_regsDCN20(0), 662 dsc_regsDCN20(1), 663 dsc_regsDCN20(2), 664 dsc_regsDCN20(3), 665 dsc_regsDCN20(4) 666 }; 667 668 static const struct dcn20_dsc_shift dsc_shift = { 669 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 670 }; 671 672 static const struct dcn20_dsc_mask dsc_mask = { 673 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 674 }; 675 676 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 677 { 678 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 679 680 if (!dsc) { 681 BREAK_TO_DEBUGGER(); 682 return NULL; 683 } 684 685 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 686 return &dsc->base; 687 } 688 689 #define dwbc_regs_dcn3(id)\ 690 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 691 692 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 693 dwbc_regs_dcn3(0) 694 }; 695 696 static const struct dcn30_dwbc_shift dwbc30_shift = { 697 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 698 }; 699 700 static const struct dcn30_dwbc_mask dwbc30_mask = { 701 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 702 }; 703 704 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 705 { 706 int i; 707 uint32_t pipe_count = pool->res_cap->num_dwb; 708 709 for (i = 0; i < pipe_count; i++) { 710 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 711 712 if (!dwbc30) { 713 dm_error("DC: failed to create dwbc30!\n"); 714 return false; 715 } 716 717 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 718 719 pool->dwbc[i] = &dwbc30->base; 720 } 721 return true; 722 } 723 724 #define mcif_wb_regs_dcn3(id)\ 725 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 726 727 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 728 mcif_wb_regs_dcn3(0) 729 }; 730 731 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 732 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 733 }; 734 735 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 736 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 737 }; 738 739 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 740 { 741 int i; 742 uint32_t pipe_count = pool->res_cap->num_dwb; 743 744 for (i = 0; i < pipe_count; i++) { 745 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 746 747 if (!mcif_wb30) { 748 dm_error("DC: failed to create mcif_wb30!\n"); 749 return false; 750 } 751 752 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 753 754 pool->mcif_wb[i] = &mcif_wb30->base; 755 } 756 return true; 757 } 758 759 #define aux_engine_regs(id)\ 760 [id] = {\ 761 AUX_COMMON_REG_LIST0(id), \ 762 .AUXN_IMPCAL = 0, \ 763 .AUXP_IMPCAL = 0, \ 764 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 765 } 766 767 static const struct dce110_aux_registers aux_engine_regs[] = { 768 aux_engine_regs(0), 769 aux_engine_regs(1), 770 aux_engine_regs(2), 771 aux_engine_regs(3), 772 aux_engine_regs(4) 773 }; 774 775 static const struct dce110_aux_registers_shift aux_shift = { 776 DCN_AUX_MASK_SH_LIST(__SHIFT) 777 }; 778 779 static const struct dce110_aux_registers_mask aux_mask = { 780 DCN_AUX_MASK_SH_LIST(_MASK) 781 }; 782 783 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 784 { 785 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 786 787 if (!aux_engine) 788 return NULL; 789 790 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 791 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 792 793 return &aux_engine->base; 794 } 795 796 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 797 798 static const struct dce_i2c_registers i2c_hw_regs[] = { 799 i2c_inst_regs(1), 800 i2c_inst_regs(2), 801 i2c_inst_regs(3), 802 i2c_inst_regs(4), 803 i2c_inst_regs(5) 804 }; 805 806 static const struct dce_i2c_shift i2c_shifts = { 807 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 808 }; 809 810 static const struct dce_i2c_mask i2c_masks = { 811 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 812 }; 813 814 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 815 { 816 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 817 818 if (!dce_i2c_hw) 819 return NULL; 820 821 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 822 823 return dce_i2c_hw; 824 } 825 826 static const struct encoder_feature_support link_enc_feature = { 827 .max_hdmi_deep_color = COLOR_DEPTH_121212, 828 .max_hdmi_pixel_clock = 600000, 829 .hdmi_ycbcr420_supported = true, 830 .dp_ycbcr420_supported = true, 831 .fec_supported = true, 832 .flags.bits.IS_HBR2_CAPABLE = true, 833 .flags.bits.IS_HBR3_CAPABLE = true, 834 .flags.bits.IS_TPS3_CAPABLE = true, 835 .flags.bits.IS_TPS4_CAPABLE = true 836 }; 837 838 #define link_regs(id, phyid)\ 839 [id] = {\ 840 LE_DCN3_REG_LIST(id), \ 841 UNIPHY_DCN2_REG_LIST(phyid), \ 842 DPCS_DCN2_REG_LIST(id), \ 843 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 844 } 845 846 static const struct dcn10_link_enc_registers link_enc_regs[] = { 847 link_regs(0, A), 848 link_regs(1, B), 849 link_regs(2, C), 850 link_regs(3, D), 851 link_regs(4, E) 852 }; 853 854 static const struct dcn10_link_enc_shift le_shift = { 855 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 856 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 857 }; 858 859 static const struct dcn10_link_enc_mask le_mask = { 860 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 861 DPCS_DCN2_MASK_SH_LIST(_MASK) 862 }; 863 864 #define aux_regs(id)\ 865 [id] = { DCN2_AUX_REG_LIST(id) } 866 867 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 868 aux_regs(0), 869 aux_regs(1), 870 aux_regs(2), 871 aux_regs(3), 872 aux_regs(4) 873 }; 874 875 #define hpd_regs(id)\ 876 [id] = { HPD_REG_LIST(id) } 877 878 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 879 hpd_regs(0), 880 hpd_regs(1), 881 hpd_regs(2), 882 hpd_regs(3), 883 hpd_regs(4) 884 }; 885 886 static struct link_encoder *dcn302_link_encoder_create( 887 struct dc_context *ctx, 888 const struct encoder_init_data *enc_init_data) 889 { 890 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 891 892 if (!enc20) 893 return NULL; 894 895 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 896 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 897 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 898 899 return &enc20->enc10.base; 900 } 901 902 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 903 { DCN_PANEL_CNTL_REG_LIST() } 904 }; 905 906 static const struct dce_panel_cntl_shift panel_cntl_shift = { 907 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 908 }; 909 910 static const struct dce_panel_cntl_mask panel_cntl_mask = { 911 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 912 }; 913 914 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 915 { 916 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 917 918 if (!panel_cntl) 919 return NULL; 920 921 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 922 &panel_cntl_shift, &panel_cntl_mask); 923 924 return &panel_cntl->base; 925 } 926 927 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 928 { 929 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 930 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 931 } 932 933 static const struct resource_create_funcs res_create_funcs = { 934 .read_dce_straps = read_dce_straps, 935 .create_audio = dcn302_create_audio, 936 .create_stream_encoder = dcn302_stream_encoder_create, 937 .create_hwseq = dcn302_hwseq_create, 938 }; 939 940 static bool is_soc_bounding_box_valid(struct dc *dc) 941 { 942 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 943 944 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 945 return true; 946 947 return false; 948 } 949 950 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 951 { 952 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 953 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 954 955 DC_LOGGER_INIT(dc->ctx->logger); 956 957 if (!is_soc_bounding_box_valid(dc)) { 958 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 959 return false; 960 } 961 962 loaded_ip->max_num_otg = pool->pipe_count; 963 loaded_ip->max_num_dpp = pool->pipe_count; 964 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 965 DC_FP_START(); 966 dcn20_patch_bounding_box(dc, loaded_bb); 967 DC_FP_END(); 968 969 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 970 struct bp_soc_bb_info bb_info = { 0 }; 971 972 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 973 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 974 975 DC_FP_START(); 976 dcn302_fpu_init_soc_bounding_box(bb_info); 977 DC_FP_END(); 978 } 979 } 980 981 return true; 982 } 983 984 static void dcn302_resource_destruct(struct resource_pool *pool) 985 { 986 unsigned int i; 987 988 for (i = 0; i < pool->stream_enc_count; i++) { 989 if (pool->stream_enc[i] != NULL) { 990 if (pool->stream_enc[i]->vpg != NULL) { 991 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 992 pool->stream_enc[i]->vpg = NULL; 993 } 994 if (pool->stream_enc[i]->afmt != NULL) { 995 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 996 pool->stream_enc[i]->afmt = NULL; 997 } 998 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 999 pool->stream_enc[i] = NULL; 1000 } 1001 } 1002 1003 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1004 if (pool->dscs[i] != NULL) 1005 dcn20_dsc_destroy(&pool->dscs[i]); 1006 } 1007 1008 if (pool->mpc != NULL) { 1009 kfree(TO_DCN20_MPC(pool->mpc)); 1010 pool->mpc = NULL; 1011 } 1012 1013 if (pool->hubbub != NULL) { 1014 kfree(pool->hubbub); 1015 pool->hubbub = NULL; 1016 } 1017 1018 for (i = 0; i < pool->pipe_count; i++) { 1019 if (pool->dpps[i] != NULL) { 1020 kfree(TO_DCN20_DPP(pool->dpps[i])); 1021 pool->dpps[i] = NULL; 1022 } 1023 1024 if (pool->hubps[i] != NULL) { 1025 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1026 pool->hubps[i] = NULL; 1027 } 1028 1029 if (pool->irqs != NULL) 1030 dal_irq_service_destroy(&pool->irqs); 1031 } 1032 1033 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1034 if (pool->engines[i] != NULL) 1035 dce110_engine_destroy(&pool->engines[i]); 1036 if (pool->hw_i2cs[i] != NULL) { 1037 kfree(pool->hw_i2cs[i]); 1038 pool->hw_i2cs[i] = NULL; 1039 } 1040 if (pool->sw_i2cs[i] != NULL) { 1041 kfree(pool->sw_i2cs[i]); 1042 pool->sw_i2cs[i] = NULL; 1043 } 1044 } 1045 1046 for (i = 0; i < pool->res_cap->num_opp; i++) { 1047 if (pool->opps[i] != NULL) 1048 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1049 } 1050 1051 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1052 if (pool->timing_generators[i] != NULL) { 1053 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1054 pool->timing_generators[i] = NULL; 1055 } 1056 } 1057 1058 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1059 if (pool->dwbc[i] != NULL) { 1060 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1061 pool->dwbc[i] = NULL; 1062 } 1063 if (pool->mcif_wb[i] != NULL) { 1064 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1065 pool->mcif_wb[i] = NULL; 1066 } 1067 } 1068 1069 for (i = 0; i < pool->audio_count; i++) { 1070 if (pool->audios[i]) 1071 dce_aud_destroy(&pool->audios[i]); 1072 } 1073 1074 for (i = 0; i < pool->clk_src_count; i++) { 1075 if (pool->clock_sources[i] != NULL) 1076 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1077 } 1078 1079 if (pool->dp_clock_source != NULL) 1080 dcn20_clock_source_destroy(&pool->dp_clock_source); 1081 1082 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1083 if (pool->mpc_lut[i] != NULL) { 1084 dc_3dlut_func_release(pool->mpc_lut[i]); 1085 pool->mpc_lut[i] = NULL; 1086 } 1087 if (pool->mpc_shaper[i] != NULL) { 1088 dc_transfer_func_release(pool->mpc_shaper[i]); 1089 pool->mpc_shaper[i] = NULL; 1090 } 1091 } 1092 1093 for (i = 0; i < pool->pipe_count; i++) { 1094 if (pool->multiple_abms[i] != NULL) 1095 dce_abm_destroy(&pool->multiple_abms[i]); 1096 } 1097 1098 if (pool->psr != NULL) 1099 dmub_psr_destroy(&pool->psr); 1100 1101 if (pool->dccg != NULL) 1102 dcn_dccg_destroy(&pool->dccg); 1103 1104 if (pool->oem_device != NULL) { 1105 struct dc *dc = pool->oem_device->ctx->dc; 1106 1107 dc->link_srv->destroy_ddc_service(&pool->oem_device); 1108 } 1109 } 1110 1111 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1112 { 1113 dcn302_resource_destruct(*pool); 1114 kfree(*pool); 1115 *pool = NULL; 1116 } 1117 1118 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1119 { 1120 DC_FP_START(); 1121 dcn302_fpu_update_bw_bounding_box(dc, bw_params); 1122 DC_FP_END(); 1123 } 1124 1125 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config) 1126 { 1127 *panel_config = panel_config_defaults; 1128 } 1129 1130 static struct resource_funcs dcn302_res_pool_funcs = { 1131 .destroy = dcn302_destroy_resource_pool, 1132 .link_enc_create = dcn302_link_encoder_create, 1133 .panel_cntl_create = dcn302_panel_cntl_create, 1134 .validate_bandwidth = dcn30_validate_bandwidth, 1135 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1136 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1137 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1138 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1139 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1140 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1141 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1142 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1143 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1144 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1145 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1146 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1147 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1148 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1149 .get_panel_config_defaults = dcn302_get_panel_config_defaults, 1150 }; 1151 1152 static struct dc_cap_funcs cap_funcs = { 1153 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1154 }; 1155 1156 static const struct bios_registers bios_regs = { 1157 NBIO_SR(BIOS_SCRATCH_3), 1158 NBIO_SR(BIOS_SCRATCH_6) 1159 }; 1160 1161 static const struct dccg_registers dccg_regs = { 1162 DCCG_REG_LIST_DCN3_02() 1163 }; 1164 1165 static const struct dccg_shift dccg_shift = { 1166 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1167 }; 1168 1169 static const struct dccg_mask dccg_mask = { 1170 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1171 }; 1172 1173 #define abm_regs(id)\ 1174 [id] = { ABM_DCN302_REG_LIST(id) } 1175 1176 static const struct dce_abm_registers abm_regs[] = { 1177 abm_regs(0), 1178 abm_regs(1), 1179 abm_regs(2), 1180 abm_regs(3), 1181 abm_regs(4) 1182 }; 1183 1184 static const struct dce_abm_shift abm_shift = { 1185 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1186 }; 1187 1188 static const struct dce_abm_mask abm_mask = { 1189 ABM_MASK_SH_LIST_DCN30(_MASK) 1190 }; 1191 1192 static bool dcn302_resource_construct( 1193 uint8_t num_virtual_links, 1194 struct dc *dc, 1195 struct resource_pool *pool) 1196 { 1197 int i; 1198 struct dc_context *ctx = dc->ctx; 1199 struct irq_service_init_data init_data; 1200 struct ddc_service_init_data ddc_init_data = {0}; 1201 1202 ctx->dc_bios->regs = &bios_regs; 1203 1204 pool->res_cap = &res_cap_dcn302; 1205 1206 pool->funcs = &dcn302_res_pool_funcs; 1207 1208 /************************************************* 1209 * Resource + asic cap harcoding * 1210 *************************************************/ 1211 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1212 pool->pipe_count = pool->res_cap->num_timing_generator; 1213 pool->mpcc_count = pool->res_cap->num_timing_generator; 1214 dc->caps.max_downscale_ratio = 600; 1215 dc->caps.i2c_speed_in_khz = 100; 1216 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1217 dc->caps.max_cursor_size = 256; 1218 dc->caps.min_horizontal_blanking_period = 80; 1219 dc->caps.dmdata_alloc_size = 2048; 1220 dc->caps.mall_size_per_mem_channel = 4; 1221 /* total size = mall per channel * num channels * 1024 * 1024 */ 1222 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1223 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1224 dc->caps.max_slave_planes = 2; 1225 dc->caps.max_slave_yuv_planes = 2; 1226 dc->caps.max_slave_rgb_planes = 2; 1227 dc->caps.post_blend_color_processing = true; 1228 dc->caps.force_dp_tps4_for_cp2520 = true; 1229 dc->caps.extended_aux_timeout_support = true; 1230 dc->caps.dmcub_support = true; 1231 dc->caps.max_v_total = (1 << 15) - 1; 1232 1233 /* Color pipeline capabilities */ 1234 dc->caps.color.dpp.dcn_arch = 1; 1235 dc->caps.color.dpp.input_lut_shared = 0; 1236 dc->caps.color.dpp.icsc = 1; 1237 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1238 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1239 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1240 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1241 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1242 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1243 dc->caps.color.dpp.post_csc = 1; 1244 dc->caps.color.dpp.gamma_corr = 1; 1245 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1246 1247 dc->caps.color.dpp.hw_3d_lut = 1; 1248 dc->caps.color.dpp.ogam_ram = 1; 1249 // no OGAM ROM on DCN3 1250 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1251 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1252 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1253 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1254 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1255 dc->caps.color.dpp.ocsc = 0; 1256 1257 dc->caps.color.mpc.gamut_remap = 1; 1258 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1259 dc->caps.color.mpc.ogam_ram = 1; 1260 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1261 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1262 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1263 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1264 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1265 dc->caps.color.mpc.ocsc = 1; 1266 1267 dc->caps.dp_hdmi21_pcon_support = true; 1268 1269 /* read VBIOS LTTPR caps */ 1270 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1271 enum bp_result bp_query_result; 1272 uint8_t is_vbios_lttpr_enable = 0; 1273 1274 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1275 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1276 } 1277 1278 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1279 enum bp_result bp_query_result; 1280 uint8_t is_vbios_interop_enabled = 0; 1281 1282 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 1283 &is_vbios_interop_enabled); 1284 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1285 } 1286 1287 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1288 dc->debug = debug_defaults_drv; 1289 1290 // Init the vm_helper 1291 if (dc->vm_helper) 1292 vm_helper_init(dc->vm_helper, 16); 1293 1294 /************************************************* 1295 * Create resources * 1296 *************************************************/ 1297 1298 /* Clock Sources for Pixel Clock*/ 1299 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1300 dcn302_clock_source_create(ctx, ctx->dc_bios, 1301 CLOCK_SOURCE_COMBO_PHY_PLL0, 1302 &clk_src_regs[0], false); 1303 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1304 dcn302_clock_source_create(ctx, ctx->dc_bios, 1305 CLOCK_SOURCE_COMBO_PHY_PLL1, 1306 &clk_src_regs[1], false); 1307 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1308 dcn302_clock_source_create(ctx, ctx->dc_bios, 1309 CLOCK_SOURCE_COMBO_PHY_PLL2, 1310 &clk_src_regs[2], false); 1311 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1312 dcn302_clock_source_create(ctx, ctx->dc_bios, 1313 CLOCK_SOURCE_COMBO_PHY_PLL3, 1314 &clk_src_regs[3], false); 1315 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1316 dcn302_clock_source_create(ctx, ctx->dc_bios, 1317 CLOCK_SOURCE_COMBO_PHY_PLL4, 1318 &clk_src_regs[4], false); 1319 1320 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1321 1322 /* todo: not reuse phy_pll registers */ 1323 pool->dp_clock_source = 1324 dcn302_clock_source_create(ctx, ctx->dc_bios, 1325 CLOCK_SOURCE_ID_DP_DTO, 1326 &clk_src_regs[0], true); 1327 1328 for (i = 0; i < pool->clk_src_count; i++) { 1329 if (pool->clock_sources[i] == NULL) { 1330 dm_error("DC: failed to create clock sources!\n"); 1331 BREAK_TO_DEBUGGER(); 1332 goto create_fail; 1333 } 1334 } 1335 1336 /* DCCG */ 1337 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1338 if (pool->dccg == NULL) { 1339 dm_error("DC: failed to create dccg!\n"); 1340 BREAK_TO_DEBUGGER(); 1341 goto create_fail; 1342 } 1343 1344 /* PP Lib and SMU interfaces */ 1345 init_soc_bounding_box(dc, pool); 1346 1347 /* DML */ 1348 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1349 1350 /* IRQ */ 1351 init_data.ctx = dc->ctx; 1352 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1353 if (!pool->irqs) 1354 goto create_fail; 1355 1356 /* HUBBUB */ 1357 pool->hubbub = dcn302_hubbub_create(ctx); 1358 if (pool->hubbub == NULL) { 1359 BREAK_TO_DEBUGGER(); 1360 dm_error("DC: failed to create hubbub!\n"); 1361 goto create_fail; 1362 } 1363 1364 /* HUBPs, DPPs, OPPs and TGs */ 1365 for (i = 0; i < pool->pipe_count; i++) { 1366 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1367 if (pool->hubps[i] == NULL) { 1368 BREAK_TO_DEBUGGER(); 1369 dm_error("DC: failed to create hubps!\n"); 1370 goto create_fail; 1371 } 1372 1373 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1374 if (pool->dpps[i] == NULL) { 1375 BREAK_TO_DEBUGGER(); 1376 dm_error("DC: failed to create dpps!\n"); 1377 goto create_fail; 1378 } 1379 } 1380 1381 for (i = 0; i < pool->res_cap->num_opp; i++) { 1382 pool->opps[i] = dcn302_opp_create(ctx, i); 1383 if (pool->opps[i] == NULL) { 1384 BREAK_TO_DEBUGGER(); 1385 dm_error("DC: failed to create output pixel processor!\n"); 1386 goto create_fail; 1387 } 1388 } 1389 1390 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1391 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1392 if (pool->timing_generators[i] == NULL) { 1393 BREAK_TO_DEBUGGER(); 1394 dm_error("DC: failed to create tg!\n"); 1395 goto create_fail; 1396 } 1397 } 1398 pool->timing_generator_count = i; 1399 1400 /* PSR */ 1401 pool->psr = dmub_psr_create(ctx); 1402 if (pool->psr == NULL) { 1403 dm_error("DC: failed to create psr!\n"); 1404 BREAK_TO_DEBUGGER(); 1405 goto create_fail; 1406 } 1407 1408 /* ABMs */ 1409 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1410 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1411 if (pool->multiple_abms[i] == NULL) { 1412 dm_error("DC: failed to create abm for pipe %d!\n", i); 1413 BREAK_TO_DEBUGGER(); 1414 goto create_fail; 1415 } 1416 } 1417 1418 /* MPC and DSC */ 1419 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1420 if (pool->mpc == NULL) { 1421 BREAK_TO_DEBUGGER(); 1422 dm_error("DC: failed to create mpc!\n"); 1423 goto create_fail; 1424 } 1425 1426 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1427 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1428 if (pool->dscs[i] == NULL) { 1429 BREAK_TO_DEBUGGER(); 1430 dm_error("DC: failed to create display stream compressor %d!\n", i); 1431 goto create_fail; 1432 } 1433 } 1434 1435 /* DWB and MMHUBBUB */ 1436 if (!dcn302_dwbc_create(ctx, pool)) { 1437 BREAK_TO_DEBUGGER(); 1438 dm_error("DC: failed to create dwbc!\n"); 1439 goto create_fail; 1440 } 1441 1442 if (!dcn302_mmhubbub_create(ctx, pool)) { 1443 BREAK_TO_DEBUGGER(); 1444 dm_error("DC: failed to create mcif_wb!\n"); 1445 goto create_fail; 1446 } 1447 1448 /* AUX and I2C */ 1449 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1450 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1451 if (pool->engines[i] == NULL) { 1452 BREAK_TO_DEBUGGER(); 1453 dm_error("DC:failed to create aux engine!!\n"); 1454 goto create_fail; 1455 } 1456 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1457 if (pool->hw_i2cs[i] == NULL) { 1458 BREAK_TO_DEBUGGER(); 1459 dm_error("DC:failed to create hw i2c!!\n"); 1460 goto create_fail; 1461 } 1462 pool->sw_i2cs[i] = NULL; 1463 } 1464 1465 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1466 if (!resource_construct(num_virtual_links, dc, pool, 1467 &res_create_funcs)) 1468 goto create_fail; 1469 1470 /* HW Sequencer and Plane caps */ 1471 dcn302_hw_sequencer_construct(dc); 1472 1473 dc->caps.max_planes = pool->pipe_count; 1474 1475 for (i = 0; i < dc->caps.max_planes; ++i) 1476 dc->caps.planes[i] = plane_cap; 1477 1478 dc->cap_funcs = cap_funcs; 1479 1480 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1481 ddc_init_data.ctx = dc->ctx; 1482 ddc_init_data.link = NULL; 1483 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1484 ddc_init_data.id.enum_id = 0; 1485 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1486 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 1487 } else { 1488 pool->oem_device = NULL; 1489 } 1490 1491 return true; 1492 1493 create_fail: 1494 1495 dcn302_resource_destruct(pool); 1496 1497 return false; 1498 } 1499 1500 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1501 { 1502 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1503 1504 if (!pool) 1505 return NULL; 1506 1507 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1508 return pool; 1509 1510 BREAK_TO_DEBUGGER(); 1511 kfree(pool); 1512 return NULL; 1513 } 1514