1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dml/dcn30/dcn30_fpu.h" 47 48 #include "dcn10/dcn10_resource.h" 49 50 #include "link.h" 51 #include "dce/dce_abm.h" 52 #include "dce/dce_audio.h" 53 #include "dce/dce_aux.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_hwseq.h" 56 #include "dce/dce_i2c_hw.h" 57 #include "dce/dce_panel_cntl.h" 58 #include "dce/dmub_abm.h" 59 #include "dce/dmub_psr.h" 60 #include "clk_mgr.h" 61 62 #include "hw_sequencer_private.h" 63 #include "reg_helper.h" 64 #include "resource.h" 65 #include "vm_helper.h" 66 67 #include "dml/dcn302/dcn302_fpu.h" 68 69 #include "dimgrey_cavefish_ip_offset.h" 70 #include "dcn/dcn_3_0_2_offset.h" 71 #include "dcn/dcn_3_0_2_sh_mask.h" 72 #include "dpcs/dpcs_3_0_0_offset.h" 73 #include "dpcs/dpcs_3_0_0_sh_mask.h" 74 #include "nbio/nbio_7_4_offset.h" 75 #include "amdgpu_socbb.h" 76 77 #define DC_LOGGER_INIT(logger) 78 79 static const struct dc_debug_options debug_defaults_drv = { 80 .disable_dmcu = true, 81 .force_abm_enable = false, 82 .timing_trace = false, 83 .clock_trace = true, 84 .disable_pplib_clock_request = true, 85 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 86 .force_single_disp_pipe_split = false, 87 .disable_dcc = DCC_ENABLE, 88 .vsr_support = true, 89 .performance_trace = false, 90 .max_downscale_src_width = 7680,/*upto 8K*/ 91 .disable_pplib_wm_range = false, 92 .scl_reset_length10 = true, 93 .sanity_checks = false, 94 .underflow_assert_delay_us = 0xFFFFFFFF, 95 .dwb_fi_phase = -1, // -1 = disable, 96 .dmub_command_table = true, 97 .use_max_lb = true, 98 .exit_idle_opt_for_cursor_updates = true 99 }; 100 101 static const struct dc_debug_options debug_defaults_diags = { 102 .disable_dmcu = true, 103 .force_abm_enable = false, 104 .timing_trace = true, 105 .clock_trace = true, 106 .disable_dpp_power_gate = true, 107 .disable_hubp_power_gate = true, 108 .disable_clock_gate = true, 109 .disable_pplib_clock_request = true, 110 .disable_pplib_wm_range = true, 111 .disable_stutter = false, 112 .scl_reset_length10 = true, 113 .dwb_fi_phase = -1, // -1 = disable 114 .dmub_command_table = true, 115 .enable_tri_buf = true, 116 .use_max_lb = true 117 }; 118 119 static const struct dc_panel_config panel_config_defaults = { 120 .psr = { 121 .disable_psr = false, 122 .disallow_psrsu = false, 123 }, 124 }; 125 126 enum dcn302_clk_src_array_id { 127 DCN302_CLK_SRC_PLL0, 128 DCN302_CLK_SRC_PLL1, 129 DCN302_CLK_SRC_PLL2, 130 DCN302_CLK_SRC_PLL3, 131 DCN302_CLK_SRC_PLL4, 132 DCN302_CLK_SRC_TOTAL 133 }; 134 135 static const struct resource_caps res_cap_dcn302 = { 136 .num_timing_generator = 5, 137 .num_opp = 5, 138 .num_video_plane = 5, 139 .num_audio = 5, 140 .num_stream_encoder = 5, 141 .num_dwb = 1, 142 .num_ddc = 5, 143 .num_vmid = 16, 144 .num_mpc_3dlut = 2, 145 .num_dsc = 5, 146 }; 147 148 static const struct dc_plane_cap plane_cap = { 149 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 150 .per_pixel_alpha = true, 151 .pixel_format_support = { 152 .argb8888 = true, 153 .nv12 = true, 154 .fp16 = true, 155 .p010 = true, 156 .ayuv = false, 157 }, 158 .max_upscale_factor = { 159 .argb8888 = 16000, 160 .nv12 = 16000, 161 .fp16 = 16000 162 }, 163 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 164 .max_downscale_factor = { 165 .argb8888 = 167, 166 .nv12 = 167, 167 .fp16 = 167 168 }, 169 16, 170 16 171 }; 172 173 /* NBIO */ 174 #define NBIO_BASE_INNER(seg) \ 175 NBIO_BASE__INST0_SEG ## seg 176 177 #define NBIO_BASE(seg) \ 178 NBIO_BASE_INNER(seg) 179 180 #define NBIO_SR(reg_name)\ 181 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 182 mm ## reg_name 183 184 /* DCN */ 185 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 186 187 #define BASE(seg) BASE_INNER(seg) 188 189 #define SR(reg_name)\ 190 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 191 192 #define SF(reg_name, field_name, post_fix)\ 193 .field_name = reg_name ## __ ## field_name ## post_fix 194 195 #define SRI(reg_name, block, id)\ 196 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 197 198 #define SRI2(reg_name, block, id)\ 199 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 200 201 #define SRII(reg_name, block, id)\ 202 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 203 mm ## block ## id ## _ ## reg_name 204 205 #define DCCG_SRII(reg_name, block, id)\ 206 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 207 mm ## block ## id ## _ ## reg_name 208 209 #define VUPDATE_SRII(reg_name, block, id)\ 210 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 211 mm ## reg_name ## _ ## block ## id 212 213 #define SRII_DWB(reg_name, temp_name, block, id)\ 214 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 215 mm ## block ## id ## _ ## temp_name 216 217 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 218 .field_name = reg_name ## __ ## field_name ## post_fix 219 220 #define SRII_MPC_RMU(reg_name, block, id)\ 221 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 222 mm ## block ## id ## _ ## reg_name 223 224 static const struct dcn_hubbub_registers hubbub_reg = { 225 HUBBUB_REG_LIST_DCN30(0) 226 }; 227 228 static const struct dcn_hubbub_shift hubbub_shift = { 229 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 230 }; 231 232 static const struct dcn_hubbub_mask hubbub_mask = { 233 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 234 }; 235 236 #define vmid_regs(id)\ 237 [id] = { DCN20_VMID_REG_LIST(id) } 238 239 static const struct dcn_vmid_registers vmid_regs[] = { 240 vmid_regs(0), 241 vmid_regs(1), 242 vmid_regs(2), 243 vmid_regs(3), 244 vmid_regs(4), 245 vmid_regs(5), 246 vmid_regs(6), 247 vmid_regs(7), 248 vmid_regs(8), 249 vmid_regs(9), 250 vmid_regs(10), 251 vmid_regs(11), 252 vmid_regs(12), 253 vmid_regs(13), 254 vmid_regs(14), 255 vmid_regs(15) 256 }; 257 258 static const struct dcn20_vmid_shift vmid_shifts = { 259 DCN20_VMID_MASK_SH_LIST(__SHIFT) 260 }; 261 262 static const struct dcn20_vmid_mask vmid_masks = { 263 DCN20_VMID_MASK_SH_LIST(_MASK) 264 }; 265 266 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 267 { 268 int i; 269 270 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 271 272 if (!hubbub3) 273 return NULL; 274 275 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 276 277 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 278 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 279 280 vmid->ctx = ctx; 281 282 vmid->regs = &vmid_regs[i]; 283 vmid->shifts = &vmid_shifts; 284 vmid->masks = &vmid_masks; 285 } 286 287 return &hubbub3->base; 288 } 289 290 #define vpg_regs(id)\ 291 [id] = { VPG_DCN3_REG_LIST(id) } 292 293 static const struct dcn30_vpg_registers vpg_regs[] = { 294 vpg_regs(0), 295 vpg_regs(1), 296 vpg_regs(2), 297 vpg_regs(3), 298 vpg_regs(4), 299 vpg_regs(5) 300 }; 301 302 static const struct dcn30_vpg_shift vpg_shift = { 303 DCN3_VPG_MASK_SH_LIST(__SHIFT) 304 }; 305 306 static const struct dcn30_vpg_mask vpg_mask = { 307 DCN3_VPG_MASK_SH_LIST(_MASK) 308 }; 309 310 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 311 { 312 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 313 314 if (!vpg3) 315 return NULL; 316 317 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 318 319 return &vpg3->base; 320 } 321 322 #define afmt_regs(id)\ 323 [id] = { AFMT_DCN3_REG_LIST(id) } 324 325 static const struct dcn30_afmt_registers afmt_regs[] = { 326 afmt_regs(0), 327 afmt_regs(1), 328 afmt_regs(2), 329 afmt_regs(3), 330 afmt_regs(4), 331 afmt_regs(5) 332 }; 333 334 static const struct dcn30_afmt_shift afmt_shift = { 335 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 336 }; 337 338 static const struct dcn30_afmt_mask afmt_mask = { 339 DCN3_AFMT_MASK_SH_LIST(_MASK) 340 }; 341 342 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 343 { 344 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 345 346 if (!afmt3) 347 return NULL; 348 349 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 350 351 return &afmt3->base; 352 } 353 354 #define audio_regs(id)\ 355 [id] = { AUD_COMMON_REG_LIST(id) } 356 357 static const struct dce_audio_registers audio_regs[] = { 358 audio_regs(0), 359 audio_regs(1), 360 audio_regs(2), 361 audio_regs(3), 362 audio_regs(4), 363 audio_regs(5), 364 audio_regs(6) 365 }; 366 367 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 368 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 369 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 370 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 371 372 static const struct dce_audio_shift audio_shift = { 373 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 374 }; 375 376 static const struct dce_audio_mask audio_mask = { 377 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 378 }; 379 380 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 381 { 382 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 383 } 384 385 #define stream_enc_regs(id)\ 386 [id] = { SE_DCN3_REG_LIST(id) } 387 388 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 389 stream_enc_regs(0), 390 stream_enc_regs(1), 391 stream_enc_regs(2), 392 stream_enc_regs(3), 393 stream_enc_regs(4) 394 }; 395 396 static const struct dcn10_stream_encoder_shift se_shift = { 397 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 398 }; 399 400 static const struct dcn10_stream_encoder_mask se_mask = { 401 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 402 }; 403 404 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 405 { 406 struct dcn10_stream_encoder *enc1; 407 struct vpg *vpg; 408 struct afmt *afmt; 409 int vpg_inst; 410 int afmt_inst; 411 412 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 413 if (eng_id <= ENGINE_ID_DIGE) { 414 vpg_inst = eng_id; 415 afmt_inst = eng_id; 416 } else 417 return NULL; 418 419 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 420 vpg = dcn302_vpg_create(ctx, vpg_inst); 421 afmt = dcn302_afmt_create(ctx, afmt_inst); 422 423 if (!enc1 || !vpg || !afmt) { 424 kfree(enc1); 425 kfree(vpg); 426 kfree(afmt); 427 return NULL; 428 } 429 430 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 431 &se_shift, &se_mask); 432 433 return &enc1->base; 434 } 435 436 #define clk_src_regs(index, pllid)\ 437 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 438 439 static const struct dce110_clk_src_regs clk_src_regs[] = { 440 clk_src_regs(0, A), 441 clk_src_regs(1, B), 442 clk_src_regs(2, C), 443 clk_src_regs(3, D), 444 clk_src_regs(4, E) 445 }; 446 447 static const struct dce110_clk_src_shift cs_shift = { 448 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 449 }; 450 451 static const struct dce110_clk_src_mask cs_mask = { 452 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 453 }; 454 455 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 456 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 457 { 458 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 459 460 if (!clk_src) 461 return NULL; 462 463 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 464 clk_src->base.dp_clk_src = dp_clk_src; 465 return &clk_src->base; 466 } 467 468 kfree(clk_src); 469 BREAK_TO_DEBUGGER(); 470 return NULL; 471 } 472 473 static const struct dce_hwseq_registers hwseq_reg = { 474 HWSEQ_DCN302_REG_LIST() 475 }; 476 477 static const struct dce_hwseq_shift hwseq_shift = { 478 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 479 }; 480 481 static const struct dce_hwseq_mask hwseq_mask = { 482 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 483 }; 484 485 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 486 { 487 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 488 489 if (hws) { 490 hws->ctx = ctx; 491 hws->regs = &hwseq_reg; 492 hws->shifts = &hwseq_shift; 493 hws->masks = &hwseq_mask; 494 } 495 return hws; 496 } 497 498 #define hubp_regs(id)\ 499 [id] = { HUBP_REG_LIST_DCN30(id) } 500 501 static const struct dcn_hubp2_registers hubp_regs[] = { 502 hubp_regs(0), 503 hubp_regs(1), 504 hubp_regs(2), 505 hubp_regs(3), 506 hubp_regs(4) 507 }; 508 509 static const struct dcn_hubp2_shift hubp_shift = { 510 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 511 }; 512 513 static const struct dcn_hubp2_mask hubp_mask = { 514 HUBP_MASK_SH_LIST_DCN30(_MASK) 515 }; 516 517 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 518 { 519 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 520 521 if (!hubp2) 522 return NULL; 523 524 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 525 return &hubp2->base; 526 527 BREAK_TO_DEBUGGER(); 528 kfree(hubp2); 529 return NULL; 530 } 531 532 #define dpp_regs(id)\ 533 [id] = { DPP_REG_LIST_DCN30(id) } 534 535 static const struct dcn3_dpp_registers dpp_regs[] = { 536 dpp_regs(0), 537 dpp_regs(1), 538 dpp_regs(2), 539 dpp_regs(3), 540 dpp_regs(4) 541 }; 542 543 static const struct dcn3_dpp_shift tf_shift = { 544 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 545 }; 546 547 static const struct dcn3_dpp_mask tf_mask = { 548 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 549 }; 550 551 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 552 { 553 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 554 555 if (!dpp) 556 return NULL; 557 558 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 559 return &dpp->base; 560 561 BREAK_TO_DEBUGGER(); 562 kfree(dpp); 563 return NULL; 564 } 565 566 #define opp_regs(id)\ 567 [id] = { OPP_REG_LIST_DCN30(id) } 568 569 static const struct dcn20_opp_registers opp_regs[] = { 570 opp_regs(0), 571 opp_regs(1), 572 opp_regs(2), 573 opp_regs(3), 574 opp_regs(4) 575 }; 576 577 static const struct dcn20_opp_shift opp_shift = { 578 OPP_MASK_SH_LIST_DCN20(__SHIFT) 579 }; 580 581 static const struct dcn20_opp_mask opp_mask = { 582 OPP_MASK_SH_LIST_DCN20(_MASK) 583 }; 584 585 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 586 { 587 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 588 589 if (!opp) { 590 BREAK_TO_DEBUGGER(); 591 return NULL; 592 } 593 594 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 595 return &opp->base; 596 } 597 598 #define optc_regs(id)\ 599 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 600 601 static const struct dcn_optc_registers optc_regs[] = { 602 optc_regs(0), 603 optc_regs(1), 604 optc_regs(2), 605 optc_regs(3), 606 optc_regs(4) 607 }; 608 609 static const struct dcn_optc_shift optc_shift = { 610 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 611 }; 612 613 static const struct dcn_optc_mask optc_mask = { 614 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 615 }; 616 617 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 618 { 619 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 620 621 if (!tgn10) 622 return NULL; 623 624 tgn10->base.inst = instance; 625 tgn10->base.ctx = ctx; 626 627 tgn10->tg_regs = &optc_regs[instance]; 628 tgn10->tg_shift = &optc_shift; 629 tgn10->tg_mask = &optc_mask; 630 631 dcn30_timing_generator_init(tgn10); 632 633 return &tgn10->base; 634 } 635 636 static const struct dcn30_mpc_registers mpc_regs = { 637 MPC_REG_LIST_DCN3_0(0), 638 MPC_REG_LIST_DCN3_0(1), 639 MPC_REG_LIST_DCN3_0(2), 640 MPC_REG_LIST_DCN3_0(3), 641 MPC_REG_LIST_DCN3_0(4), 642 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 643 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 644 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 645 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 646 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 647 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 648 MPC_RMU_REG_LIST_DCN3AG(0), 649 MPC_RMU_REG_LIST_DCN3AG(1), 650 MPC_RMU_REG_LIST_DCN3AG(2), 651 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 652 }; 653 654 static const struct dcn30_mpc_shift mpc_shift = { 655 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 656 }; 657 658 static const struct dcn30_mpc_mask mpc_mask = { 659 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 660 }; 661 662 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 663 { 664 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 665 666 if (!mpc30) 667 return NULL; 668 669 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 670 671 return &mpc30->base; 672 } 673 674 #define dsc_regsDCN20(id)\ 675 [id] = { DSC_REG_LIST_DCN20(id) } 676 677 static const struct dcn20_dsc_registers dsc_regs[] = { 678 dsc_regsDCN20(0), 679 dsc_regsDCN20(1), 680 dsc_regsDCN20(2), 681 dsc_regsDCN20(3), 682 dsc_regsDCN20(4) 683 }; 684 685 static const struct dcn20_dsc_shift dsc_shift = { 686 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 687 }; 688 689 static const struct dcn20_dsc_mask dsc_mask = { 690 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 691 }; 692 693 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 694 { 695 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 696 697 if (!dsc) { 698 BREAK_TO_DEBUGGER(); 699 return NULL; 700 } 701 702 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 703 return &dsc->base; 704 } 705 706 #define dwbc_regs_dcn3(id)\ 707 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 708 709 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 710 dwbc_regs_dcn3(0) 711 }; 712 713 static const struct dcn30_dwbc_shift dwbc30_shift = { 714 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 715 }; 716 717 static const struct dcn30_dwbc_mask dwbc30_mask = { 718 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 719 }; 720 721 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 722 { 723 int i; 724 uint32_t pipe_count = pool->res_cap->num_dwb; 725 726 for (i = 0; i < pipe_count; i++) { 727 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 728 729 if (!dwbc30) { 730 dm_error("DC: failed to create dwbc30!\n"); 731 return false; 732 } 733 734 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 735 736 pool->dwbc[i] = &dwbc30->base; 737 } 738 return true; 739 } 740 741 #define mcif_wb_regs_dcn3(id)\ 742 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 743 744 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 745 mcif_wb_regs_dcn3(0) 746 }; 747 748 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 749 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 750 }; 751 752 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 753 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 754 }; 755 756 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 757 { 758 int i; 759 uint32_t pipe_count = pool->res_cap->num_dwb; 760 761 for (i = 0; i < pipe_count; i++) { 762 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 763 764 if (!mcif_wb30) { 765 dm_error("DC: failed to create mcif_wb30!\n"); 766 return false; 767 } 768 769 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 770 771 pool->mcif_wb[i] = &mcif_wb30->base; 772 } 773 return true; 774 } 775 776 #define aux_engine_regs(id)\ 777 [id] = {\ 778 AUX_COMMON_REG_LIST0(id), \ 779 .AUXN_IMPCAL = 0, \ 780 .AUXP_IMPCAL = 0, \ 781 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 782 } 783 784 static const struct dce110_aux_registers aux_engine_regs[] = { 785 aux_engine_regs(0), 786 aux_engine_regs(1), 787 aux_engine_regs(2), 788 aux_engine_regs(3), 789 aux_engine_regs(4) 790 }; 791 792 static const struct dce110_aux_registers_shift aux_shift = { 793 DCN_AUX_MASK_SH_LIST(__SHIFT) 794 }; 795 796 static const struct dce110_aux_registers_mask aux_mask = { 797 DCN_AUX_MASK_SH_LIST(_MASK) 798 }; 799 800 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 801 { 802 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 803 804 if (!aux_engine) 805 return NULL; 806 807 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 808 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 809 810 return &aux_engine->base; 811 } 812 813 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 814 815 static const struct dce_i2c_registers i2c_hw_regs[] = { 816 i2c_inst_regs(1), 817 i2c_inst_regs(2), 818 i2c_inst_regs(3), 819 i2c_inst_regs(4), 820 i2c_inst_regs(5) 821 }; 822 823 static const struct dce_i2c_shift i2c_shifts = { 824 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 825 }; 826 827 static const struct dce_i2c_mask i2c_masks = { 828 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 829 }; 830 831 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 832 { 833 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 834 835 if (!dce_i2c_hw) 836 return NULL; 837 838 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 839 840 return dce_i2c_hw; 841 } 842 843 static const struct encoder_feature_support link_enc_feature = { 844 .max_hdmi_deep_color = COLOR_DEPTH_121212, 845 .max_hdmi_pixel_clock = 600000, 846 .hdmi_ycbcr420_supported = true, 847 .dp_ycbcr420_supported = true, 848 .fec_supported = true, 849 .flags.bits.IS_HBR2_CAPABLE = true, 850 .flags.bits.IS_HBR3_CAPABLE = true, 851 .flags.bits.IS_TPS3_CAPABLE = true, 852 .flags.bits.IS_TPS4_CAPABLE = true 853 }; 854 855 #define link_regs(id, phyid)\ 856 [id] = {\ 857 LE_DCN3_REG_LIST(id), \ 858 UNIPHY_DCN2_REG_LIST(phyid), \ 859 DPCS_DCN2_REG_LIST(id), \ 860 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 861 } 862 863 static const struct dcn10_link_enc_registers link_enc_regs[] = { 864 link_regs(0, A), 865 link_regs(1, B), 866 link_regs(2, C), 867 link_regs(3, D), 868 link_regs(4, E) 869 }; 870 871 static const struct dcn10_link_enc_shift le_shift = { 872 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 873 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 874 }; 875 876 static const struct dcn10_link_enc_mask le_mask = { 877 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 878 DPCS_DCN2_MASK_SH_LIST(_MASK) 879 }; 880 881 #define aux_regs(id)\ 882 [id] = { DCN2_AUX_REG_LIST(id) } 883 884 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 885 aux_regs(0), 886 aux_regs(1), 887 aux_regs(2), 888 aux_regs(3), 889 aux_regs(4) 890 }; 891 892 #define hpd_regs(id)\ 893 [id] = { HPD_REG_LIST(id) } 894 895 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 896 hpd_regs(0), 897 hpd_regs(1), 898 hpd_regs(2), 899 hpd_regs(3), 900 hpd_regs(4) 901 }; 902 903 static struct link_encoder *dcn302_link_encoder_create( 904 struct dc_context *ctx, 905 const struct encoder_init_data *enc_init_data) 906 { 907 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 908 909 if (!enc20) 910 return NULL; 911 912 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 913 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 914 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 915 916 return &enc20->enc10.base; 917 } 918 919 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 920 { DCN_PANEL_CNTL_REG_LIST() } 921 }; 922 923 static const struct dce_panel_cntl_shift panel_cntl_shift = { 924 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 925 }; 926 927 static const struct dce_panel_cntl_mask panel_cntl_mask = { 928 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 929 }; 930 931 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 932 { 933 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 934 935 if (!panel_cntl) 936 return NULL; 937 938 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 939 &panel_cntl_shift, &panel_cntl_mask); 940 941 return &panel_cntl->base; 942 } 943 944 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 945 { 946 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 947 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 948 } 949 950 static const struct resource_create_funcs res_create_funcs = { 951 .read_dce_straps = read_dce_straps, 952 .create_audio = dcn302_create_audio, 953 .create_stream_encoder = dcn302_stream_encoder_create, 954 .create_hwseq = dcn302_hwseq_create, 955 }; 956 957 static const struct resource_create_funcs res_create_maximus_funcs = { 958 .read_dce_straps = NULL, 959 .create_audio = NULL, 960 .create_stream_encoder = NULL, 961 .create_hwseq = dcn302_hwseq_create, 962 }; 963 964 static bool is_soc_bounding_box_valid(struct dc *dc) 965 { 966 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 967 968 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 969 return true; 970 971 return false; 972 } 973 974 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 975 { 976 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 977 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 978 979 DC_LOGGER_INIT(dc->ctx->logger); 980 981 if (!is_soc_bounding_box_valid(dc)) { 982 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 983 return false; 984 } 985 986 loaded_ip->max_num_otg = pool->pipe_count; 987 loaded_ip->max_num_dpp = pool->pipe_count; 988 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 989 DC_FP_START(); 990 dcn20_patch_bounding_box(dc, loaded_bb); 991 DC_FP_END(); 992 993 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 994 struct bp_soc_bb_info bb_info = { 0 }; 995 996 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 997 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 998 999 DC_FP_START(); 1000 dcn302_fpu_init_soc_bounding_box(bb_info); 1001 DC_FP_END(); 1002 } 1003 } 1004 1005 return true; 1006 } 1007 1008 static void dcn302_resource_destruct(struct resource_pool *pool) 1009 { 1010 unsigned int i; 1011 1012 for (i = 0; i < pool->stream_enc_count; i++) { 1013 if (pool->stream_enc[i] != NULL) { 1014 if (pool->stream_enc[i]->vpg != NULL) { 1015 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1016 pool->stream_enc[i]->vpg = NULL; 1017 } 1018 if (pool->stream_enc[i]->afmt != NULL) { 1019 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1020 pool->stream_enc[i]->afmt = NULL; 1021 } 1022 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1023 pool->stream_enc[i] = NULL; 1024 } 1025 } 1026 1027 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1028 if (pool->dscs[i] != NULL) 1029 dcn20_dsc_destroy(&pool->dscs[i]); 1030 } 1031 1032 if (pool->mpc != NULL) { 1033 kfree(TO_DCN20_MPC(pool->mpc)); 1034 pool->mpc = NULL; 1035 } 1036 1037 if (pool->hubbub != NULL) { 1038 kfree(pool->hubbub); 1039 pool->hubbub = NULL; 1040 } 1041 1042 for (i = 0; i < pool->pipe_count; i++) { 1043 if (pool->dpps[i] != NULL) { 1044 kfree(TO_DCN20_DPP(pool->dpps[i])); 1045 pool->dpps[i] = NULL; 1046 } 1047 1048 if (pool->hubps[i] != NULL) { 1049 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1050 pool->hubps[i] = NULL; 1051 } 1052 1053 if (pool->irqs != NULL) 1054 dal_irq_service_destroy(&pool->irqs); 1055 } 1056 1057 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1058 if (pool->engines[i] != NULL) 1059 dce110_engine_destroy(&pool->engines[i]); 1060 if (pool->hw_i2cs[i] != NULL) { 1061 kfree(pool->hw_i2cs[i]); 1062 pool->hw_i2cs[i] = NULL; 1063 } 1064 if (pool->sw_i2cs[i] != NULL) { 1065 kfree(pool->sw_i2cs[i]); 1066 pool->sw_i2cs[i] = NULL; 1067 } 1068 } 1069 1070 for (i = 0; i < pool->res_cap->num_opp; i++) { 1071 if (pool->opps[i] != NULL) 1072 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1073 } 1074 1075 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1076 if (pool->timing_generators[i] != NULL) { 1077 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1078 pool->timing_generators[i] = NULL; 1079 } 1080 } 1081 1082 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1083 if (pool->dwbc[i] != NULL) { 1084 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1085 pool->dwbc[i] = NULL; 1086 } 1087 if (pool->mcif_wb[i] != NULL) { 1088 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1089 pool->mcif_wb[i] = NULL; 1090 } 1091 } 1092 1093 for (i = 0; i < pool->audio_count; i++) { 1094 if (pool->audios[i]) 1095 dce_aud_destroy(&pool->audios[i]); 1096 } 1097 1098 for (i = 0; i < pool->clk_src_count; i++) { 1099 if (pool->clock_sources[i] != NULL) 1100 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1101 } 1102 1103 if (pool->dp_clock_source != NULL) 1104 dcn20_clock_source_destroy(&pool->dp_clock_source); 1105 1106 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1107 if (pool->mpc_lut[i] != NULL) { 1108 dc_3dlut_func_release(pool->mpc_lut[i]); 1109 pool->mpc_lut[i] = NULL; 1110 } 1111 if (pool->mpc_shaper[i] != NULL) { 1112 dc_transfer_func_release(pool->mpc_shaper[i]); 1113 pool->mpc_shaper[i] = NULL; 1114 } 1115 } 1116 1117 for (i = 0; i < pool->pipe_count; i++) { 1118 if (pool->multiple_abms[i] != NULL) 1119 dce_abm_destroy(&pool->multiple_abms[i]); 1120 } 1121 1122 if (pool->psr != NULL) 1123 dmub_psr_destroy(&pool->psr); 1124 1125 if (pool->dccg != NULL) 1126 dcn_dccg_destroy(&pool->dccg); 1127 1128 if (pool->oem_device != NULL) { 1129 struct dc *dc = pool->oem_device->ctx->dc; 1130 1131 dc->link_srv->destroy_ddc_service(&pool->oem_device); 1132 } 1133 } 1134 1135 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1136 { 1137 dcn302_resource_destruct(*pool); 1138 kfree(*pool); 1139 *pool = NULL; 1140 } 1141 1142 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1143 { 1144 DC_FP_START(); 1145 dcn302_fpu_update_bw_bounding_box(dc, bw_params); 1146 DC_FP_END(); 1147 } 1148 1149 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config) 1150 { 1151 *panel_config = panel_config_defaults; 1152 } 1153 1154 static struct resource_funcs dcn302_res_pool_funcs = { 1155 .destroy = dcn302_destroy_resource_pool, 1156 .link_enc_create = dcn302_link_encoder_create, 1157 .panel_cntl_create = dcn302_panel_cntl_create, 1158 .validate_bandwidth = dcn30_validate_bandwidth, 1159 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1160 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1161 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1162 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1163 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1164 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1165 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1166 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1167 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1168 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1169 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1170 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1171 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1172 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1173 .get_panel_config_defaults = dcn302_get_panel_config_defaults, 1174 }; 1175 1176 static struct dc_cap_funcs cap_funcs = { 1177 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1178 }; 1179 1180 static const struct bios_registers bios_regs = { 1181 NBIO_SR(BIOS_SCRATCH_3), 1182 NBIO_SR(BIOS_SCRATCH_6) 1183 }; 1184 1185 static const struct dccg_registers dccg_regs = { 1186 DCCG_REG_LIST_DCN3_02() 1187 }; 1188 1189 static const struct dccg_shift dccg_shift = { 1190 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1191 }; 1192 1193 static const struct dccg_mask dccg_mask = { 1194 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1195 }; 1196 1197 #define abm_regs(id)\ 1198 [id] = { ABM_DCN302_REG_LIST(id) } 1199 1200 static const struct dce_abm_registers abm_regs[] = { 1201 abm_regs(0), 1202 abm_regs(1), 1203 abm_regs(2), 1204 abm_regs(3), 1205 abm_regs(4) 1206 }; 1207 1208 static const struct dce_abm_shift abm_shift = { 1209 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1210 }; 1211 1212 static const struct dce_abm_mask abm_mask = { 1213 ABM_MASK_SH_LIST_DCN30(_MASK) 1214 }; 1215 1216 static bool dcn302_resource_construct( 1217 uint8_t num_virtual_links, 1218 struct dc *dc, 1219 struct resource_pool *pool) 1220 { 1221 int i; 1222 struct dc_context *ctx = dc->ctx; 1223 struct irq_service_init_data init_data; 1224 struct ddc_service_init_data ddc_init_data = {0}; 1225 1226 ctx->dc_bios->regs = &bios_regs; 1227 1228 pool->res_cap = &res_cap_dcn302; 1229 1230 pool->funcs = &dcn302_res_pool_funcs; 1231 1232 /************************************************* 1233 * Resource + asic cap harcoding * 1234 *************************************************/ 1235 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1236 pool->pipe_count = pool->res_cap->num_timing_generator; 1237 pool->mpcc_count = pool->res_cap->num_timing_generator; 1238 dc->caps.max_downscale_ratio = 600; 1239 dc->caps.i2c_speed_in_khz = 100; 1240 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1241 dc->caps.max_cursor_size = 256; 1242 dc->caps.min_horizontal_blanking_period = 80; 1243 dc->caps.dmdata_alloc_size = 2048; 1244 dc->caps.mall_size_per_mem_channel = 4; 1245 /* total size = mall per channel * num channels * 1024 * 1024 */ 1246 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1247 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1248 dc->caps.max_slave_planes = 2; 1249 dc->caps.max_slave_yuv_planes = 2; 1250 dc->caps.max_slave_rgb_planes = 2; 1251 dc->caps.post_blend_color_processing = true; 1252 dc->caps.force_dp_tps4_for_cp2520 = true; 1253 dc->caps.extended_aux_timeout_support = true; 1254 dc->caps.dmcub_support = true; 1255 1256 /* Color pipeline capabilities */ 1257 dc->caps.color.dpp.dcn_arch = 1; 1258 dc->caps.color.dpp.input_lut_shared = 0; 1259 dc->caps.color.dpp.icsc = 1; 1260 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1261 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1262 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1263 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1264 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1265 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1266 dc->caps.color.dpp.post_csc = 1; 1267 dc->caps.color.dpp.gamma_corr = 1; 1268 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1269 1270 dc->caps.color.dpp.hw_3d_lut = 1; 1271 dc->caps.color.dpp.ogam_ram = 1; 1272 // no OGAM ROM on DCN3 1273 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1274 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1275 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1276 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1277 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1278 dc->caps.color.dpp.ocsc = 0; 1279 1280 dc->caps.color.mpc.gamut_remap = 1; 1281 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1282 dc->caps.color.mpc.ogam_ram = 1; 1283 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1284 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1285 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1286 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1287 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1288 dc->caps.color.mpc.ocsc = 1; 1289 1290 dc->caps.dp_hdmi21_pcon_support = true; 1291 1292 /* read VBIOS LTTPR caps */ 1293 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1294 enum bp_result bp_query_result; 1295 uint8_t is_vbios_lttpr_enable = 0; 1296 1297 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1298 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1299 } 1300 1301 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1302 enum bp_result bp_query_result; 1303 uint8_t is_vbios_interop_enabled = 0; 1304 1305 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 1306 &is_vbios_interop_enabled); 1307 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1308 } 1309 1310 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1311 dc->debug = debug_defaults_drv; 1312 else 1313 dc->debug = debug_defaults_diags; 1314 1315 // Init the vm_helper 1316 if (dc->vm_helper) 1317 vm_helper_init(dc->vm_helper, 16); 1318 1319 /************************************************* 1320 * Create resources * 1321 *************************************************/ 1322 1323 /* Clock Sources for Pixel Clock*/ 1324 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1325 dcn302_clock_source_create(ctx, ctx->dc_bios, 1326 CLOCK_SOURCE_COMBO_PHY_PLL0, 1327 &clk_src_regs[0], false); 1328 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1329 dcn302_clock_source_create(ctx, ctx->dc_bios, 1330 CLOCK_SOURCE_COMBO_PHY_PLL1, 1331 &clk_src_regs[1], false); 1332 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1333 dcn302_clock_source_create(ctx, ctx->dc_bios, 1334 CLOCK_SOURCE_COMBO_PHY_PLL2, 1335 &clk_src_regs[2], false); 1336 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1337 dcn302_clock_source_create(ctx, ctx->dc_bios, 1338 CLOCK_SOURCE_COMBO_PHY_PLL3, 1339 &clk_src_regs[3], false); 1340 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1341 dcn302_clock_source_create(ctx, ctx->dc_bios, 1342 CLOCK_SOURCE_COMBO_PHY_PLL4, 1343 &clk_src_regs[4], false); 1344 1345 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1346 1347 /* todo: not reuse phy_pll registers */ 1348 pool->dp_clock_source = 1349 dcn302_clock_source_create(ctx, ctx->dc_bios, 1350 CLOCK_SOURCE_ID_DP_DTO, 1351 &clk_src_regs[0], true); 1352 1353 for (i = 0; i < pool->clk_src_count; i++) { 1354 if (pool->clock_sources[i] == NULL) { 1355 dm_error("DC: failed to create clock sources!\n"); 1356 BREAK_TO_DEBUGGER(); 1357 goto create_fail; 1358 } 1359 } 1360 1361 /* DCCG */ 1362 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1363 if (pool->dccg == NULL) { 1364 dm_error("DC: failed to create dccg!\n"); 1365 BREAK_TO_DEBUGGER(); 1366 goto create_fail; 1367 } 1368 1369 /* PP Lib and SMU interfaces */ 1370 init_soc_bounding_box(dc, pool); 1371 1372 /* DML */ 1373 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1374 1375 /* IRQ */ 1376 init_data.ctx = dc->ctx; 1377 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1378 if (!pool->irqs) 1379 goto create_fail; 1380 1381 /* HUBBUB */ 1382 pool->hubbub = dcn302_hubbub_create(ctx); 1383 if (pool->hubbub == NULL) { 1384 BREAK_TO_DEBUGGER(); 1385 dm_error("DC: failed to create hubbub!\n"); 1386 goto create_fail; 1387 } 1388 1389 /* HUBPs, DPPs, OPPs and TGs */ 1390 for (i = 0; i < pool->pipe_count; i++) { 1391 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1392 if (pool->hubps[i] == NULL) { 1393 BREAK_TO_DEBUGGER(); 1394 dm_error("DC: failed to create hubps!\n"); 1395 goto create_fail; 1396 } 1397 1398 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1399 if (pool->dpps[i] == NULL) { 1400 BREAK_TO_DEBUGGER(); 1401 dm_error("DC: failed to create dpps!\n"); 1402 goto create_fail; 1403 } 1404 } 1405 1406 for (i = 0; i < pool->res_cap->num_opp; i++) { 1407 pool->opps[i] = dcn302_opp_create(ctx, i); 1408 if (pool->opps[i] == NULL) { 1409 BREAK_TO_DEBUGGER(); 1410 dm_error("DC: failed to create output pixel processor!\n"); 1411 goto create_fail; 1412 } 1413 } 1414 1415 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1416 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1417 if (pool->timing_generators[i] == NULL) { 1418 BREAK_TO_DEBUGGER(); 1419 dm_error("DC: failed to create tg!\n"); 1420 goto create_fail; 1421 } 1422 } 1423 pool->timing_generator_count = i; 1424 1425 /* PSR */ 1426 pool->psr = dmub_psr_create(ctx); 1427 if (pool->psr == NULL) { 1428 dm_error("DC: failed to create psr!\n"); 1429 BREAK_TO_DEBUGGER(); 1430 goto create_fail; 1431 } 1432 1433 /* ABMs */ 1434 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1435 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1436 if (pool->multiple_abms[i] == NULL) { 1437 dm_error("DC: failed to create abm for pipe %d!\n", i); 1438 BREAK_TO_DEBUGGER(); 1439 goto create_fail; 1440 } 1441 } 1442 1443 /* MPC and DSC */ 1444 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1445 if (pool->mpc == NULL) { 1446 BREAK_TO_DEBUGGER(); 1447 dm_error("DC: failed to create mpc!\n"); 1448 goto create_fail; 1449 } 1450 1451 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1452 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1453 if (pool->dscs[i] == NULL) { 1454 BREAK_TO_DEBUGGER(); 1455 dm_error("DC: failed to create display stream compressor %d!\n", i); 1456 goto create_fail; 1457 } 1458 } 1459 1460 /* DWB and MMHUBBUB */ 1461 if (!dcn302_dwbc_create(ctx, pool)) { 1462 BREAK_TO_DEBUGGER(); 1463 dm_error("DC: failed to create dwbc!\n"); 1464 goto create_fail; 1465 } 1466 1467 if (!dcn302_mmhubbub_create(ctx, pool)) { 1468 BREAK_TO_DEBUGGER(); 1469 dm_error("DC: failed to create mcif_wb!\n"); 1470 goto create_fail; 1471 } 1472 1473 /* AUX and I2C */ 1474 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1475 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1476 if (pool->engines[i] == NULL) { 1477 BREAK_TO_DEBUGGER(); 1478 dm_error("DC:failed to create aux engine!!\n"); 1479 goto create_fail; 1480 } 1481 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1482 if (pool->hw_i2cs[i] == NULL) { 1483 BREAK_TO_DEBUGGER(); 1484 dm_error("DC:failed to create hw i2c!!\n"); 1485 goto create_fail; 1486 } 1487 pool->sw_i2cs[i] = NULL; 1488 } 1489 1490 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1491 if (!resource_construct(num_virtual_links, dc, pool, 1492 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1493 &res_create_funcs : &res_create_maximus_funcs))) 1494 goto create_fail; 1495 1496 /* HW Sequencer and Plane caps */ 1497 dcn302_hw_sequencer_construct(dc); 1498 1499 dc->caps.max_planes = pool->pipe_count; 1500 1501 for (i = 0; i < dc->caps.max_planes; ++i) 1502 dc->caps.planes[i] = plane_cap; 1503 1504 dc->cap_funcs = cap_funcs; 1505 1506 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1507 ddc_init_data.ctx = dc->ctx; 1508 ddc_init_data.link = NULL; 1509 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1510 ddc_init_data.id.enum_id = 0; 1511 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1512 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 1513 } else { 1514 pool->oem_device = NULL; 1515 } 1516 1517 return true; 1518 1519 create_fail: 1520 1521 dcn302_resource_destruct(pool); 1522 1523 return false; 1524 } 1525 1526 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1527 { 1528 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1529 1530 if (!pool) 1531 return NULL; 1532 1533 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1534 return pool; 1535 1536 BREAK_TO_DEBUGGER(); 1537 kfree(pool); 1538 return NULL; 1539 } 1540