1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dcn10/dcn10_resource.h" 47 48 #include "dce/dce_abm.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_clock_source.h" 52 #include "dce/dce_hwseq.h" 53 #include "dce/dce_i2c_hw.h" 54 #include "dce/dce_panel_cntl.h" 55 #include "dce/dmub_abm.h" 56 #include "dce/dmub_psr.h" 57 #include "clk_mgr.h" 58 59 #include "hw_sequencer_private.h" 60 #include "reg_helper.h" 61 #include "resource.h" 62 #include "vm_helper.h" 63 64 #include "dml/dcn302/dcn302_fpu.h" 65 66 #include "dimgrey_cavefish_ip_offset.h" 67 #include "dcn/dcn_3_0_2_offset.h" 68 #include "dcn/dcn_3_0_2_sh_mask.h" 69 #include "dpcs/dpcs_3_0_0_offset.h" 70 #include "dpcs/dpcs_3_0_0_sh_mask.h" 71 #include "nbio/nbio_7_4_offset.h" 72 #include "amdgpu_socbb.h" 73 74 #define DC_LOGGER_INIT(logger) 75 76 static const struct dc_debug_options debug_defaults_drv = { 77 .disable_dmcu = true, 78 .force_abm_enable = false, 79 .timing_trace = false, 80 .clock_trace = true, 81 .disable_pplib_clock_request = true, 82 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 83 .force_single_disp_pipe_split = false, 84 .disable_dcc = DCC_ENABLE, 85 .vsr_support = true, 86 .performance_trace = false, 87 .max_downscale_src_width = 7680,/*upto 8K*/ 88 .disable_pplib_wm_range = false, 89 .scl_reset_length10 = true, 90 .sanity_checks = false, 91 .underflow_assert_delay_us = 0xFFFFFFFF, 92 .dwb_fi_phase = -1, // -1 = disable, 93 .dmub_command_table = true, 94 .use_max_lb = true 95 }; 96 97 static const struct dc_debug_options debug_defaults_diags = { 98 .disable_dmcu = true, 99 .force_abm_enable = false, 100 .timing_trace = true, 101 .clock_trace = true, 102 .disable_dpp_power_gate = true, 103 .disable_hubp_power_gate = true, 104 .disable_clock_gate = true, 105 .disable_pplib_clock_request = true, 106 .disable_pplib_wm_range = true, 107 .disable_stutter = false, 108 .scl_reset_length10 = true, 109 .dwb_fi_phase = -1, // -1 = disable 110 .dmub_command_table = true, 111 .enable_tri_buf = true, 112 .disable_psr = true, 113 .use_max_lb = true 114 }; 115 116 enum dcn302_clk_src_array_id { 117 DCN302_CLK_SRC_PLL0, 118 DCN302_CLK_SRC_PLL1, 119 DCN302_CLK_SRC_PLL2, 120 DCN302_CLK_SRC_PLL3, 121 DCN302_CLK_SRC_PLL4, 122 DCN302_CLK_SRC_TOTAL 123 }; 124 125 static const struct resource_caps res_cap_dcn302 = { 126 .num_timing_generator = 5, 127 .num_opp = 5, 128 .num_video_plane = 5, 129 .num_audio = 5, 130 .num_stream_encoder = 5, 131 .num_dwb = 1, 132 .num_ddc = 5, 133 .num_vmid = 16, 134 .num_mpc_3dlut = 2, 135 .num_dsc = 5, 136 }; 137 138 static const struct dc_plane_cap plane_cap = { 139 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 140 .blends_with_above = true, 141 .blends_with_below = true, 142 .per_pixel_alpha = true, 143 .pixel_format_support = { 144 .argb8888 = true, 145 .nv12 = true, 146 .fp16 = true, 147 .p010 = true, 148 .ayuv = false, 149 }, 150 .max_upscale_factor = { 151 .argb8888 = 16000, 152 .nv12 = 16000, 153 .fp16 = 16000 154 }, 155 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 156 .max_downscale_factor = { 157 .argb8888 = 167, 158 .nv12 = 167, 159 .fp16 = 167 160 }, 161 16, 162 16 163 }; 164 165 /* NBIO */ 166 #define NBIO_BASE_INNER(seg) \ 167 NBIO_BASE__INST0_SEG ## seg 168 169 #define NBIO_BASE(seg) \ 170 NBIO_BASE_INNER(seg) 171 172 #define NBIO_SR(reg_name)\ 173 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 174 mm ## reg_name 175 176 /* DCN */ 177 #undef BASE_INNER 178 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 179 180 #define BASE(seg) BASE_INNER(seg) 181 182 #define SR(reg_name)\ 183 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 184 185 #define SF(reg_name, field_name, post_fix)\ 186 .field_name = reg_name ## __ ## field_name ## post_fix 187 188 #define SRI(reg_name, block, id)\ 189 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 190 191 #define SRI2(reg_name, block, id)\ 192 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 193 194 #define SRII(reg_name, block, id)\ 195 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 196 mm ## block ## id ## _ ## reg_name 197 198 #define DCCG_SRII(reg_name, block, id)\ 199 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 200 mm ## block ## id ## _ ## reg_name 201 202 #define VUPDATE_SRII(reg_name, block, id)\ 203 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 204 mm ## reg_name ## _ ## block ## id 205 206 #define SRII_DWB(reg_name, temp_name, block, id)\ 207 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 208 mm ## block ## id ## _ ## temp_name 209 210 #define SRII_MPC_RMU(reg_name, block, id)\ 211 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 212 mm ## block ## id ## _ ## reg_name 213 214 static const struct dcn_hubbub_registers hubbub_reg = { 215 HUBBUB_REG_LIST_DCN30(0) 216 }; 217 218 static const struct dcn_hubbub_shift hubbub_shift = { 219 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 220 }; 221 222 static const struct dcn_hubbub_mask hubbub_mask = { 223 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 224 }; 225 226 #define vmid_regs(id)\ 227 [id] = { DCN20_VMID_REG_LIST(id) } 228 229 static const struct dcn_vmid_registers vmid_regs[] = { 230 vmid_regs(0), 231 vmid_regs(1), 232 vmid_regs(2), 233 vmid_regs(3), 234 vmid_regs(4), 235 vmid_regs(5), 236 vmid_regs(6), 237 vmid_regs(7), 238 vmid_regs(8), 239 vmid_regs(9), 240 vmid_regs(10), 241 vmid_regs(11), 242 vmid_regs(12), 243 vmid_regs(13), 244 vmid_regs(14), 245 vmid_regs(15) 246 }; 247 248 static const struct dcn20_vmid_shift vmid_shifts = { 249 DCN20_VMID_MASK_SH_LIST(__SHIFT) 250 }; 251 252 static const struct dcn20_vmid_mask vmid_masks = { 253 DCN20_VMID_MASK_SH_LIST(_MASK) 254 }; 255 256 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 257 { 258 int i; 259 260 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 261 262 if (!hubbub3) 263 return NULL; 264 265 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 266 267 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 268 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 269 270 vmid->ctx = ctx; 271 272 vmid->regs = &vmid_regs[i]; 273 vmid->shifts = &vmid_shifts; 274 vmid->masks = &vmid_masks; 275 } 276 277 return &hubbub3->base; 278 } 279 280 #define vpg_regs(id)\ 281 [id] = { VPG_DCN3_REG_LIST(id) } 282 283 static const struct dcn30_vpg_registers vpg_regs[] = { 284 vpg_regs(0), 285 vpg_regs(1), 286 vpg_regs(2), 287 vpg_regs(3), 288 vpg_regs(4), 289 vpg_regs(5) 290 }; 291 292 static const struct dcn30_vpg_shift vpg_shift = { 293 DCN3_VPG_MASK_SH_LIST(__SHIFT) 294 }; 295 296 static const struct dcn30_vpg_mask vpg_mask = { 297 DCN3_VPG_MASK_SH_LIST(_MASK) 298 }; 299 300 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 301 { 302 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 303 304 if (!vpg3) 305 return NULL; 306 307 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 308 309 return &vpg3->base; 310 } 311 312 #define afmt_regs(id)\ 313 [id] = { AFMT_DCN3_REG_LIST(id) } 314 315 static const struct dcn30_afmt_registers afmt_regs[] = { 316 afmt_regs(0), 317 afmt_regs(1), 318 afmt_regs(2), 319 afmt_regs(3), 320 afmt_regs(4), 321 afmt_regs(5) 322 }; 323 324 static const struct dcn30_afmt_shift afmt_shift = { 325 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 326 }; 327 328 static const struct dcn30_afmt_mask afmt_mask = { 329 DCN3_AFMT_MASK_SH_LIST(_MASK) 330 }; 331 332 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 333 { 334 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 335 336 if (!afmt3) 337 return NULL; 338 339 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 340 341 return &afmt3->base; 342 } 343 344 #define audio_regs(id)\ 345 [id] = { AUD_COMMON_REG_LIST(id) } 346 347 static const struct dce_audio_registers audio_regs[] = { 348 audio_regs(0), 349 audio_regs(1), 350 audio_regs(2), 351 audio_regs(3), 352 audio_regs(4), 353 audio_regs(5), 354 audio_regs(6) 355 }; 356 357 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 358 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 359 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 360 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 361 362 static const struct dce_audio_shift audio_shift = { 363 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 364 }; 365 366 static const struct dce_audio_mask audio_mask = { 367 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 368 }; 369 370 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 371 { 372 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 373 } 374 375 #define stream_enc_regs(id)\ 376 [id] = { SE_DCN3_REG_LIST(id) } 377 378 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 379 stream_enc_regs(0), 380 stream_enc_regs(1), 381 stream_enc_regs(2), 382 stream_enc_regs(3), 383 stream_enc_regs(4) 384 }; 385 386 static const struct dcn10_stream_encoder_shift se_shift = { 387 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 388 }; 389 390 static const struct dcn10_stream_encoder_mask se_mask = { 391 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 392 }; 393 394 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 395 { 396 struct dcn10_stream_encoder *enc1; 397 struct vpg *vpg; 398 struct afmt *afmt; 399 int vpg_inst; 400 int afmt_inst; 401 402 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 403 if (eng_id <= ENGINE_ID_DIGE) { 404 vpg_inst = eng_id; 405 afmt_inst = eng_id; 406 } else 407 return NULL; 408 409 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 410 vpg = dcn302_vpg_create(ctx, vpg_inst); 411 afmt = dcn302_afmt_create(ctx, afmt_inst); 412 413 if (!enc1 || !vpg || !afmt) { 414 kfree(enc1); 415 kfree(vpg); 416 kfree(afmt); 417 return NULL; 418 } 419 420 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 421 &se_shift, &se_mask); 422 423 return &enc1->base; 424 } 425 426 #define clk_src_regs(index, pllid)\ 427 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 428 429 static const struct dce110_clk_src_regs clk_src_regs[] = { 430 clk_src_regs(0, A), 431 clk_src_regs(1, B), 432 clk_src_regs(2, C), 433 clk_src_regs(3, D), 434 clk_src_regs(4, E) 435 }; 436 437 static const struct dce110_clk_src_shift cs_shift = { 438 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 439 }; 440 441 static const struct dce110_clk_src_mask cs_mask = { 442 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 443 }; 444 445 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 446 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 447 { 448 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 449 450 if (!clk_src) 451 return NULL; 452 453 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 454 clk_src->base.dp_clk_src = dp_clk_src; 455 return &clk_src->base; 456 } 457 458 BREAK_TO_DEBUGGER(); 459 return NULL; 460 } 461 462 static const struct dce_hwseq_registers hwseq_reg = { 463 HWSEQ_DCN302_REG_LIST() 464 }; 465 466 static const struct dce_hwseq_shift hwseq_shift = { 467 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 468 }; 469 470 static const struct dce_hwseq_mask hwseq_mask = { 471 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 472 }; 473 474 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 475 { 476 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 477 478 if (hws) { 479 hws->ctx = ctx; 480 hws->regs = &hwseq_reg; 481 hws->shifts = &hwseq_shift; 482 hws->masks = &hwseq_mask; 483 } 484 return hws; 485 } 486 487 #define hubp_regs(id)\ 488 [id] = { HUBP_REG_LIST_DCN30(id) } 489 490 static const struct dcn_hubp2_registers hubp_regs[] = { 491 hubp_regs(0), 492 hubp_regs(1), 493 hubp_regs(2), 494 hubp_regs(3), 495 hubp_regs(4) 496 }; 497 498 static const struct dcn_hubp2_shift hubp_shift = { 499 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 500 }; 501 502 static const struct dcn_hubp2_mask hubp_mask = { 503 HUBP_MASK_SH_LIST_DCN30(_MASK) 504 }; 505 506 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 507 { 508 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 509 510 if (!hubp2) 511 return NULL; 512 513 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 514 return &hubp2->base; 515 516 BREAK_TO_DEBUGGER(); 517 kfree(hubp2); 518 return NULL; 519 } 520 521 #define dpp_regs(id)\ 522 [id] = { DPP_REG_LIST_DCN30(id) } 523 524 static const struct dcn3_dpp_registers dpp_regs[] = { 525 dpp_regs(0), 526 dpp_regs(1), 527 dpp_regs(2), 528 dpp_regs(3), 529 dpp_regs(4) 530 }; 531 532 static const struct dcn3_dpp_shift tf_shift = { 533 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 534 }; 535 536 static const struct dcn3_dpp_mask tf_mask = { 537 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 538 }; 539 540 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 541 { 542 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 543 544 if (!dpp) 545 return NULL; 546 547 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 548 return &dpp->base; 549 550 BREAK_TO_DEBUGGER(); 551 kfree(dpp); 552 return NULL; 553 } 554 555 #define opp_regs(id)\ 556 [id] = { OPP_REG_LIST_DCN30(id) } 557 558 static const struct dcn20_opp_registers opp_regs[] = { 559 opp_regs(0), 560 opp_regs(1), 561 opp_regs(2), 562 opp_regs(3), 563 opp_regs(4) 564 }; 565 566 static const struct dcn20_opp_shift opp_shift = { 567 OPP_MASK_SH_LIST_DCN20(__SHIFT) 568 }; 569 570 static const struct dcn20_opp_mask opp_mask = { 571 OPP_MASK_SH_LIST_DCN20(_MASK) 572 }; 573 574 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 575 { 576 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 577 578 if (!opp) { 579 BREAK_TO_DEBUGGER(); 580 return NULL; 581 } 582 583 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 584 return &opp->base; 585 } 586 587 #define optc_regs(id)\ 588 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 589 590 static const struct dcn_optc_registers optc_regs[] = { 591 optc_regs(0), 592 optc_regs(1), 593 optc_regs(2), 594 optc_regs(3), 595 optc_regs(4) 596 }; 597 598 static const struct dcn_optc_shift optc_shift = { 599 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 600 }; 601 602 static const struct dcn_optc_mask optc_mask = { 603 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 604 }; 605 606 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 607 { 608 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 609 610 if (!tgn10) 611 return NULL; 612 613 tgn10->base.inst = instance; 614 tgn10->base.ctx = ctx; 615 616 tgn10->tg_regs = &optc_regs[instance]; 617 tgn10->tg_shift = &optc_shift; 618 tgn10->tg_mask = &optc_mask; 619 620 dcn30_timing_generator_init(tgn10); 621 622 return &tgn10->base; 623 } 624 625 static const struct dcn30_mpc_registers mpc_regs = { 626 MPC_REG_LIST_DCN3_0(0), 627 MPC_REG_LIST_DCN3_0(1), 628 MPC_REG_LIST_DCN3_0(2), 629 MPC_REG_LIST_DCN3_0(3), 630 MPC_REG_LIST_DCN3_0(4), 631 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 632 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 633 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 634 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 635 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 636 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 637 MPC_RMU_REG_LIST_DCN3AG(0), 638 MPC_RMU_REG_LIST_DCN3AG(1), 639 MPC_RMU_REG_LIST_DCN3AG(2), 640 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 641 }; 642 643 static const struct dcn30_mpc_shift mpc_shift = { 644 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 645 }; 646 647 static const struct dcn30_mpc_mask mpc_mask = { 648 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 649 }; 650 651 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 652 { 653 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 654 655 if (!mpc30) 656 return NULL; 657 658 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 659 660 return &mpc30->base; 661 } 662 663 #define dsc_regsDCN20(id)\ 664 [id] = { DSC_REG_LIST_DCN20(id) } 665 666 static const struct dcn20_dsc_registers dsc_regs[] = { 667 dsc_regsDCN20(0), 668 dsc_regsDCN20(1), 669 dsc_regsDCN20(2), 670 dsc_regsDCN20(3), 671 dsc_regsDCN20(4) 672 }; 673 674 static const struct dcn20_dsc_shift dsc_shift = { 675 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 676 }; 677 678 static const struct dcn20_dsc_mask dsc_mask = { 679 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 680 }; 681 682 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 683 { 684 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 685 686 if (!dsc) { 687 BREAK_TO_DEBUGGER(); 688 return NULL; 689 } 690 691 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 692 return &dsc->base; 693 } 694 695 #define dwbc_regs_dcn3(id)\ 696 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 697 698 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 699 dwbc_regs_dcn3(0) 700 }; 701 702 static const struct dcn30_dwbc_shift dwbc30_shift = { 703 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 704 }; 705 706 static const struct dcn30_dwbc_mask dwbc30_mask = { 707 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 708 }; 709 710 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 711 { 712 int i; 713 uint32_t pipe_count = pool->res_cap->num_dwb; 714 715 for (i = 0; i < pipe_count; i++) { 716 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 717 718 if (!dwbc30) { 719 dm_error("DC: failed to create dwbc30!\n"); 720 return false; 721 } 722 723 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 724 725 pool->dwbc[i] = &dwbc30->base; 726 } 727 return true; 728 } 729 730 #define mcif_wb_regs_dcn3(id)\ 731 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 732 733 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 734 mcif_wb_regs_dcn3(0) 735 }; 736 737 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 738 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 739 }; 740 741 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 742 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 743 }; 744 745 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 746 { 747 int i; 748 uint32_t pipe_count = pool->res_cap->num_dwb; 749 750 for (i = 0; i < pipe_count; i++) { 751 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 752 753 if (!mcif_wb30) { 754 dm_error("DC: failed to create mcif_wb30!\n"); 755 return false; 756 } 757 758 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 759 760 pool->mcif_wb[i] = &mcif_wb30->base; 761 } 762 return true; 763 } 764 765 #define aux_engine_regs(id)\ 766 [id] = {\ 767 AUX_COMMON_REG_LIST0(id), \ 768 .AUXN_IMPCAL = 0, \ 769 .AUXP_IMPCAL = 0, \ 770 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 771 } 772 773 static const struct dce110_aux_registers aux_engine_regs[] = { 774 aux_engine_regs(0), 775 aux_engine_regs(1), 776 aux_engine_regs(2), 777 aux_engine_regs(3), 778 aux_engine_regs(4) 779 }; 780 781 static const struct dce110_aux_registers_shift aux_shift = { 782 DCN_AUX_MASK_SH_LIST(__SHIFT) 783 }; 784 785 static const struct dce110_aux_registers_mask aux_mask = { 786 DCN_AUX_MASK_SH_LIST(_MASK) 787 }; 788 789 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 790 { 791 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 792 793 if (!aux_engine) 794 return NULL; 795 796 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 797 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 798 799 return &aux_engine->base; 800 } 801 802 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 803 804 static const struct dce_i2c_registers i2c_hw_regs[] = { 805 i2c_inst_regs(1), 806 i2c_inst_regs(2), 807 i2c_inst_regs(3), 808 i2c_inst_regs(4), 809 i2c_inst_regs(5) 810 }; 811 812 static const struct dce_i2c_shift i2c_shifts = { 813 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 814 }; 815 816 static const struct dce_i2c_mask i2c_masks = { 817 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 818 }; 819 820 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 821 { 822 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 823 824 if (!dce_i2c_hw) 825 return NULL; 826 827 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 828 829 return dce_i2c_hw; 830 } 831 832 static const struct encoder_feature_support link_enc_feature = { 833 .max_hdmi_deep_color = COLOR_DEPTH_121212, 834 .max_hdmi_pixel_clock = 600000, 835 .hdmi_ycbcr420_supported = true, 836 .dp_ycbcr420_supported = true, 837 .fec_supported = true, 838 .flags.bits.IS_HBR2_CAPABLE = true, 839 .flags.bits.IS_HBR3_CAPABLE = true, 840 .flags.bits.IS_TPS3_CAPABLE = true, 841 .flags.bits.IS_TPS4_CAPABLE = true 842 }; 843 844 #define link_regs(id, phyid)\ 845 [id] = {\ 846 LE_DCN3_REG_LIST(id), \ 847 UNIPHY_DCN2_REG_LIST(phyid), \ 848 DPCS_DCN2_REG_LIST(id), \ 849 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 850 } 851 852 static const struct dcn10_link_enc_registers link_enc_regs[] = { 853 link_regs(0, A), 854 link_regs(1, B), 855 link_regs(2, C), 856 link_regs(3, D), 857 link_regs(4, E) 858 }; 859 860 static const struct dcn10_link_enc_shift le_shift = { 861 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 862 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 863 }; 864 865 static const struct dcn10_link_enc_mask le_mask = { 866 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 867 DPCS_DCN2_MASK_SH_LIST(_MASK) 868 }; 869 870 #define aux_regs(id)\ 871 [id] = { DCN2_AUX_REG_LIST(id) } 872 873 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 874 aux_regs(0), 875 aux_regs(1), 876 aux_regs(2), 877 aux_regs(3), 878 aux_regs(4) 879 }; 880 881 #define hpd_regs(id)\ 882 [id] = { HPD_REG_LIST(id) } 883 884 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 885 hpd_regs(0), 886 hpd_regs(1), 887 hpd_regs(2), 888 hpd_regs(3), 889 hpd_regs(4) 890 }; 891 892 static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data) 893 { 894 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 895 896 if (!enc20) 897 return NULL; 898 899 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 900 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 901 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 902 903 return &enc20->enc10.base; 904 } 905 906 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 907 { DCN_PANEL_CNTL_REG_LIST() } 908 }; 909 910 static const struct dce_panel_cntl_shift panel_cntl_shift = { 911 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 912 }; 913 914 static const struct dce_panel_cntl_mask panel_cntl_mask = { 915 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 916 }; 917 918 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 919 { 920 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 921 922 if (!panel_cntl) 923 return NULL; 924 925 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 926 &panel_cntl_shift, &panel_cntl_mask); 927 928 return &panel_cntl->base; 929 } 930 931 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 932 { 933 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 934 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 935 } 936 937 static const struct resource_create_funcs res_create_funcs = { 938 .read_dce_straps = read_dce_straps, 939 .create_audio = dcn302_create_audio, 940 .create_stream_encoder = dcn302_stream_encoder_create, 941 .create_hwseq = dcn302_hwseq_create, 942 }; 943 944 static const struct resource_create_funcs res_create_maximus_funcs = { 945 .read_dce_straps = NULL, 946 .create_audio = NULL, 947 .create_stream_encoder = NULL, 948 .create_hwseq = dcn302_hwseq_create, 949 }; 950 951 static bool is_soc_bounding_box_valid(struct dc *dc) 952 { 953 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 954 955 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 956 return true; 957 958 return false; 959 } 960 961 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 962 { 963 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 964 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 965 966 DC_LOGGER_INIT(dc->ctx->logger); 967 968 if (!is_soc_bounding_box_valid(dc)) { 969 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 970 return false; 971 } 972 973 loaded_ip->max_num_otg = pool->pipe_count; 974 loaded_ip->max_num_dpp = pool->pipe_count; 975 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 976 DC_FP_START(); 977 dcn20_patch_bounding_box(dc, loaded_bb); 978 DC_FP_END(); 979 980 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 981 struct bp_soc_bb_info bb_info = { 0 }; 982 983 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 984 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 985 986 DC_FP_START(); 987 dcn302_fpu_init_soc_bounding_box(bb_info); 988 DC_FP_END(); 989 } 990 } 991 992 return true; 993 } 994 995 static void dcn302_resource_destruct(struct resource_pool *pool) 996 { 997 unsigned int i; 998 999 for (i = 0; i < pool->stream_enc_count; i++) { 1000 if (pool->stream_enc[i] != NULL) { 1001 if (pool->stream_enc[i]->vpg != NULL) { 1002 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1003 pool->stream_enc[i]->vpg = NULL; 1004 } 1005 if (pool->stream_enc[i]->afmt != NULL) { 1006 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1007 pool->stream_enc[i]->afmt = NULL; 1008 } 1009 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1010 pool->stream_enc[i] = NULL; 1011 } 1012 } 1013 1014 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1015 if (pool->dscs[i] != NULL) 1016 dcn20_dsc_destroy(&pool->dscs[i]); 1017 } 1018 1019 if (pool->mpc != NULL) { 1020 kfree(TO_DCN20_MPC(pool->mpc)); 1021 pool->mpc = NULL; 1022 } 1023 1024 if (pool->hubbub != NULL) { 1025 kfree(pool->hubbub); 1026 pool->hubbub = NULL; 1027 } 1028 1029 for (i = 0; i < pool->pipe_count; i++) { 1030 if (pool->dpps[i] != NULL) { 1031 kfree(TO_DCN20_DPP(pool->dpps[i])); 1032 pool->dpps[i] = NULL; 1033 } 1034 1035 if (pool->hubps[i] != NULL) { 1036 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1037 pool->hubps[i] = NULL; 1038 } 1039 1040 if (pool->irqs != NULL) 1041 dal_irq_service_destroy(&pool->irqs); 1042 } 1043 1044 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1045 if (pool->engines[i] != NULL) 1046 dce110_engine_destroy(&pool->engines[i]); 1047 if (pool->hw_i2cs[i] != NULL) { 1048 kfree(pool->hw_i2cs[i]); 1049 pool->hw_i2cs[i] = NULL; 1050 } 1051 if (pool->sw_i2cs[i] != NULL) { 1052 kfree(pool->sw_i2cs[i]); 1053 pool->sw_i2cs[i] = NULL; 1054 } 1055 } 1056 1057 for (i = 0; i < pool->res_cap->num_opp; i++) { 1058 if (pool->opps[i] != NULL) 1059 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1060 } 1061 1062 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1063 if (pool->timing_generators[i] != NULL) { 1064 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1065 pool->timing_generators[i] = NULL; 1066 } 1067 } 1068 1069 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1070 if (pool->dwbc[i] != NULL) { 1071 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1072 pool->dwbc[i] = NULL; 1073 } 1074 if (pool->mcif_wb[i] != NULL) { 1075 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1076 pool->mcif_wb[i] = NULL; 1077 } 1078 } 1079 1080 for (i = 0; i < pool->audio_count; i++) { 1081 if (pool->audios[i]) 1082 dce_aud_destroy(&pool->audios[i]); 1083 } 1084 1085 for (i = 0; i < pool->clk_src_count; i++) { 1086 if (pool->clock_sources[i] != NULL) 1087 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1088 } 1089 1090 if (pool->dp_clock_source != NULL) 1091 dcn20_clock_source_destroy(&pool->dp_clock_source); 1092 1093 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1094 if (pool->mpc_lut[i] != NULL) { 1095 dc_3dlut_func_release(pool->mpc_lut[i]); 1096 pool->mpc_lut[i] = NULL; 1097 } 1098 if (pool->mpc_shaper[i] != NULL) { 1099 dc_transfer_func_release(pool->mpc_shaper[i]); 1100 pool->mpc_shaper[i] = NULL; 1101 } 1102 } 1103 1104 for (i = 0; i < pool->pipe_count; i++) { 1105 if (pool->multiple_abms[i] != NULL) 1106 dce_abm_destroy(&pool->multiple_abms[i]); 1107 } 1108 1109 if (pool->psr != NULL) 1110 dmub_psr_destroy(&pool->psr); 1111 1112 if (pool->dccg != NULL) 1113 dcn_dccg_destroy(&pool->dccg); 1114 } 1115 1116 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1117 { 1118 dcn302_resource_destruct(*pool); 1119 kfree(*pool); 1120 *pool = NULL; 1121 } 1122 1123 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1124 { 1125 DC_FP_START(); 1126 dcn302_fpu_update_bw_bounding_box(dc, bw_params); 1127 DC_FP_END(); 1128 } 1129 1130 static struct resource_funcs dcn302_res_pool_funcs = { 1131 .destroy = dcn302_destroy_resource_pool, 1132 .link_enc_create = dcn302_link_encoder_create, 1133 .panel_cntl_create = dcn302_panel_cntl_create, 1134 .validate_bandwidth = dcn30_validate_bandwidth, 1135 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1136 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1137 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1138 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1139 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1140 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1141 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1142 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1143 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1144 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1145 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1146 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1147 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1148 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1149 }; 1150 1151 static struct dc_cap_funcs cap_funcs = { 1152 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1153 }; 1154 1155 static const struct bios_registers bios_regs = { 1156 NBIO_SR(BIOS_SCRATCH_3), 1157 NBIO_SR(BIOS_SCRATCH_6) 1158 }; 1159 1160 static const struct dccg_registers dccg_regs = { 1161 DCCG_REG_LIST_DCN3_02() 1162 }; 1163 1164 static const struct dccg_shift dccg_shift = { 1165 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1166 }; 1167 1168 static const struct dccg_mask dccg_mask = { 1169 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1170 }; 1171 1172 #define abm_regs(id)\ 1173 [id] = { ABM_DCN302_REG_LIST(id) } 1174 1175 static const struct dce_abm_registers abm_regs[] = { 1176 abm_regs(0), 1177 abm_regs(1), 1178 abm_regs(2), 1179 abm_regs(3), 1180 abm_regs(4) 1181 }; 1182 1183 static const struct dce_abm_shift abm_shift = { 1184 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1185 }; 1186 1187 static const struct dce_abm_mask abm_mask = { 1188 ABM_MASK_SH_LIST_DCN30(_MASK) 1189 }; 1190 1191 static bool dcn302_resource_construct( 1192 uint8_t num_virtual_links, 1193 struct dc *dc, 1194 struct resource_pool *pool) 1195 { 1196 int i; 1197 struct dc_context *ctx = dc->ctx; 1198 struct irq_service_init_data init_data; 1199 1200 ctx->dc_bios->regs = &bios_regs; 1201 1202 pool->res_cap = &res_cap_dcn302; 1203 1204 pool->funcs = &dcn302_res_pool_funcs; 1205 1206 /************************************************* 1207 * Resource + asic cap harcoding * 1208 *************************************************/ 1209 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1210 pool->pipe_count = pool->res_cap->num_timing_generator; 1211 pool->mpcc_count = pool->res_cap->num_timing_generator; 1212 dc->caps.max_downscale_ratio = 600; 1213 dc->caps.i2c_speed_in_khz = 100; 1214 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1215 dc->caps.max_cursor_size = 256; 1216 dc->caps.min_horizontal_blanking_period = 80; 1217 dc->caps.dmdata_alloc_size = 2048; 1218 dc->caps.mall_size_per_mem_channel = 4; 1219 /* total size = mall per channel * num channels * 1024 * 1024 */ 1220 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1221 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1222 dc->caps.max_slave_planes = 1; 1223 dc->caps.max_slave_yuv_planes = 1; 1224 dc->caps.max_slave_rgb_planes = 1; 1225 dc->caps.post_blend_color_processing = true; 1226 dc->caps.force_dp_tps4_for_cp2520 = true; 1227 dc->caps.extended_aux_timeout_support = true; 1228 dc->caps.dmcub_support = true; 1229 1230 /* Color pipeline capabilities */ 1231 dc->caps.color.dpp.dcn_arch = 1; 1232 dc->caps.color.dpp.input_lut_shared = 0; 1233 dc->caps.color.dpp.icsc = 1; 1234 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1235 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1236 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1237 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1238 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1239 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1240 dc->caps.color.dpp.post_csc = 1; 1241 dc->caps.color.dpp.gamma_corr = 1; 1242 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1243 1244 dc->caps.color.dpp.hw_3d_lut = 1; 1245 dc->caps.color.dpp.ogam_ram = 1; 1246 // no OGAM ROM on DCN3 1247 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1248 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1249 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1250 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1251 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1252 dc->caps.color.dpp.ocsc = 0; 1253 1254 dc->caps.color.mpc.gamut_remap = 1; 1255 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1256 dc->caps.color.mpc.ogam_ram = 1; 1257 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1258 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1259 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1260 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1261 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1262 dc->caps.color.mpc.ocsc = 1; 1263 1264 /* read VBIOS LTTPR caps */ 1265 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1266 enum bp_result bp_query_result; 1267 uint8_t is_vbios_lttpr_enable = 0; 1268 1269 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1270 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1271 } 1272 1273 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1274 enum bp_result bp_query_result; 1275 uint8_t is_vbios_interop_enabled = 0; 1276 1277 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 1278 &is_vbios_interop_enabled); 1279 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1280 } 1281 1282 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1283 dc->debug = debug_defaults_drv; 1284 else 1285 dc->debug = debug_defaults_diags; 1286 1287 // Init the vm_helper 1288 if (dc->vm_helper) 1289 vm_helper_init(dc->vm_helper, 16); 1290 1291 /************************************************* 1292 * Create resources * 1293 *************************************************/ 1294 1295 /* Clock Sources for Pixel Clock*/ 1296 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1297 dcn302_clock_source_create(ctx, ctx->dc_bios, 1298 CLOCK_SOURCE_COMBO_PHY_PLL0, 1299 &clk_src_regs[0], false); 1300 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1301 dcn302_clock_source_create(ctx, ctx->dc_bios, 1302 CLOCK_SOURCE_COMBO_PHY_PLL1, 1303 &clk_src_regs[1], false); 1304 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1305 dcn302_clock_source_create(ctx, ctx->dc_bios, 1306 CLOCK_SOURCE_COMBO_PHY_PLL2, 1307 &clk_src_regs[2], false); 1308 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1309 dcn302_clock_source_create(ctx, ctx->dc_bios, 1310 CLOCK_SOURCE_COMBO_PHY_PLL3, 1311 &clk_src_regs[3], false); 1312 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1313 dcn302_clock_source_create(ctx, ctx->dc_bios, 1314 CLOCK_SOURCE_COMBO_PHY_PLL4, 1315 &clk_src_regs[4], false); 1316 1317 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1318 1319 /* todo: not reuse phy_pll registers */ 1320 pool->dp_clock_source = 1321 dcn302_clock_source_create(ctx, ctx->dc_bios, 1322 CLOCK_SOURCE_ID_DP_DTO, 1323 &clk_src_regs[0], true); 1324 1325 for (i = 0; i < pool->clk_src_count; i++) { 1326 if (pool->clock_sources[i] == NULL) { 1327 dm_error("DC: failed to create clock sources!\n"); 1328 BREAK_TO_DEBUGGER(); 1329 goto create_fail; 1330 } 1331 } 1332 1333 /* DCCG */ 1334 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1335 if (pool->dccg == NULL) { 1336 dm_error("DC: failed to create dccg!\n"); 1337 BREAK_TO_DEBUGGER(); 1338 goto create_fail; 1339 } 1340 1341 /* PP Lib and SMU interfaces */ 1342 init_soc_bounding_box(dc, pool); 1343 1344 /* DML */ 1345 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1346 1347 /* IRQ */ 1348 init_data.ctx = dc->ctx; 1349 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1350 if (!pool->irqs) 1351 goto create_fail; 1352 1353 /* HUBBUB */ 1354 pool->hubbub = dcn302_hubbub_create(ctx); 1355 if (pool->hubbub == NULL) { 1356 BREAK_TO_DEBUGGER(); 1357 dm_error("DC: failed to create hubbub!\n"); 1358 goto create_fail; 1359 } 1360 1361 /* HUBPs, DPPs, OPPs and TGs */ 1362 for (i = 0; i < pool->pipe_count; i++) { 1363 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1364 if (pool->hubps[i] == NULL) { 1365 BREAK_TO_DEBUGGER(); 1366 dm_error("DC: failed to create hubps!\n"); 1367 goto create_fail; 1368 } 1369 1370 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1371 if (pool->dpps[i] == NULL) { 1372 BREAK_TO_DEBUGGER(); 1373 dm_error("DC: failed to create dpps!\n"); 1374 goto create_fail; 1375 } 1376 } 1377 1378 for (i = 0; i < pool->res_cap->num_opp; i++) { 1379 pool->opps[i] = dcn302_opp_create(ctx, i); 1380 if (pool->opps[i] == NULL) { 1381 BREAK_TO_DEBUGGER(); 1382 dm_error("DC: failed to create output pixel processor!\n"); 1383 goto create_fail; 1384 } 1385 } 1386 1387 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1388 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1389 if (pool->timing_generators[i] == NULL) { 1390 BREAK_TO_DEBUGGER(); 1391 dm_error("DC: failed to create tg!\n"); 1392 goto create_fail; 1393 } 1394 } 1395 pool->timing_generator_count = i; 1396 1397 /* PSR */ 1398 pool->psr = dmub_psr_create(ctx); 1399 if (pool->psr == NULL) { 1400 dm_error("DC: failed to create psr!\n"); 1401 BREAK_TO_DEBUGGER(); 1402 goto create_fail; 1403 } 1404 1405 /* ABMs */ 1406 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1407 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1408 if (pool->multiple_abms[i] == NULL) { 1409 dm_error("DC: failed to create abm for pipe %d!\n", i); 1410 BREAK_TO_DEBUGGER(); 1411 goto create_fail; 1412 } 1413 } 1414 1415 /* MPC and DSC */ 1416 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1417 if (pool->mpc == NULL) { 1418 BREAK_TO_DEBUGGER(); 1419 dm_error("DC: failed to create mpc!\n"); 1420 goto create_fail; 1421 } 1422 1423 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1424 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1425 if (pool->dscs[i] == NULL) { 1426 BREAK_TO_DEBUGGER(); 1427 dm_error("DC: failed to create display stream compressor %d!\n", i); 1428 goto create_fail; 1429 } 1430 } 1431 1432 /* DWB and MMHUBBUB */ 1433 if (!dcn302_dwbc_create(ctx, pool)) { 1434 BREAK_TO_DEBUGGER(); 1435 dm_error("DC: failed to create dwbc!\n"); 1436 goto create_fail; 1437 } 1438 1439 if (!dcn302_mmhubbub_create(ctx, pool)) { 1440 BREAK_TO_DEBUGGER(); 1441 dm_error("DC: failed to create mcif_wb!\n"); 1442 goto create_fail; 1443 } 1444 1445 /* AUX and I2C */ 1446 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1447 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1448 if (pool->engines[i] == NULL) { 1449 BREAK_TO_DEBUGGER(); 1450 dm_error("DC:failed to create aux engine!!\n"); 1451 goto create_fail; 1452 } 1453 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1454 if (pool->hw_i2cs[i] == NULL) { 1455 BREAK_TO_DEBUGGER(); 1456 dm_error("DC:failed to create hw i2c!!\n"); 1457 goto create_fail; 1458 } 1459 pool->sw_i2cs[i] = NULL; 1460 } 1461 1462 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1463 if (!resource_construct(num_virtual_links, dc, pool, 1464 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1465 &res_create_funcs : &res_create_maximus_funcs))) 1466 goto create_fail; 1467 1468 /* HW Sequencer and Plane caps */ 1469 dcn302_hw_sequencer_construct(dc); 1470 1471 dc->caps.max_planes = pool->pipe_count; 1472 1473 for (i = 0; i < dc->caps.max_planes; ++i) 1474 dc->caps.planes[i] = plane_cap; 1475 1476 dc->cap_funcs = cap_funcs; 1477 1478 return true; 1479 1480 create_fail: 1481 1482 dcn302_resource_destruct(pool); 1483 1484 return false; 1485 } 1486 1487 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1488 { 1489 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1490 1491 if (!pool) 1492 return NULL; 1493 1494 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1495 return pool; 1496 1497 BREAK_TO_DEBUGGER(); 1498 kfree(pool); 1499 return NULL; 1500 } 1501