136d26912SBhawanpreet Lakha /* 236d26912SBhawanpreet Lakha * Copyright 2020 Advanced Micro Devices, Inc. 336d26912SBhawanpreet Lakha * 436d26912SBhawanpreet Lakha * Permission is hereby granted, free of charge, to any person obtaining a 536d26912SBhawanpreet Lakha * copy of this software and associated documentation files (the "Software"), 636d26912SBhawanpreet Lakha * to deal in the Software without restriction, including without limitation 736d26912SBhawanpreet Lakha * the rights to use, copy, modify, merge, publish, distribute, sublicense, 836d26912SBhawanpreet Lakha * and/or sell copies of the Software, and to permit persons to whom the 936d26912SBhawanpreet Lakha * Software is furnished to do so, subject to the following conditions: 1036d26912SBhawanpreet Lakha * 1136d26912SBhawanpreet Lakha * The above copyright notice and this permission notice shall be included in 1236d26912SBhawanpreet Lakha * all copies or substantial portions of the Software. 1336d26912SBhawanpreet Lakha * 1436d26912SBhawanpreet Lakha * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1536d26912SBhawanpreet Lakha * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1636d26912SBhawanpreet Lakha * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1736d26912SBhawanpreet Lakha * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1836d26912SBhawanpreet Lakha * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1936d26912SBhawanpreet Lakha * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2036d26912SBhawanpreet Lakha * OTHER DEALINGS IN THE SOFTWARE. 2136d26912SBhawanpreet Lakha * 2236d26912SBhawanpreet Lakha * Authors: AMD 2336d26912SBhawanpreet Lakha * 2436d26912SBhawanpreet Lakha */ 2536d26912SBhawanpreet Lakha 2636d26912SBhawanpreet Lakha #include "dcn302_init.h" 2736d26912SBhawanpreet Lakha #include "dcn302_resource.h" 2836d26912SBhawanpreet Lakha #include "dcn302_dccg.h" 2936d26912SBhawanpreet Lakha #include "irq/dcn302/irq_service_dcn302.h" 3036d26912SBhawanpreet Lakha 3136d26912SBhawanpreet Lakha #include "dcn30/dcn30_dio_link_encoder.h" 3236d26912SBhawanpreet Lakha #include "dcn30/dcn30_dio_stream_encoder.h" 3336d26912SBhawanpreet Lakha #include "dcn30/dcn30_dwb.h" 3436d26912SBhawanpreet Lakha #include "dcn30/dcn30_dpp.h" 3536d26912SBhawanpreet Lakha #include "dcn30/dcn30_hubbub.h" 3636d26912SBhawanpreet Lakha #include "dcn30/dcn30_hubp.h" 3736d26912SBhawanpreet Lakha #include "dcn30/dcn30_mmhubbub.h" 3836d26912SBhawanpreet Lakha #include "dcn30/dcn30_mpc.h" 3936d26912SBhawanpreet Lakha #include "dcn30/dcn30_opp.h" 4036d26912SBhawanpreet Lakha #include "dcn30/dcn30_optc.h" 4136d26912SBhawanpreet Lakha #include "dcn30/dcn30_resource.h" 4236d26912SBhawanpreet Lakha 4336d26912SBhawanpreet Lakha #include "dcn20/dcn20_dsc.h" 4436d26912SBhawanpreet Lakha #include "dcn20/dcn20_resource.h" 4536d26912SBhawanpreet Lakha 4636d26912SBhawanpreet Lakha #include "dcn10/dcn10_resource.h" 4736d26912SBhawanpreet Lakha 4836d26912SBhawanpreet Lakha #include "dce/dce_abm.h" 4936d26912SBhawanpreet Lakha #include "dce/dce_audio.h" 5036d26912SBhawanpreet Lakha #include "dce/dce_aux.h" 5136d26912SBhawanpreet Lakha #include "dce/dce_clock_source.h" 5236d26912SBhawanpreet Lakha #include "dce/dce_hwseq.h" 5336d26912SBhawanpreet Lakha #include "dce/dce_i2c_hw.h" 5436d26912SBhawanpreet Lakha #include "dce/dce_panel_cntl.h" 5536d26912SBhawanpreet Lakha #include "dce/dmub_abm.h" 5665e05ca7SJoshua Aberback #include "dce/dmub_psr.h" 57163e3bcbSSamson Tam #include "clk_mgr.h" 5836d26912SBhawanpreet Lakha 5936d26912SBhawanpreet Lakha #include "hw_sequencer_private.h" 6036d26912SBhawanpreet Lakha #include "reg_helper.h" 6136d26912SBhawanpreet Lakha #include "resource.h" 6236d26912SBhawanpreet Lakha #include "vm_helper.h" 6336d26912SBhawanpreet Lakha 6436d26912SBhawanpreet Lakha #include "dimgrey_cavefish_ip_offset.h" 659713158cSBhawanpreet Lakha #include "dcn/dcn_3_0_2_offset.h" 669713158cSBhawanpreet Lakha #include "dcn/dcn_3_0_2_sh_mask.h" 6736d26912SBhawanpreet Lakha #include "dcn/dpcs_3_0_0_offset.h" 6836d26912SBhawanpreet Lakha #include "dcn/dpcs_3_0_0_sh_mask.h" 6936d26912SBhawanpreet Lakha #include "nbio/nbio_7_4_offset.h" 7026d94a46SBhawanpreet Lakha #include "amdgpu_socbb.h" 7136d26912SBhawanpreet Lakha 7236d26912SBhawanpreet Lakha #define DC_LOGGER_INIT(logger) 7336d26912SBhawanpreet Lakha 7436d26912SBhawanpreet Lakha struct _vcs_dpi_ip_params_st dcn3_02_ip = { 7536d26912SBhawanpreet Lakha .use_min_dcfclk = 0, 7636d26912SBhawanpreet Lakha .clamp_min_dcfclk = 0, 7736d26912SBhawanpreet Lakha .odm_capable = 1, 7836d26912SBhawanpreet Lakha .gpuvm_enable = 1, 7936d26912SBhawanpreet Lakha .hostvm_enable = 0, 8036d26912SBhawanpreet Lakha .gpuvm_max_page_table_levels = 4, 8136d26912SBhawanpreet Lakha .hostvm_max_page_table_levels = 4, 8236d26912SBhawanpreet Lakha .hostvm_cached_page_table_levels = 0, 8336d26912SBhawanpreet Lakha .pte_group_size_bytes = 2048, 8436d26912SBhawanpreet Lakha .num_dsc = 5, 8536d26912SBhawanpreet Lakha .rob_buffer_size_kbytes = 184, 8636d26912SBhawanpreet Lakha .det_buffer_size_kbytes = 184, 8736d26912SBhawanpreet Lakha .dpte_buffer_size_in_pte_reqs_luma = 64, 8836d26912SBhawanpreet Lakha .dpte_buffer_size_in_pte_reqs_chroma = 34, 8936d26912SBhawanpreet Lakha .pde_proc_buffer_size_64k_reqs = 48, 9036d26912SBhawanpreet Lakha .dpp_output_buffer_pixels = 2560, 9136d26912SBhawanpreet Lakha .opp_output_buffer_lines = 1, 9236d26912SBhawanpreet Lakha .pixel_chunk_size_kbytes = 8, 9336d26912SBhawanpreet Lakha .pte_enable = 1, 9436d26912SBhawanpreet Lakha .max_page_table_levels = 2, 9536d26912SBhawanpreet Lakha .pte_chunk_size_kbytes = 2, // ? 9636d26912SBhawanpreet Lakha .meta_chunk_size_kbytes = 2, 9736d26912SBhawanpreet Lakha .writeback_chunk_size_kbytes = 8, 9836d26912SBhawanpreet Lakha .line_buffer_size_bits = 789504, 9936d26912SBhawanpreet Lakha .is_line_buffer_bpp_fixed = 0, // ? 10036d26912SBhawanpreet Lakha .line_buffer_fixed_bpp = 0, // ? 10136d26912SBhawanpreet Lakha .dcc_supported = true, 10236d26912SBhawanpreet Lakha .writeback_interface_buffer_size_kbytes = 90, 10336d26912SBhawanpreet Lakha .writeback_line_buffer_buffer_size = 0, 104234cc26fSDmytro Laktyushkin .max_line_buffer_lines = 12, 10536d26912SBhawanpreet Lakha .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 10636d26912SBhawanpreet Lakha .writeback_chroma_buffer_size_kbytes = 8, 10736d26912SBhawanpreet Lakha .writeback_chroma_line_buffer_width_pixels = 4, 10836d26912SBhawanpreet Lakha .writeback_max_hscl_ratio = 1, 10936d26912SBhawanpreet Lakha .writeback_max_vscl_ratio = 1, 11036d26912SBhawanpreet Lakha .writeback_min_hscl_ratio = 1, 11136d26912SBhawanpreet Lakha .writeback_min_vscl_ratio = 1, 11236d26912SBhawanpreet Lakha .writeback_max_hscl_taps = 1, 11336d26912SBhawanpreet Lakha .writeback_max_vscl_taps = 1, 11436d26912SBhawanpreet Lakha .writeback_line_buffer_luma_buffer_size = 0, 11536d26912SBhawanpreet Lakha .writeback_line_buffer_chroma_buffer_size = 14643, 11636d26912SBhawanpreet Lakha .cursor_buffer_size = 8, 11736d26912SBhawanpreet Lakha .cursor_chunk_size = 2, 11836d26912SBhawanpreet Lakha .max_num_otg = 5, 11936d26912SBhawanpreet Lakha .max_num_dpp = 5, 12036d26912SBhawanpreet Lakha .max_num_wb = 1, 12136d26912SBhawanpreet Lakha .max_dchub_pscl_bw_pix_per_clk = 4, 12236d26912SBhawanpreet Lakha .max_pscl_lb_bw_pix_per_clk = 2, 12336d26912SBhawanpreet Lakha .max_lb_vscl_bw_pix_per_clk = 4, 12436d26912SBhawanpreet Lakha .max_vscl_hscl_bw_pix_per_clk = 4, 12536d26912SBhawanpreet Lakha .max_hscl_ratio = 6, 12636d26912SBhawanpreet Lakha .max_vscl_ratio = 6, 12736d26912SBhawanpreet Lakha .hscl_mults = 4, 12836d26912SBhawanpreet Lakha .vscl_mults = 4, 12936d26912SBhawanpreet Lakha .max_hscl_taps = 8, 13036d26912SBhawanpreet Lakha .max_vscl_taps = 8, 13136d26912SBhawanpreet Lakha .dispclk_ramp_margin_percent = 1, 13236d26912SBhawanpreet Lakha .underscan_factor = 1.11, 13336d26912SBhawanpreet Lakha .min_vblank_lines = 32, 13436d26912SBhawanpreet Lakha .dppclk_delay_subtotal = 46, 13536d26912SBhawanpreet Lakha .dynamic_metadata_vm_enabled = true, 13636d26912SBhawanpreet Lakha .dppclk_delay_scl_lb_only = 16, 13736d26912SBhawanpreet Lakha .dppclk_delay_scl = 50, 13836d26912SBhawanpreet Lakha .dppclk_delay_cnvc_formatter = 27, 13936d26912SBhawanpreet Lakha .dppclk_delay_cnvc_cursor = 6, 14036d26912SBhawanpreet Lakha .dispclk_delay_subtotal = 119, 14136d26912SBhawanpreet Lakha .dcfclk_cstate_latency = 5.2, // SRExitTime 14236d26912SBhawanpreet Lakha .max_inter_dcn_tile_repeaters = 8, 14336d26912SBhawanpreet Lakha .max_num_hdmi_frl_outputs = 1, 14436d26912SBhawanpreet Lakha .odm_combine_4to1_supported = true, 14536d26912SBhawanpreet Lakha 14636d26912SBhawanpreet Lakha .xfc_supported = false, 14736d26912SBhawanpreet Lakha .xfc_fill_bw_overhead_percent = 10.0, 14836d26912SBhawanpreet Lakha .xfc_fill_constant_bytes = 0, 14936d26912SBhawanpreet Lakha .gfx7_compat_tiling_supported = 0, 15036d26912SBhawanpreet Lakha .number_of_cursors = 1, 15136d26912SBhawanpreet Lakha }; 15236d26912SBhawanpreet Lakha 15336d26912SBhawanpreet Lakha struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = { 15436d26912SBhawanpreet Lakha .clock_limits = { 15536d26912SBhawanpreet Lakha { 15636d26912SBhawanpreet Lakha .state = 0, 15736d26912SBhawanpreet Lakha .dispclk_mhz = 562.0, 15836d26912SBhawanpreet Lakha .dppclk_mhz = 300.0, 15936d26912SBhawanpreet Lakha .phyclk_mhz = 300.0, 16036d26912SBhawanpreet Lakha .phyclk_d18_mhz = 667.0, 16136d26912SBhawanpreet Lakha .dscclk_mhz = 405.6, 16236d26912SBhawanpreet Lakha }, 16336d26912SBhawanpreet Lakha }, 16436d26912SBhawanpreet Lakha 16536d26912SBhawanpreet Lakha .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 16636d26912SBhawanpreet Lakha .num_states = 1, 167ceaf9f57SAurabindo Pillai .sr_exit_time_us = 26.5, 168ceaf9f57SAurabindo Pillai .sr_enter_plus_exit_time_us = 31, 16936d26912SBhawanpreet Lakha .urgent_latency_us = 4.0, 17036d26912SBhawanpreet Lakha .urgent_latency_pixel_data_only_us = 4.0, 17136d26912SBhawanpreet Lakha .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 17236d26912SBhawanpreet Lakha .urgent_latency_vm_data_only_us = 4.0, 17336d26912SBhawanpreet Lakha .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 17436d26912SBhawanpreet Lakha .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 17536d26912SBhawanpreet Lakha .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 17636d26912SBhawanpreet Lakha .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 17736d26912SBhawanpreet Lakha .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 17836d26912SBhawanpreet Lakha .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 17936d26912SBhawanpreet Lakha .max_avg_sdp_bw_use_normal_percent = 60.0, 18036d26912SBhawanpreet Lakha .max_avg_dram_bw_use_normal_percent = 40.0, 18136d26912SBhawanpreet Lakha .writeback_latency_us = 12.0, 18236d26912SBhawanpreet Lakha .max_request_size_bytes = 256, 18336d26912SBhawanpreet Lakha .fabric_datapath_to_dcn_data_return_bytes = 64, 18436d26912SBhawanpreet Lakha .dcn_downspread_percent = 0.5, 18536d26912SBhawanpreet Lakha .downspread_percent = 0.38, 18636d26912SBhawanpreet Lakha .dram_page_open_time_ns = 50.0, 18736d26912SBhawanpreet Lakha .dram_rw_turnaround_time_ns = 17.5, 18836d26912SBhawanpreet Lakha .dram_return_buffer_per_channel_bytes = 8192, 18936d26912SBhawanpreet Lakha .round_trip_ping_latency_dcfclk_cycles = 156, 19036d26912SBhawanpreet Lakha .urgent_out_of_order_return_per_channel_bytes = 4096, 19136d26912SBhawanpreet Lakha .channel_interleave_bytes = 256, 19236d26912SBhawanpreet Lakha .num_banks = 8, 19336d26912SBhawanpreet Lakha .gpuvm_min_page_size_bytes = 4096, 19436d26912SBhawanpreet Lakha .hostvm_min_page_size_bytes = 4096, 195163e3bcbSSamson Tam .dram_clock_change_latency_us = 404, 19636d26912SBhawanpreet Lakha .dummy_pstate_latency_us = 5, 19736d26912SBhawanpreet Lakha .writeback_dram_clock_change_latency_us = 23.0, 19836d26912SBhawanpreet Lakha .return_bus_width_bytes = 64, 19936d26912SBhawanpreet Lakha .dispclk_dppclk_vco_speed_mhz = 3650, 20036d26912SBhawanpreet Lakha .xfc_bus_transport_time_us = 20, // ? 20136d26912SBhawanpreet Lakha .xfc_xbuf_latency_tolerance_us = 4, // ? 20236d26912SBhawanpreet Lakha .use_urgent_burst_bw = 1, // ? 20336d26912SBhawanpreet Lakha .do_urgent_latency_adjustment = true, 20436d26912SBhawanpreet Lakha .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 20536d26912SBhawanpreet Lakha .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 20636d26912SBhawanpreet Lakha }; 20736d26912SBhawanpreet Lakha 20836d26912SBhawanpreet Lakha static const struct dc_debug_options debug_defaults_drv = { 20936d26912SBhawanpreet Lakha .disable_dmcu = true, 21036d26912SBhawanpreet Lakha .force_abm_enable = false, 21136d26912SBhawanpreet Lakha .timing_trace = false, 21236d26912SBhawanpreet Lakha .clock_trace = true, 21336d26912SBhawanpreet Lakha .disable_pplib_clock_request = true, 214136e55e7SAric Cyr .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 21536d26912SBhawanpreet Lakha .force_single_disp_pipe_split = false, 21636d26912SBhawanpreet Lakha .disable_dcc = DCC_ENABLE, 21736d26912SBhawanpreet Lakha .vsr_support = true, 21836d26912SBhawanpreet Lakha .performance_trace = false, 21936d26912SBhawanpreet Lakha .max_downscale_src_width = 7680,/*upto 8K*/ 22036d26912SBhawanpreet Lakha .disable_pplib_wm_range = false, 22136d26912SBhawanpreet Lakha .scl_reset_length10 = true, 22236d26912SBhawanpreet Lakha .sanity_checks = false, 22336d26912SBhawanpreet Lakha .underflow_assert_delay_us = 0xFFFFFFFF, 22436d26912SBhawanpreet Lakha .dwb_fi_phase = -1, // -1 = disable, 22536d26912SBhawanpreet Lakha .dmub_command_table = true, 2269d335e17SDmytro Laktyushkin .use_max_lb = true 22736d26912SBhawanpreet Lakha }; 22836d26912SBhawanpreet Lakha 22936d26912SBhawanpreet Lakha static const struct dc_debug_options debug_defaults_diags = { 23036d26912SBhawanpreet Lakha .disable_dmcu = true, 23136d26912SBhawanpreet Lakha .force_abm_enable = false, 23236d26912SBhawanpreet Lakha .timing_trace = true, 23336d26912SBhawanpreet Lakha .clock_trace = true, 23436d26912SBhawanpreet Lakha .disable_dpp_power_gate = true, 23536d26912SBhawanpreet Lakha .disable_hubp_power_gate = true, 23636d26912SBhawanpreet Lakha .disable_clock_gate = true, 23736d26912SBhawanpreet Lakha .disable_pplib_clock_request = true, 23836d26912SBhawanpreet Lakha .disable_pplib_wm_range = true, 23936d26912SBhawanpreet Lakha .disable_stutter = false, 24036d26912SBhawanpreet Lakha .scl_reset_length10 = true, 24136d26912SBhawanpreet Lakha .dwb_fi_phase = -1, // -1 = disable 24236d26912SBhawanpreet Lakha .dmub_command_table = true, 24336d26912SBhawanpreet Lakha .enable_tri_buf = true, 24465e05ca7SJoshua Aberback .disable_psr = true, 2459d335e17SDmytro Laktyushkin .use_max_lb = true 24636d26912SBhawanpreet Lakha }; 24736d26912SBhawanpreet Lakha 24836d26912SBhawanpreet Lakha enum dcn302_clk_src_array_id { 24936d26912SBhawanpreet Lakha DCN302_CLK_SRC_PLL0, 25036d26912SBhawanpreet Lakha DCN302_CLK_SRC_PLL1, 25136d26912SBhawanpreet Lakha DCN302_CLK_SRC_PLL2, 25236d26912SBhawanpreet Lakha DCN302_CLK_SRC_PLL3, 25336d26912SBhawanpreet Lakha DCN302_CLK_SRC_PLL4, 25436d26912SBhawanpreet Lakha DCN302_CLK_SRC_TOTAL 25536d26912SBhawanpreet Lakha }; 25636d26912SBhawanpreet Lakha 25736d26912SBhawanpreet Lakha static const struct resource_caps res_cap_dcn302 = { 25836d26912SBhawanpreet Lakha .num_timing_generator = 5, 25936d26912SBhawanpreet Lakha .num_opp = 5, 26036d26912SBhawanpreet Lakha .num_video_plane = 5, 26136d26912SBhawanpreet Lakha .num_audio = 5, 26236d26912SBhawanpreet Lakha .num_stream_encoder = 5, 26336d26912SBhawanpreet Lakha .num_dwb = 1, 26436d26912SBhawanpreet Lakha .num_ddc = 5, 26536d26912SBhawanpreet Lakha .num_vmid = 16, 26636d26912SBhawanpreet Lakha .num_mpc_3dlut = 2, 26736d26912SBhawanpreet Lakha .num_dsc = 5, 26836d26912SBhawanpreet Lakha }; 26936d26912SBhawanpreet Lakha 27036d26912SBhawanpreet Lakha static const struct dc_plane_cap plane_cap = { 27136d26912SBhawanpreet Lakha .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 27236d26912SBhawanpreet Lakha .blends_with_above = true, 27336d26912SBhawanpreet Lakha .blends_with_below = true, 27436d26912SBhawanpreet Lakha .per_pixel_alpha = true, 27536d26912SBhawanpreet Lakha .pixel_format_support = { 27636d26912SBhawanpreet Lakha .argb8888 = true, 27736d26912SBhawanpreet Lakha .nv12 = true, 27836d26912SBhawanpreet Lakha .fp16 = true, 27936d26912SBhawanpreet Lakha .p010 = false, 28036d26912SBhawanpreet Lakha .ayuv = false, 28136d26912SBhawanpreet Lakha }, 28236d26912SBhawanpreet Lakha .max_upscale_factor = { 28336d26912SBhawanpreet Lakha .argb8888 = 16000, 28436d26912SBhawanpreet Lakha .nv12 = 16000, 28536d26912SBhawanpreet Lakha .fp16 = 16000 28636d26912SBhawanpreet Lakha }, 28760d177fdSNikola Cornij /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 28836d26912SBhawanpreet Lakha .max_downscale_factor = { 28960d177fdSNikola Cornij .argb8888 = 167, 29060d177fdSNikola Cornij .nv12 = 167, 29160d177fdSNikola Cornij .fp16 = 167 29236d26912SBhawanpreet Lakha }, 29336d26912SBhawanpreet Lakha 16, 29436d26912SBhawanpreet Lakha 16 29536d26912SBhawanpreet Lakha }; 29636d26912SBhawanpreet Lakha 29736d26912SBhawanpreet Lakha /* NBIO */ 29836d26912SBhawanpreet Lakha #define NBIO_BASE_INNER(seg) \ 29936d26912SBhawanpreet Lakha NBIO_BASE__INST0_SEG ## seg 30036d26912SBhawanpreet Lakha 30136d26912SBhawanpreet Lakha #define NBIO_BASE(seg) \ 30236d26912SBhawanpreet Lakha NBIO_BASE_INNER(seg) 30336d26912SBhawanpreet Lakha 30436d26912SBhawanpreet Lakha #define NBIO_SR(reg_name)\ 30536d26912SBhawanpreet Lakha .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 30636d26912SBhawanpreet Lakha mm ## reg_name 30736d26912SBhawanpreet Lakha 30836d26912SBhawanpreet Lakha /* DCN */ 30936d26912SBhawanpreet Lakha #undef BASE_INNER 31036d26912SBhawanpreet Lakha #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 31136d26912SBhawanpreet Lakha 31236d26912SBhawanpreet Lakha #define BASE(seg) BASE_INNER(seg) 31336d26912SBhawanpreet Lakha 31436d26912SBhawanpreet Lakha #define SR(reg_name)\ 31536d26912SBhawanpreet Lakha .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 31636d26912SBhawanpreet Lakha 31736d26912SBhawanpreet Lakha #define SF(reg_name, field_name, post_fix)\ 31836d26912SBhawanpreet Lakha .field_name = reg_name ## __ ## field_name ## post_fix 31936d26912SBhawanpreet Lakha 32036d26912SBhawanpreet Lakha #define SRI(reg_name, block, id)\ 32136d26912SBhawanpreet Lakha .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 32236d26912SBhawanpreet Lakha 32336d26912SBhawanpreet Lakha #define SRI2(reg_name, block, id)\ 32436d26912SBhawanpreet Lakha .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 32536d26912SBhawanpreet Lakha 32636d26912SBhawanpreet Lakha #define SRII(reg_name, block, id)\ 32736d26912SBhawanpreet Lakha .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 32836d26912SBhawanpreet Lakha mm ## block ## id ## _ ## reg_name 32936d26912SBhawanpreet Lakha 33036d26912SBhawanpreet Lakha #define DCCG_SRII(reg_name, block, id)\ 33136d26912SBhawanpreet Lakha .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 33236d26912SBhawanpreet Lakha mm ## block ## id ## _ ## reg_name 33336d26912SBhawanpreet Lakha 33436d26912SBhawanpreet Lakha #define VUPDATE_SRII(reg_name, block, id)\ 33536d26912SBhawanpreet Lakha .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 33636d26912SBhawanpreet Lakha mm ## reg_name ## _ ## block ## id 33736d26912SBhawanpreet Lakha 33836d26912SBhawanpreet Lakha #define SRII_DWB(reg_name, temp_name, block, id)\ 33936d26912SBhawanpreet Lakha .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 34036d26912SBhawanpreet Lakha mm ## block ## id ## _ ## temp_name 34136d26912SBhawanpreet Lakha 34236d26912SBhawanpreet Lakha #define SRII_MPC_RMU(reg_name, block, id)\ 34336d26912SBhawanpreet Lakha .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 34436d26912SBhawanpreet Lakha mm ## block ## id ## _ ## reg_name 34536d26912SBhawanpreet Lakha 34636d26912SBhawanpreet Lakha static const struct dcn_hubbub_registers hubbub_reg = { 34736d26912SBhawanpreet Lakha HUBBUB_REG_LIST_DCN30(0) 34836d26912SBhawanpreet Lakha }; 34936d26912SBhawanpreet Lakha 35036d26912SBhawanpreet Lakha static const struct dcn_hubbub_shift hubbub_shift = { 35136d26912SBhawanpreet Lakha HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 35236d26912SBhawanpreet Lakha }; 35336d26912SBhawanpreet Lakha 35436d26912SBhawanpreet Lakha static const struct dcn_hubbub_mask hubbub_mask = { 35536d26912SBhawanpreet Lakha HUBBUB_MASK_SH_LIST_DCN30(_MASK) 35636d26912SBhawanpreet Lakha }; 35736d26912SBhawanpreet Lakha 35836d26912SBhawanpreet Lakha #define vmid_regs(id)\ 35936d26912SBhawanpreet Lakha [id] = { DCN20_VMID_REG_LIST(id) } 36036d26912SBhawanpreet Lakha 36136d26912SBhawanpreet Lakha static const struct dcn_vmid_registers vmid_regs[] = { 36236d26912SBhawanpreet Lakha vmid_regs(0), 36336d26912SBhawanpreet Lakha vmid_regs(1), 36436d26912SBhawanpreet Lakha vmid_regs(2), 36536d26912SBhawanpreet Lakha vmid_regs(3), 36636d26912SBhawanpreet Lakha vmid_regs(4), 36736d26912SBhawanpreet Lakha vmid_regs(5), 36836d26912SBhawanpreet Lakha vmid_regs(6), 36936d26912SBhawanpreet Lakha vmid_regs(7), 37036d26912SBhawanpreet Lakha vmid_regs(8), 37136d26912SBhawanpreet Lakha vmid_regs(9), 37236d26912SBhawanpreet Lakha vmid_regs(10), 37336d26912SBhawanpreet Lakha vmid_regs(11), 37436d26912SBhawanpreet Lakha vmid_regs(12), 37536d26912SBhawanpreet Lakha vmid_regs(13), 37636d26912SBhawanpreet Lakha vmid_regs(14), 37736d26912SBhawanpreet Lakha vmid_regs(15) 37836d26912SBhawanpreet Lakha }; 37936d26912SBhawanpreet Lakha 38036d26912SBhawanpreet Lakha static const struct dcn20_vmid_shift vmid_shifts = { 38136d26912SBhawanpreet Lakha DCN20_VMID_MASK_SH_LIST(__SHIFT) 38236d26912SBhawanpreet Lakha }; 38336d26912SBhawanpreet Lakha 38436d26912SBhawanpreet Lakha static const struct dcn20_vmid_mask vmid_masks = { 38536d26912SBhawanpreet Lakha DCN20_VMID_MASK_SH_LIST(_MASK) 38636d26912SBhawanpreet Lakha }; 38736d26912SBhawanpreet Lakha 38836d26912SBhawanpreet Lakha static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 38936d26912SBhawanpreet Lakha { 39036d26912SBhawanpreet Lakha int i; 39136d26912SBhawanpreet Lakha 39236d26912SBhawanpreet Lakha struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 39336d26912SBhawanpreet Lakha 39436d26912SBhawanpreet Lakha if (!hubbub3) 39536d26912SBhawanpreet Lakha return NULL; 39636d26912SBhawanpreet Lakha 39736d26912SBhawanpreet Lakha hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 39836d26912SBhawanpreet Lakha 39936d26912SBhawanpreet Lakha for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 40036d26912SBhawanpreet Lakha struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 40136d26912SBhawanpreet Lakha 40236d26912SBhawanpreet Lakha vmid->ctx = ctx; 40336d26912SBhawanpreet Lakha 40436d26912SBhawanpreet Lakha vmid->regs = &vmid_regs[i]; 40536d26912SBhawanpreet Lakha vmid->shifts = &vmid_shifts; 40636d26912SBhawanpreet Lakha vmid->masks = &vmid_masks; 40736d26912SBhawanpreet Lakha } 40836d26912SBhawanpreet Lakha 40936d26912SBhawanpreet Lakha return &hubbub3->base; 41036d26912SBhawanpreet Lakha } 41136d26912SBhawanpreet Lakha 41236d26912SBhawanpreet Lakha #define vpg_regs(id)\ 41336d26912SBhawanpreet Lakha [id] = { VPG_DCN3_REG_LIST(id) } 41436d26912SBhawanpreet Lakha 41536d26912SBhawanpreet Lakha static const struct dcn30_vpg_registers vpg_regs[] = { 41636d26912SBhawanpreet Lakha vpg_regs(0), 41736d26912SBhawanpreet Lakha vpg_regs(1), 41836d26912SBhawanpreet Lakha vpg_regs(2), 41936d26912SBhawanpreet Lakha vpg_regs(3), 42036d26912SBhawanpreet Lakha vpg_regs(4), 42136d26912SBhawanpreet Lakha vpg_regs(5) 42236d26912SBhawanpreet Lakha }; 42336d26912SBhawanpreet Lakha 42436d26912SBhawanpreet Lakha static const struct dcn30_vpg_shift vpg_shift = { 42536d26912SBhawanpreet Lakha DCN3_VPG_MASK_SH_LIST(__SHIFT) 42636d26912SBhawanpreet Lakha }; 42736d26912SBhawanpreet Lakha 42836d26912SBhawanpreet Lakha static const struct dcn30_vpg_mask vpg_mask = { 42936d26912SBhawanpreet Lakha DCN3_VPG_MASK_SH_LIST(_MASK) 43036d26912SBhawanpreet Lakha }; 43136d26912SBhawanpreet Lakha 43236d26912SBhawanpreet Lakha static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 43336d26912SBhawanpreet Lakha { 43436d26912SBhawanpreet Lakha struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 43536d26912SBhawanpreet Lakha 43636d26912SBhawanpreet Lakha if (!vpg3) 43736d26912SBhawanpreet Lakha return NULL; 43836d26912SBhawanpreet Lakha 43936d26912SBhawanpreet Lakha vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 44036d26912SBhawanpreet Lakha 44136d26912SBhawanpreet Lakha return &vpg3->base; 44236d26912SBhawanpreet Lakha } 44336d26912SBhawanpreet Lakha 44436d26912SBhawanpreet Lakha #define afmt_regs(id)\ 44536d26912SBhawanpreet Lakha [id] = { AFMT_DCN3_REG_LIST(id) } 44636d26912SBhawanpreet Lakha 44736d26912SBhawanpreet Lakha static const struct dcn30_afmt_registers afmt_regs[] = { 44836d26912SBhawanpreet Lakha afmt_regs(0), 44936d26912SBhawanpreet Lakha afmt_regs(1), 45036d26912SBhawanpreet Lakha afmt_regs(2), 45136d26912SBhawanpreet Lakha afmt_regs(3), 45236d26912SBhawanpreet Lakha afmt_regs(4), 45336d26912SBhawanpreet Lakha afmt_regs(5) 45436d26912SBhawanpreet Lakha }; 45536d26912SBhawanpreet Lakha 45636d26912SBhawanpreet Lakha static const struct dcn30_afmt_shift afmt_shift = { 45736d26912SBhawanpreet Lakha DCN3_AFMT_MASK_SH_LIST(__SHIFT) 45836d26912SBhawanpreet Lakha }; 45936d26912SBhawanpreet Lakha 46036d26912SBhawanpreet Lakha static const struct dcn30_afmt_mask afmt_mask = { 46136d26912SBhawanpreet Lakha DCN3_AFMT_MASK_SH_LIST(_MASK) 46236d26912SBhawanpreet Lakha }; 46336d26912SBhawanpreet Lakha 46436d26912SBhawanpreet Lakha static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 46536d26912SBhawanpreet Lakha { 46636d26912SBhawanpreet Lakha struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 46736d26912SBhawanpreet Lakha 46836d26912SBhawanpreet Lakha if (!afmt3) 46936d26912SBhawanpreet Lakha return NULL; 47036d26912SBhawanpreet Lakha 47136d26912SBhawanpreet Lakha afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 47236d26912SBhawanpreet Lakha 47336d26912SBhawanpreet Lakha return &afmt3->base; 47436d26912SBhawanpreet Lakha } 47536d26912SBhawanpreet Lakha 47636d26912SBhawanpreet Lakha #define audio_regs(id)\ 47736d26912SBhawanpreet Lakha [id] = { AUD_COMMON_REG_LIST(id) } 47836d26912SBhawanpreet Lakha 47936d26912SBhawanpreet Lakha static const struct dce_audio_registers audio_regs[] = { 48036d26912SBhawanpreet Lakha audio_regs(0), 48136d26912SBhawanpreet Lakha audio_regs(1), 48236d26912SBhawanpreet Lakha audio_regs(2), 48336d26912SBhawanpreet Lakha audio_regs(3), 48436d26912SBhawanpreet Lakha audio_regs(4), 48536d26912SBhawanpreet Lakha audio_regs(5), 48636d26912SBhawanpreet Lakha audio_regs(6) 48736d26912SBhawanpreet Lakha }; 48836d26912SBhawanpreet Lakha 48936d26912SBhawanpreet Lakha #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 49036d26912SBhawanpreet Lakha SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 49136d26912SBhawanpreet Lakha SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 49236d26912SBhawanpreet Lakha AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 49336d26912SBhawanpreet Lakha 49436d26912SBhawanpreet Lakha static const struct dce_audio_shift audio_shift = { 49536d26912SBhawanpreet Lakha DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 49636d26912SBhawanpreet Lakha }; 49736d26912SBhawanpreet Lakha 49836d26912SBhawanpreet Lakha static const struct dce_audio_mask audio_mask = { 49936d26912SBhawanpreet Lakha DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 50036d26912SBhawanpreet Lakha }; 50136d26912SBhawanpreet Lakha 50236d26912SBhawanpreet Lakha static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 50336d26912SBhawanpreet Lakha { 50436d26912SBhawanpreet Lakha return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 50536d26912SBhawanpreet Lakha } 50636d26912SBhawanpreet Lakha 50736d26912SBhawanpreet Lakha #define stream_enc_regs(id)\ 50836d26912SBhawanpreet Lakha [id] = { SE_DCN3_REG_LIST(id) } 50936d26912SBhawanpreet Lakha 51036d26912SBhawanpreet Lakha static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 51136d26912SBhawanpreet Lakha stream_enc_regs(0), 51236d26912SBhawanpreet Lakha stream_enc_regs(1), 51336d26912SBhawanpreet Lakha stream_enc_regs(2), 51436d26912SBhawanpreet Lakha stream_enc_regs(3), 51536d26912SBhawanpreet Lakha stream_enc_regs(4) 51636d26912SBhawanpreet Lakha }; 51736d26912SBhawanpreet Lakha 51836d26912SBhawanpreet Lakha static const struct dcn10_stream_encoder_shift se_shift = { 51936d26912SBhawanpreet Lakha SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 52036d26912SBhawanpreet Lakha }; 52136d26912SBhawanpreet Lakha 52236d26912SBhawanpreet Lakha static const struct dcn10_stream_encoder_mask se_mask = { 52336d26912SBhawanpreet Lakha SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 52436d26912SBhawanpreet Lakha }; 52536d26912SBhawanpreet Lakha 52636d26912SBhawanpreet Lakha static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 52736d26912SBhawanpreet Lakha { 52836d26912SBhawanpreet Lakha struct dcn10_stream_encoder *enc1; 52936d26912SBhawanpreet Lakha struct vpg *vpg; 53036d26912SBhawanpreet Lakha struct afmt *afmt; 53136d26912SBhawanpreet Lakha int vpg_inst; 53236d26912SBhawanpreet Lakha int afmt_inst; 53336d26912SBhawanpreet Lakha 53436d26912SBhawanpreet Lakha /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 53536d26912SBhawanpreet Lakha if (eng_id <= ENGINE_ID_DIGE) { 53636d26912SBhawanpreet Lakha vpg_inst = eng_id; 53736d26912SBhawanpreet Lakha afmt_inst = eng_id; 53836d26912SBhawanpreet Lakha } else 53936d26912SBhawanpreet Lakha return NULL; 54036d26912SBhawanpreet Lakha 54136d26912SBhawanpreet Lakha enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 54236d26912SBhawanpreet Lakha vpg = dcn302_vpg_create(ctx, vpg_inst); 54336d26912SBhawanpreet Lakha afmt = dcn302_afmt_create(ctx, afmt_inst); 54436d26912SBhawanpreet Lakha 54536d26912SBhawanpreet Lakha if (!enc1 || !vpg || !afmt) 54636d26912SBhawanpreet Lakha return NULL; 54736d26912SBhawanpreet Lakha 54836d26912SBhawanpreet Lakha dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 54936d26912SBhawanpreet Lakha &se_shift, &se_mask); 55036d26912SBhawanpreet Lakha 55136d26912SBhawanpreet Lakha return &enc1->base; 55236d26912SBhawanpreet Lakha } 55336d26912SBhawanpreet Lakha 55436d26912SBhawanpreet Lakha #define clk_src_regs(index, pllid)\ 55536d26912SBhawanpreet Lakha [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 55636d26912SBhawanpreet Lakha 55736d26912SBhawanpreet Lakha static const struct dce110_clk_src_regs clk_src_regs[] = { 55836d26912SBhawanpreet Lakha clk_src_regs(0, A), 55936d26912SBhawanpreet Lakha clk_src_regs(1, B), 56036d26912SBhawanpreet Lakha clk_src_regs(2, C), 56136d26912SBhawanpreet Lakha clk_src_regs(3, D), 56236d26912SBhawanpreet Lakha clk_src_regs(4, E) 56336d26912SBhawanpreet Lakha }; 56436d26912SBhawanpreet Lakha 56536d26912SBhawanpreet Lakha static const struct dce110_clk_src_shift cs_shift = { 56636d26912SBhawanpreet Lakha CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 56736d26912SBhawanpreet Lakha }; 56836d26912SBhawanpreet Lakha 56936d26912SBhawanpreet Lakha static const struct dce110_clk_src_mask cs_mask = { 57036d26912SBhawanpreet Lakha CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 57136d26912SBhawanpreet Lakha }; 57236d26912SBhawanpreet Lakha 57336d26912SBhawanpreet Lakha static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 57436d26912SBhawanpreet Lakha enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 57536d26912SBhawanpreet Lakha { 57636d26912SBhawanpreet Lakha struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 57736d26912SBhawanpreet Lakha 57836d26912SBhawanpreet Lakha if (!clk_src) 57936d26912SBhawanpreet Lakha return NULL; 58036d26912SBhawanpreet Lakha 58136d26912SBhawanpreet Lakha if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 58236d26912SBhawanpreet Lakha clk_src->base.dp_clk_src = dp_clk_src; 58336d26912SBhawanpreet Lakha return &clk_src->base; 58436d26912SBhawanpreet Lakha } 58536d26912SBhawanpreet Lakha 58636d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 58736d26912SBhawanpreet Lakha return NULL; 58836d26912SBhawanpreet Lakha } 58936d26912SBhawanpreet Lakha 59036d26912SBhawanpreet Lakha static const struct dce_hwseq_registers hwseq_reg = { 59136d26912SBhawanpreet Lakha HWSEQ_DCN302_REG_LIST() 59236d26912SBhawanpreet Lakha }; 59336d26912SBhawanpreet Lakha 59436d26912SBhawanpreet Lakha static const struct dce_hwseq_shift hwseq_shift = { 59536d26912SBhawanpreet Lakha HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 59636d26912SBhawanpreet Lakha }; 59736d26912SBhawanpreet Lakha 59836d26912SBhawanpreet Lakha static const struct dce_hwseq_mask hwseq_mask = { 59936d26912SBhawanpreet Lakha HWSEQ_DCN302_MASK_SH_LIST(_MASK) 60036d26912SBhawanpreet Lakha }; 60136d26912SBhawanpreet Lakha 60236d26912SBhawanpreet Lakha static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 60336d26912SBhawanpreet Lakha { 60436d26912SBhawanpreet Lakha struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 60536d26912SBhawanpreet Lakha 60636d26912SBhawanpreet Lakha if (hws) { 60736d26912SBhawanpreet Lakha hws->ctx = ctx; 60836d26912SBhawanpreet Lakha hws->regs = &hwseq_reg; 60936d26912SBhawanpreet Lakha hws->shifts = &hwseq_shift; 61036d26912SBhawanpreet Lakha hws->masks = &hwseq_mask; 61136d26912SBhawanpreet Lakha } 61236d26912SBhawanpreet Lakha return hws; 61336d26912SBhawanpreet Lakha } 61436d26912SBhawanpreet Lakha 61536d26912SBhawanpreet Lakha #define hubp_regs(id)\ 61636d26912SBhawanpreet Lakha [id] = { HUBP_REG_LIST_DCN30(id) } 61736d26912SBhawanpreet Lakha 61836d26912SBhawanpreet Lakha static const struct dcn_hubp2_registers hubp_regs[] = { 61936d26912SBhawanpreet Lakha hubp_regs(0), 62036d26912SBhawanpreet Lakha hubp_regs(1), 62136d26912SBhawanpreet Lakha hubp_regs(2), 62236d26912SBhawanpreet Lakha hubp_regs(3), 62336d26912SBhawanpreet Lakha hubp_regs(4) 62436d26912SBhawanpreet Lakha }; 62536d26912SBhawanpreet Lakha 62636d26912SBhawanpreet Lakha static const struct dcn_hubp2_shift hubp_shift = { 62736d26912SBhawanpreet Lakha HUBP_MASK_SH_LIST_DCN30(__SHIFT) 62836d26912SBhawanpreet Lakha }; 62936d26912SBhawanpreet Lakha 63036d26912SBhawanpreet Lakha static const struct dcn_hubp2_mask hubp_mask = { 63136d26912SBhawanpreet Lakha HUBP_MASK_SH_LIST_DCN30(_MASK) 63236d26912SBhawanpreet Lakha }; 63336d26912SBhawanpreet Lakha 63436d26912SBhawanpreet Lakha static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 63536d26912SBhawanpreet Lakha { 63636d26912SBhawanpreet Lakha struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 63736d26912SBhawanpreet Lakha 63836d26912SBhawanpreet Lakha if (!hubp2) 63936d26912SBhawanpreet Lakha return NULL; 64036d26912SBhawanpreet Lakha 64136d26912SBhawanpreet Lakha if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 64236d26912SBhawanpreet Lakha return &hubp2->base; 64336d26912SBhawanpreet Lakha 64436d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 64536d26912SBhawanpreet Lakha kfree(hubp2); 64636d26912SBhawanpreet Lakha return NULL; 64736d26912SBhawanpreet Lakha } 64836d26912SBhawanpreet Lakha 64936d26912SBhawanpreet Lakha #define dpp_regs(id)\ 65036d26912SBhawanpreet Lakha [id] = { DPP_REG_LIST_DCN30(id) } 65136d26912SBhawanpreet Lakha 65236d26912SBhawanpreet Lakha static const struct dcn3_dpp_registers dpp_regs[] = { 65336d26912SBhawanpreet Lakha dpp_regs(0), 65436d26912SBhawanpreet Lakha dpp_regs(1), 65536d26912SBhawanpreet Lakha dpp_regs(2), 65636d26912SBhawanpreet Lakha dpp_regs(3), 65736d26912SBhawanpreet Lakha dpp_regs(4) 65836d26912SBhawanpreet Lakha }; 65936d26912SBhawanpreet Lakha 66036d26912SBhawanpreet Lakha static const struct dcn3_dpp_shift tf_shift = { 66136d26912SBhawanpreet Lakha DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 66236d26912SBhawanpreet Lakha }; 66336d26912SBhawanpreet Lakha 66436d26912SBhawanpreet Lakha static const struct dcn3_dpp_mask tf_mask = { 66536d26912SBhawanpreet Lakha DPP_REG_LIST_SH_MASK_DCN30(_MASK) 66636d26912SBhawanpreet Lakha }; 66736d26912SBhawanpreet Lakha 66836d26912SBhawanpreet Lakha static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 66936d26912SBhawanpreet Lakha { 67036d26912SBhawanpreet Lakha struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 67136d26912SBhawanpreet Lakha 67236d26912SBhawanpreet Lakha if (!dpp) 67336d26912SBhawanpreet Lakha return NULL; 67436d26912SBhawanpreet Lakha 67536d26912SBhawanpreet Lakha if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 67636d26912SBhawanpreet Lakha return &dpp->base; 67736d26912SBhawanpreet Lakha 67836d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 67936d26912SBhawanpreet Lakha kfree(dpp); 68036d26912SBhawanpreet Lakha return NULL; 68136d26912SBhawanpreet Lakha } 68236d26912SBhawanpreet Lakha 68336d26912SBhawanpreet Lakha #define opp_regs(id)\ 68436d26912SBhawanpreet Lakha [id] = { OPP_REG_LIST_DCN30(id) } 68536d26912SBhawanpreet Lakha 68636d26912SBhawanpreet Lakha static const struct dcn20_opp_registers opp_regs[] = { 68736d26912SBhawanpreet Lakha opp_regs(0), 68836d26912SBhawanpreet Lakha opp_regs(1), 68936d26912SBhawanpreet Lakha opp_regs(2), 69036d26912SBhawanpreet Lakha opp_regs(3), 69136d26912SBhawanpreet Lakha opp_regs(4) 69236d26912SBhawanpreet Lakha }; 69336d26912SBhawanpreet Lakha 69436d26912SBhawanpreet Lakha static const struct dcn20_opp_shift opp_shift = { 69536d26912SBhawanpreet Lakha OPP_MASK_SH_LIST_DCN20(__SHIFT) 69636d26912SBhawanpreet Lakha }; 69736d26912SBhawanpreet Lakha 69836d26912SBhawanpreet Lakha static const struct dcn20_opp_mask opp_mask = { 69936d26912SBhawanpreet Lakha OPP_MASK_SH_LIST_DCN20(_MASK) 70036d26912SBhawanpreet Lakha }; 70136d26912SBhawanpreet Lakha 70236d26912SBhawanpreet Lakha static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 70336d26912SBhawanpreet Lakha { 70436d26912SBhawanpreet Lakha struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 70536d26912SBhawanpreet Lakha 70636d26912SBhawanpreet Lakha if (!opp) { 70736d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 70836d26912SBhawanpreet Lakha return NULL; 70936d26912SBhawanpreet Lakha } 71036d26912SBhawanpreet Lakha 71136d26912SBhawanpreet Lakha dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 71236d26912SBhawanpreet Lakha return &opp->base; 71336d26912SBhawanpreet Lakha } 71436d26912SBhawanpreet Lakha 71536d26912SBhawanpreet Lakha #define optc_regs(id)\ 71636d26912SBhawanpreet Lakha [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 71736d26912SBhawanpreet Lakha 71836d26912SBhawanpreet Lakha static const struct dcn_optc_registers optc_regs[] = { 71936d26912SBhawanpreet Lakha optc_regs(0), 72036d26912SBhawanpreet Lakha optc_regs(1), 72136d26912SBhawanpreet Lakha optc_regs(2), 72236d26912SBhawanpreet Lakha optc_regs(3), 72336d26912SBhawanpreet Lakha optc_regs(4) 72436d26912SBhawanpreet Lakha }; 72536d26912SBhawanpreet Lakha 72636d26912SBhawanpreet Lakha static const struct dcn_optc_shift optc_shift = { 72736d26912SBhawanpreet Lakha OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 72836d26912SBhawanpreet Lakha }; 72936d26912SBhawanpreet Lakha 73036d26912SBhawanpreet Lakha static const struct dcn_optc_mask optc_mask = { 73136d26912SBhawanpreet Lakha OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 73236d26912SBhawanpreet Lakha }; 73336d26912SBhawanpreet Lakha 73436d26912SBhawanpreet Lakha static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 73536d26912SBhawanpreet Lakha { 73636d26912SBhawanpreet Lakha struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 73736d26912SBhawanpreet Lakha 73836d26912SBhawanpreet Lakha if (!tgn10) 73936d26912SBhawanpreet Lakha return NULL; 74036d26912SBhawanpreet Lakha 74136d26912SBhawanpreet Lakha tgn10->base.inst = instance; 74236d26912SBhawanpreet Lakha tgn10->base.ctx = ctx; 74336d26912SBhawanpreet Lakha 74436d26912SBhawanpreet Lakha tgn10->tg_regs = &optc_regs[instance]; 74536d26912SBhawanpreet Lakha tgn10->tg_shift = &optc_shift; 74636d26912SBhawanpreet Lakha tgn10->tg_mask = &optc_mask; 74736d26912SBhawanpreet Lakha 74836d26912SBhawanpreet Lakha dcn30_timing_generator_init(tgn10); 74936d26912SBhawanpreet Lakha 75036d26912SBhawanpreet Lakha return &tgn10->base; 75136d26912SBhawanpreet Lakha } 75236d26912SBhawanpreet Lakha 75336d26912SBhawanpreet Lakha static const struct dcn30_mpc_registers mpc_regs = { 75436d26912SBhawanpreet Lakha MPC_REG_LIST_DCN3_0(0), 75536d26912SBhawanpreet Lakha MPC_REG_LIST_DCN3_0(1), 75636d26912SBhawanpreet Lakha MPC_REG_LIST_DCN3_0(2), 75736d26912SBhawanpreet Lakha MPC_REG_LIST_DCN3_0(3), 75836d26912SBhawanpreet Lakha MPC_REG_LIST_DCN3_0(4), 75936d26912SBhawanpreet Lakha MPC_OUT_MUX_REG_LIST_DCN3_0(0), 76036d26912SBhawanpreet Lakha MPC_OUT_MUX_REG_LIST_DCN3_0(1), 76136d26912SBhawanpreet Lakha MPC_OUT_MUX_REG_LIST_DCN3_0(2), 76236d26912SBhawanpreet Lakha MPC_OUT_MUX_REG_LIST_DCN3_0(3), 76336d26912SBhawanpreet Lakha MPC_OUT_MUX_REG_LIST_DCN3_0(4), 76436d26912SBhawanpreet Lakha MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 76536d26912SBhawanpreet Lakha MPC_RMU_REG_LIST_DCN3AG(0), 76636d26912SBhawanpreet Lakha MPC_RMU_REG_LIST_DCN3AG(1), 76736d26912SBhawanpreet Lakha MPC_RMU_REG_LIST_DCN3AG(2), 76836d26912SBhawanpreet Lakha MPC_DWB_MUX_REG_LIST_DCN3_0(0), 76936d26912SBhawanpreet Lakha }; 77036d26912SBhawanpreet Lakha 77136d26912SBhawanpreet Lakha static const struct dcn30_mpc_shift mpc_shift = { 77236d26912SBhawanpreet Lakha MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 77336d26912SBhawanpreet Lakha }; 77436d26912SBhawanpreet Lakha 77536d26912SBhawanpreet Lakha static const struct dcn30_mpc_mask mpc_mask = { 77636d26912SBhawanpreet Lakha MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 77736d26912SBhawanpreet Lakha }; 77836d26912SBhawanpreet Lakha 77936d26912SBhawanpreet Lakha static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 78036d26912SBhawanpreet Lakha { 78136d26912SBhawanpreet Lakha struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 78236d26912SBhawanpreet Lakha 78336d26912SBhawanpreet Lakha if (!mpc30) 78436d26912SBhawanpreet Lakha return NULL; 78536d26912SBhawanpreet Lakha 78636d26912SBhawanpreet Lakha dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 78736d26912SBhawanpreet Lakha 78836d26912SBhawanpreet Lakha return &mpc30->base; 78936d26912SBhawanpreet Lakha } 79036d26912SBhawanpreet Lakha 79136d26912SBhawanpreet Lakha #define dsc_regsDCN20(id)\ 79236d26912SBhawanpreet Lakha [id] = { DSC_REG_LIST_DCN20(id) } 79336d26912SBhawanpreet Lakha 79436d26912SBhawanpreet Lakha static const struct dcn20_dsc_registers dsc_regs[] = { 79536d26912SBhawanpreet Lakha dsc_regsDCN20(0), 79636d26912SBhawanpreet Lakha dsc_regsDCN20(1), 79736d26912SBhawanpreet Lakha dsc_regsDCN20(2), 79836d26912SBhawanpreet Lakha dsc_regsDCN20(3), 79936d26912SBhawanpreet Lakha dsc_regsDCN20(4) 80036d26912SBhawanpreet Lakha }; 80136d26912SBhawanpreet Lakha 80236d26912SBhawanpreet Lakha static const struct dcn20_dsc_shift dsc_shift = { 80336d26912SBhawanpreet Lakha DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 80436d26912SBhawanpreet Lakha }; 80536d26912SBhawanpreet Lakha 80636d26912SBhawanpreet Lakha static const struct dcn20_dsc_mask dsc_mask = { 80736d26912SBhawanpreet Lakha DSC_REG_LIST_SH_MASK_DCN20(_MASK) 80836d26912SBhawanpreet Lakha }; 80936d26912SBhawanpreet Lakha 81036d26912SBhawanpreet Lakha static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 81136d26912SBhawanpreet Lakha { 81236d26912SBhawanpreet Lakha struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 81336d26912SBhawanpreet Lakha 81436d26912SBhawanpreet Lakha if (!dsc) { 81536d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 81636d26912SBhawanpreet Lakha return NULL; 81736d26912SBhawanpreet Lakha } 81836d26912SBhawanpreet Lakha 81936d26912SBhawanpreet Lakha dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 82036d26912SBhawanpreet Lakha return &dsc->base; 82136d26912SBhawanpreet Lakha } 82236d26912SBhawanpreet Lakha 82336d26912SBhawanpreet Lakha #define dwbc_regs_dcn3(id)\ 82436d26912SBhawanpreet Lakha [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 82536d26912SBhawanpreet Lakha 82636d26912SBhawanpreet Lakha static const struct dcn30_dwbc_registers dwbc30_regs[] = { 82736d26912SBhawanpreet Lakha dwbc_regs_dcn3(0) 82836d26912SBhawanpreet Lakha }; 82936d26912SBhawanpreet Lakha 83036d26912SBhawanpreet Lakha static const struct dcn30_dwbc_shift dwbc30_shift = { 83136d26912SBhawanpreet Lakha DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 83236d26912SBhawanpreet Lakha }; 83336d26912SBhawanpreet Lakha 83436d26912SBhawanpreet Lakha static const struct dcn30_dwbc_mask dwbc30_mask = { 83536d26912SBhawanpreet Lakha DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 83636d26912SBhawanpreet Lakha }; 83736d26912SBhawanpreet Lakha 83836d26912SBhawanpreet Lakha static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 83936d26912SBhawanpreet Lakha { 84036d26912SBhawanpreet Lakha int i; 84136d26912SBhawanpreet Lakha uint32_t pipe_count = pool->res_cap->num_dwb; 84236d26912SBhawanpreet Lakha 84336d26912SBhawanpreet Lakha for (i = 0; i < pipe_count; i++) { 84436d26912SBhawanpreet Lakha struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 84536d26912SBhawanpreet Lakha 84636d26912SBhawanpreet Lakha if (!dwbc30) { 84736d26912SBhawanpreet Lakha dm_error("DC: failed to create dwbc30!\n"); 84836d26912SBhawanpreet Lakha return false; 84936d26912SBhawanpreet Lakha } 85036d26912SBhawanpreet Lakha 85136d26912SBhawanpreet Lakha dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 85236d26912SBhawanpreet Lakha 85336d26912SBhawanpreet Lakha pool->dwbc[i] = &dwbc30->base; 85436d26912SBhawanpreet Lakha } 85536d26912SBhawanpreet Lakha return true; 85636d26912SBhawanpreet Lakha } 85736d26912SBhawanpreet Lakha 85836d26912SBhawanpreet Lakha #define mcif_wb_regs_dcn3(id)\ 85936d26912SBhawanpreet Lakha [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 86036d26912SBhawanpreet Lakha 86136d26912SBhawanpreet Lakha static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 86236d26912SBhawanpreet Lakha mcif_wb_regs_dcn3(0) 86336d26912SBhawanpreet Lakha }; 86436d26912SBhawanpreet Lakha 86536d26912SBhawanpreet Lakha static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 86636d26912SBhawanpreet Lakha MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 86736d26912SBhawanpreet Lakha }; 86836d26912SBhawanpreet Lakha 86936d26912SBhawanpreet Lakha static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 87036d26912SBhawanpreet Lakha MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 87136d26912SBhawanpreet Lakha }; 87236d26912SBhawanpreet Lakha 87336d26912SBhawanpreet Lakha static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 87436d26912SBhawanpreet Lakha { 87536d26912SBhawanpreet Lakha int i; 87636d26912SBhawanpreet Lakha uint32_t pipe_count = pool->res_cap->num_dwb; 87736d26912SBhawanpreet Lakha 87836d26912SBhawanpreet Lakha for (i = 0; i < pipe_count; i++) { 87936d26912SBhawanpreet Lakha struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 88036d26912SBhawanpreet Lakha 88136d26912SBhawanpreet Lakha if (!mcif_wb30) { 88236d26912SBhawanpreet Lakha dm_error("DC: failed to create mcif_wb30!\n"); 88336d26912SBhawanpreet Lakha return false; 88436d26912SBhawanpreet Lakha } 88536d26912SBhawanpreet Lakha 88636d26912SBhawanpreet Lakha dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 88736d26912SBhawanpreet Lakha 88836d26912SBhawanpreet Lakha pool->mcif_wb[i] = &mcif_wb30->base; 88936d26912SBhawanpreet Lakha } 89036d26912SBhawanpreet Lakha return true; 89136d26912SBhawanpreet Lakha } 89236d26912SBhawanpreet Lakha 89336d26912SBhawanpreet Lakha #define aux_engine_regs(id)\ 89436d26912SBhawanpreet Lakha [id] = {\ 89536d26912SBhawanpreet Lakha AUX_COMMON_REG_LIST0(id), \ 89636d26912SBhawanpreet Lakha .AUXN_IMPCAL = 0, \ 89736d26912SBhawanpreet Lakha .AUXP_IMPCAL = 0, \ 89836d26912SBhawanpreet Lakha .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 89936d26912SBhawanpreet Lakha } 90036d26912SBhawanpreet Lakha 90136d26912SBhawanpreet Lakha static const struct dce110_aux_registers aux_engine_regs[] = { 90236d26912SBhawanpreet Lakha aux_engine_regs(0), 90336d26912SBhawanpreet Lakha aux_engine_regs(1), 90436d26912SBhawanpreet Lakha aux_engine_regs(2), 90536d26912SBhawanpreet Lakha aux_engine_regs(3), 90636d26912SBhawanpreet Lakha aux_engine_regs(4) 90736d26912SBhawanpreet Lakha }; 90836d26912SBhawanpreet Lakha 90936d26912SBhawanpreet Lakha static const struct dce110_aux_registers_shift aux_shift = { 91036d26912SBhawanpreet Lakha DCN_AUX_MASK_SH_LIST(__SHIFT) 91136d26912SBhawanpreet Lakha }; 91236d26912SBhawanpreet Lakha 91336d26912SBhawanpreet Lakha static const struct dce110_aux_registers_mask aux_mask = { 91436d26912SBhawanpreet Lakha DCN_AUX_MASK_SH_LIST(_MASK) 91536d26912SBhawanpreet Lakha }; 91636d26912SBhawanpreet Lakha 91736d26912SBhawanpreet Lakha static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 91836d26912SBhawanpreet Lakha { 91936d26912SBhawanpreet Lakha struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 92036d26912SBhawanpreet Lakha 92136d26912SBhawanpreet Lakha if (!aux_engine) 92236d26912SBhawanpreet Lakha return NULL; 92336d26912SBhawanpreet Lakha 92436d26912SBhawanpreet Lakha dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 92536d26912SBhawanpreet Lakha &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 92636d26912SBhawanpreet Lakha 92736d26912SBhawanpreet Lakha return &aux_engine->base; 92836d26912SBhawanpreet Lakha } 92936d26912SBhawanpreet Lakha 93036d26912SBhawanpreet Lakha #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 93136d26912SBhawanpreet Lakha 93236d26912SBhawanpreet Lakha static const struct dce_i2c_registers i2c_hw_regs[] = { 93336d26912SBhawanpreet Lakha i2c_inst_regs(1), 93436d26912SBhawanpreet Lakha i2c_inst_regs(2), 93536d26912SBhawanpreet Lakha i2c_inst_regs(3), 93636d26912SBhawanpreet Lakha i2c_inst_regs(4), 93736d26912SBhawanpreet Lakha i2c_inst_regs(5) 93836d26912SBhawanpreet Lakha }; 93936d26912SBhawanpreet Lakha 94036d26912SBhawanpreet Lakha static const struct dce_i2c_shift i2c_shifts = { 94136d26912SBhawanpreet Lakha I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 94236d26912SBhawanpreet Lakha }; 94336d26912SBhawanpreet Lakha 94436d26912SBhawanpreet Lakha static const struct dce_i2c_mask i2c_masks = { 94536d26912SBhawanpreet Lakha I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 94636d26912SBhawanpreet Lakha }; 94736d26912SBhawanpreet Lakha 94836d26912SBhawanpreet Lakha static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 94936d26912SBhawanpreet Lakha { 95036d26912SBhawanpreet Lakha struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 95136d26912SBhawanpreet Lakha 95236d26912SBhawanpreet Lakha if (!dce_i2c_hw) 95336d26912SBhawanpreet Lakha return NULL; 95436d26912SBhawanpreet Lakha 95536d26912SBhawanpreet Lakha dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 95636d26912SBhawanpreet Lakha 95736d26912SBhawanpreet Lakha return dce_i2c_hw; 95836d26912SBhawanpreet Lakha } 95936d26912SBhawanpreet Lakha 96036d26912SBhawanpreet Lakha static const struct encoder_feature_support link_enc_feature = { 96136d26912SBhawanpreet Lakha .max_hdmi_deep_color = COLOR_DEPTH_121212, 96236d26912SBhawanpreet Lakha .max_hdmi_pixel_clock = 600000, 96336d26912SBhawanpreet Lakha .hdmi_ycbcr420_supported = true, 96436d26912SBhawanpreet Lakha .dp_ycbcr420_supported = true, 96536d26912SBhawanpreet Lakha .fec_supported = true, 96636d26912SBhawanpreet Lakha .flags.bits.IS_HBR2_CAPABLE = true, 96736d26912SBhawanpreet Lakha .flags.bits.IS_HBR3_CAPABLE = true, 96836d26912SBhawanpreet Lakha .flags.bits.IS_TPS3_CAPABLE = true, 96936d26912SBhawanpreet Lakha .flags.bits.IS_TPS4_CAPABLE = true 97036d26912SBhawanpreet Lakha }; 97136d26912SBhawanpreet Lakha 97236d26912SBhawanpreet Lakha #define link_regs(id, phyid)\ 97336d26912SBhawanpreet Lakha [id] = {\ 97436d26912SBhawanpreet Lakha LE_DCN3_REG_LIST(id), \ 97536d26912SBhawanpreet Lakha UNIPHY_DCN2_REG_LIST(phyid), \ 97678deaf5fSBhawanpreet Lakha DPCS_DCN2_REG_LIST(id), \ 97791bda9e9SChris Park SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 97836d26912SBhawanpreet Lakha } 97936d26912SBhawanpreet Lakha 98036d26912SBhawanpreet Lakha static const struct dcn10_link_enc_registers link_enc_regs[] = { 98136d26912SBhawanpreet Lakha link_regs(0, A), 98236d26912SBhawanpreet Lakha link_regs(1, B), 98336d26912SBhawanpreet Lakha link_regs(2, C), 98436d26912SBhawanpreet Lakha link_regs(3, D), 98536d26912SBhawanpreet Lakha link_regs(4, E) 98636d26912SBhawanpreet Lakha }; 98736d26912SBhawanpreet Lakha 98836d26912SBhawanpreet Lakha static const struct dcn10_link_enc_shift le_shift = { 98936d26912SBhawanpreet Lakha LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 99036d26912SBhawanpreet Lakha DPCS_DCN2_MASK_SH_LIST(__SHIFT) 99136d26912SBhawanpreet Lakha }; 99236d26912SBhawanpreet Lakha 99336d26912SBhawanpreet Lakha static const struct dcn10_link_enc_mask le_mask = { 99436d26912SBhawanpreet Lakha LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 99536d26912SBhawanpreet Lakha DPCS_DCN2_MASK_SH_LIST(_MASK) 99636d26912SBhawanpreet Lakha }; 99736d26912SBhawanpreet Lakha 99836d26912SBhawanpreet Lakha #define aux_regs(id)\ 99936d26912SBhawanpreet Lakha [id] = { DCN2_AUX_REG_LIST(id) } 100036d26912SBhawanpreet Lakha 100136d26912SBhawanpreet Lakha static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 100236d26912SBhawanpreet Lakha aux_regs(0), 100336d26912SBhawanpreet Lakha aux_regs(1), 100436d26912SBhawanpreet Lakha aux_regs(2), 100536d26912SBhawanpreet Lakha aux_regs(3), 100636d26912SBhawanpreet Lakha aux_regs(4) 100736d26912SBhawanpreet Lakha }; 100836d26912SBhawanpreet Lakha 100936d26912SBhawanpreet Lakha #define hpd_regs(id)\ 101036d26912SBhawanpreet Lakha [id] = { HPD_REG_LIST(id) } 101136d26912SBhawanpreet Lakha 101236d26912SBhawanpreet Lakha static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 101336d26912SBhawanpreet Lakha hpd_regs(0), 101436d26912SBhawanpreet Lakha hpd_regs(1), 101536d26912SBhawanpreet Lakha hpd_regs(2), 101636d26912SBhawanpreet Lakha hpd_regs(3), 101736d26912SBhawanpreet Lakha hpd_regs(4) 101836d26912SBhawanpreet Lakha }; 101936d26912SBhawanpreet Lakha 102036d26912SBhawanpreet Lakha static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data) 102136d26912SBhawanpreet Lakha { 102236d26912SBhawanpreet Lakha struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 102336d26912SBhawanpreet Lakha 102436d26912SBhawanpreet Lakha if (!enc20) 102536d26912SBhawanpreet Lakha return NULL; 102636d26912SBhawanpreet Lakha 102736d26912SBhawanpreet Lakha dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 102836d26912SBhawanpreet Lakha &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 102936d26912SBhawanpreet Lakha &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 103036d26912SBhawanpreet Lakha 103136d26912SBhawanpreet Lakha return &enc20->enc10.base; 103236d26912SBhawanpreet Lakha } 103336d26912SBhawanpreet Lakha 103436d26912SBhawanpreet Lakha static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 103536d26912SBhawanpreet Lakha { DCN_PANEL_CNTL_REG_LIST() } 103636d26912SBhawanpreet Lakha }; 103736d26912SBhawanpreet Lakha 103836d26912SBhawanpreet Lakha static const struct dce_panel_cntl_shift panel_cntl_shift = { 103936d26912SBhawanpreet Lakha DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 104036d26912SBhawanpreet Lakha }; 104136d26912SBhawanpreet Lakha 104236d26912SBhawanpreet Lakha static const struct dce_panel_cntl_mask panel_cntl_mask = { 104336d26912SBhawanpreet Lakha DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 104436d26912SBhawanpreet Lakha }; 104536d26912SBhawanpreet Lakha 104636d26912SBhawanpreet Lakha static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 104736d26912SBhawanpreet Lakha { 104836d26912SBhawanpreet Lakha struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 104936d26912SBhawanpreet Lakha 105036d26912SBhawanpreet Lakha if (!panel_cntl) 105136d26912SBhawanpreet Lakha return NULL; 105236d26912SBhawanpreet Lakha 105336d26912SBhawanpreet Lakha dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 105436d26912SBhawanpreet Lakha &panel_cntl_shift, &panel_cntl_mask); 105536d26912SBhawanpreet Lakha 105636d26912SBhawanpreet Lakha return &panel_cntl->base; 105736d26912SBhawanpreet Lakha } 105836d26912SBhawanpreet Lakha 105936d26912SBhawanpreet Lakha static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 106036d26912SBhawanpreet Lakha { 106136d26912SBhawanpreet Lakha generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 106236d26912SBhawanpreet Lakha FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 106336d26912SBhawanpreet Lakha } 106436d26912SBhawanpreet Lakha 106536d26912SBhawanpreet Lakha static const struct resource_create_funcs res_create_funcs = { 106636d26912SBhawanpreet Lakha .read_dce_straps = read_dce_straps, 106736d26912SBhawanpreet Lakha .create_audio = dcn302_create_audio, 106836d26912SBhawanpreet Lakha .create_stream_encoder = dcn302_stream_encoder_create, 106936d26912SBhawanpreet Lakha .create_hwseq = dcn302_hwseq_create, 107036d26912SBhawanpreet Lakha }; 107136d26912SBhawanpreet Lakha 107236d26912SBhawanpreet Lakha static const struct resource_create_funcs res_create_maximus_funcs = { 107336d26912SBhawanpreet Lakha .read_dce_straps = NULL, 107436d26912SBhawanpreet Lakha .create_audio = NULL, 107536d26912SBhawanpreet Lakha .create_stream_encoder = NULL, 107636d26912SBhawanpreet Lakha .create_hwseq = dcn302_hwseq_create, 107736d26912SBhawanpreet Lakha }; 107836d26912SBhawanpreet Lakha 107936d26912SBhawanpreet Lakha static bool is_soc_bounding_box_valid(struct dc *dc) 108036d26912SBhawanpreet Lakha { 108136d26912SBhawanpreet Lakha uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 108236d26912SBhawanpreet Lakha 108336d26912SBhawanpreet Lakha if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 108436d26912SBhawanpreet Lakha return true; 108536d26912SBhawanpreet Lakha 108636d26912SBhawanpreet Lakha return false; 108736d26912SBhawanpreet Lakha } 108836d26912SBhawanpreet Lakha 108936d26912SBhawanpreet Lakha static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 109036d26912SBhawanpreet Lakha { 109136d26912SBhawanpreet Lakha struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 109236d26912SBhawanpreet Lakha struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 109336d26912SBhawanpreet Lakha 109436d26912SBhawanpreet Lakha DC_LOGGER_INIT(dc->ctx->logger); 109536d26912SBhawanpreet Lakha 109636d26912SBhawanpreet Lakha if (!is_soc_bounding_box_valid(dc)) { 109749da4c2bSJoe Perches DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 109836d26912SBhawanpreet Lakha return false; 109936d26912SBhawanpreet Lakha } 110036d26912SBhawanpreet Lakha 110136d26912SBhawanpreet Lakha loaded_ip->max_num_otg = pool->pipe_count; 110236d26912SBhawanpreet Lakha loaded_ip->max_num_dpp = pool->pipe_count; 110336d26912SBhawanpreet Lakha loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 110436d26912SBhawanpreet Lakha dcn20_patch_bounding_box(dc, loaded_bb); 11059253e115SAurabindo Pillai 11069253e115SAurabindo Pillai if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 11079253e115SAurabindo Pillai struct bp_soc_bb_info bb_info = { 0 }; 11089253e115SAurabindo Pillai 11099253e115SAurabindo Pillai if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 11109253e115SAurabindo Pillai dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 11119253e115SAurabindo Pillai if (bb_info.dram_clock_change_latency_100ns > 0) 11129253e115SAurabindo Pillai dcn3_02_soc.dram_clock_change_latency_us = 11139253e115SAurabindo Pillai bb_info.dram_clock_change_latency_100ns * 10; 11149253e115SAurabindo Pillai 11159253e115SAurabindo Pillai if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 11169253e115SAurabindo Pillai dcn3_02_soc.sr_enter_plus_exit_time_us = 11179253e115SAurabindo Pillai bb_info.dram_sr_enter_exit_latency_100ns * 10; 11189253e115SAurabindo Pillai 11199253e115SAurabindo Pillai if (bb_info.dram_sr_exit_latency_100ns > 0) 11209253e115SAurabindo Pillai dcn3_02_soc.sr_exit_time_us = 11219253e115SAurabindo Pillai bb_info.dram_sr_exit_latency_100ns * 10; 11229253e115SAurabindo Pillai } 11239253e115SAurabindo Pillai } 11249253e115SAurabindo Pillai 112536d26912SBhawanpreet Lakha return true; 112636d26912SBhawanpreet Lakha } 112736d26912SBhawanpreet Lakha 112836d26912SBhawanpreet Lakha static void dcn302_resource_destruct(struct resource_pool *pool) 112936d26912SBhawanpreet Lakha { 113036d26912SBhawanpreet Lakha unsigned int i; 113136d26912SBhawanpreet Lakha 113236d26912SBhawanpreet Lakha for (i = 0; i < pool->stream_enc_count; i++) { 113336d26912SBhawanpreet Lakha if (pool->stream_enc[i] != NULL) { 113436d26912SBhawanpreet Lakha if (pool->stream_enc[i]->vpg != NULL) { 113536d26912SBhawanpreet Lakha kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 113636d26912SBhawanpreet Lakha pool->stream_enc[i]->vpg = NULL; 113736d26912SBhawanpreet Lakha } 113836d26912SBhawanpreet Lakha if (pool->stream_enc[i]->afmt != NULL) { 113936d26912SBhawanpreet Lakha kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 114036d26912SBhawanpreet Lakha pool->stream_enc[i]->afmt = NULL; 114136d26912SBhawanpreet Lakha } 114236d26912SBhawanpreet Lakha kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 114336d26912SBhawanpreet Lakha pool->stream_enc[i] = NULL; 114436d26912SBhawanpreet Lakha } 114536d26912SBhawanpreet Lakha } 114636d26912SBhawanpreet Lakha 114736d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_dsc; i++) { 114836d26912SBhawanpreet Lakha if (pool->dscs[i] != NULL) 114936d26912SBhawanpreet Lakha dcn20_dsc_destroy(&pool->dscs[i]); 115036d26912SBhawanpreet Lakha } 115136d26912SBhawanpreet Lakha 115236d26912SBhawanpreet Lakha if (pool->mpc != NULL) { 115336d26912SBhawanpreet Lakha kfree(TO_DCN20_MPC(pool->mpc)); 115436d26912SBhawanpreet Lakha pool->mpc = NULL; 115536d26912SBhawanpreet Lakha } 115636d26912SBhawanpreet Lakha 115736d26912SBhawanpreet Lakha if (pool->hubbub != NULL) { 115836d26912SBhawanpreet Lakha kfree(pool->hubbub); 115936d26912SBhawanpreet Lakha pool->hubbub = NULL; 116036d26912SBhawanpreet Lakha } 116136d26912SBhawanpreet Lakha 116236d26912SBhawanpreet Lakha for (i = 0; i < pool->pipe_count; i++) { 116336d26912SBhawanpreet Lakha if (pool->dpps[i] != NULL) { 116436d26912SBhawanpreet Lakha kfree(TO_DCN20_DPP(pool->dpps[i])); 116536d26912SBhawanpreet Lakha pool->dpps[i] = NULL; 116636d26912SBhawanpreet Lakha } 116736d26912SBhawanpreet Lakha 116836d26912SBhawanpreet Lakha if (pool->hubps[i] != NULL) { 116936d26912SBhawanpreet Lakha kfree(TO_DCN20_HUBP(pool->hubps[i])); 117036d26912SBhawanpreet Lakha pool->hubps[i] = NULL; 117136d26912SBhawanpreet Lakha } 117236d26912SBhawanpreet Lakha 117336d26912SBhawanpreet Lakha if (pool->irqs != NULL) 117436d26912SBhawanpreet Lakha dal_irq_service_destroy(&pool->irqs); 117536d26912SBhawanpreet Lakha } 117636d26912SBhawanpreet Lakha 117736d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_ddc; i++) { 117836d26912SBhawanpreet Lakha if (pool->engines[i] != NULL) 117936d26912SBhawanpreet Lakha dce110_engine_destroy(&pool->engines[i]); 118036d26912SBhawanpreet Lakha if (pool->hw_i2cs[i] != NULL) { 118136d26912SBhawanpreet Lakha kfree(pool->hw_i2cs[i]); 118236d26912SBhawanpreet Lakha pool->hw_i2cs[i] = NULL; 118336d26912SBhawanpreet Lakha } 118436d26912SBhawanpreet Lakha if (pool->sw_i2cs[i] != NULL) { 118536d26912SBhawanpreet Lakha kfree(pool->sw_i2cs[i]); 118636d26912SBhawanpreet Lakha pool->sw_i2cs[i] = NULL; 118736d26912SBhawanpreet Lakha } 118836d26912SBhawanpreet Lakha } 118936d26912SBhawanpreet Lakha 119036d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_opp; i++) { 119136d26912SBhawanpreet Lakha if (pool->opps[i] != NULL) 119236d26912SBhawanpreet Lakha pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 119336d26912SBhawanpreet Lakha } 119436d26912SBhawanpreet Lakha 119536d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 119636d26912SBhawanpreet Lakha if (pool->timing_generators[i] != NULL) { 119736d26912SBhawanpreet Lakha kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 119836d26912SBhawanpreet Lakha pool->timing_generators[i] = NULL; 119936d26912SBhawanpreet Lakha } 120036d26912SBhawanpreet Lakha } 120136d26912SBhawanpreet Lakha 120236d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_dwb; i++) { 120336d26912SBhawanpreet Lakha if (pool->dwbc[i] != NULL) { 120436d26912SBhawanpreet Lakha kfree(TO_DCN30_DWBC(pool->dwbc[i])); 120536d26912SBhawanpreet Lakha pool->dwbc[i] = NULL; 120636d26912SBhawanpreet Lakha } 120736d26912SBhawanpreet Lakha if (pool->mcif_wb[i] != NULL) { 120836d26912SBhawanpreet Lakha kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 120936d26912SBhawanpreet Lakha pool->mcif_wb[i] = NULL; 121036d26912SBhawanpreet Lakha } 121136d26912SBhawanpreet Lakha } 121236d26912SBhawanpreet Lakha 121336d26912SBhawanpreet Lakha for (i = 0; i < pool->audio_count; i++) { 121436d26912SBhawanpreet Lakha if (pool->audios[i]) 121536d26912SBhawanpreet Lakha dce_aud_destroy(&pool->audios[i]); 121636d26912SBhawanpreet Lakha } 121736d26912SBhawanpreet Lakha 121836d26912SBhawanpreet Lakha for (i = 0; i < pool->clk_src_count; i++) { 121936d26912SBhawanpreet Lakha if (pool->clock_sources[i] != NULL) 122036d26912SBhawanpreet Lakha dcn20_clock_source_destroy(&pool->clock_sources[i]); 122136d26912SBhawanpreet Lakha } 122236d26912SBhawanpreet Lakha 122336d26912SBhawanpreet Lakha if (pool->dp_clock_source != NULL) 122436d26912SBhawanpreet Lakha dcn20_clock_source_destroy(&pool->dp_clock_source); 122536d26912SBhawanpreet Lakha 122636d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 122736d26912SBhawanpreet Lakha if (pool->mpc_lut[i] != NULL) { 122836d26912SBhawanpreet Lakha dc_3dlut_func_release(pool->mpc_lut[i]); 122936d26912SBhawanpreet Lakha pool->mpc_lut[i] = NULL; 123036d26912SBhawanpreet Lakha } 123136d26912SBhawanpreet Lakha if (pool->mpc_shaper[i] != NULL) { 123236d26912SBhawanpreet Lakha dc_transfer_func_release(pool->mpc_shaper[i]); 123336d26912SBhawanpreet Lakha pool->mpc_shaper[i] = NULL; 123436d26912SBhawanpreet Lakha } 123536d26912SBhawanpreet Lakha } 123636d26912SBhawanpreet Lakha 123736d26912SBhawanpreet Lakha for (i = 0; i < pool->pipe_count; i++) { 123836d26912SBhawanpreet Lakha if (pool->multiple_abms[i] != NULL) 123936d26912SBhawanpreet Lakha dce_abm_destroy(&pool->multiple_abms[i]); 124036d26912SBhawanpreet Lakha } 124136d26912SBhawanpreet Lakha 124265e05ca7SJoshua Aberback if (pool->psr != NULL) 124365e05ca7SJoshua Aberback dmub_psr_destroy(&pool->psr); 124465e05ca7SJoshua Aberback 124536d26912SBhawanpreet Lakha if (pool->dccg != NULL) 124636d26912SBhawanpreet Lakha dcn_dccg_destroy(&pool->dccg); 124736d26912SBhawanpreet Lakha } 124836d26912SBhawanpreet Lakha 124936d26912SBhawanpreet Lakha static void dcn302_destroy_resource_pool(struct resource_pool **pool) 125036d26912SBhawanpreet Lakha { 125136d26912SBhawanpreet Lakha dcn302_resource_destruct(*pool); 125236d26912SBhawanpreet Lakha kfree(*pool); 125336d26912SBhawanpreet Lakha *pool = NULL; 125436d26912SBhawanpreet Lakha } 125536d26912SBhawanpreet Lakha 1256163e3bcbSSamson Tam static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1257163e3bcbSSamson Tam unsigned int *optimal_dcfclk, 1258163e3bcbSSamson Tam unsigned int *optimal_fclk) 1259163e3bcbSSamson Tam { 1260163e3bcbSSamson Tam double bw_from_dram, bw_from_dram1, bw_from_dram2; 1261163e3bcbSSamson Tam 1262163e3bcbSSamson Tam bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans * 1263163e3bcbSSamson Tam dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_dram_bw_use_normal_percent / 100); 1264163e3bcbSSamson Tam bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans * 1265163e3bcbSSamson Tam dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100); 1266163e3bcbSSamson Tam 1267163e3bcbSSamson Tam bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1268163e3bcbSSamson Tam 1269163e3bcbSSamson Tam if (optimal_fclk) 1270163e3bcbSSamson Tam *optimal_fclk = bw_from_dram / 1271163e3bcbSSamson Tam (dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1272163e3bcbSSamson Tam 1273163e3bcbSSamson Tam if (optimal_dcfclk) 1274163e3bcbSSamson Tam *optimal_dcfclk = bw_from_dram / 1275163e3bcbSSamson Tam (dcn3_02_soc.return_bus_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1276163e3bcbSSamson Tam } 1277163e3bcbSSamson Tam 1278163e3bcbSSamson Tam void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1279163e3bcbSSamson Tam { 1280163e3bcbSSamson Tam unsigned int i, j; 1281163e3bcbSSamson Tam unsigned int num_states = 0; 1282163e3bcbSSamson Tam 1283163e3bcbSSamson Tam unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 1284163e3bcbSSamson Tam unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 1285163e3bcbSSamson Tam unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 1286163e3bcbSSamson Tam unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 1287163e3bcbSSamson Tam 1288163e3bcbSSamson Tam unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; 1289163e3bcbSSamson Tam unsigned int num_dcfclk_sta_targets = 4; 1290163e3bcbSSamson Tam unsigned int num_uclk_states; 1291163e3bcbSSamson Tam 1292163e3bcbSSamson Tam 1293163e3bcbSSamson Tam if (dc->ctx->dc_bios->vram_info.num_chans) 1294163e3bcbSSamson Tam dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 1295163e3bcbSSamson Tam 1296163e3bcbSSamson Tam if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 1297163e3bcbSSamson Tam dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 1298163e3bcbSSamson Tam 1299163e3bcbSSamson Tam dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1300163e3bcbSSamson Tam dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1301163e3bcbSSamson Tam 1302163e3bcbSSamson Tam if (bw_params->clk_table.entries[0].memclk_mhz) { 1303163e3bcbSSamson Tam int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 1304163e3bcbSSamson Tam 1305163e3bcbSSamson Tam for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 1306163e3bcbSSamson Tam if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 1307163e3bcbSSamson Tam max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 1308163e3bcbSSamson Tam if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 1309163e3bcbSSamson Tam max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 1310163e3bcbSSamson Tam if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 1311163e3bcbSSamson Tam max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 1312163e3bcbSSamson Tam if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 1313163e3bcbSSamson Tam max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 1314163e3bcbSSamson Tam } 1315163e3bcbSSamson Tam if (!max_dcfclk_mhz) 1316163e3bcbSSamson Tam max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; 1317163e3bcbSSamson Tam if (!max_dispclk_mhz) 1318163e3bcbSSamson Tam max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; 1319163e3bcbSSamson Tam if (!max_dppclk_mhz) 1320163e3bcbSSamson Tam max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; 1321163e3bcbSSamson Tam if (!max_phyclk_mhz) 1322163e3bcbSSamson Tam max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; 1323163e3bcbSSamson Tam 1324163e3bcbSSamson Tam if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1325163e3bcbSSamson Tam /* If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array */ 1326163e3bcbSSamson Tam dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 1327163e3bcbSSamson Tam num_dcfclk_sta_targets++; 1328163e3bcbSSamson Tam } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1329163e3bcbSSamson Tam /* If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates */ 1330163e3bcbSSamson Tam for (i = 0; i < num_dcfclk_sta_targets; i++) { 1331163e3bcbSSamson Tam if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 1332163e3bcbSSamson Tam dcfclk_sta_targets[i] = max_dcfclk_mhz; 1333163e3bcbSSamson Tam break; 1334163e3bcbSSamson Tam } 1335163e3bcbSSamson Tam } 1336163e3bcbSSamson Tam /* Update size of array since we "removed" duplicates */ 1337163e3bcbSSamson Tam num_dcfclk_sta_targets = i + 1; 1338163e3bcbSSamson Tam } 1339163e3bcbSSamson Tam 1340163e3bcbSSamson Tam num_uclk_states = bw_params->clk_table.num_entries; 1341163e3bcbSSamson Tam 1342163e3bcbSSamson Tam /* Calculate optimal dcfclk for each uclk */ 1343163e3bcbSSamson Tam for (i = 0; i < num_uclk_states; i++) { 1344163e3bcbSSamson Tam dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 1345163e3bcbSSamson Tam &optimal_dcfclk_for_uclk[i], NULL); 1346163e3bcbSSamson Tam if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 1347163e3bcbSSamson Tam optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 1348163e3bcbSSamson Tam } 1349163e3bcbSSamson Tam } 1350163e3bcbSSamson Tam 1351163e3bcbSSamson Tam /* Calculate optimal uclk for each dcfclk sta target */ 1352163e3bcbSSamson Tam for (i = 0; i < num_dcfclk_sta_targets; i++) { 1353163e3bcbSSamson Tam for (j = 0; j < num_uclk_states; j++) { 1354163e3bcbSSamson Tam if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 1355163e3bcbSSamson Tam optimal_uclk_for_dcfclk_sta_targets[i] = 1356163e3bcbSSamson Tam bw_params->clk_table.entries[j].memclk_mhz * 16; 1357163e3bcbSSamson Tam break; 1358163e3bcbSSamson Tam } 1359163e3bcbSSamson Tam } 1360163e3bcbSSamson Tam } 1361163e3bcbSSamson Tam 1362163e3bcbSSamson Tam i = 0; 1363163e3bcbSSamson Tam j = 0; 1364163e3bcbSSamson Tam /* create the final dcfclk and uclk table */ 1365163e3bcbSSamson Tam while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 1366163e3bcbSSamson Tam if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 1367163e3bcbSSamson Tam dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1368163e3bcbSSamson Tam dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1369163e3bcbSSamson Tam } else { 1370163e3bcbSSamson Tam if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1371163e3bcbSSamson Tam dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1372163e3bcbSSamson Tam dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1373163e3bcbSSamson Tam } else { 1374163e3bcbSSamson Tam j = num_uclk_states; 1375163e3bcbSSamson Tam } 1376163e3bcbSSamson Tam } 1377163e3bcbSSamson Tam } 1378163e3bcbSSamson Tam 1379163e3bcbSSamson Tam while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 1380163e3bcbSSamson Tam dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1381163e3bcbSSamson Tam dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1382163e3bcbSSamson Tam } 1383163e3bcbSSamson Tam 1384163e3bcbSSamson Tam while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 1385163e3bcbSSamson Tam optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1386163e3bcbSSamson Tam dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1387163e3bcbSSamson Tam dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1388163e3bcbSSamson Tam } 1389163e3bcbSSamson Tam 1390163e3bcbSSamson Tam dcn3_02_soc.num_states = num_states; 1391163e3bcbSSamson Tam for (i = 0; i < dcn3_02_soc.num_states; i++) { 1392163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].state = i; 1393163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 1394163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 1395163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 1396163e3bcbSSamson Tam 1397163e3bcbSSamson Tam /* Fill all states with max values of all other clocks */ 1398163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1399163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1400163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1401163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz; 1402*f30f5515SBindu Ramamurthy if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 1403*f30f5515SBindu Ramamurthy dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz; 1404*f30f5515SBindu Ramamurthy else 1405*f30f5515SBindu Ramamurthy dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; 1406163e3bcbSSamson Tam /* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */ 1407*f30f5515SBindu Ramamurthy /* FCLK, PHYCLK_D18, DSCCLK */ 1408163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz; 1409163e3bcbSSamson Tam dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz; 1410163e3bcbSSamson Tam } 1411163e3bcbSSamson Tam /* re-init DML with updated bb */ 1412163e3bcbSSamson Tam dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1413163e3bcbSSamson Tam if (dc->current_state) 1414163e3bcbSSamson Tam dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1415163e3bcbSSamson Tam } 1416163e3bcbSSamson Tam } 1417163e3bcbSSamson Tam 141836d26912SBhawanpreet Lakha static struct resource_funcs dcn302_res_pool_funcs = { 141936d26912SBhawanpreet Lakha .destroy = dcn302_destroy_resource_pool, 142036d26912SBhawanpreet Lakha .link_enc_create = dcn302_link_encoder_create, 142136d26912SBhawanpreet Lakha .panel_cntl_create = dcn302_panel_cntl_create, 142236d26912SBhawanpreet Lakha .validate_bandwidth = dcn30_validate_bandwidth, 142336d26912SBhawanpreet Lakha .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1424443dfba0SDmytro Laktyushkin .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 142536d26912SBhawanpreet Lakha .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 142636d26912SBhawanpreet Lakha .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 142736d26912SBhawanpreet Lakha .add_stream_to_ctx = dcn30_add_stream_to_ctx, 142836d26912SBhawanpreet Lakha .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 142936d26912SBhawanpreet Lakha .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 143036d26912SBhawanpreet Lakha .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 143136d26912SBhawanpreet Lakha .set_mcif_arb_params = dcn30_set_mcif_arb_params, 143236d26912SBhawanpreet Lakha .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 143336d26912SBhawanpreet Lakha .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 143436d26912SBhawanpreet Lakha .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1435163e3bcbSSamson Tam .update_bw_bounding_box = dcn302_update_bw_bounding_box, 143636d26912SBhawanpreet Lakha .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 143736d26912SBhawanpreet Lakha }; 143836d26912SBhawanpreet Lakha 143936d26912SBhawanpreet Lakha static struct dc_cap_funcs cap_funcs = { 144036d26912SBhawanpreet Lakha .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 144136d26912SBhawanpreet Lakha }; 144236d26912SBhawanpreet Lakha 144336d26912SBhawanpreet Lakha static const struct bios_registers bios_regs = { 144436d26912SBhawanpreet Lakha NBIO_SR(BIOS_SCRATCH_3), 144536d26912SBhawanpreet Lakha NBIO_SR(BIOS_SCRATCH_6) 144636d26912SBhawanpreet Lakha }; 144736d26912SBhawanpreet Lakha 144836d26912SBhawanpreet Lakha static const struct dccg_registers dccg_regs = { 144936d26912SBhawanpreet Lakha DCCG_REG_LIST_DCN3_02() 145036d26912SBhawanpreet Lakha }; 145136d26912SBhawanpreet Lakha 145236d26912SBhawanpreet Lakha static const struct dccg_shift dccg_shift = { 145336d26912SBhawanpreet Lakha DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 145436d26912SBhawanpreet Lakha }; 145536d26912SBhawanpreet Lakha 145636d26912SBhawanpreet Lakha static const struct dccg_mask dccg_mask = { 145736d26912SBhawanpreet Lakha DCCG_MASK_SH_LIST_DCN3_02(_MASK) 145836d26912SBhawanpreet Lakha }; 145936d26912SBhawanpreet Lakha 146036d26912SBhawanpreet Lakha #define abm_regs(id)\ 146136d26912SBhawanpreet Lakha [id] = { ABM_DCN301_REG_LIST(id) } 146236d26912SBhawanpreet Lakha 146336d26912SBhawanpreet Lakha static const struct dce_abm_registers abm_regs[] = { 146436d26912SBhawanpreet Lakha abm_regs(0), 146536d26912SBhawanpreet Lakha abm_regs(1), 146636d26912SBhawanpreet Lakha abm_regs(2), 146736d26912SBhawanpreet Lakha abm_regs(3), 146836d26912SBhawanpreet Lakha abm_regs(4) 146936d26912SBhawanpreet Lakha }; 147036d26912SBhawanpreet Lakha 147136d26912SBhawanpreet Lakha static const struct dce_abm_shift abm_shift = { 1472df043738SRoman Li ABM_MASK_SH_LIST_DCN30(__SHIFT) 147336d26912SBhawanpreet Lakha }; 147436d26912SBhawanpreet Lakha 147536d26912SBhawanpreet Lakha static const struct dce_abm_mask abm_mask = { 1476df043738SRoman Li ABM_MASK_SH_LIST_DCN30(_MASK) 147736d26912SBhawanpreet Lakha }; 147836d26912SBhawanpreet Lakha 147936d26912SBhawanpreet Lakha static bool dcn302_resource_construct( 148036d26912SBhawanpreet Lakha uint8_t num_virtual_links, 148136d26912SBhawanpreet Lakha struct dc *dc, 148236d26912SBhawanpreet Lakha struct resource_pool *pool) 148336d26912SBhawanpreet Lakha { 148436d26912SBhawanpreet Lakha int i; 148536d26912SBhawanpreet Lakha struct dc_context *ctx = dc->ctx; 148636d26912SBhawanpreet Lakha struct irq_service_init_data init_data; 148736d26912SBhawanpreet Lakha 148836d26912SBhawanpreet Lakha ctx->dc_bios->regs = &bios_regs; 148936d26912SBhawanpreet Lakha 149036d26912SBhawanpreet Lakha pool->res_cap = &res_cap_dcn302; 149136d26912SBhawanpreet Lakha 149236d26912SBhawanpreet Lakha pool->funcs = &dcn302_res_pool_funcs; 149336d26912SBhawanpreet Lakha 149436d26912SBhawanpreet Lakha /************************************************* 149536d26912SBhawanpreet Lakha * Resource + asic cap harcoding * 149636d26912SBhawanpreet Lakha *************************************************/ 149736d26912SBhawanpreet Lakha pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 149836d26912SBhawanpreet Lakha pool->pipe_count = pool->res_cap->num_timing_generator; 149936d26912SBhawanpreet Lakha pool->mpcc_count = pool->res_cap->num_timing_generator; 150036d26912SBhawanpreet Lakha dc->caps.max_downscale_ratio = 600; 150136d26912SBhawanpreet Lakha dc->caps.i2c_speed_in_khz = 100; 1502e97978e8SCharlene Liu dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 150336d26912SBhawanpreet Lakha dc->caps.max_cursor_size = 256; 150406722b37SAshley Thomas dc->caps.min_horizontal_blanking_period = 80; 150536d26912SBhawanpreet Lakha dc->caps.dmdata_alloc_size = 2048; 1506ea7154d8SBhawanpreet Lakha dc->caps.mall_size_per_mem_channel = 4; 1507ea7154d8SBhawanpreet Lakha /* total size = mall per channel * num channels * 1024 * 1024 */ 1508ea7154d8SBhawanpreet Lakha dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 15097fc75382SBhawanpreet Lakha dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 151036d26912SBhawanpreet Lakha dc->caps.max_slave_planes = 1; 1511ae030570SAtufa Khan dc->caps.max_slave_yuv_planes = 1; 1512ae030570SAtufa Khan dc->caps.max_slave_rgb_planes = 1; 151336d26912SBhawanpreet Lakha dc->caps.post_blend_color_processing = true; 151436d26912SBhawanpreet Lakha dc->caps.force_dp_tps4_for_cp2520 = true; 151536d26912SBhawanpreet Lakha dc->caps.extended_aux_timeout_support = true; 151636d26912SBhawanpreet Lakha dc->caps.dmcub_support = true; 151736d26912SBhawanpreet Lakha 151836d26912SBhawanpreet Lakha /* Color pipeline capabilities */ 151936d26912SBhawanpreet Lakha dc->caps.color.dpp.dcn_arch = 1; 152036d26912SBhawanpreet Lakha dc->caps.color.dpp.input_lut_shared = 0; 152136d26912SBhawanpreet Lakha dc->caps.color.dpp.icsc = 1; 152236d26912SBhawanpreet Lakha dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 152336d26912SBhawanpreet Lakha dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 152436d26912SBhawanpreet Lakha dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 152536d26912SBhawanpreet Lakha dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 152636d26912SBhawanpreet Lakha dc->caps.color.dpp.dgam_rom_caps.pq = 1; 152736d26912SBhawanpreet Lakha dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 152836d26912SBhawanpreet Lakha dc->caps.color.dpp.post_csc = 1; 152936d26912SBhawanpreet Lakha dc->caps.color.dpp.gamma_corr = 1; 1530c6160900SJing Zhou dc->caps.color.dpp.dgam_rom_for_yuv = 0; 153136d26912SBhawanpreet Lakha 153236d26912SBhawanpreet Lakha dc->caps.color.dpp.hw_3d_lut = 1; 153336d26912SBhawanpreet Lakha dc->caps.color.dpp.ogam_ram = 1; 153436d26912SBhawanpreet Lakha // no OGAM ROM on DCN3 153536d26912SBhawanpreet Lakha dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 153636d26912SBhawanpreet Lakha dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 153736d26912SBhawanpreet Lakha dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 153836d26912SBhawanpreet Lakha dc->caps.color.dpp.ogam_rom_caps.pq = 0; 153936d26912SBhawanpreet Lakha dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 154036d26912SBhawanpreet Lakha dc->caps.color.dpp.ocsc = 0; 154136d26912SBhawanpreet Lakha 154236d26912SBhawanpreet Lakha dc->caps.color.mpc.gamut_remap = 1; 154336d26912SBhawanpreet Lakha dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 154436d26912SBhawanpreet Lakha dc->caps.color.mpc.ogam_ram = 1; 154536d26912SBhawanpreet Lakha dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 154636d26912SBhawanpreet Lakha dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 154736d26912SBhawanpreet Lakha dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 154836d26912SBhawanpreet Lakha dc->caps.color.mpc.ogam_rom_caps.pq = 0; 154936d26912SBhawanpreet Lakha dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 155036d26912SBhawanpreet Lakha dc->caps.color.mpc.ocsc = 1; 155136d26912SBhawanpreet Lakha 155236d26912SBhawanpreet Lakha if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 155336d26912SBhawanpreet Lakha dc->debug = debug_defaults_drv; 155436d26912SBhawanpreet Lakha else 155536d26912SBhawanpreet Lakha dc->debug = debug_defaults_diags; 155636d26912SBhawanpreet Lakha 155736d26912SBhawanpreet Lakha // Init the vm_helper 155836d26912SBhawanpreet Lakha if (dc->vm_helper) 155936d26912SBhawanpreet Lakha vm_helper_init(dc->vm_helper, 16); 156036d26912SBhawanpreet Lakha 156136d26912SBhawanpreet Lakha /************************************************* 156236d26912SBhawanpreet Lakha * Create resources * 156336d26912SBhawanpreet Lakha *************************************************/ 156436d26912SBhawanpreet Lakha 156536d26912SBhawanpreet Lakha /* Clock Sources for Pixel Clock*/ 156636d26912SBhawanpreet Lakha pool->clock_sources[DCN302_CLK_SRC_PLL0] = 156736d26912SBhawanpreet Lakha dcn302_clock_source_create(ctx, ctx->dc_bios, 156836d26912SBhawanpreet Lakha CLOCK_SOURCE_COMBO_PHY_PLL0, 156936d26912SBhawanpreet Lakha &clk_src_regs[0], false); 157036d26912SBhawanpreet Lakha pool->clock_sources[DCN302_CLK_SRC_PLL1] = 157136d26912SBhawanpreet Lakha dcn302_clock_source_create(ctx, ctx->dc_bios, 157236d26912SBhawanpreet Lakha CLOCK_SOURCE_COMBO_PHY_PLL1, 157336d26912SBhawanpreet Lakha &clk_src_regs[1], false); 157436d26912SBhawanpreet Lakha pool->clock_sources[DCN302_CLK_SRC_PLL2] = 157536d26912SBhawanpreet Lakha dcn302_clock_source_create(ctx, ctx->dc_bios, 157636d26912SBhawanpreet Lakha CLOCK_SOURCE_COMBO_PHY_PLL2, 157736d26912SBhawanpreet Lakha &clk_src_regs[2], false); 157836d26912SBhawanpreet Lakha pool->clock_sources[DCN302_CLK_SRC_PLL3] = 157936d26912SBhawanpreet Lakha dcn302_clock_source_create(ctx, ctx->dc_bios, 158036d26912SBhawanpreet Lakha CLOCK_SOURCE_COMBO_PHY_PLL3, 158136d26912SBhawanpreet Lakha &clk_src_regs[3], false); 158236d26912SBhawanpreet Lakha pool->clock_sources[DCN302_CLK_SRC_PLL4] = 158336d26912SBhawanpreet Lakha dcn302_clock_source_create(ctx, ctx->dc_bios, 158436d26912SBhawanpreet Lakha CLOCK_SOURCE_COMBO_PHY_PLL4, 158536d26912SBhawanpreet Lakha &clk_src_regs[4], false); 158636d26912SBhawanpreet Lakha 158736d26912SBhawanpreet Lakha pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 158836d26912SBhawanpreet Lakha 158936d26912SBhawanpreet Lakha /* todo: not reuse phy_pll registers */ 159036d26912SBhawanpreet Lakha pool->dp_clock_source = 159136d26912SBhawanpreet Lakha dcn302_clock_source_create(ctx, ctx->dc_bios, 159236d26912SBhawanpreet Lakha CLOCK_SOURCE_ID_DP_DTO, 159336d26912SBhawanpreet Lakha &clk_src_regs[0], true); 159436d26912SBhawanpreet Lakha 159536d26912SBhawanpreet Lakha for (i = 0; i < pool->clk_src_count; i++) { 159636d26912SBhawanpreet Lakha if (pool->clock_sources[i] == NULL) { 159736d26912SBhawanpreet Lakha dm_error("DC: failed to create clock sources!\n"); 159836d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 159936d26912SBhawanpreet Lakha goto create_fail; 160036d26912SBhawanpreet Lakha } 160136d26912SBhawanpreet Lakha } 160236d26912SBhawanpreet Lakha 160336d26912SBhawanpreet Lakha /* DCCG */ 160436d26912SBhawanpreet Lakha pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 160536d26912SBhawanpreet Lakha if (pool->dccg == NULL) { 160636d26912SBhawanpreet Lakha dm_error("DC: failed to create dccg!\n"); 160736d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 160836d26912SBhawanpreet Lakha goto create_fail; 160936d26912SBhawanpreet Lakha } 161036d26912SBhawanpreet Lakha 161136d26912SBhawanpreet Lakha /* PP Lib and SMU interfaces */ 161236d26912SBhawanpreet Lakha init_soc_bounding_box(dc, pool); 161336d26912SBhawanpreet Lakha 161436d26912SBhawanpreet Lakha /* DML */ 161536d26912SBhawanpreet Lakha dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 161636d26912SBhawanpreet Lakha 161736d26912SBhawanpreet Lakha /* IRQ */ 161836d26912SBhawanpreet Lakha init_data.ctx = dc->ctx; 161936d26912SBhawanpreet Lakha pool->irqs = dal_irq_service_dcn302_create(&init_data); 162036d26912SBhawanpreet Lakha if (!pool->irqs) 162136d26912SBhawanpreet Lakha goto create_fail; 162236d26912SBhawanpreet Lakha 162336d26912SBhawanpreet Lakha /* HUBBUB */ 162436d26912SBhawanpreet Lakha pool->hubbub = dcn302_hubbub_create(ctx); 162536d26912SBhawanpreet Lakha if (pool->hubbub == NULL) { 162636d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 162736d26912SBhawanpreet Lakha dm_error("DC: failed to create hubbub!\n"); 162836d26912SBhawanpreet Lakha goto create_fail; 162936d26912SBhawanpreet Lakha } 163036d26912SBhawanpreet Lakha 163136d26912SBhawanpreet Lakha /* HUBPs, DPPs, OPPs and TGs */ 163236d26912SBhawanpreet Lakha for (i = 0; i < pool->pipe_count; i++) { 163336d26912SBhawanpreet Lakha pool->hubps[i] = dcn302_hubp_create(ctx, i); 163436d26912SBhawanpreet Lakha if (pool->hubps[i] == NULL) { 163536d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 163636d26912SBhawanpreet Lakha dm_error("DC: failed to create hubps!\n"); 163736d26912SBhawanpreet Lakha goto create_fail; 163836d26912SBhawanpreet Lakha } 163936d26912SBhawanpreet Lakha 164036d26912SBhawanpreet Lakha pool->dpps[i] = dcn302_dpp_create(ctx, i); 164136d26912SBhawanpreet Lakha if (pool->dpps[i] == NULL) { 164236d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 164336d26912SBhawanpreet Lakha dm_error("DC: failed to create dpps!\n"); 164436d26912SBhawanpreet Lakha goto create_fail; 164536d26912SBhawanpreet Lakha } 164636d26912SBhawanpreet Lakha } 164736d26912SBhawanpreet Lakha 164836d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_opp; i++) { 164936d26912SBhawanpreet Lakha pool->opps[i] = dcn302_opp_create(ctx, i); 165036d26912SBhawanpreet Lakha if (pool->opps[i] == NULL) { 165136d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 165236d26912SBhawanpreet Lakha dm_error("DC: failed to create output pixel processor!\n"); 165336d26912SBhawanpreet Lakha goto create_fail; 165436d26912SBhawanpreet Lakha } 165536d26912SBhawanpreet Lakha } 165636d26912SBhawanpreet Lakha 165736d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 165836d26912SBhawanpreet Lakha pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 165936d26912SBhawanpreet Lakha if (pool->timing_generators[i] == NULL) { 166036d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 166136d26912SBhawanpreet Lakha dm_error("DC: failed to create tg!\n"); 166236d26912SBhawanpreet Lakha goto create_fail; 166336d26912SBhawanpreet Lakha } 166436d26912SBhawanpreet Lakha } 166536d26912SBhawanpreet Lakha pool->timing_generator_count = i; 166636d26912SBhawanpreet Lakha 166765e05ca7SJoshua Aberback /* PSR */ 166865e05ca7SJoshua Aberback pool->psr = dmub_psr_create(ctx); 166965e05ca7SJoshua Aberback if (pool->psr == NULL) { 167065e05ca7SJoshua Aberback dm_error("DC: failed to create psr!\n"); 167165e05ca7SJoshua Aberback BREAK_TO_DEBUGGER(); 167265e05ca7SJoshua Aberback goto create_fail; 167365e05ca7SJoshua Aberback } 167465e05ca7SJoshua Aberback 167536d26912SBhawanpreet Lakha /* ABMs */ 167636d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 167736d26912SBhawanpreet Lakha pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 167836d26912SBhawanpreet Lakha if (pool->multiple_abms[i] == NULL) { 167936d26912SBhawanpreet Lakha dm_error("DC: failed to create abm for pipe %d!\n", i); 168036d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 168136d26912SBhawanpreet Lakha goto create_fail; 168236d26912SBhawanpreet Lakha } 168336d26912SBhawanpreet Lakha } 168436d26912SBhawanpreet Lakha 168536d26912SBhawanpreet Lakha /* MPC and DSC */ 168636d26912SBhawanpreet Lakha pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 168736d26912SBhawanpreet Lakha if (pool->mpc == NULL) { 168836d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 168936d26912SBhawanpreet Lakha dm_error("DC: failed to create mpc!\n"); 169036d26912SBhawanpreet Lakha goto create_fail; 169136d26912SBhawanpreet Lakha } 169236d26912SBhawanpreet Lakha 169336d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_dsc; i++) { 169436d26912SBhawanpreet Lakha pool->dscs[i] = dcn302_dsc_create(ctx, i); 169536d26912SBhawanpreet Lakha if (pool->dscs[i] == NULL) { 169636d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 169736d26912SBhawanpreet Lakha dm_error("DC: failed to create display stream compressor %d!\n", i); 169836d26912SBhawanpreet Lakha goto create_fail; 169936d26912SBhawanpreet Lakha } 170036d26912SBhawanpreet Lakha } 170136d26912SBhawanpreet Lakha 170236d26912SBhawanpreet Lakha /* DWB and MMHUBBUB */ 170336d26912SBhawanpreet Lakha if (!dcn302_dwbc_create(ctx, pool)) { 170436d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 170536d26912SBhawanpreet Lakha dm_error("DC: failed to create dwbc!\n"); 170636d26912SBhawanpreet Lakha goto create_fail; 170736d26912SBhawanpreet Lakha } 170836d26912SBhawanpreet Lakha 170936d26912SBhawanpreet Lakha if (!dcn302_mmhubbub_create(ctx, pool)) { 171036d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 171136d26912SBhawanpreet Lakha dm_error("DC: failed to create mcif_wb!\n"); 171236d26912SBhawanpreet Lakha goto create_fail; 171336d26912SBhawanpreet Lakha } 171436d26912SBhawanpreet Lakha 171536d26912SBhawanpreet Lakha /* AUX and I2C */ 171636d26912SBhawanpreet Lakha for (i = 0; i < pool->res_cap->num_ddc; i++) { 171736d26912SBhawanpreet Lakha pool->engines[i] = dcn302_aux_engine_create(ctx, i); 171836d26912SBhawanpreet Lakha if (pool->engines[i] == NULL) { 171936d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 172036d26912SBhawanpreet Lakha dm_error("DC:failed to create aux engine!!\n"); 172136d26912SBhawanpreet Lakha goto create_fail; 172236d26912SBhawanpreet Lakha } 172336d26912SBhawanpreet Lakha pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 172436d26912SBhawanpreet Lakha if (pool->hw_i2cs[i] == NULL) { 172536d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 172636d26912SBhawanpreet Lakha dm_error("DC:failed to create hw i2c!!\n"); 172736d26912SBhawanpreet Lakha goto create_fail; 172836d26912SBhawanpreet Lakha } 172936d26912SBhawanpreet Lakha pool->sw_i2cs[i] = NULL; 173036d26912SBhawanpreet Lakha } 173136d26912SBhawanpreet Lakha 173236d26912SBhawanpreet Lakha /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 173336d26912SBhawanpreet Lakha if (!resource_construct(num_virtual_links, dc, pool, 173436d26912SBhawanpreet Lakha (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 173536d26912SBhawanpreet Lakha &res_create_funcs : &res_create_maximus_funcs))) 173636d26912SBhawanpreet Lakha goto create_fail; 173736d26912SBhawanpreet Lakha 173836d26912SBhawanpreet Lakha /* HW Sequencer and Plane caps */ 173936d26912SBhawanpreet Lakha dcn302_hw_sequencer_construct(dc); 174036d26912SBhawanpreet Lakha 174136d26912SBhawanpreet Lakha dc->caps.max_planes = pool->pipe_count; 174236d26912SBhawanpreet Lakha 174336d26912SBhawanpreet Lakha for (i = 0; i < dc->caps.max_planes; ++i) 174436d26912SBhawanpreet Lakha dc->caps.planes[i] = plane_cap; 174536d26912SBhawanpreet Lakha 174636d26912SBhawanpreet Lakha dc->cap_funcs = cap_funcs; 174736d26912SBhawanpreet Lakha 174836d26912SBhawanpreet Lakha return true; 174936d26912SBhawanpreet Lakha 175036d26912SBhawanpreet Lakha create_fail: 175136d26912SBhawanpreet Lakha 175236d26912SBhawanpreet Lakha dcn302_resource_destruct(pool); 175336d26912SBhawanpreet Lakha 175436d26912SBhawanpreet Lakha return false; 175536d26912SBhawanpreet Lakha } 175636d26912SBhawanpreet Lakha 175736d26912SBhawanpreet Lakha struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 175836d26912SBhawanpreet Lakha { 175936d26912SBhawanpreet Lakha struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 176036d26912SBhawanpreet Lakha 176136d26912SBhawanpreet Lakha if (!pool) 176236d26912SBhawanpreet Lakha return NULL; 176336d26912SBhawanpreet Lakha 176436d26912SBhawanpreet Lakha if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 176536d26912SBhawanpreet Lakha return pool; 176636d26912SBhawanpreet Lakha 176736d26912SBhawanpreet Lakha BREAK_TO_DEBUGGER(); 176836d26912SBhawanpreet Lakha kfree(pool); 176936d26912SBhawanpreet Lakha return NULL; 177036d26912SBhawanpreet Lakha } 1771