136d26912SBhawanpreet Lakha /*
236d26912SBhawanpreet Lakha  * Copyright 2020 Advanced Micro Devices, Inc.
336d26912SBhawanpreet Lakha  *
436d26912SBhawanpreet Lakha  * Permission is hereby granted, free of charge, to any person obtaining a
536d26912SBhawanpreet Lakha  * copy of this software and associated documentation files (the "Software"),
636d26912SBhawanpreet Lakha  * to deal in the Software without restriction, including without limitation
736d26912SBhawanpreet Lakha  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
836d26912SBhawanpreet Lakha  * and/or sell copies of the Software, and to permit persons to whom the
936d26912SBhawanpreet Lakha  * Software is furnished to do so, subject to the following conditions:
1036d26912SBhawanpreet Lakha  *
1136d26912SBhawanpreet Lakha  * The above copyright notice and this permission notice shall be included in
1236d26912SBhawanpreet Lakha  * all copies or substantial portions of the Software.
1336d26912SBhawanpreet Lakha  *
1436d26912SBhawanpreet Lakha  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1536d26912SBhawanpreet Lakha  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1636d26912SBhawanpreet Lakha  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1736d26912SBhawanpreet Lakha  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1836d26912SBhawanpreet Lakha  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1936d26912SBhawanpreet Lakha  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2036d26912SBhawanpreet Lakha  * OTHER DEALINGS IN THE SOFTWARE.
2136d26912SBhawanpreet Lakha  *
2236d26912SBhawanpreet Lakha  * Authors: AMD
2336d26912SBhawanpreet Lakha  *
2436d26912SBhawanpreet Lakha  */
2536d26912SBhawanpreet Lakha 
2636d26912SBhawanpreet Lakha #include "dcn302_init.h"
2736d26912SBhawanpreet Lakha #include "dcn302_resource.h"
2836d26912SBhawanpreet Lakha #include "dcn302_dccg.h"
2936d26912SBhawanpreet Lakha #include "irq/dcn302/irq_service_dcn302.h"
3036d26912SBhawanpreet Lakha 
3136d26912SBhawanpreet Lakha #include "dcn30/dcn30_dio_link_encoder.h"
3236d26912SBhawanpreet Lakha #include "dcn30/dcn30_dio_stream_encoder.h"
3336d26912SBhawanpreet Lakha #include "dcn30/dcn30_dwb.h"
3436d26912SBhawanpreet Lakha #include "dcn30/dcn30_dpp.h"
3536d26912SBhawanpreet Lakha #include "dcn30/dcn30_hubbub.h"
3636d26912SBhawanpreet Lakha #include "dcn30/dcn30_hubp.h"
3736d26912SBhawanpreet Lakha #include "dcn30/dcn30_mmhubbub.h"
3836d26912SBhawanpreet Lakha #include "dcn30/dcn30_mpc.h"
3936d26912SBhawanpreet Lakha #include "dcn30/dcn30_opp.h"
4036d26912SBhawanpreet Lakha #include "dcn30/dcn30_optc.h"
4136d26912SBhawanpreet Lakha #include "dcn30/dcn30_resource.h"
4236d26912SBhawanpreet Lakha 
4336d26912SBhawanpreet Lakha #include "dcn20/dcn20_dsc.h"
4436d26912SBhawanpreet Lakha #include "dcn20/dcn20_resource.h"
4536d26912SBhawanpreet Lakha 
4636d26912SBhawanpreet Lakha #include "dcn10/dcn10_resource.h"
4736d26912SBhawanpreet Lakha 
4836d26912SBhawanpreet Lakha #include "dce/dce_abm.h"
4936d26912SBhawanpreet Lakha #include "dce/dce_audio.h"
5036d26912SBhawanpreet Lakha #include "dce/dce_aux.h"
5136d26912SBhawanpreet Lakha #include "dce/dce_clock_source.h"
5236d26912SBhawanpreet Lakha #include "dce/dce_hwseq.h"
5336d26912SBhawanpreet Lakha #include "dce/dce_i2c_hw.h"
5436d26912SBhawanpreet Lakha #include "dce/dce_panel_cntl.h"
5536d26912SBhawanpreet Lakha #include "dce/dmub_abm.h"
5665e05ca7SJoshua Aberback #include "dce/dmub_psr.h"
57*163e3bcbSSamson Tam #include "clk_mgr.h"
5836d26912SBhawanpreet Lakha 
5936d26912SBhawanpreet Lakha #include "hw_sequencer_private.h"
6036d26912SBhawanpreet Lakha #include "reg_helper.h"
6136d26912SBhawanpreet Lakha #include "resource.h"
6236d26912SBhawanpreet Lakha #include "vm_helper.h"
6336d26912SBhawanpreet Lakha 
6436d26912SBhawanpreet Lakha #include "dimgrey_cavefish_ip_offset.h"
659713158cSBhawanpreet Lakha #include "dcn/dcn_3_0_2_offset.h"
669713158cSBhawanpreet Lakha #include "dcn/dcn_3_0_2_sh_mask.h"
6736d26912SBhawanpreet Lakha #include "dcn/dpcs_3_0_0_offset.h"
6836d26912SBhawanpreet Lakha #include "dcn/dpcs_3_0_0_sh_mask.h"
6936d26912SBhawanpreet Lakha #include "nbio/nbio_7_4_offset.h"
7026d94a46SBhawanpreet Lakha #include "amdgpu_socbb.h"
7136d26912SBhawanpreet Lakha 
7236d26912SBhawanpreet Lakha #define DC_LOGGER_INIT(logger)
7336d26912SBhawanpreet Lakha 
7436d26912SBhawanpreet Lakha struct _vcs_dpi_ip_params_st dcn3_02_ip = {
7536d26912SBhawanpreet Lakha 		.use_min_dcfclk = 0,
7636d26912SBhawanpreet Lakha 		.clamp_min_dcfclk = 0,
7736d26912SBhawanpreet Lakha 		.odm_capable = 1,
7836d26912SBhawanpreet Lakha 		.gpuvm_enable = 1,
7936d26912SBhawanpreet Lakha 		.hostvm_enable = 0,
8036d26912SBhawanpreet Lakha 		.gpuvm_max_page_table_levels = 4,
8136d26912SBhawanpreet Lakha 		.hostvm_max_page_table_levels = 4,
8236d26912SBhawanpreet Lakha 		.hostvm_cached_page_table_levels = 0,
8336d26912SBhawanpreet Lakha 		.pte_group_size_bytes = 2048,
8436d26912SBhawanpreet Lakha 		.num_dsc = 5,
8536d26912SBhawanpreet Lakha 		.rob_buffer_size_kbytes = 184,
8636d26912SBhawanpreet Lakha 		.det_buffer_size_kbytes = 184,
8736d26912SBhawanpreet Lakha 		.dpte_buffer_size_in_pte_reqs_luma = 64,
8836d26912SBhawanpreet Lakha 		.dpte_buffer_size_in_pte_reqs_chroma = 34,
8936d26912SBhawanpreet Lakha 		.pde_proc_buffer_size_64k_reqs = 48,
9036d26912SBhawanpreet Lakha 		.dpp_output_buffer_pixels = 2560,
9136d26912SBhawanpreet Lakha 		.opp_output_buffer_lines = 1,
9236d26912SBhawanpreet Lakha 		.pixel_chunk_size_kbytes = 8,
9336d26912SBhawanpreet Lakha 		.pte_enable = 1,
9436d26912SBhawanpreet Lakha 		.max_page_table_levels = 2,
9536d26912SBhawanpreet Lakha 		.pte_chunk_size_kbytes = 2,  // ?
9636d26912SBhawanpreet Lakha 		.meta_chunk_size_kbytes = 2,
9736d26912SBhawanpreet Lakha 		.writeback_chunk_size_kbytes = 8,
9836d26912SBhawanpreet Lakha 		.line_buffer_size_bits = 789504,
9936d26912SBhawanpreet Lakha 		.is_line_buffer_bpp_fixed = 0,  // ?
10036d26912SBhawanpreet Lakha 		.line_buffer_fixed_bpp = 0,     // ?
10136d26912SBhawanpreet Lakha 		.dcc_supported = true,
10236d26912SBhawanpreet Lakha 		.writeback_interface_buffer_size_kbytes = 90,
10336d26912SBhawanpreet Lakha 		.writeback_line_buffer_buffer_size = 0,
10436d26912SBhawanpreet Lakha 		.max_line_buffer_lines = 12,
10536d26912SBhawanpreet Lakha 		.writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
10636d26912SBhawanpreet Lakha 		.writeback_chroma_buffer_size_kbytes = 8,
10736d26912SBhawanpreet Lakha 		.writeback_chroma_line_buffer_width_pixels = 4,
10836d26912SBhawanpreet Lakha 		.writeback_max_hscl_ratio = 1,
10936d26912SBhawanpreet Lakha 		.writeback_max_vscl_ratio = 1,
11036d26912SBhawanpreet Lakha 		.writeback_min_hscl_ratio = 1,
11136d26912SBhawanpreet Lakha 		.writeback_min_vscl_ratio = 1,
11236d26912SBhawanpreet Lakha 		.writeback_max_hscl_taps = 1,
11336d26912SBhawanpreet Lakha 		.writeback_max_vscl_taps = 1,
11436d26912SBhawanpreet Lakha 		.writeback_line_buffer_luma_buffer_size = 0,
11536d26912SBhawanpreet Lakha 		.writeback_line_buffer_chroma_buffer_size = 14643,
11636d26912SBhawanpreet Lakha 		.cursor_buffer_size = 8,
11736d26912SBhawanpreet Lakha 		.cursor_chunk_size = 2,
11836d26912SBhawanpreet Lakha 		.max_num_otg = 5,
11936d26912SBhawanpreet Lakha 		.max_num_dpp = 5,
12036d26912SBhawanpreet Lakha 		.max_num_wb = 1,
12136d26912SBhawanpreet Lakha 		.max_dchub_pscl_bw_pix_per_clk = 4,
12236d26912SBhawanpreet Lakha 		.max_pscl_lb_bw_pix_per_clk = 2,
12336d26912SBhawanpreet Lakha 		.max_lb_vscl_bw_pix_per_clk = 4,
12436d26912SBhawanpreet Lakha 		.max_vscl_hscl_bw_pix_per_clk = 4,
12536d26912SBhawanpreet Lakha 		.max_hscl_ratio = 6,
12636d26912SBhawanpreet Lakha 		.max_vscl_ratio = 6,
12736d26912SBhawanpreet Lakha 		.hscl_mults = 4,
12836d26912SBhawanpreet Lakha 		.vscl_mults = 4,
12936d26912SBhawanpreet Lakha 		.max_hscl_taps = 8,
13036d26912SBhawanpreet Lakha 		.max_vscl_taps = 8,
13136d26912SBhawanpreet Lakha 		.dispclk_ramp_margin_percent = 1,
13236d26912SBhawanpreet Lakha 		.underscan_factor = 1.11,
13336d26912SBhawanpreet Lakha 		.min_vblank_lines = 32,
13436d26912SBhawanpreet Lakha 		.dppclk_delay_subtotal = 46,
13536d26912SBhawanpreet Lakha 		.dynamic_metadata_vm_enabled = true,
13636d26912SBhawanpreet Lakha 		.dppclk_delay_scl_lb_only = 16,
13736d26912SBhawanpreet Lakha 		.dppclk_delay_scl = 50,
13836d26912SBhawanpreet Lakha 		.dppclk_delay_cnvc_formatter = 27,
13936d26912SBhawanpreet Lakha 		.dppclk_delay_cnvc_cursor = 6,
14036d26912SBhawanpreet Lakha 		.dispclk_delay_subtotal = 119,
14136d26912SBhawanpreet Lakha 		.dcfclk_cstate_latency = 5.2, // SRExitTime
14236d26912SBhawanpreet Lakha 		.max_inter_dcn_tile_repeaters = 8,
14336d26912SBhawanpreet Lakha 		.max_num_hdmi_frl_outputs = 1,
14436d26912SBhawanpreet Lakha 		.odm_combine_4to1_supported = true,
14536d26912SBhawanpreet Lakha 
14636d26912SBhawanpreet Lakha 		.xfc_supported = false,
14736d26912SBhawanpreet Lakha 		.xfc_fill_bw_overhead_percent = 10.0,
14836d26912SBhawanpreet Lakha 		.xfc_fill_constant_bytes = 0,
14936d26912SBhawanpreet Lakha 		.gfx7_compat_tiling_supported = 0,
15036d26912SBhawanpreet Lakha 		.number_of_cursors = 1,
15136d26912SBhawanpreet Lakha };
15236d26912SBhawanpreet Lakha 
15336d26912SBhawanpreet Lakha struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = {
15436d26912SBhawanpreet Lakha 		.clock_limits = {
15536d26912SBhawanpreet Lakha 				{
15636d26912SBhawanpreet Lakha 						.state = 0,
15736d26912SBhawanpreet Lakha 						.dispclk_mhz = 562.0,
15836d26912SBhawanpreet Lakha 						.dppclk_mhz = 300.0,
15936d26912SBhawanpreet Lakha 						.phyclk_mhz = 300.0,
16036d26912SBhawanpreet Lakha 						.phyclk_d18_mhz = 667.0,
16136d26912SBhawanpreet Lakha 						.dscclk_mhz = 405.6,
16236d26912SBhawanpreet Lakha 				},
16336d26912SBhawanpreet Lakha 		},
16436d26912SBhawanpreet Lakha 
16536d26912SBhawanpreet Lakha 		.min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
16636d26912SBhawanpreet Lakha 		.num_states = 1,
167*163e3bcbSSamson Tam 		.sr_exit_time_us = 12,
168*163e3bcbSSamson Tam 		.sr_enter_plus_exit_time_us = 20,
16936d26912SBhawanpreet Lakha 		.urgent_latency_us = 4.0,
17036d26912SBhawanpreet Lakha 		.urgent_latency_pixel_data_only_us = 4.0,
17136d26912SBhawanpreet Lakha 		.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
17236d26912SBhawanpreet Lakha 		.urgent_latency_vm_data_only_us = 4.0,
17336d26912SBhawanpreet Lakha 		.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
17436d26912SBhawanpreet Lakha 		.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
17536d26912SBhawanpreet Lakha 		.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
17636d26912SBhawanpreet Lakha 		.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
17736d26912SBhawanpreet Lakha 		.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
17836d26912SBhawanpreet Lakha 		.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
17936d26912SBhawanpreet Lakha 		.max_avg_sdp_bw_use_normal_percent = 60.0,
18036d26912SBhawanpreet Lakha 		.max_avg_dram_bw_use_normal_percent = 40.0,
18136d26912SBhawanpreet Lakha 		.writeback_latency_us = 12.0,
18236d26912SBhawanpreet Lakha 		.max_request_size_bytes = 256,
18336d26912SBhawanpreet Lakha 		.fabric_datapath_to_dcn_data_return_bytes = 64,
18436d26912SBhawanpreet Lakha 		.dcn_downspread_percent = 0.5,
18536d26912SBhawanpreet Lakha 		.downspread_percent = 0.38,
18636d26912SBhawanpreet Lakha 		.dram_page_open_time_ns = 50.0,
18736d26912SBhawanpreet Lakha 		.dram_rw_turnaround_time_ns = 17.5,
18836d26912SBhawanpreet Lakha 		.dram_return_buffer_per_channel_bytes = 8192,
18936d26912SBhawanpreet Lakha 		.round_trip_ping_latency_dcfclk_cycles = 156,
19036d26912SBhawanpreet Lakha 		.urgent_out_of_order_return_per_channel_bytes = 4096,
19136d26912SBhawanpreet Lakha 		.channel_interleave_bytes = 256,
19236d26912SBhawanpreet Lakha 		.num_banks = 8,
19336d26912SBhawanpreet Lakha 		.gpuvm_min_page_size_bytes = 4096,
19436d26912SBhawanpreet Lakha 		.hostvm_min_page_size_bytes = 4096,
195*163e3bcbSSamson Tam 		.dram_clock_change_latency_us = 404,
19636d26912SBhawanpreet Lakha 		.dummy_pstate_latency_us = 5,
19736d26912SBhawanpreet Lakha 		.writeback_dram_clock_change_latency_us = 23.0,
19836d26912SBhawanpreet Lakha 		.return_bus_width_bytes = 64,
19936d26912SBhawanpreet Lakha 		.dispclk_dppclk_vco_speed_mhz = 3650,
20036d26912SBhawanpreet Lakha 		.xfc_bus_transport_time_us = 20,      // ?
20136d26912SBhawanpreet Lakha 		.xfc_xbuf_latency_tolerance_us = 4,  // ?
20236d26912SBhawanpreet Lakha 		.use_urgent_burst_bw = 1,            // ?
20336d26912SBhawanpreet Lakha 		.do_urgent_latency_adjustment = true,
20436d26912SBhawanpreet Lakha 		.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
20536d26912SBhawanpreet Lakha 		.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
20636d26912SBhawanpreet Lakha };
20736d26912SBhawanpreet Lakha 
20836d26912SBhawanpreet Lakha static const struct dc_debug_options debug_defaults_drv = {
20936d26912SBhawanpreet Lakha 		.disable_dmcu = true,
21036d26912SBhawanpreet Lakha 		.force_abm_enable = false,
21136d26912SBhawanpreet Lakha 		.timing_trace = false,
21236d26912SBhawanpreet Lakha 		.clock_trace = true,
21336d26912SBhawanpreet Lakha 		.disable_pplib_clock_request = true,
21436d26912SBhawanpreet Lakha 		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
21536d26912SBhawanpreet Lakha 		.force_single_disp_pipe_split = false,
21636d26912SBhawanpreet Lakha 		.disable_dcc = DCC_ENABLE,
21736d26912SBhawanpreet Lakha 		.vsr_support = true,
21836d26912SBhawanpreet Lakha 		.performance_trace = false,
21936d26912SBhawanpreet Lakha 		.max_downscale_src_width = 7680,/*upto 8K*/
22036d26912SBhawanpreet Lakha 		.disable_pplib_wm_range = false,
22136d26912SBhawanpreet Lakha 		.scl_reset_length10 = true,
22236d26912SBhawanpreet Lakha 		.sanity_checks = false,
22336d26912SBhawanpreet Lakha 		.underflow_assert_delay_us = 0xFFFFFFFF,
22436d26912SBhawanpreet Lakha 		.dwb_fi_phase = -1, // -1 = disable,
22536d26912SBhawanpreet Lakha 		.dmub_command_table = true,
22636d26912SBhawanpreet Lakha };
22736d26912SBhawanpreet Lakha 
22836d26912SBhawanpreet Lakha static const struct dc_debug_options debug_defaults_diags = {
22936d26912SBhawanpreet Lakha 		.disable_dmcu = true,
23036d26912SBhawanpreet Lakha 		.force_abm_enable = false,
23136d26912SBhawanpreet Lakha 		.timing_trace = true,
23236d26912SBhawanpreet Lakha 		.clock_trace = true,
23336d26912SBhawanpreet Lakha 		.disable_dpp_power_gate = true,
23436d26912SBhawanpreet Lakha 		.disable_hubp_power_gate = true,
23536d26912SBhawanpreet Lakha 		.disable_clock_gate = true,
23636d26912SBhawanpreet Lakha 		.disable_pplib_clock_request = true,
23736d26912SBhawanpreet Lakha 		.disable_pplib_wm_range = true,
23836d26912SBhawanpreet Lakha 		.disable_stutter = false,
23936d26912SBhawanpreet Lakha 		.scl_reset_length10 = true,
24036d26912SBhawanpreet Lakha 		.dwb_fi_phase = -1, // -1 = disable
24136d26912SBhawanpreet Lakha 		.dmub_command_table = true,
24236d26912SBhawanpreet Lakha 		.enable_tri_buf = true,
24365e05ca7SJoshua Aberback 		.disable_psr = true,
24436d26912SBhawanpreet Lakha };
24536d26912SBhawanpreet Lakha 
24636d26912SBhawanpreet Lakha enum dcn302_clk_src_array_id {
24736d26912SBhawanpreet Lakha 	DCN302_CLK_SRC_PLL0,
24836d26912SBhawanpreet Lakha 	DCN302_CLK_SRC_PLL1,
24936d26912SBhawanpreet Lakha 	DCN302_CLK_SRC_PLL2,
25036d26912SBhawanpreet Lakha 	DCN302_CLK_SRC_PLL3,
25136d26912SBhawanpreet Lakha 	DCN302_CLK_SRC_PLL4,
25236d26912SBhawanpreet Lakha 	DCN302_CLK_SRC_TOTAL
25336d26912SBhawanpreet Lakha };
25436d26912SBhawanpreet Lakha 
25536d26912SBhawanpreet Lakha static const struct resource_caps res_cap_dcn302 = {
25636d26912SBhawanpreet Lakha 		.num_timing_generator = 5,
25736d26912SBhawanpreet Lakha 		.num_opp = 5,
25836d26912SBhawanpreet Lakha 		.num_video_plane = 5,
25936d26912SBhawanpreet Lakha 		.num_audio = 5,
26036d26912SBhawanpreet Lakha 		.num_stream_encoder = 5,
26136d26912SBhawanpreet Lakha 		.num_dwb = 1,
26236d26912SBhawanpreet Lakha 		.num_ddc = 5,
26336d26912SBhawanpreet Lakha 		.num_vmid = 16,
26436d26912SBhawanpreet Lakha 		.num_mpc_3dlut = 2,
26536d26912SBhawanpreet Lakha 		.num_dsc = 5,
26636d26912SBhawanpreet Lakha };
26736d26912SBhawanpreet Lakha 
26836d26912SBhawanpreet Lakha static const struct dc_plane_cap plane_cap = {
26936d26912SBhawanpreet Lakha 		.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
27036d26912SBhawanpreet Lakha 		.blends_with_above = true,
27136d26912SBhawanpreet Lakha 		.blends_with_below = true,
27236d26912SBhawanpreet Lakha 		.per_pixel_alpha = true,
27336d26912SBhawanpreet Lakha 		.pixel_format_support = {
27436d26912SBhawanpreet Lakha 				.argb8888 = true,
27536d26912SBhawanpreet Lakha 				.nv12 = true,
27636d26912SBhawanpreet Lakha 				.fp16 = true,
27736d26912SBhawanpreet Lakha 				.p010 = false,
27836d26912SBhawanpreet Lakha 				.ayuv = false,
27936d26912SBhawanpreet Lakha 		},
28036d26912SBhawanpreet Lakha 		.max_upscale_factor = {
28136d26912SBhawanpreet Lakha 				.argb8888 = 16000,
28236d26912SBhawanpreet Lakha 				.nv12 = 16000,
28336d26912SBhawanpreet Lakha 				.fp16 = 16000
28436d26912SBhawanpreet Lakha 		},
28536d26912SBhawanpreet Lakha 		.max_downscale_factor = {
28636d26912SBhawanpreet Lakha 				.argb8888 = 600,
28736d26912SBhawanpreet Lakha 				.nv12 = 600,
28836d26912SBhawanpreet Lakha 				.fp16 = 600
28936d26912SBhawanpreet Lakha 		},
29036d26912SBhawanpreet Lakha 		16,
29136d26912SBhawanpreet Lakha 		16
29236d26912SBhawanpreet Lakha };
29336d26912SBhawanpreet Lakha 
29436d26912SBhawanpreet Lakha /* NBIO */
29536d26912SBhawanpreet Lakha #define NBIO_BASE_INNER(seg) \
29636d26912SBhawanpreet Lakha 		NBIO_BASE__INST0_SEG ## seg
29736d26912SBhawanpreet Lakha 
29836d26912SBhawanpreet Lakha #define NBIO_BASE(seg) \
29936d26912SBhawanpreet Lakha 		NBIO_BASE_INNER(seg)
30036d26912SBhawanpreet Lakha 
30136d26912SBhawanpreet Lakha #define NBIO_SR(reg_name)\
30236d26912SBhawanpreet Lakha 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
30336d26912SBhawanpreet Lakha 		mm ## reg_name
30436d26912SBhawanpreet Lakha 
30536d26912SBhawanpreet Lakha /* DCN */
30636d26912SBhawanpreet Lakha #undef BASE_INNER
30736d26912SBhawanpreet Lakha #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
30836d26912SBhawanpreet Lakha 
30936d26912SBhawanpreet Lakha #define BASE(seg) BASE_INNER(seg)
31036d26912SBhawanpreet Lakha 
31136d26912SBhawanpreet Lakha #define SR(reg_name)\
31236d26912SBhawanpreet Lakha 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
31336d26912SBhawanpreet Lakha 
31436d26912SBhawanpreet Lakha #define SF(reg_name, field_name, post_fix)\
31536d26912SBhawanpreet Lakha 		.field_name = reg_name ## __ ## field_name ## post_fix
31636d26912SBhawanpreet Lakha 
31736d26912SBhawanpreet Lakha #define SRI(reg_name, block, id)\
31836d26912SBhawanpreet Lakha 		.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
31936d26912SBhawanpreet Lakha 
32036d26912SBhawanpreet Lakha #define SRI2(reg_name, block, id)\
32136d26912SBhawanpreet Lakha 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
32236d26912SBhawanpreet Lakha 
32336d26912SBhawanpreet Lakha #define SRII(reg_name, block, id)\
32436d26912SBhawanpreet Lakha 		.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
32536d26912SBhawanpreet Lakha 		mm ## block ## id ## _ ## reg_name
32636d26912SBhawanpreet Lakha 
32736d26912SBhawanpreet Lakha #define DCCG_SRII(reg_name, block, id)\
32836d26912SBhawanpreet Lakha 		.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
32936d26912SBhawanpreet Lakha 		mm ## block ## id ## _ ## reg_name
33036d26912SBhawanpreet Lakha 
33136d26912SBhawanpreet Lakha #define VUPDATE_SRII(reg_name, block, id)\
33236d26912SBhawanpreet Lakha 		.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
33336d26912SBhawanpreet Lakha 		mm ## reg_name ## _ ## block ## id
33436d26912SBhawanpreet Lakha 
33536d26912SBhawanpreet Lakha #define SRII_DWB(reg_name, temp_name, block, id)\
33636d26912SBhawanpreet Lakha 		.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
33736d26912SBhawanpreet Lakha 		mm ## block ## id ## _ ## temp_name
33836d26912SBhawanpreet Lakha 
33936d26912SBhawanpreet Lakha #define SRII_MPC_RMU(reg_name, block, id)\
34036d26912SBhawanpreet Lakha 		.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
34136d26912SBhawanpreet Lakha 		mm ## block ## id ## _ ## reg_name
34236d26912SBhawanpreet Lakha 
34336d26912SBhawanpreet Lakha static const struct dcn_hubbub_registers hubbub_reg = {
34436d26912SBhawanpreet Lakha 		HUBBUB_REG_LIST_DCN30(0)
34536d26912SBhawanpreet Lakha };
34636d26912SBhawanpreet Lakha 
34736d26912SBhawanpreet Lakha static const struct dcn_hubbub_shift hubbub_shift = {
34836d26912SBhawanpreet Lakha 		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
34936d26912SBhawanpreet Lakha };
35036d26912SBhawanpreet Lakha 
35136d26912SBhawanpreet Lakha static const struct dcn_hubbub_mask hubbub_mask = {
35236d26912SBhawanpreet Lakha 		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
35336d26912SBhawanpreet Lakha };
35436d26912SBhawanpreet Lakha 
35536d26912SBhawanpreet Lakha #define vmid_regs(id)\
35636d26912SBhawanpreet Lakha 		[id] = { DCN20_VMID_REG_LIST(id) }
35736d26912SBhawanpreet Lakha 
35836d26912SBhawanpreet Lakha static const struct dcn_vmid_registers vmid_regs[] = {
35936d26912SBhawanpreet Lakha 		vmid_regs(0),
36036d26912SBhawanpreet Lakha 		vmid_regs(1),
36136d26912SBhawanpreet Lakha 		vmid_regs(2),
36236d26912SBhawanpreet Lakha 		vmid_regs(3),
36336d26912SBhawanpreet Lakha 		vmid_regs(4),
36436d26912SBhawanpreet Lakha 		vmid_regs(5),
36536d26912SBhawanpreet Lakha 		vmid_regs(6),
36636d26912SBhawanpreet Lakha 		vmid_regs(7),
36736d26912SBhawanpreet Lakha 		vmid_regs(8),
36836d26912SBhawanpreet Lakha 		vmid_regs(9),
36936d26912SBhawanpreet Lakha 		vmid_regs(10),
37036d26912SBhawanpreet Lakha 		vmid_regs(11),
37136d26912SBhawanpreet Lakha 		vmid_regs(12),
37236d26912SBhawanpreet Lakha 		vmid_regs(13),
37336d26912SBhawanpreet Lakha 		vmid_regs(14),
37436d26912SBhawanpreet Lakha 		vmid_regs(15)
37536d26912SBhawanpreet Lakha };
37636d26912SBhawanpreet Lakha 
37736d26912SBhawanpreet Lakha static const struct dcn20_vmid_shift vmid_shifts = {
37836d26912SBhawanpreet Lakha 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
37936d26912SBhawanpreet Lakha };
38036d26912SBhawanpreet Lakha 
38136d26912SBhawanpreet Lakha static const struct dcn20_vmid_mask vmid_masks = {
38236d26912SBhawanpreet Lakha 		DCN20_VMID_MASK_SH_LIST(_MASK)
38336d26912SBhawanpreet Lakha };
38436d26912SBhawanpreet Lakha 
38536d26912SBhawanpreet Lakha static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
38636d26912SBhawanpreet Lakha {
38736d26912SBhawanpreet Lakha 	int i;
38836d26912SBhawanpreet Lakha 
38936d26912SBhawanpreet Lakha 	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
39036d26912SBhawanpreet Lakha 
39136d26912SBhawanpreet Lakha 	if (!hubbub3)
39236d26912SBhawanpreet Lakha 		return NULL;
39336d26912SBhawanpreet Lakha 
39436d26912SBhawanpreet Lakha 	hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
39536d26912SBhawanpreet Lakha 
39636d26912SBhawanpreet Lakha 	for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
39736d26912SBhawanpreet Lakha 		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
39836d26912SBhawanpreet Lakha 
39936d26912SBhawanpreet Lakha 		vmid->ctx = ctx;
40036d26912SBhawanpreet Lakha 
40136d26912SBhawanpreet Lakha 		vmid->regs = &vmid_regs[i];
40236d26912SBhawanpreet Lakha 		vmid->shifts = &vmid_shifts;
40336d26912SBhawanpreet Lakha 		vmid->masks = &vmid_masks;
40436d26912SBhawanpreet Lakha 	}
40536d26912SBhawanpreet Lakha 
40636d26912SBhawanpreet Lakha 	return &hubbub3->base;
40736d26912SBhawanpreet Lakha }
40836d26912SBhawanpreet Lakha 
40936d26912SBhawanpreet Lakha #define vpg_regs(id)\
41036d26912SBhawanpreet Lakha 		[id] = { VPG_DCN3_REG_LIST(id) }
41136d26912SBhawanpreet Lakha 
41236d26912SBhawanpreet Lakha static const struct dcn30_vpg_registers vpg_regs[] = {
41336d26912SBhawanpreet Lakha 		vpg_regs(0),
41436d26912SBhawanpreet Lakha 		vpg_regs(1),
41536d26912SBhawanpreet Lakha 		vpg_regs(2),
41636d26912SBhawanpreet Lakha 		vpg_regs(3),
41736d26912SBhawanpreet Lakha 		vpg_regs(4),
41836d26912SBhawanpreet Lakha 		vpg_regs(5)
41936d26912SBhawanpreet Lakha };
42036d26912SBhawanpreet Lakha 
42136d26912SBhawanpreet Lakha static const struct dcn30_vpg_shift vpg_shift = {
42236d26912SBhawanpreet Lakha 		DCN3_VPG_MASK_SH_LIST(__SHIFT)
42336d26912SBhawanpreet Lakha };
42436d26912SBhawanpreet Lakha 
42536d26912SBhawanpreet Lakha static const struct dcn30_vpg_mask vpg_mask = {
42636d26912SBhawanpreet Lakha 		DCN3_VPG_MASK_SH_LIST(_MASK)
42736d26912SBhawanpreet Lakha };
42836d26912SBhawanpreet Lakha 
42936d26912SBhawanpreet Lakha static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
43036d26912SBhawanpreet Lakha {
43136d26912SBhawanpreet Lakha 	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
43236d26912SBhawanpreet Lakha 
43336d26912SBhawanpreet Lakha 	if (!vpg3)
43436d26912SBhawanpreet Lakha 		return NULL;
43536d26912SBhawanpreet Lakha 
43636d26912SBhawanpreet Lakha 	vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
43736d26912SBhawanpreet Lakha 
43836d26912SBhawanpreet Lakha 	return &vpg3->base;
43936d26912SBhawanpreet Lakha }
44036d26912SBhawanpreet Lakha 
44136d26912SBhawanpreet Lakha #define afmt_regs(id)\
44236d26912SBhawanpreet Lakha 		[id] = { AFMT_DCN3_REG_LIST(id) }
44336d26912SBhawanpreet Lakha 
44436d26912SBhawanpreet Lakha static const struct dcn30_afmt_registers afmt_regs[] = {
44536d26912SBhawanpreet Lakha 		afmt_regs(0),
44636d26912SBhawanpreet Lakha 		afmt_regs(1),
44736d26912SBhawanpreet Lakha 		afmt_regs(2),
44836d26912SBhawanpreet Lakha 		afmt_regs(3),
44936d26912SBhawanpreet Lakha 		afmt_regs(4),
45036d26912SBhawanpreet Lakha 		afmt_regs(5)
45136d26912SBhawanpreet Lakha };
45236d26912SBhawanpreet Lakha 
45336d26912SBhawanpreet Lakha static const struct dcn30_afmt_shift afmt_shift = {
45436d26912SBhawanpreet Lakha 		DCN3_AFMT_MASK_SH_LIST(__SHIFT)
45536d26912SBhawanpreet Lakha };
45636d26912SBhawanpreet Lakha 
45736d26912SBhawanpreet Lakha static const struct dcn30_afmt_mask afmt_mask = {
45836d26912SBhawanpreet Lakha 		DCN3_AFMT_MASK_SH_LIST(_MASK)
45936d26912SBhawanpreet Lakha };
46036d26912SBhawanpreet Lakha 
46136d26912SBhawanpreet Lakha static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
46236d26912SBhawanpreet Lakha {
46336d26912SBhawanpreet Lakha 	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
46436d26912SBhawanpreet Lakha 
46536d26912SBhawanpreet Lakha 	if (!afmt3)
46636d26912SBhawanpreet Lakha 		return NULL;
46736d26912SBhawanpreet Lakha 
46836d26912SBhawanpreet Lakha 	afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
46936d26912SBhawanpreet Lakha 
47036d26912SBhawanpreet Lakha 	return &afmt3->base;
47136d26912SBhawanpreet Lakha }
47236d26912SBhawanpreet Lakha 
47336d26912SBhawanpreet Lakha #define audio_regs(id)\
47436d26912SBhawanpreet Lakha 		[id] = { AUD_COMMON_REG_LIST(id) }
47536d26912SBhawanpreet Lakha 
47636d26912SBhawanpreet Lakha static const struct dce_audio_registers audio_regs[] = {
47736d26912SBhawanpreet Lakha 		audio_regs(0),
47836d26912SBhawanpreet Lakha 		audio_regs(1),
47936d26912SBhawanpreet Lakha 		audio_regs(2),
48036d26912SBhawanpreet Lakha 		audio_regs(3),
48136d26912SBhawanpreet Lakha 		audio_regs(4),
48236d26912SBhawanpreet Lakha 		audio_regs(5),
48336d26912SBhawanpreet Lakha 		audio_regs(6)
48436d26912SBhawanpreet Lakha };
48536d26912SBhawanpreet Lakha 
48636d26912SBhawanpreet Lakha #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
48736d26912SBhawanpreet Lakha 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
48836d26912SBhawanpreet Lakha 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
48936d26912SBhawanpreet Lakha 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
49036d26912SBhawanpreet Lakha 
49136d26912SBhawanpreet Lakha static const struct dce_audio_shift audio_shift = {
49236d26912SBhawanpreet Lakha 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
49336d26912SBhawanpreet Lakha };
49436d26912SBhawanpreet Lakha 
49536d26912SBhawanpreet Lakha static const struct dce_audio_mask audio_mask = {
49636d26912SBhawanpreet Lakha 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
49736d26912SBhawanpreet Lakha };
49836d26912SBhawanpreet Lakha 
49936d26912SBhawanpreet Lakha static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
50036d26912SBhawanpreet Lakha {
50136d26912SBhawanpreet Lakha 	return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
50236d26912SBhawanpreet Lakha }
50336d26912SBhawanpreet Lakha 
50436d26912SBhawanpreet Lakha #define stream_enc_regs(id)\
50536d26912SBhawanpreet Lakha 		[id] = { SE_DCN3_REG_LIST(id) }
50636d26912SBhawanpreet Lakha 
50736d26912SBhawanpreet Lakha static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
50836d26912SBhawanpreet Lakha 		stream_enc_regs(0),
50936d26912SBhawanpreet Lakha 		stream_enc_regs(1),
51036d26912SBhawanpreet Lakha 		stream_enc_regs(2),
51136d26912SBhawanpreet Lakha 		stream_enc_regs(3),
51236d26912SBhawanpreet Lakha 		stream_enc_regs(4)
51336d26912SBhawanpreet Lakha };
51436d26912SBhawanpreet Lakha 
51536d26912SBhawanpreet Lakha static const struct dcn10_stream_encoder_shift se_shift = {
51636d26912SBhawanpreet Lakha 		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
51736d26912SBhawanpreet Lakha };
51836d26912SBhawanpreet Lakha 
51936d26912SBhawanpreet Lakha static const struct dcn10_stream_encoder_mask se_mask = {
52036d26912SBhawanpreet Lakha 		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
52136d26912SBhawanpreet Lakha };
52236d26912SBhawanpreet Lakha 
52336d26912SBhawanpreet Lakha static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
52436d26912SBhawanpreet Lakha {
52536d26912SBhawanpreet Lakha 	struct dcn10_stream_encoder *enc1;
52636d26912SBhawanpreet Lakha 	struct vpg *vpg;
52736d26912SBhawanpreet Lakha 	struct afmt *afmt;
52836d26912SBhawanpreet Lakha 	int vpg_inst;
52936d26912SBhawanpreet Lakha 	int afmt_inst;
53036d26912SBhawanpreet Lakha 
53136d26912SBhawanpreet Lakha 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
53236d26912SBhawanpreet Lakha 	if (eng_id <= ENGINE_ID_DIGE) {
53336d26912SBhawanpreet Lakha 		vpg_inst = eng_id;
53436d26912SBhawanpreet Lakha 		afmt_inst = eng_id;
53536d26912SBhawanpreet Lakha 	} else
53636d26912SBhawanpreet Lakha 		return NULL;
53736d26912SBhawanpreet Lakha 
53836d26912SBhawanpreet Lakha 	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
53936d26912SBhawanpreet Lakha 	vpg = dcn302_vpg_create(ctx, vpg_inst);
54036d26912SBhawanpreet Lakha 	afmt = dcn302_afmt_create(ctx, afmt_inst);
54136d26912SBhawanpreet Lakha 
54236d26912SBhawanpreet Lakha 	if (!enc1 || !vpg || !afmt)
54336d26912SBhawanpreet Lakha 		return NULL;
54436d26912SBhawanpreet Lakha 
54536d26912SBhawanpreet Lakha 	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
54636d26912SBhawanpreet Lakha 			&se_shift, &se_mask);
54736d26912SBhawanpreet Lakha 
54836d26912SBhawanpreet Lakha 	return &enc1->base;
54936d26912SBhawanpreet Lakha }
55036d26912SBhawanpreet Lakha 
55136d26912SBhawanpreet Lakha #define clk_src_regs(index, pllid)\
55236d26912SBhawanpreet Lakha 		[index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
55336d26912SBhawanpreet Lakha 
55436d26912SBhawanpreet Lakha static const struct dce110_clk_src_regs clk_src_regs[] = {
55536d26912SBhawanpreet Lakha 		clk_src_regs(0, A),
55636d26912SBhawanpreet Lakha 		clk_src_regs(1, B),
55736d26912SBhawanpreet Lakha 		clk_src_regs(2, C),
55836d26912SBhawanpreet Lakha 		clk_src_regs(3, D),
55936d26912SBhawanpreet Lakha 		clk_src_regs(4, E)
56036d26912SBhawanpreet Lakha };
56136d26912SBhawanpreet Lakha 
56236d26912SBhawanpreet Lakha static const struct dce110_clk_src_shift cs_shift = {
56336d26912SBhawanpreet Lakha 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
56436d26912SBhawanpreet Lakha };
56536d26912SBhawanpreet Lakha 
56636d26912SBhawanpreet Lakha static const struct dce110_clk_src_mask cs_mask = {
56736d26912SBhawanpreet Lakha 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
56836d26912SBhawanpreet Lakha };
56936d26912SBhawanpreet Lakha 
57036d26912SBhawanpreet Lakha static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
57136d26912SBhawanpreet Lakha 		enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
57236d26912SBhawanpreet Lakha {
57336d26912SBhawanpreet Lakha 	struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
57436d26912SBhawanpreet Lakha 
57536d26912SBhawanpreet Lakha 	if (!clk_src)
57636d26912SBhawanpreet Lakha 		return NULL;
57736d26912SBhawanpreet Lakha 
57836d26912SBhawanpreet Lakha 	if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
57936d26912SBhawanpreet Lakha 		clk_src->base.dp_clk_src = dp_clk_src;
58036d26912SBhawanpreet Lakha 		return &clk_src->base;
58136d26912SBhawanpreet Lakha 	}
58236d26912SBhawanpreet Lakha 
58336d26912SBhawanpreet Lakha 	BREAK_TO_DEBUGGER();
58436d26912SBhawanpreet Lakha 	return NULL;
58536d26912SBhawanpreet Lakha }
58636d26912SBhawanpreet Lakha 
58736d26912SBhawanpreet Lakha static const struct dce_hwseq_registers hwseq_reg = {
58836d26912SBhawanpreet Lakha 		HWSEQ_DCN302_REG_LIST()
58936d26912SBhawanpreet Lakha };
59036d26912SBhawanpreet Lakha 
59136d26912SBhawanpreet Lakha static const struct dce_hwseq_shift hwseq_shift = {
59236d26912SBhawanpreet Lakha 		HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
59336d26912SBhawanpreet Lakha };
59436d26912SBhawanpreet Lakha 
59536d26912SBhawanpreet Lakha static const struct dce_hwseq_mask hwseq_mask = {
59636d26912SBhawanpreet Lakha 		HWSEQ_DCN302_MASK_SH_LIST(_MASK)
59736d26912SBhawanpreet Lakha };
59836d26912SBhawanpreet Lakha 
59936d26912SBhawanpreet Lakha static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
60036d26912SBhawanpreet Lakha {
60136d26912SBhawanpreet Lakha 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
60236d26912SBhawanpreet Lakha 
60336d26912SBhawanpreet Lakha 	if (hws) {
60436d26912SBhawanpreet Lakha 		hws->ctx = ctx;
60536d26912SBhawanpreet Lakha 		hws->regs = &hwseq_reg;
60636d26912SBhawanpreet Lakha 		hws->shifts = &hwseq_shift;
60736d26912SBhawanpreet Lakha 		hws->masks = &hwseq_mask;
60836d26912SBhawanpreet Lakha 	}
60936d26912SBhawanpreet Lakha 	return hws;
61036d26912SBhawanpreet Lakha }
61136d26912SBhawanpreet Lakha 
61236d26912SBhawanpreet Lakha #define hubp_regs(id)\
61336d26912SBhawanpreet Lakha 		[id] = { HUBP_REG_LIST_DCN30(id) }
61436d26912SBhawanpreet Lakha 
61536d26912SBhawanpreet Lakha static const struct dcn_hubp2_registers hubp_regs[] = {
61636d26912SBhawanpreet Lakha 		hubp_regs(0),
61736d26912SBhawanpreet Lakha 		hubp_regs(1),
61836d26912SBhawanpreet Lakha 		hubp_regs(2),
61936d26912SBhawanpreet Lakha 		hubp_regs(3),
62036d26912SBhawanpreet Lakha 		hubp_regs(4)
62136d26912SBhawanpreet Lakha };
62236d26912SBhawanpreet Lakha 
62336d26912SBhawanpreet Lakha static const struct dcn_hubp2_shift hubp_shift = {
62436d26912SBhawanpreet Lakha 		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
62536d26912SBhawanpreet Lakha };
62636d26912SBhawanpreet Lakha 
62736d26912SBhawanpreet Lakha static const struct dcn_hubp2_mask hubp_mask = {
62836d26912SBhawanpreet Lakha 		HUBP_MASK_SH_LIST_DCN30(_MASK)
62936d26912SBhawanpreet Lakha };
63036d26912SBhawanpreet Lakha 
63136d26912SBhawanpreet Lakha static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
63236d26912SBhawanpreet Lakha {
63336d26912SBhawanpreet Lakha 	struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
63436d26912SBhawanpreet Lakha 
63536d26912SBhawanpreet Lakha 	if (!hubp2)
63636d26912SBhawanpreet Lakha 		return NULL;
63736d26912SBhawanpreet Lakha 
63836d26912SBhawanpreet Lakha 	if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
63936d26912SBhawanpreet Lakha 		return &hubp2->base;
64036d26912SBhawanpreet Lakha 
64136d26912SBhawanpreet Lakha 	BREAK_TO_DEBUGGER();
64236d26912SBhawanpreet Lakha 	kfree(hubp2);
64336d26912SBhawanpreet Lakha 	return NULL;
64436d26912SBhawanpreet Lakha }
64536d26912SBhawanpreet Lakha 
64636d26912SBhawanpreet Lakha #define dpp_regs(id)\
64736d26912SBhawanpreet Lakha 		[id] = { DPP_REG_LIST_DCN30(id) }
64836d26912SBhawanpreet Lakha 
64936d26912SBhawanpreet Lakha static const struct dcn3_dpp_registers dpp_regs[] = {
65036d26912SBhawanpreet Lakha 		dpp_regs(0),
65136d26912SBhawanpreet Lakha 		dpp_regs(1),
65236d26912SBhawanpreet Lakha 		dpp_regs(2),
65336d26912SBhawanpreet Lakha 		dpp_regs(3),
65436d26912SBhawanpreet Lakha 		dpp_regs(4)
65536d26912SBhawanpreet Lakha };
65636d26912SBhawanpreet Lakha 
65736d26912SBhawanpreet Lakha static const struct dcn3_dpp_shift tf_shift = {
65836d26912SBhawanpreet Lakha 		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
65936d26912SBhawanpreet Lakha };
66036d26912SBhawanpreet Lakha 
66136d26912SBhawanpreet Lakha static const struct dcn3_dpp_mask tf_mask = {
66236d26912SBhawanpreet Lakha 		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
66336d26912SBhawanpreet Lakha };
66436d26912SBhawanpreet Lakha 
66536d26912SBhawanpreet Lakha static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
66636d26912SBhawanpreet Lakha {
66736d26912SBhawanpreet Lakha 	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
66836d26912SBhawanpreet Lakha 
66936d26912SBhawanpreet Lakha 	if (!dpp)
67036d26912SBhawanpreet Lakha 		return NULL;
67136d26912SBhawanpreet Lakha 
67236d26912SBhawanpreet Lakha 	if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
67336d26912SBhawanpreet Lakha 		return &dpp->base;
67436d26912SBhawanpreet Lakha 
67536d26912SBhawanpreet Lakha 	BREAK_TO_DEBUGGER();
67636d26912SBhawanpreet Lakha 	kfree(dpp);
67736d26912SBhawanpreet Lakha 	return NULL;
67836d26912SBhawanpreet Lakha }
67936d26912SBhawanpreet Lakha 
68036d26912SBhawanpreet Lakha #define opp_regs(id)\
68136d26912SBhawanpreet Lakha 		[id] = { OPP_REG_LIST_DCN30(id) }
68236d26912SBhawanpreet Lakha 
68336d26912SBhawanpreet Lakha static const struct dcn20_opp_registers opp_regs[] = {
68436d26912SBhawanpreet Lakha 		opp_regs(0),
68536d26912SBhawanpreet Lakha 		opp_regs(1),
68636d26912SBhawanpreet Lakha 		opp_regs(2),
68736d26912SBhawanpreet Lakha 		opp_regs(3),
68836d26912SBhawanpreet Lakha 		opp_regs(4)
68936d26912SBhawanpreet Lakha };
69036d26912SBhawanpreet Lakha 
69136d26912SBhawanpreet Lakha static const struct dcn20_opp_shift opp_shift = {
69236d26912SBhawanpreet Lakha 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
69336d26912SBhawanpreet Lakha };
69436d26912SBhawanpreet Lakha 
69536d26912SBhawanpreet Lakha static const struct dcn20_opp_mask opp_mask = {
69636d26912SBhawanpreet Lakha 		OPP_MASK_SH_LIST_DCN20(_MASK)
69736d26912SBhawanpreet Lakha };
69836d26912SBhawanpreet Lakha 
69936d26912SBhawanpreet Lakha static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
70036d26912SBhawanpreet Lakha {
70136d26912SBhawanpreet Lakha 	struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
70236d26912SBhawanpreet Lakha 
70336d26912SBhawanpreet Lakha 	if (!opp) {
70436d26912SBhawanpreet Lakha 		BREAK_TO_DEBUGGER();
70536d26912SBhawanpreet Lakha 		return NULL;
70636d26912SBhawanpreet Lakha 	}
70736d26912SBhawanpreet Lakha 
70836d26912SBhawanpreet Lakha 	dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
70936d26912SBhawanpreet Lakha 	return &opp->base;
71036d26912SBhawanpreet Lakha }
71136d26912SBhawanpreet Lakha 
71236d26912SBhawanpreet Lakha #define optc_regs(id)\
71336d26912SBhawanpreet Lakha 		[id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
71436d26912SBhawanpreet Lakha 
71536d26912SBhawanpreet Lakha static const struct dcn_optc_registers optc_regs[] = {
71636d26912SBhawanpreet Lakha 		optc_regs(0),
71736d26912SBhawanpreet Lakha 		optc_regs(1),
71836d26912SBhawanpreet Lakha 		optc_regs(2),
71936d26912SBhawanpreet Lakha 		optc_regs(3),
72036d26912SBhawanpreet Lakha 		optc_regs(4)
72136d26912SBhawanpreet Lakha };
72236d26912SBhawanpreet Lakha 
72336d26912SBhawanpreet Lakha static const struct dcn_optc_shift optc_shift = {
72436d26912SBhawanpreet Lakha 		OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
72536d26912SBhawanpreet Lakha };
72636d26912SBhawanpreet Lakha 
72736d26912SBhawanpreet Lakha static const struct dcn_optc_mask optc_mask = {
72836d26912SBhawanpreet Lakha 		OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
72936d26912SBhawanpreet Lakha };
73036d26912SBhawanpreet Lakha 
73136d26912SBhawanpreet Lakha static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
73236d26912SBhawanpreet Lakha {
73336d26912SBhawanpreet Lakha 	struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
73436d26912SBhawanpreet Lakha 
73536d26912SBhawanpreet Lakha 	if (!tgn10)
73636d26912SBhawanpreet Lakha 		return NULL;
73736d26912SBhawanpreet Lakha 
73836d26912SBhawanpreet Lakha 	tgn10->base.inst = instance;
73936d26912SBhawanpreet Lakha 	tgn10->base.ctx = ctx;
74036d26912SBhawanpreet Lakha 
74136d26912SBhawanpreet Lakha 	tgn10->tg_regs = &optc_regs[instance];
74236d26912SBhawanpreet Lakha 	tgn10->tg_shift = &optc_shift;
74336d26912SBhawanpreet Lakha 	tgn10->tg_mask = &optc_mask;
74436d26912SBhawanpreet Lakha 
74536d26912SBhawanpreet Lakha 	dcn30_timing_generator_init(tgn10);
74636d26912SBhawanpreet Lakha 
74736d26912SBhawanpreet Lakha 	return &tgn10->base;
74836d26912SBhawanpreet Lakha }
74936d26912SBhawanpreet Lakha 
75036d26912SBhawanpreet Lakha static const struct dcn30_mpc_registers mpc_regs = {
75136d26912SBhawanpreet Lakha 		MPC_REG_LIST_DCN3_0(0),
75236d26912SBhawanpreet Lakha 		MPC_REG_LIST_DCN3_0(1),
75336d26912SBhawanpreet Lakha 		MPC_REG_LIST_DCN3_0(2),
75436d26912SBhawanpreet Lakha 		MPC_REG_LIST_DCN3_0(3),
75536d26912SBhawanpreet Lakha 		MPC_REG_LIST_DCN3_0(4),
75636d26912SBhawanpreet Lakha 		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
75736d26912SBhawanpreet Lakha 		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
75836d26912SBhawanpreet Lakha 		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
75936d26912SBhawanpreet Lakha 		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
76036d26912SBhawanpreet Lakha 		MPC_OUT_MUX_REG_LIST_DCN3_0(4),
76136d26912SBhawanpreet Lakha 		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
76236d26912SBhawanpreet Lakha 		MPC_RMU_REG_LIST_DCN3AG(0),
76336d26912SBhawanpreet Lakha 		MPC_RMU_REG_LIST_DCN3AG(1),
76436d26912SBhawanpreet Lakha 		MPC_RMU_REG_LIST_DCN3AG(2),
76536d26912SBhawanpreet Lakha 		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
76636d26912SBhawanpreet Lakha };
76736d26912SBhawanpreet Lakha 
76836d26912SBhawanpreet Lakha static const struct dcn30_mpc_shift mpc_shift = {
76936d26912SBhawanpreet Lakha 		MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
77036d26912SBhawanpreet Lakha };
77136d26912SBhawanpreet Lakha 
77236d26912SBhawanpreet Lakha static const struct dcn30_mpc_mask mpc_mask = {
77336d26912SBhawanpreet Lakha 		MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
77436d26912SBhawanpreet Lakha };
77536d26912SBhawanpreet Lakha 
77636d26912SBhawanpreet Lakha static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
77736d26912SBhawanpreet Lakha {
77836d26912SBhawanpreet Lakha 	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
77936d26912SBhawanpreet Lakha 
78036d26912SBhawanpreet Lakha 	if (!mpc30)
78136d26912SBhawanpreet Lakha 		return NULL;
78236d26912SBhawanpreet Lakha 
78336d26912SBhawanpreet Lakha 	dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
78436d26912SBhawanpreet Lakha 
78536d26912SBhawanpreet Lakha 	return &mpc30->base;
78636d26912SBhawanpreet Lakha }
78736d26912SBhawanpreet Lakha 
78836d26912SBhawanpreet Lakha #define dsc_regsDCN20(id)\
78936d26912SBhawanpreet Lakha [id] = { DSC_REG_LIST_DCN20(id) }
79036d26912SBhawanpreet Lakha 
79136d26912SBhawanpreet Lakha static const struct dcn20_dsc_registers dsc_regs[] = {
79236d26912SBhawanpreet Lakha 		dsc_regsDCN20(0),
79336d26912SBhawanpreet Lakha 		dsc_regsDCN20(1),
79436d26912SBhawanpreet Lakha 		dsc_regsDCN20(2),
79536d26912SBhawanpreet Lakha 		dsc_regsDCN20(3),
79636d26912SBhawanpreet Lakha 		dsc_regsDCN20(4)
79736d26912SBhawanpreet Lakha };
79836d26912SBhawanpreet Lakha 
79936d26912SBhawanpreet Lakha static const struct dcn20_dsc_shift dsc_shift = {
80036d26912SBhawanpreet Lakha 		DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
80136d26912SBhawanpreet Lakha };
80236d26912SBhawanpreet Lakha 
80336d26912SBhawanpreet Lakha static const struct dcn20_dsc_mask dsc_mask = {
80436d26912SBhawanpreet Lakha 		DSC_REG_LIST_SH_MASK_DCN20(_MASK)
80536d26912SBhawanpreet Lakha };
80636d26912SBhawanpreet Lakha 
80736d26912SBhawanpreet Lakha static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
80836d26912SBhawanpreet Lakha {
80936d26912SBhawanpreet Lakha 	struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
81036d26912SBhawanpreet Lakha 
81136d26912SBhawanpreet Lakha 	if (!dsc) {
81236d26912SBhawanpreet Lakha 		BREAK_TO_DEBUGGER();
81336d26912SBhawanpreet Lakha 		return NULL;
81436d26912SBhawanpreet Lakha 	}
81536d26912SBhawanpreet Lakha 
81636d26912SBhawanpreet Lakha 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
81736d26912SBhawanpreet Lakha 	return &dsc->base;
81836d26912SBhawanpreet Lakha }
81936d26912SBhawanpreet Lakha 
82036d26912SBhawanpreet Lakha #define dwbc_regs_dcn3(id)\
82136d26912SBhawanpreet Lakha [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
82236d26912SBhawanpreet Lakha 
82336d26912SBhawanpreet Lakha static const struct dcn30_dwbc_registers dwbc30_regs[] = {
82436d26912SBhawanpreet Lakha 		dwbc_regs_dcn3(0)
82536d26912SBhawanpreet Lakha };
82636d26912SBhawanpreet Lakha 
82736d26912SBhawanpreet Lakha static const struct dcn30_dwbc_shift dwbc30_shift = {
82836d26912SBhawanpreet Lakha 		DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
82936d26912SBhawanpreet Lakha };
83036d26912SBhawanpreet Lakha 
83136d26912SBhawanpreet Lakha static const struct dcn30_dwbc_mask dwbc30_mask = {
83236d26912SBhawanpreet Lakha 		DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
83336d26912SBhawanpreet Lakha };
83436d26912SBhawanpreet Lakha 
83536d26912SBhawanpreet Lakha static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
83636d26912SBhawanpreet Lakha {
83736d26912SBhawanpreet Lakha 	int i;
83836d26912SBhawanpreet Lakha 	uint32_t pipe_count = pool->res_cap->num_dwb;
83936d26912SBhawanpreet Lakha 
84036d26912SBhawanpreet Lakha 	for (i = 0; i < pipe_count; i++) {
84136d26912SBhawanpreet Lakha 		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
84236d26912SBhawanpreet Lakha 
84336d26912SBhawanpreet Lakha 		if (!dwbc30) {
84436d26912SBhawanpreet Lakha 			dm_error("DC: failed to create dwbc30!\n");
84536d26912SBhawanpreet Lakha 			return false;
84636d26912SBhawanpreet Lakha 		}
84736d26912SBhawanpreet Lakha 
84836d26912SBhawanpreet Lakha 		dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
84936d26912SBhawanpreet Lakha 
85036d26912SBhawanpreet Lakha 		pool->dwbc[i] = &dwbc30->base;
85136d26912SBhawanpreet Lakha 	}
85236d26912SBhawanpreet Lakha 	return true;
85336d26912SBhawanpreet Lakha }
85436d26912SBhawanpreet Lakha 
85536d26912SBhawanpreet Lakha #define mcif_wb_regs_dcn3(id)\
85636d26912SBhawanpreet Lakha [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
85736d26912SBhawanpreet Lakha 
85836d26912SBhawanpreet Lakha static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
85936d26912SBhawanpreet Lakha 		mcif_wb_regs_dcn3(0)
86036d26912SBhawanpreet Lakha };
86136d26912SBhawanpreet Lakha 
86236d26912SBhawanpreet Lakha static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
86336d26912SBhawanpreet Lakha 		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
86436d26912SBhawanpreet Lakha };
86536d26912SBhawanpreet Lakha 
86636d26912SBhawanpreet Lakha static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
86736d26912SBhawanpreet Lakha 		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
86836d26912SBhawanpreet Lakha };
86936d26912SBhawanpreet Lakha 
87036d26912SBhawanpreet Lakha static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
87136d26912SBhawanpreet Lakha {
87236d26912SBhawanpreet Lakha 	int i;
87336d26912SBhawanpreet Lakha 	uint32_t pipe_count = pool->res_cap->num_dwb;
87436d26912SBhawanpreet Lakha 
87536d26912SBhawanpreet Lakha 	for (i = 0; i < pipe_count; i++) {
87636d26912SBhawanpreet Lakha 		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
87736d26912SBhawanpreet Lakha 
87836d26912SBhawanpreet Lakha 		if (!mcif_wb30) {
87936d26912SBhawanpreet Lakha 			dm_error("DC: failed to create mcif_wb30!\n");
88036d26912SBhawanpreet Lakha 			return false;
88136d26912SBhawanpreet Lakha 		}
88236d26912SBhawanpreet Lakha 
88336d26912SBhawanpreet Lakha 		dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
88436d26912SBhawanpreet Lakha 
88536d26912SBhawanpreet Lakha 		pool->mcif_wb[i] = &mcif_wb30->base;
88636d26912SBhawanpreet Lakha 	}
88736d26912SBhawanpreet Lakha 	return true;
88836d26912SBhawanpreet Lakha }
88936d26912SBhawanpreet Lakha 
89036d26912SBhawanpreet Lakha #define aux_engine_regs(id)\
89136d26912SBhawanpreet Lakha [id] = {\
89236d26912SBhawanpreet Lakha 		AUX_COMMON_REG_LIST0(id), \
89336d26912SBhawanpreet Lakha 		.AUXN_IMPCAL = 0, \
89436d26912SBhawanpreet Lakha 		.AUXP_IMPCAL = 0, \
89536d26912SBhawanpreet Lakha 		.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
89636d26912SBhawanpreet Lakha }
89736d26912SBhawanpreet Lakha 
89836d26912SBhawanpreet Lakha static const struct dce110_aux_registers aux_engine_regs[] = {
89936d26912SBhawanpreet Lakha 		aux_engine_regs(0),
90036d26912SBhawanpreet Lakha 		aux_engine_regs(1),
90136d26912SBhawanpreet Lakha 		aux_engine_regs(2),
90236d26912SBhawanpreet Lakha 		aux_engine_regs(3),
90336d26912SBhawanpreet Lakha 		aux_engine_regs(4)
90436d26912SBhawanpreet Lakha };
90536d26912SBhawanpreet Lakha 
90636d26912SBhawanpreet Lakha static const struct dce110_aux_registers_shift aux_shift = {
90736d26912SBhawanpreet Lakha 		DCN_AUX_MASK_SH_LIST(__SHIFT)
90836d26912SBhawanpreet Lakha };
90936d26912SBhawanpreet Lakha 
91036d26912SBhawanpreet Lakha static const struct dce110_aux_registers_mask aux_mask = {
91136d26912SBhawanpreet Lakha 		DCN_AUX_MASK_SH_LIST(_MASK)
91236d26912SBhawanpreet Lakha };
91336d26912SBhawanpreet Lakha 
91436d26912SBhawanpreet Lakha static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
91536d26912SBhawanpreet Lakha {
91636d26912SBhawanpreet Lakha 	struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
91736d26912SBhawanpreet Lakha 
91836d26912SBhawanpreet Lakha 	if (!aux_engine)
91936d26912SBhawanpreet Lakha 		return NULL;
92036d26912SBhawanpreet Lakha 
92136d26912SBhawanpreet Lakha 	dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
92236d26912SBhawanpreet Lakha 			&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
92336d26912SBhawanpreet Lakha 
92436d26912SBhawanpreet Lakha 	return &aux_engine->base;
92536d26912SBhawanpreet Lakha }
92636d26912SBhawanpreet Lakha 
92736d26912SBhawanpreet Lakha #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
92836d26912SBhawanpreet Lakha 
92936d26912SBhawanpreet Lakha static const struct dce_i2c_registers i2c_hw_regs[] = {
93036d26912SBhawanpreet Lakha 		i2c_inst_regs(1),
93136d26912SBhawanpreet Lakha 		i2c_inst_regs(2),
93236d26912SBhawanpreet Lakha 		i2c_inst_regs(3),
93336d26912SBhawanpreet Lakha 		i2c_inst_regs(4),
93436d26912SBhawanpreet Lakha 		i2c_inst_regs(5)
93536d26912SBhawanpreet Lakha };
93636d26912SBhawanpreet Lakha 
93736d26912SBhawanpreet Lakha static const struct dce_i2c_shift i2c_shifts = {
93836d26912SBhawanpreet Lakha 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
93936d26912SBhawanpreet Lakha };
94036d26912SBhawanpreet Lakha 
94136d26912SBhawanpreet Lakha static const struct dce_i2c_mask i2c_masks = {
94236d26912SBhawanpreet Lakha 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
94336d26912SBhawanpreet Lakha };
94436d26912SBhawanpreet Lakha 
94536d26912SBhawanpreet Lakha static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
94636d26912SBhawanpreet Lakha {
94736d26912SBhawanpreet Lakha 	struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
94836d26912SBhawanpreet Lakha 
94936d26912SBhawanpreet Lakha 	if (!dce_i2c_hw)
95036d26912SBhawanpreet Lakha 		return NULL;
95136d26912SBhawanpreet Lakha 
95236d26912SBhawanpreet Lakha 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
95336d26912SBhawanpreet Lakha 
95436d26912SBhawanpreet Lakha 	return dce_i2c_hw;
95536d26912SBhawanpreet Lakha }
95636d26912SBhawanpreet Lakha 
95736d26912SBhawanpreet Lakha static const struct encoder_feature_support link_enc_feature = {
95836d26912SBhawanpreet Lakha 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
95936d26912SBhawanpreet Lakha 		.max_hdmi_pixel_clock = 600000,
96036d26912SBhawanpreet Lakha 		.hdmi_ycbcr420_supported = true,
96136d26912SBhawanpreet Lakha 		.dp_ycbcr420_supported = true,
96236d26912SBhawanpreet Lakha 		.fec_supported = true,
96336d26912SBhawanpreet Lakha 		.flags.bits.IS_HBR2_CAPABLE = true,
96436d26912SBhawanpreet Lakha 		.flags.bits.IS_HBR3_CAPABLE = true,
96536d26912SBhawanpreet Lakha 		.flags.bits.IS_TPS3_CAPABLE = true,
96636d26912SBhawanpreet Lakha 		.flags.bits.IS_TPS4_CAPABLE = true
96736d26912SBhawanpreet Lakha };
96836d26912SBhawanpreet Lakha 
96936d26912SBhawanpreet Lakha #define link_regs(id, phyid)\
97036d26912SBhawanpreet Lakha 		[id] = {\
97136d26912SBhawanpreet Lakha 				LE_DCN3_REG_LIST(id), \
97236d26912SBhawanpreet Lakha 				UNIPHY_DCN2_REG_LIST(phyid), \
97378deaf5fSBhawanpreet Lakha 				DPCS_DCN2_REG_LIST(id), \
97491bda9e9SChris Park 				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
97536d26912SBhawanpreet Lakha 		}
97636d26912SBhawanpreet Lakha 
97736d26912SBhawanpreet Lakha static const struct dcn10_link_enc_registers link_enc_regs[] = {
97836d26912SBhawanpreet Lakha 		link_regs(0, A),
97936d26912SBhawanpreet Lakha 		link_regs(1, B),
98036d26912SBhawanpreet Lakha 		link_regs(2, C),
98136d26912SBhawanpreet Lakha 		link_regs(3, D),
98236d26912SBhawanpreet Lakha 		link_regs(4, E)
98336d26912SBhawanpreet Lakha };
98436d26912SBhawanpreet Lakha 
98536d26912SBhawanpreet Lakha static const struct dcn10_link_enc_shift le_shift = {
98636d26912SBhawanpreet Lakha 		LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
98736d26912SBhawanpreet Lakha 		DPCS_DCN2_MASK_SH_LIST(__SHIFT)
98836d26912SBhawanpreet Lakha };
98936d26912SBhawanpreet Lakha 
99036d26912SBhawanpreet Lakha static const struct dcn10_link_enc_mask le_mask = {
99136d26912SBhawanpreet Lakha 		LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
99236d26912SBhawanpreet Lakha 		DPCS_DCN2_MASK_SH_LIST(_MASK)
99336d26912SBhawanpreet Lakha };
99436d26912SBhawanpreet Lakha 
99536d26912SBhawanpreet Lakha #define aux_regs(id)\
99636d26912SBhawanpreet Lakha 		[id] = { DCN2_AUX_REG_LIST(id) }
99736d26912SBhawanpreet Lakha 
99836d26912SBhawanpreet Lakha static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
99936d26912SBhawanpreet Lakha 		aux_regs(0),
100036d26912SBhawanpreet Lakha 		aux_regs(1),
100136d26912SBhawanpreet Lakha 		aux_regs(2),
100236d26912SBhawanpreet Lakha 		aux_regs(3),
100336d26912SBhawanpreet Lakha 		aux_regs(4)
100436d26912SBhawanpreet Lakha };
100536d26912SBhawanpreet Lakha 
100636d26912SBhawanpreet Lakha #define hpd_regs(id)\
100736d26912SBhawanpreet Lakha 		[id] = { HPD_REG_LIST(id) }
100836d26912SBhawanpreet Lakha 
100936d26912SBhawanpreet Lakha static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
101036d26912SBhawanpreet Lakha 		hpd_regs(0),
101136d26912SBhawanpreet Lakha 		hpd_regs(1),
101236d26912SBhawanpreet Lakha 		hpd_regs(2),
101336d26912SBhawanpreet Lakha 		hpd_regs(3),
101436d26912SBhawanpreet Lakha 		hpd_regs(4)
101536d26912SBhawanpreet Lakha };
101636d26912SBhawanpreet Lakha 
101736d26912SBhawanpreet Lakha static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data)
101836d26912SBhawanpreet Lakha {
101936d26912SBhawanpreet Lakha 	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
102036d26912SBhawanpreet Lakha 
102136d26912SBhawanpreet Lakha 	if (!enc20)
102236d26912SBhawanpreet Lakha 		return NULL;
102336d26912SBhawanpreet Lakha 
102436d26912SBhawanpreet Lakha 	dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
102536d26912SBhawanpreet Lakha 			&link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
102636d26912SBhawanpreet Lakha 			&link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
102736d26912SBhawanpreet Lakha 
102836d26912SBhawanpreet Lakha 	return &enc20->enc10.base;
102936d26912SBhawanpreet Lakha }
103036d26912SBhawanpreet Lakha 
103136d26912SBhawanpreet Lakha static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
103236d26912SBhawanpreet Lakha 		{ DCN_PANEL_CNTL_REG_LIST() }
103336d26912SBhawanpreet Lakha };
103436d26912SBhawanpreet Lakha 
103536d26912SBhawanpreet Lakha static const struct dce_panel_cntl_shift panel_cntl_shift = {
103636d26912SBhawanpreet Lakha 		DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
103736d26912SBhawanpreet Lakha };
103836d26912SBhawanpreet Lakha 
103936d26912SBhawanpreet Lakha static const struct dce_panel_cntl_mask panel_cntl_mask = {
104036d26912SBhawanpreet Lakha 		DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
104136d26912SBhawanpreet Lakha };
104236d26912SBhawanpreet Lakha 
104336d26912SBhawanpreet Lakha static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
104436d26912SBhawanpreet Lakha {
104536d26912SBhawanpreet Lakha 	struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
104636d26912SBhawanpreet Lakha 
104736d26912SBhawanpreet Lakha 	if (!panel_cntl)
104836d26912SBhawanpreet Lakha 		return NULL;
104936d26912SBhawanpreet Lakha 
105036d26912SBhawanpreet Lakha 	dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
105136d26912SBhawanpreet Lakha 			&panel_cntl_shift, &panel_cntl_mask);
105236d26912SBhawanpreet Lakha 
105336d26912SBhawanpreet Lakha 	return &panel_cntl->base;
105436d26912SBhawanpreet Lakha }
105536d26912SBhawanpreet Lakha 
105636d26912SBhawanpreet Lakha static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
105736d26912SBhawanpreet Lakha {
105836d26912SBhawanpreet Lakha 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
105936d26912SBhawanpreet Lakha 			FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
106036d26912SBhawanpreet Lakha }
106136d26912SBhawanpreet Lakha 
106236d26912SBhawanpreet Lakha static const struct resource_create_funcs res_create_funcs = {
106336d26912SBhawanpreet Lakha 		.read_dce_straps = read_dce_straps,
106436d26912SBhawanpreet Lakha 		.create_audio = dcn302_create_audio,
106536d26912SBhawanpreet Lakha 		.create_stream_encoder = dcn302_stream_encoder_create,
106636d26912SBhawanpreet Lakha 		.create_hwseq = dcn302_hwseq_create,
106736d26912SBhawanpreet Lakha };
106836d26912SBhawanpreet Lakha 
106936d26912SBhawanpreet Lakha static const struct resource_create_funcs res_create_maximus_funcs = {
107036d26912SBhawanpreet Lakha 		.read_dce_straps = NULL,
107136d26912SBhawanpreet Lakha 		.create_audio = NULL,
107236d26912SBhawanpreet Lakha 		.create_stream_encoder = NULL,
107336d26912SBhawanpreet Lakha 		.create_hwseq = dcn302_hwseq_create,
107436d26912SBhawanpreet Lakha };
107536d26912SBhawanpreet Lakha 
107636d26912SBhawanpreet Lakha static bool is_soc_bounding_box_valid(struct dc *dc)
107736d26912SBhawanpreet Lakha {
107836d26912SBhawanpreet Lakha 	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
107936d26912SBhawanpreet Lakha 
108036d26912SBhawanpreet Lakha 	if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
108136d26912SBhawanpreet Lakha 		return true;
108236d26912SBhawanpreet Lakha 
108336d26912SBhawanpreet Lakha 	return false;
108436d26912SBhawanpreet Lakha }
108536d26912SBhawanpreet Lakha 
108636d26912SBhawanpreet Lakha static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
108736d26912SBhawanpreet Lakha {
108836d26912SBhawanpreet Lakha 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
108936d26912SBhawanpreet Lakha 	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
109036d26912SBhawanpreet Lakha 
109136d26912SBhawanpreet Lakha 	DC_LOGGER_INIT(dc->ctx->logger);
109236d26912SBhawanpreet Lakha 
109336d26912SBhawanpreet Lakha 	if (!is_soc_bounding_box_valid(dc)) {
109436d26912SBhawanpreet Lakha 		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
109536d26912SBhawanpreet Lakha 		return false;
109636d26912SBhawanpreet Lakha 	}
109736d26912SBhawanpreet Lakha 
109836d26912SBhawanpreet Lakha 	loaded_ip->max_num_otg = pool->pipe_count;
109936d26912SBhawanpreet Lakha 	loaded_ip->max_num_dpp = pool->pipe_count;
110036d26912SBhawanpreet Lakha 	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
110136d26912SBhawanpreet Lakha 	dcn20_patch_bounding_box(dc, loaded_bb);
110236d26912SBhawanpreet Lakha 	return true;
110336d26912SBhawanpreet Lakha }
110436d26912SBhawanpreet Lakha 
110536d26912SBhawanpreet Lakha static void dcn302_resource_destruct(struct resource_pool *pool)
110636d26912SBhawanpreet Lakha {
110736d26912SBhawanpreet Lakha 	unsigned int i;
110836d26912SBhawanpreet Lakha 
110936d26912SBhawanpreet Lakha 	for (i = 0; i < pool->stream_enc_count; i++) {
111036d26912SBhawanpreet Lakha 		if (pool->stream_enc[i] != NULL) {
111136d26912SBhawanpreet Lakha 			if (pool->stream_enc[i]->vpg != NULL) {
111236d26912SBhawanpreet Lakha 				kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
111336d26912SBhawanpreet Lakha 				pool->stream_enc[i]->vpg = NULL;
111436d26912SBhawanpreet Lakha 			}
111536d26912SBhawanpreet Lakha 			if (pool->stream_enc[i]->afmt != NULL) {
111636d26912SBhawanpreet Lakha 				kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
111736d26912SBhawanpreet Lakha 				pool->stream_enc[i]->afmt = NULL;
111836d26912SBhawanpreet Lakha 			}
111936d26912SBhawanpreet Lakha 			kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
112036d26912SBhawanpreet Lakha 			pool->stream_enc[i] = NULL;
112136d26912SBhawanpreet Lakha 		}
112236d26912SBhawanpreet Lakha 	}
112336d26912SBhawanpreet Lakha 
112436d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
112536d26912SBhawanpreet Lakha 		if (pool->dscs[i] != NULL)
112636d26912SBhawanpreet Lakha 			dcn20_dsc_destroy(&pool->dscs[i]);
112736d26912SBhawanpreet Lakha 	}
112836d26912SBhawanpreet Lakha 
112936d26912SBhawanpreet Lakha 	if (pool->mpc != NULL) {
113036d26912SBhawanpreet Lakha 		kfree(TO_DCN20_MPC(pool->mpc));
113136d26912SBhawanpreet Lakha 		pool->mpc = NULL;
113236d26912SBhawanpreet Lakha 	}
113336d26912SBhawanpreet Lakha 
113436d26912SBhawanpreet Lakha 	if (pool->hubbub != NULL) {
113536d26912SBhawanpreet Lakha 		kfree(pool->hubbub);
113636d26912SBhawanpreet Lakha 		pool->hubbub = NULL;
113736d26912SBhawanpreet Lakha 	}
113836d26912SBhawanpreet Lakha 
113936d26912SBhawanpreet Lakha 	for (i = 0; i < pool->pipe_count; i++) {
114036d26912SBhawanpreet Lakha 		if (pool->dpps[i] != NULL) {
114136d26912SBhawanpreet Lakha 			kfree(TO_DCN20_DPP(pool->dpps[i]));
114236d26912SBhawanpreet Lakha 			pool->dpps[i] = NULL;
114336d26912SBhawanpreet Lakha 		}
114436d26912SBhawanpreet Lakha 
114536d26912SBhawanpreet Lakha 		if (pool->hubps[i] != NULL) {
114636d26912SBhawanpreet Lakha 			kfree(TO_DCN20_HUBP(pool->hubps[i]));
114736d26912SBhawanpreet Lakha 			pool->hubps[i] = NULL;
114836d26912SBhawanpreet Lakha 		}
114936d26912SBhawanpreet Lakha 
115036d26912SBhawanpreet Lakha 		if (pool->irqs != NULL)
115136d26912SBhawanpreet Lakha 			dal_irq_service_destroy(&pool->irqs);
115236d26912SBhawanpreet Lakha 	}
115336d26912SBhawanpreet Lakha 
115436d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_ddc; i++) {
115536d26912SBhawanpreet Lakha 		if (pool->engines[i] != NULL)
115636d26912SBhawanpreet Lakha 			dce110_engine_destroy(&pool->engines[i]);
115736d26912SBhawanpreet Lakha 		if (pool->hw_i2cs[i] != NULL) {
115836d26912SBhawanpreet Lakha 			kfree(pool->hw_i2cs[i]);
115936d26912SBhawanpreet Lakha 			pool->hw_i2cs[i] = NULL;
116036d26912SBhawanpreet Lakha 		}
116136d26912SBhawanpreet Lakha 		if (pool->sw_i2cs[i] != NULL) {
116236d26912SBhawanpreet Lakha 			kfree(pool->sw_i2cs[i]);
116336d26912SBhawanpreet Lakha 			pool->sw_i2cs[i] = NULL;
116436d26912SBhawanpreet Lakha 		}
116536d26912SBhawanpreet Lakha 	}
116636d26912SBhawanpreet Lakha 
116736d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_opp; i++) {
116836d26912SBhawanpreet Lakha 		if (pool->opps[i] != NULL)
116936d26912SBhawanpreet Lakha 			pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
117036d26912SBhawanpreet Lakha 	}
117136d26912SBhawanpreet Lakha 
117236d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
117336d26912SBhawanpreet Lakha 		if (pool->timing_generators[i] != NULL)	{
117436d26912SBhawanpreet Lakha 			kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
117536d26912SBhawanpreet Lakha 			pool->timing_generators[i] = NULL;
117636d26912SBhawanpreet Lakha 		}
117736d26912SBhawanpreet Lakha 	}
117836d26912SBhawanpreet Lakha 
117936d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_dwb; i++) {
118036d26912SBhawanpreet Lakha 		if (pool->dwbc[i] != NULL) {
118136d26912SBhawanpreet Lakha 			kfree(TO_DCN30_DWBC(pool->dwbc[i]));
118236d26912SBhawanpreet Lakha 			pool->dwbc[i] = NULL;
118336d26912SBhawanpreet Lakha 		}
118436d26912SBhawanpreet Lakha 		if (pool->mcif_wb[i] != NULL) {
118536d26912SBhawanpreet Lakha 			kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
118636d26912SBhawanpreet Lakha 			pool->mcif_wb[i] = NULL;
118736d26912SBhawanpreet Lakha 		}
118836d26912SBhawanpreet Lakha 	}
118936d26912SBhawanpreet Lakha 
119036d26912SBhawanpreet Lakha 	for (i = 0; i < pool->audio_count; i++) {
119136d26912SBhawanpreet Lakha 		if (pool->audios[i])
119236d26912SBhawanpreet Lakha 			dce_aud_destroy(&pool->audios[i]);
119336d26912SBhawanpreet Lakha 	}
119436d26912SBhawanpreet Lakha 
119536d26912SBhawanpreet Lakha 	for (i = 0; i < pool->clk_src_count; i++) {
119636d26912SBhawanpreet Lakha 		if (pool->clock_sources[i] != NULL)
119736d26912SBhawanpreet Lakha 			dcn20_clock_source_destroy(&pool->clock_sources[i]);
119836d26912SBhawanpreet Lakha 	}
119936d26912SBhawanpreet Lakha 
120036d26912SBhawanpreet Lakha 	if (pool->dp_clock_source != NULL)
120136d26912SBhawanpreet Lakha 		dcn20_clock_source_destroy(&pool->dp_clock_source);
120236d26912SBhawanpreet Lakha 
120336d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
120436d26912SBhawanpreet Lakha 		if (pool->mpc_lut[i] != NULL) {
120536d26912SBhawanpreet Lakha 			dc_3dlut_func_release(pool->mpc_lut[i]);
120636d26912SBhawanpreet Lakha 			pool->mpc_lut[i] = NULL;
120736d26912SBhawanpreet Lakha 		}
120836d26912SBhawanpreet Lakha 		if (pool->mpc_shaper[i] != NULL) {
120936d26912SBhawanpreet Lakha 			dc_transfer_func_release(pool->mpc_shaper[i]);
121036d26912SBhawanpreet Lakha 			pool->mpc_shaper[i] = NULL;
121136d26912SBhawanpreet Lakha 		}
121236d26912SBhawanpreet Lakha 	}
121336d26912SBhawanpreet Lakha 
121436d26912SBhawanpreet Lakha 	for (i = 0; i < pool->pipe_count; i++) {
121536d26912SBhawanpreet Lakha 		if (pool->multiple_abms[i] != NULL)
121636d26912SBhawanpreet Lakha 			dce_abm_destroy(&pool->multiple_abms[i]);
121736d26912SBhawanpreet Lakha 	}
121836d26912SBhawanpreet Lakha 
121965e05ca7SJoshua Aberback 	if (pool->psr != NULL)
122065e05ca7SJoshua Aberback 		dmub_psr_destroy(&pool->psr);
122165e05ca7SJoshua Aberback 
122236d26912SBhawanpreet Lakha 	if (pool->dccg != NULL)
122336d26912SBhawanpreet Lakha 		dcn_dccg_destroy(&pool->dccg);
122436d26912SBhawanpreet Lakha }
122536d26912SBhawanpreet Lakha 
122636d26912SBhawanpreet Lakha static void dcn302_destroy_resource_pool(struct resource_pool **pool)
122736d26912SBhawanpreet Lakha {
122836d26912SBhawanpreet Lakha 	dcn302_resource_destruct(*pool);
122936d26912SBhawanpreet Lakha 	kfree(*pool);
123036d26912SBhawanpreet Lakha 	*pool = NULL;
123136d26912SBhawanpreet Lakha }
123236d26912SBhawanpreet Lakha 
1233*163e3bcbSSamson Tam static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
1234*163e3bcbSSamson Tam 		unsigned int *optimal_dcfclk,
1235*163e3bcbSSamson Tam 		unsigned int *optimal_fclk)
1236*163e3bcbSSamson Tam {
1237*163e3bcbSSamson Tam 	double bw_from_dram, bw_from_dram1, bw_from_dram2;
1238*163e3bcbSSamson Tam 
1239*163e3bcbSSamson Tam 	bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans *
1240*163e3bcbSSamson Tam 		dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_dram_bw_use_normal_percent / 100);
1241*163e3bcbSSamson Tam 	bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans *
1242*163e3bcbSSamson Tam 		dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100);
1243*163e3bcbSSamson Tam 
1244*163e3bcbSSamson Tam 	bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
1245*163e3bcbSSamson Tam 
1246*163e3bcbSSamson Tam 	if (optimal_fclk)
1247*163e3bcbSSamson Tam 		*optimal_fclk = bw_from_dram /
1248*163e3bcbSSamson Tam 		(dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100));
1249*163e3bcbSSamson Tam 
1250*163e3bcbSSamson Tam 	if (optimal_dcfclk)
1251*163e3bcbSSamson Tam 		*optimal_dcfclk =  bw_from_dram /
1252*163e3bcbSSamson Tam 		(dcn3_02_soc.return_bus_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100));
1253*163e3bcbSSamson Tam }
1254*163e3bcbSSamson Tam 
1255*163e3bcbSSamson Tam void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1256*163e3bcbSSamson Tam {
1257*163e3bcbSSamson Tam 	unsigned int i, j;
1258*163e3bcbSSamson Tam 	unsigned int num_states = 0;
1259*163e3bcbSSamson Tam 
1260*163e3bcbSSamson Tam 	unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
1261*163e3bcbSSamson Tam 	unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
1262*163e3bcbSSamson Tam 	unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
1263*163e3bcbSSamson Tam 	unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
1264*163e3bcbSSamson Tam 
1265*163e3bcbSSamson Tam 	unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
1266*163e3bcbSSamson Tam 	unsigned int num_dcfclk_sta_targets = 4;
1267*163e3bcbSSamson Tam 	unsigned int num_uclk_states;
1268*163e3bcbSSamson Tam 
1269*163e3bcbSSamson Tam 
1270*163e3bcbSSamson Tam 	if (dc->ctx->dc_bios->vram_info.num_chans)
1271*163e3bcbSSamson Tam 		dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
1272*163e3bcbSSamson Tam 
1273*163e3bcbSSamson Tam 	if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
1274*163e3bcbSSamson Tam 		dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
1275*163e3bcbSSamson Tam 
1276*163e3bcbSSamson Tam 	dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1277*163e3bcbSSamson Tam 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1278*163e3bcbSSamson Tam 
1279*163e3bcbSSamson Tam 	if (bw_params->clk_table.entries[0].memclk_mhz) {
1280*163e3bcbSSamson Tam 		int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
1281*163e3bcbSSamson Tam 
1282*163e3bcbSSamson Tam 		for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
1283*163e3bcbSSamson Tam 			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
1284*163e3bcbSSamson Tam 				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
1285*163e3bcbSSamson Tam 			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
1286*163e3bcbSSamson Tam 				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
1287*163e3bcbSSamson Tam 			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
1288*163e3bcbSSamson Tam 				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
1289*163e3bcbSSamson Tam 			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
1290*163e3bcbSSamson Tam 				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
1291*163e3bcbSSamson Tam 		}
1292*163e3bcbSSamson Tam 		if (!max_dcfclk_mhz)
1293*163e3bcbSSamson Tam 			max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz;
1294*163e3bcbSSamson Tam 		if (!max_dispclk_mhz)
1295*163e3bcbSSamson Tam 			max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz;
1296*163e3bcbSSamson Tam 		if (!max_dppclk_mhz)
1297*163e3bcbSSamson Tam 			max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz;
1298*163e3bcbSSamson Tam 		if (!max_phyclk_mhz)
1299*163e3bcbSSamson Tam 			max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz;
1300*163e3bcbSSamson Tam 
1301*163e3bcbSSamson Tam 		if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1302*163e3bcbSSamson Tam 			/* If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array */
1303*163e3bcbSSamson Tam 			dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
1304*163e3bcbSSamson Tam 			num_dcfclk_sta_targets++;
1305*163e3bcbSSamson Tam 		} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1306*163e3bcbSSamson Tam 			/* If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates */
1307*163e3bcbSSamson Tam 			for (i = 0; i < num_dcfclk_sta_targets; i++) {
1308*163e3bcbSSamson Tam 				if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
1309*163e3bcbSSamson Tam 					dcfclk_sta_targets[i] = max_dcfclk_mhz;
1310*163e3bcbSSamson Tam 					break;
1311*163e3bcbSSamson Tam 				}
1312*163e3bcbSSamson Tam 			}
1313*163e3bcbSSamson Tam 			/* Update size of array since we "removed" duplicates */
1314*163e3bcbSSamson Tam 			num_dcfclk_sta_targets = i + 1;
1315*163e3bcbSSamson Tam 		}
1316*163e3bcbSSamson Tam 
1317*163e3bcbSSamson Tam 		num_uclk_states = bw_params->clk_table.num_entries;
1318*163e3bcbSSamson Tam 
1319*163e3bcbSSamson Tam 		/* Calculate optimal dcfclk for each uclk */
1320*163e3bcbSSamson Tam 		for (i = 0; i < num_uclk_states; i++) {
1321*163e3bcbSSamson Tam 			dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
1322*163e3bcbSSamson Tam 					&optimal_dcfclk_for_uclk[i], NULL);
1323*163e3bcbSSamson Tam 			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
1324*163e3bcbSSamson Tam 				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
1325*163e3bcbSSamson Tam 			}
1326*163e3bcbSSamson Tam 		}
1327*163e3bcbSSamson Tam 
1328*163e3bcbSSamson Tam 		/* Calculate optimal uclk for each dcfclk sta target */
1329*163e3bcbSSamson Tam 		for (i = 0; i < num_dcfclk_sta_targets; i++) {
1330*163e3bcbSSamson Tam 			for (j = 0; j < num_uclk_states; j++) {
1331*163e3bcbSSamson Tam 				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
1332*163e3bcbSSamson Tam 					optimal_uclk_for_dcfclk_sta_targets[i] =
1333*163e3bcbSSamson Tam 							bw_params->clk_table.entries[j].memclk_mhz * 16;
1334*163e3bcbSSamson Tam 					break;
1335*163e3bcbSSamson Tam 				}
1336*163e3bcbSSamson Tam 			}
1337*163e3bcbSSamson Tam 		}
1338*163e3bcbSSamson Tam 
1339*163e3bcbSSamson Tam 		i = 0;
1340*163e3bcbSSamson Tam 		j = 0;
1341*163e3bcbSSamson Tam 		/* create the final dcfclk and uclk table */
1342*163e3bcbSSamson Tam 		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
1343*163e3bcbSSamson Tam 			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
1344*163e3bcbSSamson Tam 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1345*163e3bcbSSamson Tam 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1346*163e3bcbSSamson Tam 			} else {
1347*163e3bcbSSamson Tam 				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1348*163e3bcbSSamson Tam 					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1349*163e3bcbSSamson Tam 					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
1350*163e3bcbSSamson Tam 				} else {
1351*163e3bcbSSamson Tam 					j = num_uclk_states;
1352*163e3bcbSSamson Tam 				}
1353*163e3bcbSSamson Tam 			}
1354*163e3bcbSSamson Tam 		}
1355*163e3bcbSSamson Tam 
1356*163e3bcbSSamson Tam 		while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
1357*163e3bcbSSamson Tam 			dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1358*163e3bcbSSamson Tam 			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1359*163e3bcbSSamson Tam 		}
1360*163e3bcbSSamson Tam 
1361*163e3bcbSSamson Tam 		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
1362*163e3bcbSSamson Tam 				optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1363*163e3bcbSSamson Tam 			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1364*163e3bcbSSamson Tam 			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
1365*163e3bcbSSamson Tam 		}
1366*163e3bcbSSamson Tam 
1367*163e3bcbSSamson Tam 		dcn3_02_soc.num_states = num_states;
1368*163e3bcbSSamson Tam 		for (i = 0; i < dcn3_02_soc.num_states; i++) {
1369*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].state = i;
1370*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
1371*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
1372*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
1373*163e3bcbSSamson Tam 
1374*163e3bcbSSamson Tam 			/* Fill all states with max values of all other clocks */
1375*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
1376*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
1377*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
1378*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz;
1379*163e3bcbSSamson Tam 			/* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */
1380*163e3bcbSSamson Tam 			/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
1381*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz;
1382*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[0].socclk_mhz;
1383*163e3bcbSSamson Tam 			dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz;
1384*163e3bcbSSamson Tam 		}
1385*163e3bcbSSamson Tam 		/* re-init DML with updated bb */
1386*163e3bcbSSamson Tam 		dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1387*163e3bcbSSamson Tam 		if (dc->current_state)
1388*163e3bcbSSamson Tam 			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1389*163e3bcbSSamson Tam 	}
1390*163e3bcbSSamson Tam }
1391*163e3bcbSSamson Tam 
139236d26912SBhawanpreet Lakha static struct resource_funcs dcn302_res_pool_funcs = {
139336d26912SBhawanpreet Lakha 		.destroy = dcn302_destroy_resource_pool,
139436d26912SBhawanpreet Lakha 		.link_enc_create = dcn302_link_encoder_create,
139536d26912SBhawanpreet Lakha 		.panel_cntl_create = dcn302_panel_cntl_create,
139636d26912SBhawanpreet Lakha 		.validate_bandwidth = dcn30_validate_bandwidth,
139736d26912SBhawanpreet Lakha 		.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
139836d26912SBhawanpreet Lakha 		.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
139936d26912SBhawanpreet Lakha 		.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
140036d26912SBhawanpreet Lakha 		.add_stream_to_ctx = dcn30_add_stream_to_ctx,
140136d26912SBhawanpreet Lakha 		.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
140236d26912SBhawanpreet Lakha 		.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
140336d26912SBhawanpreet Lakha 		.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
140436d26912SBhawanpreet Lakha 		.set_mcif_arb_params = dcn30_set_mcif_arb_params,
140536d26912SBhawanpreet Lakha 		.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
140636d26912SBhawanpreet Lakha 		.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
140736d26912SBhawanpreet Lakha 		.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1408*163e3bcbSSamson Tam 		.update_bw_bounding_box = dcn302_update_bw_bounding_box,
140936d26912SBhawanpreet Lakha 		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
141036d26912SBhawanpreet Lakha };
141136d26912SBhawanpreet Lakha 
141236d26912SBhawanpreet Lakha static struct dc_cap_funcs cap_funcs = {
141336d26912SBhawanpreet Lakha 		.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
141436d26912SBhawanpreet Lakha };
141536d26912SBhawanpreet Lakha 
141636d26912SBhawanpreet Lakha static const struct bios_registers bios_regs = {
141736d26912SBhawanpreet Lakha 		NBIO_SR(BIOS_SCRATCH_3),
141836d26912SBhawanpreet Lakha 		NBIO_SR(BIOS_SCRATCH_6)
141936d26912SBhawanpreet Lakha };
142036d26912SBhawanpreet Lakha 
142136d26912SBhawanpreet Lakha static const struct dccg_registers dccg_regs = {
142236d26912SBhawanpreet Lakha 		DCCG_REG_LIST_DCN3_02()
142336d26912SBhawanpreet Lakha };
142436d26912SBhawanpreet Lakha 
142536d26912SBhawanpreet Lakha static const struct dccg_shift dccg_shift = {
142636d26912SBhawanpreet Lakha 		DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
142736d26912SBhawanpreet Lakha };
142836d26912SBhawanpreet Lakha 
142936d26912SBhawanpreet Lakha static const struct dccg_mask dccg_mask = {
143036d26912SBhawanpreet Lakha 		DCCG_MASK_SH_LIST_DCN3_02(_MASK)
143136d26912SBhawanpreet Lakha };
143236d26912SBhawanpreet Lakha 
143336d26912SBhawanpreet Lakha #define abm_regs(id)\
143436d26912SBhawanpreet Lakha 		[id] = { ABM_DCN301_REG_LIST(id) }
143536d26912SBhawanpreet Lakha 
143636d26912SBhawanpreet Lakha static const struct dce_abm_registers abm_regs[] = {
143736d26912SBhawanpreet Lakha 		abm_regs(0),
143836d26912SBhawanpreet Lakha 		abm_regs(1),
143936d26912SBhawanpreet Lakha 		abm_regs(2),
144036d26912SBhawanpreet Lakha 		abm_regs(3),
144136d26912SBhawanpreet Lakha 		abm_regs(4)
144236d26912SBhawanpreet Lakha };
144336d26912SBhawanpreet Lakha 
144436d26912SBhawanpreet Lakha static const struct dce_abm_shift abm_shift = {
1445df043738SRoman Li 		ABM_MASK_SH_LIST_DCN30(__SHIFT)
144636d26912SBhawanpreet Lakha };
144736d26912SBhawanpreet Lakha 
144836d26912SBhawanpreet Lakha static const struct dce_abm_mask abm_mask = {
1449df043738SRoman Li 		ABM_MASK_SH_LIST_DCN30(_MASK)
145036d26912SBhawanpreet Lakha };
145136d26912SBhawanpreet Lakha 
145236d26912SBhawanpreet Lakha static bool dcn302_resource_construct(
145336d26912SBhawanpreet Lakha 		uint8_t num_virtual_links,
145436d26912SBhawanpreet Lakha 		struct dc *dc,
145536d26912SBhawanpreet Lakha 		struct resource_pool *pool)
145636d26912SBhawanpreet Lakha {
145736d26912SBhawanpreet Lakha 	int i;
145836d26912SBhawanpreet Lakha 	struct dc_context *ctx = dc->ctx;
145936d26912SBhawanpreet Lakha 	struct irq_service_init_data init_data;
146036d26912SBhawanpreet Lakha 
146136d26912SBhawanpreet Lakha 	ctx->dc_bios->regs = &bios_regs;
146236d26912SBhawanpreet Lakha 
146336d26912SBhawanpreet Lakha 	pool->res_cap = &res_cap_dcn302;
146436d26912SBhawanpreet Lakha 
146536d26912SBhawanpreet Lakha 	pool->funcs = &dcn302_res_pool_funcs;
146636d26912SBhawanpreet Lakha 
146736d26912SBhawanpreet Lakha 	/*************************************************
146836d26912SBhawanpreet Lakha 	 *  Resource + asic cap harcoding                *
146936d26912SBhawanpreet Lakha 	 *************************************************/
147036d26912SBhawanpreet Lakha 	pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
147136d26912SBhawanpreet Lakha 	pool->pipe_count = pool->res_cap->num_timing_generator;
147236d26912SBhawanpreet Lakha 	pool->mpcc_count = pool->res_cap->num_timing_generator;
147336d26912SBhawanpreet Lakha 	dc->caps.max_downscale_ratio = 600;
147436d26912SBhawanpreet Lakha 	dc->caps.i2c_speed_in_khz = 100;
1475e97978e8SCharlene Liu 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
147636d26912SBhawanpreet Lakha 	dc->caps.max_cursor_size = 256;
147706722b37SAshley Thomas 	dc->caps.min_horizontal_blanking_period = 80;
147836d26912SBhawanpreet Lakha 	dc->caps.dmdata_alloc_size = 2048;
1479ea7154d8SBhawanpreet Lakha 	dc->caps.mall_size_per_mem_channel = 4;
1480ea7154d8SBhawanpreet Lakha 	/* total size = mall per channel * num channels * 1024 * 1024 */
1481ea7154d8SBhawanpreet Lakha 	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
14827fc75382SBhawanpreet Lakha 	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
148336d26912SBhawanpreet Lakha 	dc->caps.max_slave_planes = 1;
148436d26912SBhawanpreet Lakha 	dc->caps.post_blend_color_processing = true;
148536d26912SBhawanpreet Lakha 	dc->caps.force_dp_tps4_for_cp2520 = true;
148636d26912SBhawanpreet Lakha 	dc->caps.extended_aux_timeout_support = true;
148736d26912SBhawanpreet Lakha 	dc->caps.dmcub_support = true;
148836d26912SBhawanpreet Lakha 
148936d26912SBhawanpreet Lakha 	/* Color pipeline capabilities */
149036d26912SBhawanpreet Lakha 	dc->caps.color.dpp.dcn_arch = 1;
149136d26912SBhawanpreet Lakha 	dc->caps.color.dpp.input_lut_shared = 0;
149236d26912SBhawanpreet Lakha 	dc->caps.color.dpp.icsc = 1;
149336d26912SBhawanpreet Lakha 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
149436d26912SBhawanpreet Lakha 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
149536d26912SBhawanpreet Lakha 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
149636d26912SBhawanpreet Lakha 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
149736d26912SBhawanpreet Lakha 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
149836d26912SBhawanpreet Lakha 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
149936d26912SBhawanpreet Lakha 	dc->caps.color.dpp.post_csc = 1;
150036d26912SBhawanpreet Lakha 	dc->caps.color.dpp.gamma_corr = 1;
1501c6160900SJing Zhou 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
150236d26912SBhawanpreet Lakha 
150336d26912SBhawanpreet Lakha 	dc->caps.color.dpp.hw_3d_lut = 1;
150436d26912SBhawanpreet Lakha 	dc->caps.color.dpp.ogam_ram = 1;
150536d26912SBhawanpreet Lakha 	// no OGAM ROM on DCN3
150636d26912SBhawanpreet Lakha 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
150736d26912SBhawanpreet Lakha 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
150836d26912SBhawanpreet Lakha 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
150936d26912SBhawanpreet Lakha 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
151036d26912SBhawanpreet Lakha 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
151136d26912SBhawanpreet Lakha 	dc->caps.color.dpp.ocsc = 0;
151236d26912SBhawanpreet Lakha 
151336d26912SBhawanpreet Lakha 	dc->caps.color.mpc.gamut_remap = 1;
151436d26912SBhawanpreet Lakha 	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
151536d26912SBhawanpreet Lakha 	dc->caps.color.mpc.ogam_ram = 1;
151636d26912SBhawanpreet Lakha 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
151736d26912SBhawanpreet Lakha 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
151836d26912SBhawanpreet Lakha 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
151936d26912SBhawanpreet Lakha 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
152036d26912SBhawanpreet Lakha 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
152136d26912SBhawanpreet Lakha 	dc->caps.color.mpc.ocsc = 1;
152236d26912SBhawanpreet Lakha 
152336d26912SBhawanpreet Lakha 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
152436d26912SBhawanpreet Lakha 		dc->debug = debug_defaults_drv;
152536d26912SBhawanpreet Lakha 	else
152636d26912SBhawanpreet Lakha 		dc->debug = debug_defaults_diags;
152736d26912SBhawanpreet Lakha 
152836d26912SBhawanpreet Lakha 	// Init the vm_helper
152936d26912SBhawanpreet Lakha 	if (dc->vm_helper)
153036d26912SBhawanpreet Lakha 		vm_helper_init(dc->vm_helper, 16);
153136d26912SBhawanpreet Lakha 
153236d26912SBhawanpreet Lakha 	/*************************************************
153336d26912SBhawanpreet Lakha 	 *  Create resources                             *
153436d26912SBhawanpreet Lakha 	 *************************************************/
153536d26912SBhawanpreet Lakha 
153636d26912SBhawanpreet Lakha 	/* Clock Sources for Pixel Clock*/
153736d26912SBhawanpreet Lakha 	pool->clock_sources[DCN302_CLK_SRC_PLL0] =
153836d26912SBhawanpreet Lakha 			dcn302_clock_source_create(ctx, ctx->dc_bios,
153936d26912SBhawanpreet Lakha 					CLOCK_SOURCE_COMBO_PHY_PLL0,
154036d26912SBhawanpreet Lakha 					&clk_src_regs[0], false);
154136d26912SBhawanpreet Lakha 	pool->clock_sources[DCN302_CLK_SRC_PLL1] =
154236d26912SBhawanpreet Lakha 			dcn302_clock_source_create(ctx, ctx->dc_bios,
154336d26912SBhawanpreet Lakha 					CLOCK_SOURCE_COMBO_PHY_PLL1,
154436d26912SBhawanpreet Lakha 					&clk_src_regs[1], false);
154536d26912SBhawanpreet Lakha 	pool->clock_sources[DCN302_CLK_SRC_PLL2] =
154636d26912SBhawanpreet Lakha 			dcn302_clock_source_create(ctx, ctx->dc_bios,
154736d26912SBhawanpreet Lakha 					CLOCK_SOURCE_COMBO_PHY_PLL2,
154836d26912SBhawanpreet Lakha 					&clk_src_regs[2], false);
154936d26912SBhawanpreet Lakha 	pool->clock_sources[DCN302_CLK_SRC_PLL3] =
155036d26912SBhawanpreet Lakha 			dcn302_clock_source_create(ctx, ctx->dc_bios,
155136d26912SBhawanpreet Lakha 					CLOCK_SOURCE_COMBO_PHY_PLL3,
155236d26912SBhawanpreet Lakha 					&clk_src_regs[3], false);
155336d26912SBhawanpreet Lakha 	pool->clock_sources[DCN302_CLK_SRC_PLL4] =
155436d26912SBhawanpreet Lakha 			dcn302_clock_source_create(ctx, ctx->dc_bios,
155536d26912SBhawanpreet Lakha 					CLOCK_SOURCE_COMBO_PHY_PLL4,
155636d26912SBhawanpreet Lakha 					&clk_src_regs[4], false);
155736d26912SBhawanpreet Lakha 
155836d26912SBhawanpreet Lakha 	pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
155936d26912SBhawanpreet Lakha 
156036d26912SBhawanpreet Lakha 	/* todo: not reuse phy_pll registers */
156136d26912SBhawanpreet Lakha 	pool->dp_clock_source =
156236d26912SBhawanpreet Lakha 			dcn302_clock_source_create(ctx, ctx->dc_bios,
156336d26912SBhawanpreet Lakha 					CLOCK_SOURCE_ID_DP_DTO,
156436d26912SBhawanpreet Lakha 					&clk_src_regs[0], true);
156536d26912SBhawanpreet Lakha 
156636d26912SBhawanpreet Lakha 	for (i = 0; i < pool->clk_src_count; i++) {
156736d26912SBhawanpreet Lakha 		if (pool->clock_sources[i] == NULL) {
156836d26912SBhawanpreet Lakha 			dm_error("DC: failed to create clock sources!\n");
156936d26912SBhawanpreet Lakha 			BREAK_TO_DEBUGGER();
157036d26912SBhawanpreet Lakha 			goto create_fail;
157136d26912SBhawanpreet Lakha 		}
157236d26912SBhawanpreet Lakha 	}
157336d26912SBhawanpreet Lakha 
157436d26912SBhawanpreet Lakha 	/* DCCG */
157536d26912SBhawanpreet Lakha 	pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
157636d26912SBhawanpreet Lakha 	if (pool->dccg == NULL) {
157736d26912SBhawanpreet Lakha 		dm_error("DC: failed to create dccg!\n");
157836d26912SBhawanpreet Lakha 		BREAK_TO_DEBUGGER();
157936d26912SBhawanpreet Lakha 		goto create_fail;
158036d26912SBhawanpreet Lakha 	}
158136d26912SBhawanpreet Lakha 
158236d26912SBhawanpreet Lakha 	/* PP Lib and SMU interfaces */
158336d26912SBhawanpreet Lakha 	init_soc_bounding_box(dc, pool);
158436d26912SBhawanpreet Lakha 
158536d26912SBhawanpreet Lakha 	/* DML */
158636d26912SBhawanpreet Lakha 	dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
158736d26912SBhawanpreet Lakha 
158836d26912SBhawanpreet Lakha 	/* IRQ */
158936d26912SBhawanpreet Lakha 	init_data.ctx = dc->ctx;
159036d26912SBhawanpreet Lakha 	pool->irqs = dal_irq_service_dcn302_create(&init_data);
159136d26912SBhawanpreet Lakha 	if (!pool->irqs)
159236d26912SBhawanpreet Lakha 		goto create_fail;
159336d26912SBhawanpreet Lakha 
159436d26912SBhawanpreet Lakha 	/* HUBBUB */
159536d26912SBhawanpreet Lakha 	pool->hubbub = dcn302_hubbub_create(ctx);
159636d26912SBhawanpreet Lakha 	if (pool->hubbub == NULL) {
159736d26912SBhawanpreet Lakha 		BREAK_TO_DEBUGGER();
159836d26912SBhawanpreet Lakha 		dm_error("DC: failed to create hubbub!\n");
159936d26912SBhawanpreet Lakha 		goto create_fail;
160036d26912SBhawanpreet Lakha 	}
160136d26912SBhawanpreet Lakha 
160236d26912SBhawanpreet Lakha 	/* HUBPs, DPPs, OPPs and TGs */
160336d26912SBhawanpreet Lakha 	for (i = 0; i < pool->pipe_count; i++) {
160436d26912SBhawanpreet Lakha 		pool->hubps[i] = dcn302_hubp_create(ctx, i);
160536d26912SBhawanpreet Lakha 		if (pool->hubps[i] == NULL) {
160636d26912SBhawanpreet Lakha 			BREAK_TO_DEBUGGER();
160736d26912SBhawanpreet Lakha 			dm_error("DC: failed to create hubps!\n");
160836d26912SBhawanpreet Lakha 			goto create_fail;
160936d26912SBhawanpreet Lakha 		}
161036d26912SBhawanpreet Lakha 
161136d26912SBhawanpreet Lakha 		pool->dpps[i] = dcn302_dpp_create(ctx, i);
161236d26912SBhawanpreet Lakha 		if (pool->dpps[i] == NULL) {
161336d26912SBhawanpreet Lakha 			BREAK_TO_DEBUGGER();
161436d26912SBhawanpreet Lakha 			dm_error("DC: failed to create dpps!\n");
161536d26912SBhawanpreet Lakha 			goto create_fail;
161636d26912SBhawanpreet Lakha 		}
161736d26912SBhawanpreet Lakha 	}
161836d26912SBhawanpreet Lakha 
161936d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_opp; i++) {
162036d26912SBhawanpreet Lakha 		pool->opps[i] = dcn302_opp_create(ctx, i);
162136d26912SBhawanpreet Lakha 		if (pool->opps[i] == NULL) {
162236d26912SBhawanpreet Lakha 			BREAK_TO_DEBUGGER();
162336d26912SBhawanpreet Lakha 			dm_error("DC: failed to create output pixel processor!\n");
162436d26912SBhawanpreet Lakha 			goto create_fail;
162536d26912SBhawanpreet Lakha 		}
162636d26912SBhawanpreet Lakha 	}
162736d26912SBhawanpreet Lakha 
162836d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
162936d26912SBhawanpreet Lakha 		pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
163036d26912SBhawanpreet Lakha 		if (pool->timing_generators[i] == NULL) {
163136d26912SBhawanpreet Lakha 			BREAK_TO_DEBUGGER();
163236d26912SBhawanpreet Lakha 			dm_error("DC: failed to create tg!\n");
163336d26912SBhawanpreet Lakha 			goto create_fail;
163436d26912SBhawanpreet Lakha 		}
163536d26912SBhawanpreet Lakha 	}
163636d26912SBhawanpreet Lakha 	pool->timing_generator_count = i;
163736d26912SBhawanpreet Lakha 
163865e05ca7SJoshua Aberback 	/* PSR */
163965e05ca7SJoshua Aberback 	pool->psr = dmub_psr_create(ctx);
164065e05ca7SJoshua Aberback 	if (pool->psr == NULL) {
164165e05ca7SJoshua Aberback 		dm_error("DC: failed to create psr!\n");
164265e05ca7SJoshua Aberback 		BREAK_TO_DEBUGGER();
164365e05ca7SJoshua Aberback 		goto create_fail;
164465e05ca7SJoshua Aberback 	}
164565e05ca7SJoshua Aberback 
164636d26912SBhawanpreet Lakha 	/* ABMs */
164736d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
164836d26912SBhawanpreet Lakha 		pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
164936d26912SBhawanpreet Lakha 		if (pool->multiple_abms[i] == NULL) {
165036d26912SBhawanpreet Lakha 			dm_error("DC: failed to create abm for pipe %d!\n", i);
165136d26912SBhawanpreet Lakha 			BREAK_TO_DEBUGGER();
165236d26912SBhawanpreet Lakha 			goto create_fail;
165336d26912SBhawanpreet Lakha 		}
165436d26912SBhawanpreet Lakha 	}
165536d26912SBhawanpreet Lakha 
165636d26912SBhawanpreet Lakha 	/* MPC and DSC */
165736d26912SBhawanpreet Lakha 	pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
165836d26912SBhawanpreet Lakha 	if (pool->mpc == NULL) {
165936d26912SBhawanpreet Lakha 		BREAK_TO_DEBUGGER();
166036d26912SBhawanpreet Lakha 		dm_error("DC: failed to create mpc!\n");
166136d26912SBhawanpreet Lakha 		goto create_fail;
166236d26912SBhawanpreet Lakha 	}
166336d26912SBhawanpreet Lakha 
166436d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
166536d26912SBhawanpreet Lakha 		pool->dscs[i] = dcn302_dsc_create(ctx, i);
166636d26912SBhawanpreet Lakha 		if (pool->dscs[i] == NULL) {
166736d26912SBhawanpreet Lakha 			BREAK_TO_DEBUGGER();
166836d26912SBhawanpreet Lakha 			dm_error("DC: failed to create display stream compressor %d!\n", i);
166936d26912SBhawanpreet Lakha 			goto create_fail;
167036d26912SBhawanpreet Lakha 		}
167136d26912SBhawanpreet Lakha 	}
167236d26912SBhawanpreet Lakha 
167336d26912SBhawanpreet Lakha 	/* DWB and MMHUBBUB */
167436d26912SBhawanpreet Lakha 	if (!dcn302_dwbc_create(ctx, pool)) {
167536d26912SBhawanpreet Lakha 		BREAK_TO_DEBUGGER();
167636d26912SBhawanpreet Lakha 		dm_error("DC: failed to create dwbc!\n");
167736d26912SBhawanpreet Lakha 		goto create_fail;
167836d26912SBhawanpreet Lakha 	}
167936d26912SBhawanpreet Lakha 
168036d26912SBhawanpreet Lakha 	if (!dcn302_mmhubbub_create(ctx, pool)) {
168136d26912SBhawanpreet Lakha 		BREAK_TO_DEBUGGER();
168236d26912SBhawanpreet Lakha 		dm_error("DC: failed to create mcif_wb!\n");
168336d26912SBhawanpreet Lakha 		goto create_fail;
168436d26912SBhawanpreet Lakha 	}
168536d26912SBhawanpreet Lakha 
168636d26912SBhawanpreet Lakha 	/* AUX and I2C */
168736d26912SBhawanpreet Lakha 	for (i = 0; i < pool->res_cap->num_ddc; i++) {
168836d26912SBhawanpreet Lakha 		pool->engines[i] = dcn302_aux_engine_create(ctx, i);
168936d26912SBhawanpreet Lakha 		if (pool->engines[i] == NULL) {
169036d26912SBhawanpreet Lakha 			BREAK_TO_DEBUGGER();
169136d26912SBhawanpreet Lakha 			dm_error("DC:failed to create aux engine!!\n");
169236d26912SBhawanpreet Lakha 			goto create_fail;
169336d26912SBhawanpreet Lakha 		}
169436d26912SBhawanpreet Lakha 		pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
169536d26912SBhawanpreet Lakha 		if (pool->hw_i2cs[i] == NULL) {
169636d26912SBhawanpreet Lakha 			BREAK_TO_DEBUGGER();
169736d26912SBhawanpreet Lakha 			dm_error("DC:failed to create hw i2c!!\n");
169836d26912SBhawanpreet Lakha 			goto create_fail;
169936d26912SBhawanpreet Lakha 		}
170036d26912SBhawanpreet Lakha 		pool->sw_i2cs[i] = NULL;
170136d26912SBhawanpreet Lakha 	}
170236d26912SBhawanpreet Lakha 
170336d26912SBhawanpreet Lakha 	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
170436d26912SBhawanpreet Lakha 	if (!resource_construct(num_virtual_links, dc, pool,
170536d26912SBhawanpreet Lakha 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
170636d26912SBhawanpreet Lakha 					&res_create_funcs : &res_create_maximus_funcs)))
170736d26912SBhawanpreet Lakha 		goto create_fail;
170836d26912SBhawanpreet Lakha 
170936d26912SBhawanpreet Lakha 	/* HW Sequencer and Plane caps */
171036d26912SBhawanpreet Lakha 	dcn302_hw_sequencer_construct(dc);
171136d26912SBhawanpreet Lakha 
171236d26912SBhawanpreet Lakha 	dc->caps.max_planes =  pool->pipe_count;
171336d26912SBhawanpreet Lakha 
171436d26912SBhawanpreet Lakha 	for (i = 0; i < dc->caps.max_planes; ++i)
171536d26912SBhawanpreet Lakha 		dc->caps.planes[i] = plane_cap;
171636d26912SBhawanpreet Lakha 
171736d26912SBhawanpreet Lakha 	dc->cap_funcs = cap_funcs;
171836d26912SBhawanpreet Lakha 
171936d26912SBhawanpreet Lakha 	return true;
172036d26912SBhawanpreet Lakha 
172136d26912SBhawanpreet Lakha create_fail:
172236d26912SBhawanpreet Lakha 
172336d26912SBhawanpreet Lakha 	dcn302_resource_destruct(pool);
172436d26912SBhawanpreet Lakha 
172536d26912SBhawanpreet Lakha 	return false;
172636d26912SBhawanpreet Lakha }
172736d26912SBhawanpreet Lakha 
172836d26912SBhawanpreet Lakha struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
172936d26912SBhawanpreet Lakha {
173036d26912SBhawanpreet Lakha 	struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
173136d26912SBhawanpreet Lakha 
173236d26912SBhawanpreet Lakha 	if (!pool)
173336d26912SBhawanpreet Lakha 		return NULL;
173436d26912SBhawanpreet Lakha 
173536d26912SBhawanpreet Lakha 	if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
173636d26912SBhawanpreet Lakha 		return pool;
173736d26912SBhawanpreet Lakha 
173836d26912SBhawanpreet Lakha 	BREAK_TO_DEBUGGER();
173936d26912SBhawanpreet Lakha 	kfree(pool);
174036d26912SBhawanpreet Lakha 	return NULL;
174136d26912SBhawanpreet Lakha }
1742