1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dcn10/dcn10_hubp.h"
27 #include "dcn21_hubp.h"
28 
29 #include "dm_services.h"
30 #include "reg_helper.h"
31 
32 #include "dc_dmub_srv.h"
33 
34 #define DC_LOGGER_INIT(logger)
35 
36 #define REG(reg)\
37 	hubp21->hubp_regs->reg
38 
39 #define CTX \
40 	hubp21->base.ctx
41 
42 #undef FN
43 #define FN(reg_name, field_name) \
44 	hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name
45 
46 /*
47  * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL.
48  * As a result, if S/W updates any of these registers during a mode change,
49  * the current frame before the mode change will use the new value right away
50  * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior.
51  *
52  * REFCYC_PER_VM_GROUP_FLIP[22:0]
53  * REFCYC_PER_VM_GROUP_VBLANK[22:0]
54  * REFCYC_PER_VM_REQ_FLIP[22:0]
55  * REFCYC_PER_VM_REQ_VBLANK[22:0]
56  *
57  * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated
58  * when flipping to a new surface
59  *
60  * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated
61  * during prefetch  period of a frame. The prefetch starts at a pre-determined
62  * number of lines before the display active per frame
63  *
64  * DCN may underflow due to incorrectly programming these registers
65  * during VM stage of prefetch/iflip. First lines of display active
66  * or a sub-region of active using a new surface will be corrupted
67  * until the VM data returns at flip/mode change transitions
68  *
69  * Work around:
70  * workaround is always opt to use the more aggressive settings.
71  * On any mode switch, if the new reg values are smaller than the current values,
72  * then update the regs with the new values.
73  *
74  * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142
75  *
76  */
77 void apply_DEDCN21_142_wa_for_hostvm_deadline(
78 		struct hubp *hubp,
79 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
80 {
81 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
82 	uint32_t cur_value;
83 
84 	REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
85 	if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
86 		REG_SET(VBLANK_PARAMETERS_5, 0,
87 				REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank);
88 
89 	REG_GET(VBLANK_PARAMETERS_6,
90 			REFCYC_PER_VM_REQ_VBLANK,
91 			&cur_value);
92 	if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
93 		REG_SET(VBLANK_PARAMETERS_6, 0,
94 				REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank);
95 
96 	REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
97 	if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
98 		REG_SET(FLIP_PARAMETERS_3, 0,
99 				REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip);
100 
101 	REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
102 	if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
103 		REG_SET(FLIP_PARAMETERS_4, 0,
104 					REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip);
105 
106 	REG_SET(FLIP_PARAMETERS_5, 0,
107 			REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c);
108 	REG_SET(FLIP_PARAMETERS_6, 0,
109 			REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c);
110 }
111 
112 void hubp21_program_deadline(
113 		struct hubp *hubp,
114 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
115 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
116 {
117 	hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
118 
119 	apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);
120 }
121 
122 void hubp21_program_requestor(
123 		struct hubp *hubp,
124 		struct _vcs_dpi_display_rq_regs_st *rq_regs)
125 {
126 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
127 
128 	REG_UPDATE(HUBPRET_CONTROL,
129 			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
130 	REG_SET_4(DCN_EXPANSION_MODE, 0,
131 			DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
132 			PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
133 			MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
134 			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
135 	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
136 		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
137 		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
138 		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
139 		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
140 		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
141 		VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
142 		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
143 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
144 	REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0,
145 		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
146 		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
147 		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
148 		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
149 		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
150 		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
151 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
152 }
153 
154 static void hubp21_setup(
155 		struct hubp *hubp,
156 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
157 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
158 		struct _vcs_dpi_display_rq_regs_st *rq_regs,
159 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
160 {
161 	/* otg is locked when this func is called. Register are double buffered.
162 	 * disable the requestors is not needed
163 	 */
164 
165 	hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
166 	hubp21_program_requestor(hubp, rq_regs);
167 	hubp21_program_deadline(hubp, dlg_attr, ttu_attr);
168 
169 }
170 
171 void hubp21_set_viewport(
172 	struct hubp *hubp,
173 	const struct rect *viewport,
174 	const struct rect *viewport_c)
175 {
176 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
177 
178 	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
179 		  PRI_VIEWPORT_WIDTH, viewport->width,
180 		  PRI_VIEWPORT_HEIGHT, viewport->height);
181 
182 	REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
183 		  PRI_VIEWPORT_X_START, viewport->x,
184 		  PRI_VIEWPORT_Y_START, viewport->y);
185 
186 	/*for stereo*/
187 	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
188 		  SEC_VIEWPORT_WIDTH, viewport->width,
189 		  SEC_VIEWPORT_HEIGHT, viewport->height);
190 
191 	REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
192 		  SEC_VIEWPORT_X_START, viewport->x,
193 		  SEC_VIEWPORT_Y_START, viewport->y);
194 
195 	/* DC supports NV12 only at the moment */
196 	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
197 		  PRI_VIEWPORT_WIDTH_C, viewport_c->width,
198 		  PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
199 
200 	REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
201 		  PRI_VIEWPORT_X_START_C, viewport_c->x,
202 		  PRI_VIEWPORT_Y_START_C, viewport_c->y);
203 
204 	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
205 		  SEC_VIEWPORT_WIDTH_C, viewport_c->width,
206 		  SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
207 
208 	REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
209 		  SEC_VIEWPORT_X_START_C, viewport_c->x,
210 		  SEC_VIEWPORT_Y_START_C, viewport_c->y);
211 }
212 
213 static void hubp21_apply_PLAT_54186_wa(
214 		struct hubp *hubp,
215 		const struct dc_plane_address *address)
216 {
217 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
218 	struct dc_debug_options *debug = &hubp->ctx->dc->debug;
219 	unsigned int chroma_bpe = 2;
220 	unsigned int luma_addr_high_part = 0;
221 	unsigned int row_height = 0;
222 	unsigned int chroma_pitch = 0;
223 	unsigned int viewport_c_height = 0;
224 	unsigned int viewport_c_width = 0;
225 	unsigned int patched_viewport_height = 0;
226 	unsigned int patched_viewport_width = 0;
227 	unsigned int rotation_angle = 0;
228 	unsigned int pix_format = 0;
229 	unsigned int h_mirror_en = 0;
230 	unsigned int tile_blk_size = 64 * 1024; /* 64KB for 64KB SW, 4KB for 4KB SW */
231 
232 
233 	if (!debug->nv12_iflip_vm_wa)
234 		return;
235 
236 	REG_GET(DCHUBP_REQ_SIZE_CONFIG_C,
237 		PTE_ROW_HEIGHT_LINEAR_C, &row_height);
238 
239 	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C,
240 			PRI_VIEWPORT_WIDTH_C, &viewport_c_width,
241 			PRI_VIEWPORT_HEIGHT_C, &viewport_c_height);
242 
243 	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,
244 			PRIMARY_SURFACE_ADDRESS_HIGH_C, &luma_addr_high_part);
245 
246 	REG_GET(DCSURF_SURFACE_PITCH_C,
247 			PITCH_C, &chroma_pitch);
248 
249 	chroma_pitch += 1;
250 
251 	REG_GET_3(DCSURF_SURFACE_CONFIG,
252 			SURFACE_PIXEL_FORMAT, &pix_format,
253 			ROTATION_ANGLE, &rotation_angle,
254 			H_MIRROR_EN, &h_mirror_en);
255 
256 	/* reset persistent cached data */
257 	hubp21->PLAT_54186_wa_chroma_addr_offset = 0;
258 	/* apply wa only for NV12 surface with scatter gather enabled with viewport > 512 along
259 	 * the vertical direction*/
260 	if (address->type != PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||
261 			address->video_progressive.luma_addr.high_part == 0xf4)
262 		return;
263 
264 	if ((rotation_angle == ROTATION_ANGLE_0 || rotation_angle == ROTATION_ANGLE_180)
265 			&& viewport_c_height <= 512)
266 		return;
267 
268 	if ((rotation_angle == ROTATION_ANGLE_90 || rotation_angle == ROTATION_ANGLE_270)
269 				&& viewport_c_width <= 512)
270 		return;
271 
272 	switch (rotation_angle) {
273 	case ROTATION_ANGLE_0: /* 0 degree rotation */
274 		row_height = 128;
275 		patched_viewport_height = (viewport_c_height / row_height + 1) * row_height + 1;
276 		patched_viewport_width = viewport_c_width;
277 		hubp21->PLAT_54186_wa_chroma_addr_offset = 0;
278 		break;
279 	case ROTATION_ANGLE_180: /* 180 degree rotation */
280 		row_height = 128;
281 		patched_viewport_height = viewport_c_height + row_height;
282 		patched_viewport_width = viewport_c_width;
283 		hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - chroma_pitch * row_height * chroma_bpe;
284 		break;
285 	case ROTATION_ANGLE_90: /* 90 degree rotation */
286 		row_height = 256;
287 		if (h_mirror_en) {
288 			patched_viewport_height = viewport_c_height;
289 			patched_viewport_width = viewport_c_width + row_height;
290 			hubp21->PLAT_54186_wa_chroma_addr_offset = 0;
291 		} else {
292 			patched_viewport_height = viewport_c_height;
293 			patched_viewport_width = viewport_c_width + row_height;
294 			hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size;
295 		}
296 		break;
297 	case ROTATION_ANGLE_270: /* 270 degree rotation */
298 		row_height = 256;
299 		if (h_mirror_en) {
300 			patched_viewport_height = viewport_c_height;
301 			patched_viewport_width = viewport_c_width + row_height;
302 			hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size;
303 		} else {
304 			patched_viewport_height = viewport_c_height;
305 			patched_viewport_width = viewport_c_width + row_height;
306 			hubp21->PLAT_54186_wa_chroma_addr_offset = 0;
307 		}
308 		break;
309 	default:
310 		ASSERT(0);
311 		break;
312 	}
313 
314 	/* catch cases where viewport keep growing */
315 	ASSERT(patched_viewport_height && patched_viewport_height < 5000);
316 	ASSERT(patched_viewport_width && patched_viewport_width < 5000);
317 
318 	REG_UPDATE_2(DCSURF_PRI_VIEWPORT_DIMENSION_C,
319 			PRI_VIEWPORT_WIDTH_C, patched_viewport_width,
320 			PRI_VIEWPORT_HEIGHT_C, patched_viewport_height);
321 }
322 
323 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
324 		struct vm_system_aperture_param *apt)
325 {
326 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
327 
328 	PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
329 	PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
330 	PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
331 
332 	// The format of default addr is 48:12 of the 48 bit addr
333 	mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
334 
335 	// The format of high/low are 48:18 of the 48 bit addr
336 	mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
337 	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
338 
339 	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
340 			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
341 
342 	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
343 			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
344 
345 	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
346 			ENABLE_L1_TLB, 1,
347 			SYSTEM_ACCESS_MODE, 0x3);
348 }
349 
350 void hubp21_validate_dml_output(struct hubp *hubp,
351 		struct dc_context *ctx,
352 		struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
353 		struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
354 		struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
355 {
356 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
357 	struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
358 	struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
359 	struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
360 	DC_LOGGER_INIT(ctx->logger);
361 	DC_LOG_DEBUG("DML Validation | Running Validation");
362 
363 	/* Requester - Per hubp */
364 	REG_GET(HUBPRET_CONTROL,
365 		DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
366 	REG_GET_4(DCN_EXPANSION_MODE,
367 		DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
368 		PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
369 		MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
370 		CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
371 	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
372 		CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
373 		MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
374 		META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
375 		MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
376 		DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
377 		VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
378 		SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
379 		PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
380 	REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
381 		CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
382 		MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
383 		META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
384 		MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
385 		DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
386 		SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
387 		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
388 
389 	if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
390 		DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
391 				dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
392 	if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
393 		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
394 				dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
395 	if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
396 		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
397 				dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
398 	if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
399 		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
400 				dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
401 	if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
402 		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
403 				dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
404 
405 	if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
406 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u  Actual: %u\n",
407 				dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
408 	if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
409 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u  Actual: %u\n",
410 				dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
411 	if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
412 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
413 				dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
414 	if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
415 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
416 				dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
417 	if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
418 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
419 				dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
420 	if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
421 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u  Actual: %u\n",
422 				dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
423 	if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
424 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u  Actual: %u\n",
425 				dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
426 	if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
427 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u  Actual: %u\n",
428 				dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
429 
430 	if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
431 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
432 				dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
433 	if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
434 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
435 				dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
436 	if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
437 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
438 				dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
439 	if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
440 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
441 				dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
442 	if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
443 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
444 				dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
445 	if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
446 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u  Actual: %u\n",
447 				dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
448 	if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
449 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u  Actual: %u\n",
450 				dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
451 
452 
453 	/* DLG - Per hubp */
454 	REG_GET_2(BLANK_OFFSET_0,
455 		REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
456 		DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
457 	REG_GET(BLANK_OFFSET_1,
458 		MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
459 	REG_GET(DST_DIMENSIONS,
460 		REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
461 	REG_GET_2(DST_AFTER_SCALER,
462 		REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
463 		DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
464 	REG_GET(REF_FREQ_TO_PIX_FREQ,
465 		REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
466 
467 	if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
468 		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u  Actual: %u\n",
469 				dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
470 	if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
471 		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u  Actual: %u\n",
472 				dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
473 	if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
474 		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u  Actual: %u\n",
475 				dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
476 	if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
477 		DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u  Actual: %u\n",
478 				dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
479 	if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
480 		DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u  Actual: %u\n",
481 				dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
482 	if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
483 		DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u  Actual: %u\n",
484 				dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
485 	if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
486 		DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u  Actual: %u\n",
487 				dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
488 
489 	/* DLG - Per luma/chroma */
490 	REG_GET(VBLANK_PARAMETERS_1,
491 		REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
492 	if (REG(NOM_PARAMETERS_0))
493 		REG_GET(NOM_PARAMETERS_0,
494 			DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
495 	if (REG(NOM_PARAMETERS_1))
496 		REG_GET(NOM_PARAMETERS_1,
497 			REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
498 	REG_GET(NOM_PARAMETERS_4,
499 		DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
500 	REG_GET(NOM_PARAMETERS_5,
501 		REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
502 	REG_GET_2(PER_LINE_DELIVERY,
503 		REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
504 		REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
505 	REG_GET_2(PER_LINE_DELIVERY_PRE,
506 		REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
507 		REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
508 	REG_GET(VBLANK_PARAMETERS_2,
509 		REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
510 	if (REG(NOM_PARAMETERS_2))
511 		REG_GET(NOM_PARAMETERS_2,
512 			DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
513 	if (REG(NOM_PARAMETERS_3))
514 		REG_GET(NOM_PARAMETERS_3,
515 			REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
516 	REG_GET(NOM_PARAMETERS_6,
517 		DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
518 	REG_GET(NOM_PARAMETERS_7,
519 		REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
520 	REG_GET(VBLANK_PARAMETERS_3,
521 			REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
522 	REG_GET(VBLANK_PARAMETERS_4,
523 			REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
524 
525 	if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
526 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u  Actual: %u\n",
527 				dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
528 	if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
529 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u  Actual: %u\n",
530 				dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
531 	if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
532 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u  Actual: %u\n",
533 				dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
534 	if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
535 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u  Actual: %u\n",
536 				dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
537 	if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
538 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u  Actual: %u\n",
539 				dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
540 	if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
541 		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u  Actual: %u\n",
542 				dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
543 	if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
544 		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u  Actual: %u\n",
545 				dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
546 	if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
547 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u  Actual: %u\n",
548 				dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
549 	if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
550 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u  Actual: %u\n",
551 				dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
552 	if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
553 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u  Actual: %u\n",
554 				dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
555 	if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
556 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u  Actual: %u\n",
557 				dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
558 	if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
559 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u  Actual: %u\n",
560 				dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
561 	if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
562 		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u  Actual: %u\n",
563 				dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
564 	if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
565 		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u  Actual: %u\n",
566 				dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
567 	if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
568 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u  Actual: %u\n",
569 				dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
570 	if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
571 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u  Actual: %u\n",
572 				dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
573 
574 	/* TTU - per hubp */
575 	REG_GET_2(DCN_TTU_QOS_WM,
576 		QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
577 		QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
578 
579 	if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
580 		DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u  Actual: %u\n",
581 				dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
582 	if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
583 		DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u  Actual: %u\n",
584 				dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
585 
586 	/* TTU - per luma/chroma */
587 	/* Assumed surf0 is luma and 1 is chroma */
588 	REG_GET_3(DCN_SURF0_TTU_CNTL0,
589 		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
590 		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
591 		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
592 	REG_GET_3(DCN_SURF1_TTU_CNTL0,
593 		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
594 		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
595 		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
596 	REG_GET_3(DCN_CUR0_TTU_CNTL0,
597 		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
598 		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
599 		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
600 	REG_GET(FLIP_PARAMETERS_1,
601 		REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
602 	REG_GET(DCN_CUR0_TTU_CNTL1,
603 			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
604 	REG_GET(DCN_CUR1_TTU_CNTL1,
605 			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
606 	REG_GET(DCN_SURF0_TTU_CNTL1,
607 			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
608 	REG_GET(DCN_SURF1_TTU_CNTL1,
609 			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
610 
611 	if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
612 		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
613 				dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
614 	if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
615 		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
616 				dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
617 	if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
618 		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
619 				dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
620 	if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
621 		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
622 				dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
623 	if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
624 		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
625 				dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
626 	if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
627 		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
628 				dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
629 	if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
630 		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
631 				dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
632 	if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
633 		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
634 				dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
635 	if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
636 		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
637 				dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
638 	if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
639 		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u  Actual: %u\n",
640 				dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
641 	if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
642 		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
643 				dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
644 	if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
645 		DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
646 				dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
647 	if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
648 		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
649 				dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
650 	if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
651 		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
652 				dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
653 
654 	/* Host VM deadline regs */
655 	REG_GET(VBLANK_PARAMETERS_5,
656 		REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank);
657 	REG_GET(VBLANK_PARAMETERS_6,
658 		REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank);
659 	REG_GET(FLIP_PARAMETERS_3,
660 		REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip);
661 	REG_GET(FLIP_PARAMETERS_4,
662 		REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip);
663 	REG_GET(FLIP_PARAMETERS_5,
664 		REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c);
665 	REG_GET(FLIP_PARAMETERS_6,
666 		REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c);
667 	REG_GET(FLIP_PARAMETERS_2,
668 		REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l);
669 
670 	if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank)
671 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u  Actual: %u\n",
672 				dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank);
673 	if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank)
674 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u  Actual: %u\n",
675 				dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank);
676 	if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip)
677 		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u  Actual: %u\n",
678 				dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip);
679 	if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip)
680 		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u  Actual: %u\n",
681 				dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip);
682 	if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c)
683 		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u  Actual: %u\n",
684 				dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c);
685 	if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c)
686 		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u  Actual: %u\n",
687 				dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c);
688 	if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l)
689 		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u  Actual: %u\n",
690 				dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l);
691 }
692 
693 static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs)
694 {
695 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
696 
697 	REG_UPDATE_3(DCSURF_FLIP_CONTROL,
698 					SURFACE_FLIP_TYPE, flip_regs->immediate,
699 					SURFACE_FLIP_MODE_FOR_STEREOSYNC, flip_regs->grph_stereo,
700 					SURFACE_FLIP_IN_STEREOSYNC, flip_regs->grph_stereo);
701 
702 	REG_UPDATE(VMID_SETTINGS_0,
703 				VMID, flip_regs->vmid);
704 
705 	REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
706 			PRIMARY_SURFACE_TMZ, flip_regs->tmz_surface,
707 			PRIMARY_SURFACE_TMZ_C, flip_regs->tmz_surface,
708 			PRIMARY_META_SURFACE_TMZ, flip_regs->tmz_surface,
709 			PRIMARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface,
710 			SECONDARY_SURFACE_TMZ, flip_regs->tmz_surface,
711 			SECONDARY_SURFACE_TMZ_C, flip_regs->tmz_surface,
712 			SECONDARY_META_SURFACE_TMZ, flip_regs->tmz_surface,
713 			SECONDARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface);
714 
715 	REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
716 			PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
717 			flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C);
718 
719 	REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
720 			PRIMARY_META_SURFACE_ADDRESS_C,
721 			flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_C);
722 
723 	REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
724 			PRIMARY_META_SURFACE_ADDRESS_HIGH,
725 			flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH);
726 
727 	REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
728 			PRIMARY_META_SURFACE_ADDRESS,
729 			flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS);
730 
731 	REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
732 			SECONDARY_META_SURFACE_ADDRESS_HIGH,
733 			flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH);
734 
735 	REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
736 			SECONDARY_META_SURFACE_ADDRESS,
737 			flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS);
738 
739 
740 	REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
741 			SECONDARY_SURFACE_ADDRESS_HIGH,
742 			flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH);
743 
744 	REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
745 			SECONDARY_SURFACE_ADDRESS,
746 			flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS);
747 
748 
749 	REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
750 			PRIMARY_SURFACE_ADDRESS_HIGH_C,
751 			flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C);
752 
753 	REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
754 			PRIMARY_SURFACE_ADDRESS_C,
755 			flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C);
756 
757 	REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
758 			PRIMARY_SURFACE_ADDRESS_HIGH,
759 			flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH);
760 
761 	REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
762 			PRIMARY_SURFACE_ADDRESS,
763 			flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS);
764 }
765 
766 void dmcub_PLAT_54186_wa(struct hubp *hubp, struct surface_flip_registers *flip_regs)
767 {
768 	struct dc_dmub_srv *dmcub = hubp->ctx->dmub_srv;
769 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
770 	struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa = { 0 };
771 
772 	PLAT_54186_wa.header.type = DMUB_CMD__PLAT_54186_WA;
773 	PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS;
774 	PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C;
775 	PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
776 	PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
777 	PLAT_54186_wa.flip.flip_params.grph_stereo = flip_regs->grph_stereo;
778 	PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst;
779 	PLAT_54186_wa.flip.flip_params.immediate = flip_regs->immediate;
780 	PLAT_54186_wa.flip.flip_params.tmz_surface = flip_regs->tmz_surface;
781 	PLAT_54186_wa.flip.flip_params.vmid = flip_regs->vmid;
782 
783 	PERF_TRACE();  // TODO: remove after performance is stable.
784 	dc_dmub_srv_cmd_queue(dmcub, &PLAT_54186_wa.header);
785 	PERF_TRACE();  // TODO: remove after performance is stable.
786 	dc_dmub_srv_cmd_execute(dmcub);
787 	PERF_TRACE();  // TODO: remove after performance is stable.
788 	dc_dmub_srv_wait_idle(dmcub);
789 	PERF_TRACE();  // TODO: remove after performance is stable.
790 }
791 
792 bool hubp21_program_surface_flip_and_addr(
793 		struct hubp *hubp,
794 		const struct dc_plane_address *address,
795 		bool flip_immediate)
796 {
797 	struct dc_debug_options *debug = &hubp->ctx->dc->debug;
798 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
799 	struct surface_flip_registers flip_regs = { 0 };
800 
801 	flip_regs.vmid = address->vmid;
802 
803 	switch (address->type) {
804 	case PLN_ADDR_TYPE_GRAPHICS:
805 		if (address->grph.addr.quad_part == 0) {
806 			BREAK_TO_DEBUGGER();
807 			break;
808 		}
809 
810 		if (address->grph.meta_addr.quad_part != 0) {
811 			flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS =
812 					address->grph.meta_addr.low_part;
813 			flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH =
814 					address->grph.meta_addr.high_part;
815 		}
816 
817 		flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS =
818 				address->grph.addr.low_part;
819 		flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
820 				address->grph.addr.high_part;
821 		break;
822 	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
823 		if (address->video_progressive.luma_addr.quad_part == 0
824 				|| address->video_progressive.chroma_addr.quad_part == 0)
825 			break;
826 
827 		if (address->video_progressive.luma_meta_addr.quad_part != 0) {
828 			flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS =
829 					address->video_progressive.luma_meta_addr.low_part;
830 			flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH =
831 					address->video_progressive.luma_meta_addr.high_part;
832 
833 			flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C =
834 					address->video_progressive.chroma_meta_addr.low_part;
835 			flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C =
836 					address->video_progressive.chroma_meta_addr.high_part;
837 		}
838 
839 		flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS =
840 				address->video_progressive.luma_addr.low_part;
841 		flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
842 				address->video_progressive.luma_addr.high_part;
843 
844 		if (debug->nv12_iflip_vm_wa) {
845 			flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C =
846 					address->video_progressive.chroma_addr.low_part + hubp21->PLAT_54186_wa_chroma_addr_offset;
847 		} else
848 			flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C =
849 					address->video_progressive.chroma_addr.low_part;
850 
851 		flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C =
852 				address->video_progressive.chroma_addr.high_part;
853 
854 		break;
855 	case PLN_ADDR_TYPE_GRPH_STEREO:
856 		if (address->grph_stereo.left_addr.quad_part == 0)
857 			break;
858 		if (address->grph_stereo.right_addr.quad_part == 0)
859 			break;
860 
861 		flip_regs.grph_stereo = true;
862 
863 		if (address->grph_stereo.right_meta_addr.quad_part != 0) {
864 			flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS =
865 					address->grph_stereo.right_meta_addr.low_part;
866 			flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH =
867 					address->grph_stereo.right_meta_addr.high_part;
868 		}
869 
870 		if (address->grph_stereo.left_meta_addr.quad_part != 0) {
871 			flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS =
872 					address->grph_stereo.left_meta_addr.low_part;
873 			flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH =
874 					address->grph_stereo.left_meta_addr.high_part;
875 		}
876 
877 		flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS =
878 				address->grph_stereo.left_addr.low_part;
879 		flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
880 				address->grph_stereo.left_addr.high_part;
881 
882 		flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS =
883 				address->grph_stereo.right_addr.low_part;
884 		flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH =
885 				address->grph_stereo.right_addr.high_part;
886 
887 		break;
888 	default:
889 		BREAK_TO_DEBUGGER();
890 		break;
891 	}
892 
893 	flip_regs.tmz_surface = address->tmz_surface;
894 	flip_regs.immediate = flip_immediate;
895 
896 	if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
897 		dmcub_PLAT_54186_wa(hubp, &flip_regs);
898 	else
899 		program_surface_flip_and_addr(hubp, &flip_regs);
900 
901 	hubp->request_address = *address;
902 
903 	return true;
904 }
905 
906 void hubp21_init(struct hubp *hubp)
907 {
908 	// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
909 	// This is a chicken bit to enable the ECO fix.
910 
911 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
912 	//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
913 	REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
914 }
915 static struct hubp_funcs dcn21_hubp_funcs = {
916 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
917 	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
918 	.hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr,
919 	.hubp_program_surface_config = hubp1_program_surface_config,
920 	.hubp_is_flip_pending = hubp1_is_flip_pending,
921 	.hubp_setup = hubp21_setup,
922 	.hubp_setup_interdependent = hubp2_setup_interdependent,
923 	.hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
924 	.set_blank = hubp1_set_blank,
925 	.dcc_control = hubp1_dcc_control,
926 	.mem_program_viewport = hubp21_set_viewport,
927 	.apply_PLAT_54186_wa = hubp21_apply_PLAT_54186_wa,
928 	.set_cursor_attributes	= hubp2_cursor_set_attributes,
929 	.set_cursor_position	= hubp1_cursor_set_position,
930 	.hubp_clk_cntl = hubp1_clk_cntl,
931 	.hubp_vtg_sel = hubp1_vtg_sel,
932 	.dmdata_set_attributes = hubp2_dmdata_set_attributes,
933 	.dmdata_load = hubp2_dmdata_load,
934 	.dmdata_status_done = hubp2_dmdata_status_done,
935 	.hubp_read_state = hubp1_read_state,
936 	.hubp_clear_underflow = hubp1_clear_underflow,
937 	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
938 	.hubp_init = hubp21_init,
939 	.validate_dml_output = hubp21_validate_dml_output,
940 };
941 
942 bool hubp21_construct(
943 	struct dcn21_hubp *hubp21,
944 	struct dc_context *ctx,
945 	uint32_t inst,
946 	const struct dcn_hubp2_registers *hubp_regs,
947 	const struct dcn_hubp2_shift *hubp_shift,
948 	const struct dcn_hubp2_mask *hubp_mask)
949 {
950 	hubp21->base.funcs = &dcn21_hubp_funcs;
951 	hubp21->base.ctx = ctx;
952 	hubp21->hubp_regs = hubp_regs;
953 	hubp21->hubp_shift = hubp_shift;
954 	hubp21->hubp_mask = hubp_mask;
955 	hubp21->base.inst = inst;
956 	hubp21->base.opp_id = OPP_ID_INVALID;
957 	hubp21->base.mpcc_id = 0xf;
958 
959 	return true;
960 }
961