1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dcn10/dcn10_hubp.h"
27 #include "dcn21_hubp.h"
28 
29 #include "dm_services.h"
30 #include "reg_helper.h"
31 
32 #define REG(reg)\
33 	hubp21->hubp_regs->reg
34 
35 #define CTX \
36 	hubp21->base.ctx
37 
38 #undef FN
39 #define FN(reg_name, field_name) \
40 	hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name
41 
42 /*
43  * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL.
44  * As a result, if S/W updates any of these registers during a mode change,
45  * the current frame before the mode change will use the new value right away
46  * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior.
47  *
48  * REFCYC_PER_VM_GROUP_FLIP[22:0]
49  * REFCYC_PER_VM_GROUP_VBLANK[22:0]
50  * REFCYC_PER_VM_REQ_FLIP[22:0]
51  * REFCYC_PER_VM_REQ_VBLANK[22:0]
52  *
53  * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated
54  * when flipping to a new surface
55  *
56  * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated
57  * during prefetch  period of a frame. The prefetch starts at a pre-determined
58  * number of lines before the display active per frame
59  *
60  * DCN may underflow due to incorrectly programming these registers
61  * during VM stage of prefetch/iflip. First lines of display active
62  * or a sub-region of active using a new surface will be corrupted
63  * until the VM data returns at flip/mode change transitions
64  *
65  * Work around:
66  * workaround is always opt to use the more aggressive settings.
67  * On any mode switch, if the new reg values are smaller than the current values,
68  * then update the regs with the new values.
69  *
70  * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142
71  *
72  */
73 void apply_DEDCN21_142_wa_for_hostvm_deadline(
74 		struct hubp *hubp,
75 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
76 {
77 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
78 	uint32_t cur_value;
79 
80 	REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
81 	if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
82 		REG_SET(VBLANK_PARAMETERS_5, 0,
83 				REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank);
84 
85 	REG_GET(VBLANK_PARAMETERS_6,
86 			REFCYC_PER_VM_REQ_VBLANK,
87 			&cur_value);
88 	if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
89 		REG_SET(VBLANK_PARAMETERS_6, 0,
90 				REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank);
91 
92 	REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
93 	if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
94 		REG_SET(FLIP_PARAMETERS_3, 0,
95 				REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip);
96 
97 	REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
98 	if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
99 		REG_SET(FLIP_PARAMETERS_4, 0,
100 					REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip);
101 
102 	REG_SET(FLIP_PARAMETERS_5, 0,
103 			REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c);
104 	REG_SET(FLIP_PARAMETERS_6, 0,
105 			REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c);
106 }
107 
108 void hubp21_program_deadline(
109 		struct hubp *hubp,
110 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
111 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
112 {
113 	hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
114 
115 	apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);
116 }
117 
118 void hubp21_program_requestor(
119 		struct hubp *hubp,
120 		struct _vcs_dpi_display_rq_regs_st *rq_regs)
121 {
122 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
123 
124 	REG_UPDATE(HUBPRET_CONTROL,
125 			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
126 	REG_SET_4(DCN_EXPANSION_MODE, 0,
127 			DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
128 			PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
129 			MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
130 			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
131 	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
132 		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
133 		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
134 		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
135 		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
136 		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
137 		VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
138 		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
139 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
140 	REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0,
141 		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
142 		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
143 		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
144 		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
145 		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
146 		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
147 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
148 }
149 
150 static void hubp21_setup(
151 		struct hubp *hubp,
152 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
153 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
154 		struct _vcs_dpi_display_rq_regs_st *rq_regs,
155 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
156 {
157 	/* otg is locked when this func is called. Register are double buffered.
158 	 * disable the requestors is not needed
159 	 */
160 
161 	hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
162 	hubp21_program_requestor(hubp, rq_regs);
163 	hubp21_program_deadline(hubp, dlg_attr, ttu_attr);
164 
165 }
166 
167 void hubp21_set_viewport(
168 	struct hubp *hubp,
169 	const struct rect *viewport,
170 	const struct rect *viewport_c)
171 {
172 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
173 	int patched_viewport_height = 0;
174 	struct dc_debug_options *debug = &hubp->ctx->dc->debug;
175 
176 	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
177 		  PRI_VIEWPORT_WIDTH, viewport->width,
178 		  PRI_VIEWPORT_HEIGHT, viewport->height);
179 
180 	REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
181 		  PRI_VIEWPORT_X_START, viewport->x,
182 		  PRI_VIEWPORT_Y_START, viewport->y);
183 
184 	/*for stereo*/
185 	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
186 		  SEC_VIEWPORT_WIDTH, viewport->width,
187 		  SEC_VIEWPORT_HEIGHT, viewport->height);
188 
189 	REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
190 		  SEC_VIEWPORT_X_START, viewport->x,
191 		  SEC_VIEWPORT_Y_START, viewport->y);
192 
193 	/*
194 	 *	Work around for underflow issue with NV12 + rIOMMU translation
195 	 *	+ immediate flip. This will cause hubp underflow, but will not
196 	 *	be user visible since underflow is in blank region
197 	 */
198 	patched_viewport_height = viewport_c->height;
199 	if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa) {
200 		int pte_row_height = 0;
201 		int pte_rows = 0;
202 
203 		REG_GET(DCHUBP_REQ_SIZE_CONFIG_C,
204 			PTE_ROW_HEIGHT_LINEAR_C, &pte_row_height);
205 
206 		pte_row_height = 1 << (pte_row_height + 3);
207 		pte_rows = (viewport_c->height / pte_row_height) + 1;
208 		patched_viewport_height = pte_rows * pte_row_height + 1;
209 	}
210 
211 
212 	/* DC supports NV12 only at the moment */
213 	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
214 		  PRI_VIEWPORT_WIDTH_C, viewport_c->width,
215 		  PRI_VIEWPORT_HEIGHT_C, patched_viewport_height);
216 
217 	REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
218 		  PRI_VIEWPORT_X_START_C, viewport_c->x,
219 		  PRI_VIEWPORT_Y_START_C, viewport_c->y);
220 
221 	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
222 		  SEC_VIEWPORT_WIDTH_C, viewport_c->width,
223 		  SEC_VIEWPORT_HEIGHT_C, patched_viewport_height);
224 
225 	REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
226 		  SEC_VIEWPORT_X_START_C, viewport_c->x,
227 		  SEC_VIEWPORT_Y_START_C, viewport_c->y);
228 }
229 
230 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
231 		struct vm_system_aperture_param *apt)
232 {
233 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
234 
235 	PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
236 	PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
237 	PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
238 
239 	// The format of default addr is 48:12 of the 48 bit addr
240 	mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
241 
242 	// The format of high/low are 48:18 of the 48 bit addr
243 	mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
244 	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
245 
246 	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
247 			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
248 
249 	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
250 			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
251 
252 	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
253 			ENABLE_L1_TLB, 1,
254 			SYSTEM_ACCESS_MODE, 0x3);
255 }
256 
257 void hubp21_init(struct hubp *hubp)
258 {
259 	// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
260 	// This is a chicken bit to enable the ECO fix.
261 
262 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
263 	//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
264 	REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
265 }
266 static struct hubp_funcs dcn21_hubp_funcs = {
267 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
268 	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
269 	.hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
270 	.hubp_program_surface_config = hubp1_program_surface_config,
271 	.hubp_is_flip_pending = hubp1_is_flip_pending,
272 	.hubp_setup = hubp21_setup,
273 	.hubp_setup_interdependent = hubp2_setup_interdependent,
274 	.hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
275 	.set_blank = hubp1_set_blank,
276 	.dcc_control = hubp1_dcc_control,
277 	.mem_program_viewport = hubp21_set_viewport,
278 	.set_cursor_attributes	= hubp2_cursor_set_attributes,
279 	.set_cursor_position	= hubp1_cursor_set_position,
280 	.hubp_clk_cntl = hubp1_clk_cntl,
281 	.hubp_vtg_sel = hubp1_vtg_sel,
282 	.dmdata_set_attributes = hubp2_dmdata_set_attributes,
283 	.dmdata_load = hubp2_dmdata_load,
284 	.dmdata_status_done = hubp2_dmdata_status_done,
285 	.hubp_read_state = hubp1_read_state,
286 	.hubp_clear_underflow = hubp1_clear_underflow,
287 	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
288 	.hubp_init = hubp21_init,
289 };
290 
291 bool hubp21_construct(
292 	struct dcn21_hubp *hubp21,
293 	struct dc_context *ctx,
294 	uint32_t inst,
295 	const struct dcn_hubp2_registers *hubp_regs,
296 	const struct dcn_hubp2_shift *hubp_shift,
297 	const struct dcn_hubp2_mask *hubp_mask)
298 {
299 	hubp21->base.funcs = &dcn21_hubp_funcs;
300 	hubp21->base.ctx = ctx;
301 	hubp21->hubp_regs = hubp_regs;
302 	hubp21->hubp_shift = hubp_shift;
303 	hubp21->hubp_mask = hubp_mask;
304 	hubp21->base.inst = inst;
305 	hubp21->base.opp_id = OPP_ID_INVALID;
306 	hubp21->base.mpcc_id = 0xf;
307 
308 	return true;
309 }
310