1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn10/dcn10_hubp.h" 27 #include "dcn21_hubp.h" 28 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 32 #define DC_LOGGER_INIT(logger) 33 34 #define REG(reg)\ 35 hubp21->hubp_regs->reg 36 37 #define CTX \ 38 hubp21->base.ctx 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 43 44 /* 45 * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 46 * As a result, if S/W updates any of these registers during a mode change, 47 * the current frame before the mode change will use the new value right away 48 * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 49 * 50 * REFCYC_PER_VM_GROUP_FLIP[22:0] 51 * REFCYC_PER_VM_GROUP_VBLANK[22:0] 52 * REFCYC_PER_VM_REQ_FLIP[22:0] 53 * REFCYC_PER_VM_REQ_VBLANK[22:0] 54 * 55 * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 56 * when flipping to a new surface 57 * 58 * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 59 * during prefetch period of a frame. The prefetch starts at a pre-determined 60 * number of lines before the display active per frame 61 * 62 * DCN may underflow due to incorrectly programming these registers 63 * during VM stage of prefetch/iflip. First lines of display active 64 * or a sub-region of active using a new surface will be corrupted 65 * until the VM data returns at flip/mode change transitions 66 * 67 * Work around: 68 * workaround is always opt to use the more aggressive settings. 69 * On any mode switch, if the new reg values are smaller than the current values, 70 * then update the regs with the new values. 71 * 72 * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 73 * 74 */ 75 void apply_DEDCN21_142_wa_for_hostvm_deadline( 76 struct hubp *hubp, 77 struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 78 { 79 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 80 uint32_t cur_value; 81 82 REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); 83 if (cur_value > dlg_attr->refcyc_per_vm_group_vblank) 84 REG_SET(VBLANK_PARAMETERS_5, 0, 85 REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 86 87 REG_GET(VBLANK_PARAMETERS_6, 88 REFCYC_PER_VM_REQ_VBLANK, 89 &cur_value); 90 if (cur_value > dlg_attr->refcyc_per_vm_req_vblank) 91 REG_SET(VBLANK_PARAMETERS_6, 0, 92 REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 93 94 REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); 95 if (cur_value > dlg_attr->refcyc_per_vm_group_flip) 96 REG_SET(FLIP_PARAMETERS_3, 0, 97 REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 98 99 REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); 100 if (cur_value > dlg_attr->refcyc_per_vm_req_flip) 101 REG_SET(FLIP_PARAMETERS_4, 0, 102 REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 103 104 REG_SET(FLIP_PARAMETERS_5, 0, 105 REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 106 REG_SET(FLIP_PARAMETERS_6, 0, 107 REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 108 } 109 110 void hubp21_program_deadline( 111 struct hubp *hubp, 112 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 113 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 114 { 115 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 116 117 apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 118 } 119 120 void hubp21_program_requestor( 121 struct hubp *hubp, 122 struct _vcs_dpi_display_rq_regs_st *rq_regs) 123 { 124 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 125 126 REG_UPDATE(HUBPRET_CONTROL, 127 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 128 REG_SET_4(DCN_EXPANSION_MODE, 0, 129 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 130 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 131 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 132 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 133 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 134 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 135 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 136 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 137 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 138 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 139 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 140 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 141 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 142 REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 143 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 144 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 145 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 146 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 147 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 148 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 149 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 150 } 151 152 static void hubp21_setup( 153 struct hubp *hubp, 154 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 155 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 156 struct _vcs_dpi_display_rq_regs_st *rq_regs, 157 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 158 { 159 /* otg is locked when this func is called. Register are double buffered. 160 * disable the requestors is not needed 161 */ 162 163 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 164 hubp21_program_requestor(hubp, rq_regs); 165 hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 166 167 } 168 169 void hubp21_set_viewport( 170 struct hubp *hubp, 171 const struct rect *viewport, 172 const struct rect *viewport_c) 173 { 174 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 175 int patched_viewport_height = 0; 176 struct dc_debug_options *debug = &hubp->ctx->dc->debug; 177 178 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 179 PRI_VIEWPORT_WIDTH, viewport->width, 180 PRI_VIEWPORT_HEIGHT, viewport->height); 181 182 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 183 PRI_VIEWPORT_X_START, viewport->x, 184 PRI_VIEWPORT_Y_START, viewport->y); 185 186 /*for stereo*/ 187 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 188 SEC_VIEWPORT_WIDTH, viewport->width, 189 SEC_VIEWPORT_HEIGHT, viewport->height); 190 191 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 192 SEC_VIEWPORT_X_START, viewport->x, 193 SEC_VIEWPORT_Y_START, viewport->y); 194 195 /* 196 * Work around for underflow issue with NV12 + rIOMMU translation 197 * + immediate flip. This will cause hubp underflow, but will not 198 * be user visible since underflow is in blank region 199 */ 200 patched_viewport_height = viewport_c->height; 201 if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa) { 202 int pte_row_height = 0; 203 int pte_rows = 0; 204 205 REG_GET(DCHUBP_REQ_SIZE_CONFIG_C, 206 PTE_ROW_HEIGHT_LINEAR_C, &pte_row_height); 207 208 pte_row_height = 1 << (pte_row_height + 3); 209 pte_rows = (viewport_c->height / pte_row_height) + 1; 210 patched_viewport_height = pte_rows * pte_row_height + 1; 211 } 212 213 214 /* DC supports NV12 only at the moment */ 215 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 216 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 217 PRI_VIEWPORT_HEIGHT_C, patched_viewport_height); 218 219 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 220 PRI_VIEWPORT_X_START_C, viewport_c->x, 221 PRI_VIEWPORT_Y_START_C, viewport_c->y); 222 223 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 224 SEC_VIEWPORT_WIDTH_C, viewport_c->width, 225 SEC_VIEWPORT_HEIGHT_C, patched_viewport_height); 226 227 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 228 SEC_VIEWPORT_X_START_C, viewport_c->x, 229 SEC_VIEWPORT_Y_START_C, viewport_c->y); 230 } 231 232 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 233 struct vm_system_aperture_param *apt) 234 { 235 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 236 237 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 238 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 239 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 240 241 // The format of default addr is 48:12 of the 48 bit addr 242 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 243 244 // The format of high/low are 48:18 of the 48 bit addr 245 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 246 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 247 248 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 249 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 250 251 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 252 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 253 254 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 255 ENABLE_L1_TLB, 1, 256 SYSTEM_ACCESS_MODE, 0x3); 257 } 258 259 void hubp21_validate_dml_output(struct hubp *hubp, 260 struct dc_context *ctx, 261 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 262 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 263 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 264 { 265 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 266 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 267 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 268 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 269 DC_LOGGER_INIT(ctx->logger); 270 271 /* Requester - Per hubp */ 272 REG_GET(HUBPRET_CONTROL, 273 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 274 REG_GET_4(DCN_EXPANSION_MODE, 275 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 276 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 277 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 278 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 279 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 280 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 281 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 282 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 283 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 284 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 285 VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 286 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 287 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 288 REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, 289 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 290 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 291 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 292 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 293 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 294 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 295 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 296 297 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 298 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 299 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 300 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 301 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 302 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 303 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 304 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 305 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 306 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 307 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 308 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 309 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 310 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 311 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 312 313 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 314 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 315 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 316 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 317 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 318 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 319 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 320 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 321 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 322 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 323 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 324 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 325 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 326 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 327 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 328 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 329 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", 330 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 331 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 332 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 333 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 334 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 335 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 336 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 337 338 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 339 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 340 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 341 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 342 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 343 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 344 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 345 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 346 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 347 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 348 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 349 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 350 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 351 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 352 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 353 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 354 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 355 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 356 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 357 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 358 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 359 360 361 /* DLG - Per hubp */ 362 REG_GET_2(BLANK_OFFSET_0, 363 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 364 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 365 REG_GET(BLANK_OFFSET_1, 366 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 367 REG_GET(DST_DIMENSIONS, 368 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 369 REG_GET_2(DST_AFTER_SCALER, 370 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 371 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 372 REG_GET(REF_FREQ_TO_PIX_FREQ, 373 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 374 375 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 376 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 377 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 378 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 379 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 380 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 381 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 382 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 383 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 384 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 385 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 386 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 387 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 388 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 389 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 390 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 391 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 392 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 393 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 394 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 395 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 396 397 /* DLG - Per luma/chroma */ 398 REG_GET(VBLANK_PARAMETERS_1, 399 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 400 if (REG(NOM_PARAMETERS_0)) 401 REG_GET(NOM_PARAMETERS_0, 402 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 403 if (REG(NOM_PARAMETERS_1)) 404 REG_GET(NOM_PARAMETERS_1, 405 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 406 REG_GET(NOM_PARAMETERS_4, 407 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 408 REG_GET(NOM_PARAMETERS_5, 409 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 410 REG_GET_2(PER_LINE_DELIVERY, 411 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 412 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 413 REG_GET_2(PER_LINE_DELIVERY_PRE, 414 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 415 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 416 REG_GET(VBLANK_PARAMETERS_2, 417 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 418 if (REG(NOM_PARAMETERS_2)) 419 REG_GET(NOM_PARAMETERS_2, 420 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 421 if (REG(NOM_PARAMETERS_3)) 422 REG_GET(NOM_PARAMETERS_3, 423 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 424 REG_GET(NOM_PARAMETERS_6, 425 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 426 REG_GET(NOM_PARAMETERS_7, 427 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 428 REG_GET(VBLANK_PARAMETERS_3, 429 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 430 REG_GET(VBLANK_PARAMETERS_4, 431 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 432 433 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 434 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 435 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 436 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 437 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 438 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 439 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 440 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 441 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 442 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 443 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 444 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 445 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 446 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 447 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 448 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 449 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 450 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 451 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 452 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 453 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 454 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 455 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 456 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 457 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 458 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 459 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 460 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 461 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 462 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 463 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 464 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 465 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 466 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 467 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 468 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 469 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 470 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 471 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 472 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 473 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 474 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 475 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 476 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 477 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 478 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 479 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 480 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 481 482 /* TTU - per hubp */ 483 REG_GET_2(DCN_TTU_QOS_WM, 484 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 485 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 486 487 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 488 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 489 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 490 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 491 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 492 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 493 494 /* TTU - per luma/chroma */ 495 /* Assumed surf0 is luma and 1 is chroma */ 496 REG_GET_3(DCN_SURF0_TTU_CNTL0, 497 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 498 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 499 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 500 REG_GET_3(DCN_SURF1_TTU_CNTL0, 501 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 502 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 503 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 504 REG_GET_3(DCN_CUR0_TTU_CNTL0, 505 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 506 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 507 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 508 REG_GET(FLIP_PARAMETERS_1, 509 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 510 REG_GET(DCN_CUR0_TTU_CNTL1, 511 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 512 REG_GET(DCN_CUR1_TTU_CNTL1, 513 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 514 REG_GET(DCN_SURF0_TTU_CNTL1, 515 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 516 REG_GET(DCN_SURF1_TTU_CNTL1, 517 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 518 519 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 520 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 521 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 522 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 523 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 524 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 525 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 526 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 527 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 528 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 529 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 530 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 531 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 532 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 533 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 534 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 535 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 536 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 537 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 538 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 539 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 540 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 541 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 542 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 543 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 544 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 545 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 546 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 547 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 548 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 549 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 550 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 551 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 552 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 553 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 554 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 555 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 556 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 557 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 558 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 559 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 560 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 561 562 /* Host VM deadline regs */ 563 REG_GET(VBLANK_PARAMETERS_5, 564 REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); 565 REG_GET(VBLANK_PARAMETERS_6, 566 REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); 567 REG_GET(FLIP_PARAMETERS_3, 568 REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); 569 REG_GET(FLIP_PARAMETERS_4, 570 REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); 571 REG_GET(FLIP_PARAMETERS_5, 572 REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); 573 REG_GET(FLIP_PARAMETERS_6, 574 REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); 575 REG_GET(FLIP_PARAMETERS_2, 576 REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); 577 578 if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) 579 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", 580 dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); 581 if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) 582 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", 583 dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); 584 if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) 585 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", 586 dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); 587 if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) 588 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", 589 dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); 590 if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) 591 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", 592 dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); 593 if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) 594 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", 595 dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); 596 if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) 597 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", 598 dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); 599 } 600 601 void hubp21_init(struct hubp *hubp) 602 { 603 // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 604 // This is a chicken bit to enable the ECO fix. 605 606 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 607 //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 608 REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 609 } 610 static struct hubp_funcs dcn21_hubp_funcs = { 611 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 612 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 613 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 614 .hubp_program_surface_config = hubp1_program_surface_config, 615 .hubp_is_flip_pending = hubp1_is_flip_pending, 616 .hubp_setup = hubp21_setup, 617 .hubp_setup_interdependent = hubp2_setup_interdependent, 618 .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 619 .set_blank = hubp1_set_blank, 620 .dcc_control = hubp1_dcc_control, 621 .mem_program_viewport = hubp21_set_viewport, 622 .set_cursor_attributes = hubp2_cursor_set_attributes, 623 .set_cursor_position = hubp1_cursor_set_position, 624 .hubp_clk_cntl = hubp1_clk_cntl, 625 .hubp_vtg_sel = hubp1_vtg_sel, 626 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 627 .dmdata_load = hubp2_dmdata_load, 628 .dmdata_status_done = hubp2_dmdata_status_done, 629 .hubp_read_state = hubp1_read_state, 630 .hubp_clear_underflow = hubp1_clear_underflow, 631 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 632 .hubp_init = hubp21_init, 633 .validate_dml_output = hubp21_validate_dml_output, 634 }; 635 636 bool hubp21_construct( 637 struct dcn21_hubp *hubp21, 638 struct dc_context *ctx, 639 uint32_t inst, 640 const struct dcn_hubp2_registers *hubp_regs, 641 const struct dcn_hubp2_shift *hubp_shift, 642 const struct dcn_hubp2_mask *hubp_mask) 643 { 644 hubp21->base.funcs = &dcn21_hubp_funcs; 645 hubp21->base.ctx = ctx; 646 hubp21->hubp_regs = hubp_regs; 647 hubp21->hubp_shift = hubp_shift; 648 hubp21->hubp_mask = hubp_mask; 649 hubp21->base.inst = inst; 650 hubp21->base.opp_id = OPP_ID_INVALID; 651 hubp21->base.mpcc_id = 0xf; 652 653 return true; 654 } 655