1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn10/dcn10_hubp.h" 27 #include "dcn21_hubp.h" 28 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 32 #include "dc_dmub_srv.h" 33 34 #define DC_LOGGER_INIT(logger) 35 36 #define REG(reg)\ 37 hubp21->hubp_regs->reg 38 39 #define CTX \ 40 hubp21->base.ctx 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 45 46 /* 47 * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 48 * As a result, if S/W updates any of these registers during a mode change, 49 * the current frame before the mode change will use the new value right away 50 * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 51 * 52 * REFCYC_PER_VM_GROUP_FLIP[22:0] 53 * REFCYC_PER_VM_GROUP_VBLANK[22:0] 54 * REFCYC_PER_VM_REQ_FLIP[22:0] 55 * REFCYC_PER_VM_REQ_VBLANK[22:0] 56 * 57 * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 58 * when flipping to a new surface 59 * 60 * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 61 * during prefetch period of a frame. The prefetch starts at a pre-determined 62 * number of lines before the display active per frame 63 * 64 * DCN may underflow due to incorrectly programming these registers 65 * during VM stage of prefetch/iflip. First lines of display active 66 * or a sub-region of active using a new surface will be corrupted 67 * until the VM data returns at flip/mode change transitions 68 * 69 * Work around: 70 * workaround is always opt to use the more aggressive settings. 71 * On any mode switch, if the new reg values are smaller than the current values, 72 * then update the regs with the new values. 73 * 74 * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 75 * 76 */ 77 void apply_DEDCN21_142_wa_for_hostvm_deadline( 78 struct hubp *hubp, 79 struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 80 { 81 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 82 uint32_t refcyc_per_vm_group_vblank; 83 uint32_t refcyc_per_vm_req_vblank; 84 uint32_t refcyc_per_vm_group_flip; 85 uint32_t refcyc_per_vm_req_flip; 86 const uint32_t uninitialized_hw_default = 0; 87 88 REG_GET(VBLANK_PARAMETERS_5, 89 REFCYC_PER_VM_GROUP_VBLANK, &refcyc_per_vm_group_vblank); 90 91 if (refcyc_per_vm_group_vblank == uninitialized_hw_default || 92 refcyc_per_vm_group_vblank > dlg_attr->refcyc_per_vm_group_vblank) 93 REG_SET(VBLANK_PARAMETERS_5, 0, 94 REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 95 96 REG_GET(VBLANK_PARAMETERS_6, 97 REFCYC_PER_VM_REQ_VBLANK, &refcyc_per_vm_req_vblank); 98 99 if (refcyc_per_vm_req_vblank == uninitialized_hw_default || 100 refcyc_per_vm_req_vblank > dlg_attr->refcyc_per_vm_req_vblank) 101 REG_SET(VBLANK_PARAMETERS_6, 0, 102 REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 103 104 REG_GET(FLIP_PARAMETERS_3, 105 REFCYC_PER_VM_GROUP_FLIP, &refcyc_per_vm_group_flip); 106 107 if (refcyc_per_vm_group_flip == uninitialized_hw_default || 108 refcyc_per_vm_group_flip > dlg_attr->refcyc_per_vm_group_flip) 109 REG_SET(FLIP_PARAMETERS_3, 0, 110 REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 111 112 REG_GET(FLIP_PARAMETERS_4, 113 REFCYC_PER_VM_REQ_FLIP, &refcyc_per_vm_req_flip); 114 115 if (refcyc_per_vm_req_flip == uninitialized_hw_default || 116 refcyc_per_vm_req_flip > dlg_attr->refcyc_per_vm_req_flip) 117 REG_SET(FLIP_PARAMETERS_4, 0, 118 REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 119 120 REG_SET(FLIP_PARAMETERS_5, 0, 121 REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 122 123 REG_SET(FLIP_PARAMETERS_6, 0, 124 REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 125 } 126 127 void hubp21_program_deadline( 128 struct hubp *hubp, 129 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 130 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 131 { 132 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 133 134 apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 135 } 136 137 void hubp21_program_requestor( 138 struct hubp *hubp, 139 struct _vcs_dpi_display_rq_regs_st *rq_regs) 140 { 141 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 142 143 REG_UPDATE(HUBPRET_CONTROL, 144 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 145 REG_SET_4(DCN_EXPANSION_MODE, 0, 146 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 147 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 148 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 149 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 150 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 151 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 152 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 153 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 154 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 155 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 156 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 157 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 158 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 159 REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 160 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 161 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 162 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 163 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 164 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 165 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 166 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 167 } 168 169 static void hubp21_setup( 170 struct hubp *hubp, 171 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 172 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 173 struct _vcs_dpi_display_rq_regs_st *rq_regs, 174 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 175 { 176 /* otg is locked when this func is called. Register are double buffered. 177 * disable the requestors is not needed 178 */ 179 180 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 181 hubp21_program_requestor(hubp, rq_regs); 182 hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 183 184 } 185 186 void hubp21_set_viewport( 187 struct hubp *hubp, 188 const struct rect *viewport, 189 const struct rect *viewport_c) 190 { 191 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 192 193 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 194 PRI_VIEWPORT_WIDTH, viewport->width, 195 PRI_VIEWPORT_HEIGHT, viewport->height); 196 197 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 198 PRI_VIEWPORT_X_START, viewport->x, 199 PRI_VIEWPORT_Y_START, viewport->y); 200 201 /*for stereo*/ 202 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 203 SEC_VIEWPORT_WIDTH, viewport->width, 204 SEC_VIEWPORT_HEIGHT, viewport->height); 205 206 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 207 SEC_VIEWPORT_X_START, viewport->x, 208 SEC_VIEWPORT_Y_START, viewport->y); 209 210 /* DC supports NV12 only at the moment */ 211 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 212 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 213 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 214 215 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 216 PRI_VIEWPORT_X_START_C, viewport_c->x, 217 PRI_VIEWPORT_Y_START_C, viewport_c->y); 218 219 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 220 SEC_VIEWPORT_WIDTH_C, viewport_c->width, 221 SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 222 223 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 224 SEC_VIEWPORT_X_START_C, viewport_c->x, 225 SEC_VIEWPORT_Y_START_C, viewport_c->y); 226 } 227 228 static void hubp21_apply_PLAT_54186_wa( 229 struct hubp *hubp, 230 const struct dc_plane_address *address) 231 { 232 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 233 struct dc_debug_options *debug = &hubp->ctx->dc->debug; 234 unsigned int chroma_bpe = 2; 235 unsigned int luma_addr_high_part = 0; 236 unsigned int row_height = 0; 237 unsigned int chroma_pitch = 0; 238 unsigned int viewport_c_height = 0; 239 unsigned int viewport_c_width = 0; 240 unsigned int patched_viewport_height = 0; 241 unsigned int patched_viewport_width = 0; 242 unsigned int rotation_angle = 0; 243 unsigned int pix_format = 0; 244 unsigned int h_mirror_en = 0; 245 unsigned int tile_blk_size = 64 * 1024; /* 64KB for 64KB SW, 4KB for 4KB SW */ 246 247 248 if (!debug->nv12_iflip_vm_wa) 249 return; 250 251 REG_GET(DCHUBP_REQ_SIZE_CONFIG_C, 252 PTE_ROW_HEIGHT_LINEAR_C, &row_height); 253 254 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 255 PRI_VIEWPORT_WIDTH_C, &viewport_c_width, 256 PRI_VIEWPORT_HEIGHT_C, &viewport_c_height); 257 258 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 259 PRIMARY_SURFACE_ADDRESS_HIGH_C, &luma_addr_high_part); 260 261 REG_GET(DCSURF_SURFACE_PITCH_C, 262 PITCH_C, &chroma_pitch); 263 264 chroma_pitch += 1; 265 266 REG_GET_3(DCSURF_SURFACE_CONFIG, 267 SURFACE_PIXEL_FORMAT, &pix_format, 268 ROTATION_ANGLE, &rotation_angle, 269 H_MIRROR_EN, &h_mirror_en); 270 271 /* reset persistent cached data */ 272 hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 273 /* apply wa only for NV12 surface with scatter gather enabled with viewport > 512 along 274 * the vertical direction*/ 275 if (address->type != PLN_ADDR_TYPE_VIDEO_PROGRESSIVE || 276 address->video_progressive.luma_addr.high_part == 0xf4) 277 return; 278 279 if ((rotation_angle == ROTATION_ANGLE_0 || rotation_angle == ROTATION_ANGLE_180) 280 && viewport_c_height <= 512) 281 return; 282 283 if ((rotation_angle == ROTATION_ANGLE_90 || rotation_angle == ROTATION_ANGLE_270) 284 && viewport_c_width <= 512) 285 return; 286 287 switch (rotation_angle) { 288 case ROTATION_ANGLE_0: /* 0 degree rotation */ 289 row_height = 128; 290 patched_viewport_height = (viewport_c_height / row_height + 1) * row_height + 1; 291 patched_viewport_width = viewport_c_width; 292 hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 293 break; 294 case ROTATION_ANGLE_180: /* 180 degree rotation */ 295 row_height = 128; 296 patched_viewport_height = viewport_c_height + row_height; 297 patched_viewport_width = viewport_c_width; 298 hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - chroma_pitch * row_height * chroma_bpe; 299 break; 300 case ROTATION_ANGLE_90: /* 90 degree rotation */ 301 row_height = 256; 302 if (h_mirror_en) { 303 patched_viewport_height = viewport_c_height; 304 patched_viewport_width = viewport_c_width + row_height; 305 hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 306 } else { 307 patched_viewport_height = viewport_c_height; 308 patched_viewport_width = viewport_c_width + row_height; 309 hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size; 310 } 311 break; 312 case ROTATION_ANGLE_270: /* 270 degree rotation */ 313 row_height = 256; 314 if (h_mirror_en) { 315 patched_viewport_height = viewport_c_height; 316 patched_viewport_width = viewport_c_width + row_height; 317 hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size; 318 } else { 319 patched_viewport_height = viewport_c_height; 320 patched_viewport_width = viewport_c_width + row_height; 321 hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 322 } 323 break; 324 default: 325 ASSERT(0); 326 break; 327 } 328 329 /* catch cases where viewport keep growing */ 330 ASSERT(patched_viewport_height && patched_viewport_height < 5000); 331 ASSERT(patched_viewport_width && patched_viewport_width < 5000); 332 333 REG_UPDATE_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 334 PRI_VIEWPORT_WIDTH_C, patched_viewport_width, 335 PRI_VIEWPORT_HEIGHT_C, patched_viewport_height); 336 } 337 338 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 339 struct vm_system_aperture_param *apt) 340 { 341 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 342 343 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 344 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 345 346 // The format of high/low are 48:18 of the 48 bit addr 347 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 348 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 349 350 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 351 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 352 353 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 354 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 355 356 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 357 ENABLE_L1_TLB, 1, 358 SYSTEM_ACCESS_MODE, 0x3); 359 } 360 361 void hubp21_validate_dml_output(struct hubp *hubp, 362 struct dc_context *ctx, 363 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 364 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 365 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 366 { 367 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 368 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 369 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 370 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 371 DC_LOGGER_INIT(ctx->logger); 372 DC_LOG_DEBUG("DML Validation | Running Validation"); 373 374 /* Requester - Per hubp */ 375 REG_GET(HUBPRET_CONTROL, 376 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 377 REG_GET_4(DCN_EXPANSION_MODE, 378 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 379 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 380 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 381 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 382 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 383 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 384 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 385 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 386 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 387 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 388 VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 389 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 390 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 391 REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, 392 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 393 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 394 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 395 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 396 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 397 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 398 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 399 400 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 401 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 402 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 403 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 404 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 405 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 406 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 407 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 408 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 409 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 410 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 411 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 412 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 413 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 414 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 415 416 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 417 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 418 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 419 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 420 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 421 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 422 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 423 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 424 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 425 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 426 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 427 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 428 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 429 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 430 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 431 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 432 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", 433 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 434 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 435 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 436 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 437 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 438 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 439 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 440 441 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 442 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 443 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 444 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 445 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 446 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 447 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 448 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 449 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 450 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 451 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 452 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 453 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 454 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 455 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 456 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 457 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 458 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 459 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 460 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 461 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 462 463 464 /* DLG - Per hubp */ 465 REG_GET_2(BLANK_OFFSET_0, 466 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 467 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 468 REG_GET(BLANK_OFFSET_1, 469 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 470 REG_GET(DST_DIMENSIONS, 471 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 472 REG_GET_2(DST_AFTER_SCALER, 473 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 474 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 475 REG_GET(REF_FREQ_TO_PIX_FREQ, 476 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 477 478 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 479 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 480 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 481 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 482 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 483 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 484 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 485 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 486 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 487 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 488 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 489 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 490 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 491 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 492 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 493 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 494 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 495 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 496 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 497 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 498 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 499 500 /* DLG - Per luma/chroma */ 501 REG_GET(VBLANK_PARAMETERS_1, 502 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 503 if (REG(NOM_PARAMETERS_0)) 504 REG_GET(NOM_PARAMETERS_0, 505 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 506 if (REG(NOM_PARAMETERS_1)) 507 REG_GET(NOM_PARAMETERS_1, 508 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 509 REG_GET(NOM_PARAMETERS_4, 510 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 511 REG_GET(NOM_PARAMETERS_5, 512 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 513 REG_GET_2(PER_LINE_DELIVERY, 514 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 515 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 516 REG_GET_2(PER_LINE_DELIVERY_PRE, 517 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 518 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 519 REG_GET(VBLANK_PARAMETERS_2, 520 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 521 if (REG(NOM_PARAMETERS_2)) 522 REG_GET(NOM_PARAMETERS_2, 523 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 524 if (REG(NOM_PARAMETERS_3)) 525 REG_GET(NOM_PARAMETERS_3, 526 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 527 REG_GET(NOM_PARAMETERS_6, 528 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 529 REG_GET(NOM_PARAMETERS_7, 530 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 531 REG_GET(VBLANK_PARAMETERS_3, 532 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 533 REG_GET(VBLANK_PARAMETERS_4, 534 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 535 536 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 537 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 538 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 539 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 540 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 541 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 542 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 543 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 544 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 545 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 546 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 547 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 548 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 549 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 550 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 551 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 552 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 553 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 554 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 555 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 556 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 557 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 558 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 559 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 560 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 561 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 562 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 563 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 564 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 565 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 566 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 567 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 568 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 569 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 570 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 571 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 572 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 573 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 574 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 575 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 576 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 577 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 578 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 579 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 580 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 581 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 582 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 583 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 584 585 /* TTU - per hubp */ 586 REG_GET_2(DCN_TTU_QOS_WM, 587 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 588 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 589 590 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 591 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 592 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 593 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 594 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 595 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 596 597 /* TTU - per luma/chroma */ 598 /* Assumed surf0 is luma and 1 is chroma */ 599 REG_GET_3(DCN_SURF0_TTU_CNTL0, 600 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 601 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 602 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 603 REG_GET_3(DCN_SURF1_TTU_CNTL0, 604 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 605 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 606 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 607 REG_GET_3(DCN_CUR0_TTU_CNTL0, 608 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 609 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 610 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 611 REG_GET(FLIP_PARAMETERS_1, 612 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 613 REG_GET(DCN_CUR0_TTU_CNTL1, 614 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 615 REG_GET(DCN_CUR1_TTU_CNTL1, 616 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 617 REG_GET(DCN_SURF0_TTU_CNTL1, 618 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 619 REG_GET(DCN_SURF1_TTU_CNTL1, 620 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 621 622 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 623 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 624 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 625 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 626 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 627 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 628 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 629 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 630 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 631 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 632 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 633 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 634 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 635 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 636 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 637 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 638 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 639 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 640 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 641 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 642 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 643 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 644 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 645 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 646 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 647 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 648 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 649 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 650 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 651 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 652 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 653 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 654 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 655 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 656 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 657 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 658 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 659 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 660 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 661 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 662 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 663 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 664 665 /* Host VM deadline regs */ 666 REG_GET(VBLANK_PARAMETERS_5, 667 REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); 668 REG_GET(VBLANK_PARAMETERS_6, 669 REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); 670 REG_GET(FLIP_PARAMETERS_3, 671 REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); 672 REG_GET(FLIP_PARAMETERS_4, 673 REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); 674 REG_GET(FLIP_PARAMETERS_5, 675 REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); 676 REG_GET(FLIP_PARAMETERS_6, 677 REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); 678 REG_GET(FLIP_PARAMETERS_2, 679 REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); 680 681 if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) 682 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", 683 dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); 684 if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) 685 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", 686 dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); 687 if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) 688 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", 689 dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); 690 if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) 691 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", 692 dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); 693 if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) 694 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", 695 dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); 696 if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) 697 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", 698 dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); 699 if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) 700 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", 701 dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); 702 } 703 704 static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs) 705 { 706 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 707 708 REG_UPDATE_3(DCSURF_FLIP_CONTROL, 709 SURFACE_FLIP_TYPE, flip_regs->immediate, 710 SURFACE_FLIP_MODE_FOR_STEREOSYNC, flip_regs->grph_stereo, 711 SURFACE_FLIP_IN_STEREOSYNC, flip_regs->grph_stereo); 712 713 REG_UPDATE(VMID_SETTINGS_0, 714 VMID, flip_regs->vmid); 715 716 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 717 PRIMARY_SURFACE_TMZ, flip_regs->tmz_surface, 718 PRIMARY_SURFACE_TMZ_C, flip_regs->tmz_surface, 719 PRIMARY_META_SURFACE_TMZ, flip_regs->tmz_surface, 720 PRIMARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface, 721 SECONDARY_SURFACE_TMZ, flip_regs->tmz_surface, 722 SECONDARY_SURFACE_TMZ_C, flip_regs->tmz_surface, 723 SECONDARY_META_SURFACE_TMZ, flip_regs->tmz_surface, 724 SECONDARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface); 725 726 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 727 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 728 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C); 729 730 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 731 PRIMARY_META_SURFACE_ADDRESS_C, 732 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_C); 733 734 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 735 PRIMARY_META_SURFACE_ADDRESS_HIGH, 736 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH); 737 738 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 739 PRIMARY_META_SURFACE_ADDRESS, 740 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS); 741 742 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 743 SECONDARY_META_SURFACE_ADDRESS_HIGH, 744 flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH); 745 746 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 747 SECONDARY_META_SURFACE_ADDRESS, 748 flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS); 749 750 751 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 752 SECONDARY_SURFACE_ADDRESS_HIGH, 753 flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH); 754 755 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 756 SECONDARY_SURFACE_ADDRESS, 757 flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS); 758 759 760 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 761 PRIMARY_SURFACE_ADDRESS_HIGH_C, 762 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C); 763 764 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 765 PRIMARY_SURFACE_ADDRESS_C, 766 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C); 767 768 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 769 PRIMARY_SURFACE_ADDRESS_HIGH, 770 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH); 771 772 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 773 PRIMARY_SURFACE_ADDRESS, 774 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS); 775 } 776 777 void dmcub_PLAT_54186_wa(struct hubp *hubp, struct surface_flip_registers *flip_regs) 778 { 779 struct dc_dmub_srv *dmcub = hubp->ctx->dmub_srv; 780 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 781 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa = { 0 }; 782 783 PLAT_54186_wa.header.type = DMUB_CMD__PLAT_54186_WA; 784 PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS; 785 PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C; 786 PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 787 PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 788 PLAT_54186_wa.flip.flip_params.grph_stereo = flip_regs->grph_stereo; 789 PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst; 790 PLAT_54186_wa.flip.flip_params.immediate = flip_regs->immediate; 791 PLAT_54186_wa.flip.flip_params.tmz_surface = flip_regs->tmz_surface; 792 PLAT_54186_wa.flip.flip_params.vmid = flip_regs->vmid; 793 794 PERF_TRACE(); // TODO: remove after performance is stable. 795 dc_dmub_srv_cmd_queue(dmcub, &PLAT_54186_wa.header); 796 PERF_TRACE(); // TODO: remove after performance is stable. 797 dc_dmub_srv_cmd_execute(dmcub); 798 PERF_TRACE(); // TODO: remove after performance is stable. 799 dc_dmub_srv_wait_idle(dmcub); 800 PERF_TRACE(); // TODO: remove after performance is stable. 801 } 802 803 bool hubp21_program_surface_flip_and_addr( 804 struct hubp *hubp, 805 const struct dc_plane_address *address, 806 bool flip_immediate) 807 { 808 struct dc_debug_options *debug = &hubp->ctx->dc->debug; 809 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 810 struct surface_flip_registers flip_regs = { 0 }; 811 812 flip_regs.vmid = address->vmid; 813 814 switch (address->type) { 815 case PLN_ADDR_TYPE_GRAPHICS: 816 if (address->grph.addr.quad_part == 0) { 817 BREAK_TO_DEBUGGER(); 818 break; 819 } 820 821 if (address->grph.meta_addr.quad_part != 0) { 822 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 823 address->grph.meta_addr.low_part; 824 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 825 address->grph.meta_addr.high_part; 826 } 827 828 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 829 address->grph.addr.low_part; 830 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 831 address->grph.addr.high_part; 832 break; 833 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 834 if (address->video_progressive.luma_addr.quad_part == 0 835 || address->video_progressive.chroma_addr.quad_part == 0) 836 break; 837 838 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 839 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 840 address->video_progressive.luma_meta_addr.low_part; 841 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 842 address->video_progressive.luma_meta_addr.high_part; 843 844 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 845 address->video_progressive.chroma_meta_addr.low_part; 846 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 847 address->video_progressive.chroma_meta_addr.high_part; 848 } 849 850 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 851 address->video_progressive.luma_addr.low_part; 852 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 853 address->video_progressive.luma_addr.high_part; 854 855 if (debug->nv12_iflip_vm_wa) { 856 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 857 address->video_progressive.chroma_addr.low_part + hubp21->PLAT_54186_wa_chroma_addr_offset; 858 } else 859 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 860 address->video_progressive.chroma_addr.low_part; 861 862 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 863 address->video_progressive.chroma_addr.high_part; 864 865 break; 866 case PLN_ADDR_TYPE_GRPH_STEREO: 867 if (address->grph_stereo.left_addr.quad_part == 0) 868 break; 869 if (address->grph_stereo.right_addr.quad_part == 0) 870 break; 871 872 flip_regs.grph_stereo = true; 873 874 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 875 flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS = 876 address->grph_stereo.right_meta_addr.low_part; 877 flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 878 address->grph_stereo.right_meta_addr.high_part; 879 } 880 881 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 882 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 883 address->grph_stereo.left_meta_addr.low_part; 884 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 885 address->grph_stereo.left_meta_addr.high_part; 886 } 887 888 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 889 address->grph_stereo.left_addr.low_part; 890 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 891 address->grph_stereo.left_addr.high_part; 892 893 flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS = 894 address->grph_stereo.right_addr.low_part; 895 flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 896 address->grph_stereo.right_addr.high_part; 897 898 break; 899 default: 900 BREAK_TO_DEBUGGER(); 901 break; 902 } 903 904 flip_regs.tmz_surface = address->tmz_surface; 905 flip_regs.immediate = flip_immediate; 906 907 if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 908 dmcub_PLAT_54186_wa(hubp, &flip_regs); 909 else 910 program_surface_flip_and_addr(hubp, &flip_regs); 911 912 hubp->request_address = *address; 913 914 return true; 915 } 916 917 void hubp21_init(struct hubp *hubp) 918 { 919 // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 920 // This is a chicken bit to enable the ECO fix. 921 922 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 923 //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 924 REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 925 } 926 static struct hubp_funcs dcn21_hubp_funcs = { 927 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 928 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 929 .hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr, 930 .hubp_program_surface_config = hubp1_program_surface_config, 931 .hubp_is_flip_pending = hubp1_is_flip_pending, 932 .hubp_setup = hubp21_setup, 933 .hubp_setup_interdependent = hubp2_setup_interdependent, 934 .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 935 .set_blank = hubp1_set_blank, 936 .dcc_control = hubp1_dcc_control, 937 .mem_program_viewport = hubp21_set_viewport, 938 .apply_PLAT_54186_wa = hubp21_apply_PLAT_54186_wa, 939 .set_cursor_attributes = hubp2_cursor_set_attributes, 940 .set_cursor_position = hubp1_cursor_set_position, 941 .hubp_clk_cntl = hubp1_clk_cntl, 942 .hubp_vtg_sel = hubp1_vtg_sel, 943 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 944 .dmdata_load = hubp2_dmdata_load, 945 .dmdata_status_done = hubp2_dmdata_status_done, 946 .hubp_read_state = hubp1_read_state, 947 .hubp_clear_underflow = hubp1_clear_underflow, 948 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 949 .hubp_init = hubp21_init, 950 .validate_dml_output = hubp21_validate_dml_output, 951 }; 952 953 bool hubp21_construct( 954 struct dcn21_hubp *hubp21, 955 struct dc_context *ctx, 956 uint32_t inst, 957 const struct dcn_hubp2_registers *hubp_regs, 958 const struct dcn_hubp2_shift *hubp_shift, 959 const struct dcn_hubp2_mask *hubp_mask) 960 { 961 hubp21->base.funcs = &dcn21_hubp_funcs; 962 hubp21->base.ctx = ctx; 963 hubp21->hubp_regs = hubp_regs; 964 hubp21->hubp_shift = hubp_shift; 965 hubp21->hubp_mask = hubp_mask; 966 hubp21->base.inst = inst; 967 hubp21->base.opp_id = OPP_ID_INVALID; 968 hubp21->base.mpcc_id = 0xf; 969 970 return true; 971 } 972