1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn10/dcn10_hubp.h" 27 #include "dcn21_hubp.h" 28 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 32 #define REG(reg)\ 33 hubp21->hubp_regs->reg 34 35 #define CTX \ 36 hubp21->base.ctx 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 41 42 /* 43 * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 44 * As a result, if S/W updates any of these registers during a mode change, 45 * the current frame before the mode change will use the new value right away 46 * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 47 * 48 * REFCYC_PER_VM_GROUP_FLIP[22:0] 49 * REFCYC_PER_VM_GROUP_VBLANK[22:0] 50 * REFCYC_PER_VM_REQ_FLIP[22:0] 51 * REFCYC_PER_VM_REQ_VBLANK[22:0] 52 * 53 * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 54 * when flipping to a new surface 55 * 56 * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 57 * during prefetch period of a frame. The prefetch starts at a pre-determined 58 * number of lines before the display active per frame 59 * 60 * DCN may underflow due to incorrectly programming these registers 61 * during VM stage of prefetch/iflip. First lines of display active 62 * or a sub-region of active using a new surface will be corrupted 63 * until the VM data returns at flip/mode change transitions 64 * 65 * Work around: 66 * workaround is always opt to use the more aggressive settings. 67 * On any mode switch, if the new reg values are smaller than the current values, 68 * then update the regs with the new values. 69 * 70 * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 71 * 72 */ 73 void apply_DEDCN21_142_wa_for_hostvm_deadline( 74 struct hubp *hubp, 75 struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 76 { 77 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 78 uint32_t cur_value; 79 80 REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); 81 if (cur_value > dlg_attr->refcyc_per_vm_group_vblank) 82 REG_SET(VBLANK_PARAMETERS_5, 0, 83 REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 84 85 REG_GET(VBLANK_PARAMETERS_6, 86 REFCYC_PER_VM_REQ_VBLANK, 87 &cur_value); 88 if (cur_value > dlg_attr->refcyc_per_vm_req_vblank) 89 REG_SET(VBLANK_PARAMETERS_6, 0, 90 REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 91 92 REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); 93 if (cur_value > dlg_attr->refcyc_per_vm_group_flip) 94 REG_SET(FLIP_PARAMETERS_3, 0, 95 REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 96 97 REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); 98 if (cur_value > dlg_attr->refcyc_per_vm_req_flip) 99 REG_SET(FLIP_PARAMETERS_4, 0, 100 REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 101 102 REG_SET(FLIP_PARAMETERS_5, 0, 103 REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 104 REG_SET(FLIP_PARAMETERS_6, 0, 105 REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 106 } 107 108 void hubp21_program_deadline( 109 struct hubp *hubp, 110 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 111 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 112 { 113 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 114 115 apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 116 } 117 118 void hubp21_program_requestor( 119 struct hubp *hubp, 120 struct _vcs_dpi_display_rq_regs_st *rq_regs) 121 { 122 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 123 124 REG_UPDATE(HUBPRET_CONTROL, 125 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 126 REG_SET_4(DCN_EXPANSION_MODE, 0, 127 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 128 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 129 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 130 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 131 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 132 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 133 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 134 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 135 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 136 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 137 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 138 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 139 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 140 REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 141 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 142 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 143 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 144 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 145 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 146 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 147 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 148 } 149 150 static void hubp21_setup( 151 struct hubp *hubp, 152 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 153 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 154 struct _vcs_dpi_display_rq_regs_st *rq_regs, 155 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 156 { 157 /* otg is locked when this func is called. Register are double buffered. 158 * disable the requestors is not needed 159 */ 160 161 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 162 hubp21_program_requestor(hubp, rq_regs); 163 hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 164 165 } 166 167 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 168 struct vm_system_aperture_param *apt) 169 { 170 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 171 172 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 173 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 174 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 175 176 // The format of default addr is 48:12 of the 48 bit addr 177 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 178 179 // The format of high/low are 48:18 of the 48 bit addr 180 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 181 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 182 183 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 184 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 185 186 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 187 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 188 189 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 190 ENABLE_L1_TLB, 1, 191 SYSTEM_ACCESS_MODE, 0x3); 192 } 193 194 void hubp21_init(struct hubp *hubp) 195 { 196 // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 197 // This is a chicken bit to enable the ECO fix. 198 199 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 200 //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 201 REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 202 } 203 static struct hubp_funcs dcn21_hubp_funcs = { 204 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 205 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 206 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 207 .hubp_program_surface_config = hubp1_program_surface_config, 208 .hubp_is_flip_pending = hubp1_is_flip_pending, 209 .hubp_setup = hubp21_setup, 210 .hubp_setup_interdependent = hubp2_setup_interdependent, 211 .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 212 .set_blank = hubp1_set_blank, 213 .dcc_control = hubp1_dcc_control, 214 .mem_program_viewport = min_set_viewport, 215 .set_cursor_attributes = hubp2_cursor_set_attributes, 216 .set_cursor_position = hubp1_cursor_set_position, 217 .hubp_clk_cntl = hubp1_clk_cntl, 218 .hubp_vtg_sel = hubp1_vtg_sel, 219 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 220 .dmdata_load = hubp2_dmdata_load, 221 .dmdata_status_done = hubp2_dmdata_status_done, 222 .hubp_read_state = hubp1_read_state, 223 .hubp_clear_underflow = hubp1_clear_underflow, 224 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 225 .hubp_init = hubp21_init, 226 }; 227 228 bool hubp21_construct( 229 struct dcn21_hubp *hubp21, 230 struct dc_context *ctx, 231 uint32_t inst, 232 const struct dcn_hubp2_registers *hubp_regs, 233 const struct dcn_hubp2_shift *hubp_shift, 234 const struct dcn_hubp2_mask *hubp_mask) 235 { 236 hubp21->base.funcs = &dcn21_hubp_funcs; 237 hubp21->base.ctx = ctx; 238 hubp21->hubp_regs = hubp_regs; 239 hubp21->hubp_shift = hubp_shift; 240 hubp21->hubp_mask = hubp_mask; 241 hubp21->base.inst = inst; 242 hubp21->base.opp_id = OPP_ID_INVALID; 243 hubp21->base.mpcc_id = 0xf; 244 245 return true; 246 } 247