1eced51f9SBhawanpreet Lakha /* 2eced51f9SBhawanpreet Lakha * Copyright 2018 Advanced Micro Devices, Inc. 3eced51f9SBhawanpreet Lakha * 4eced51f9SBhawanpreet Lakha * Permission is hereby granted, free of charge, to any person obtaining a 5eced51f9SBhawanpreet Lakha * copy of this software and associated documentation files (the "Software"), 6eced51f9SBhawanpreet Lakha * to deal in the Software without restriction, including without limitation 7eced51f9SBhawanpreet Lakha * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8eced51f9SBhawanpreet Lakha * and/or sell copies of the Software, and to permit persons to whom the 9eced51f9SBhawanpreet Lakha * Software is furnished to do so, subject to the following conditions: 10eced51f9SBhawanpreet Lakha * 11eced51f9SBhawanpreet Lakha * The above copyright notice and this permission notice shall be included in 12eced51f9SBhawanpreet Lakha * all copies or substantial portions of the Software. 13eced51f9SBhawanpreet Lakha * 14eced51f9SBhawanpreet Lakha * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15eced51f9SBhawanpreet Lakha * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16eced51f9SBhawanpreet Lakha * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17eced51f9SBhawanpreet Lakha * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18eced51f9SBhawanpreet Lakha * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19eced51f9SBhawanpreet Lakha * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20eced51f9SBhawanpreet Lakha * OTHER DEALINGS IN THE SOFTWARE. 21eced51f9SBhawanpreet Lakha * 22eced51f9SBhawanpreet Lakha * Authors: AMD 23eced51f9SBhawanpreet Lakha * 24eced51f9SBhawanpreet Lakha */ 2502981b28SEric Yang 2602981b28SEric Yang #include "dcn10/dcn10_hubp.h" 27eced51f9SBhawanpreet Lakha #include "dcn21_hubp.h" 28eced51f9SBhawanpreet Lakha 29eced51f9SBhawanpreet Lakha #include "dm_services.h" 30eced51f9SBhawanpreet Lakha #include "reg_helper.h" 31eced51f9SBhawanpreet Lakha 32b9fe5151SJaehyun Chung #define DC_LOGGER_INIT(logger) 33b9fe5151SJaehyun Chung 34eced51f9SBhawanpreet Lakha #define REG(reg)\ 35eced51f9SBhawanpreet Lakha hubp21->hubp_regs->reg 36eced51f9SBhawanpreet Lakha 37eced51f9SBhawanpreet Lakha #define CTX \ 38eced51f9SBhawanpreet Lakha hubp21->base.ctx 39eced51f9SBhawanpreet Lakha 40eced51f9SBhawanpreet Lakha #undef FN 41eced51f9SBhawanpreet Lakha #define FN(reg_name, field_name) \ 42eced51f9SBhawanpreet Lakha hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 43eced51f9SBhawanpreet Lakha 44eced51f9SBhawanpreet Lakha /* 45eced51f9SBhawanpreet Lakha * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 46eced51f9SBhawanpreet Lakha * As a result, if S/W updates any of these registers during a mode change, 47eced51f9SBhawanpreet Lakha * the current frame before the mode change will use the new value right away 48eced51f9SBhawanpreet Lakha * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 49eced51f9SBhawanpreet Lakha * 50eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_GROUP_FLIP[22:0] 51eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_GROUP_VBLANK[22:0] 52eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_REQ_FLIP[22:0] 53eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_REQ_VBLANK[22:0] 54eced51f9SBhawanpreet Lakha * 55eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 56eced51f9SBhawanpreet Lakha * when flipping to a new surface 57eced51f9SBhawanpreet Lakha * 58eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 59eced51f9SBhawanpreet Lakha * during prefetch period of a frame. The prefetch starts at a pre-determined 60eced51f9SBhawanpreet Lakha * number of lines before the display active per frame 61eced51f9SBhawanpreet Lakha * 62eced51f9SBhawanpreet Lakha * DCN may underflow due to incorrectly programming these registers 63eced51f9SBhawanpreet Lakha * during VM stage of prefetch/iflip. First lines of display active 64eced51f9SBhawanpreet Lakha * or a sub-region of active using a new surface will be corrupted 65eced51f9SBhawanpreet Lakha * until the VM data returns at flip/mode change transitions 66eced51f9SBhawanpreet Lakha * 67eced51f9SBhawanpreet Lakha * Work around: 68eced51f9SBhawanpreet Lakha * workaround is always opt to use the more aggressive settings. 69eced51f9SBhawanpreet Lakha * On any mode switch, if the new reg values are smaller than the current values, 70eced51f9SBhawanpreet Lakha * then update the regs with the new values. 71eced51f9SBhawanpreet Lakha * 72eced51f9SBhawanpreet Lakha * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 73eced51f9SBhawanpreet Lakha * 74eced51f9SBhawanpreet Lakha */ 75eced51f9SBhawanpreet Lakha void apply_DEDCN21_142_wa_for_hostvm_deadline( 76eced51f9SBhawanpreet Lakha struct hubp *hubp, 77eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 78eced51f9SBhawanpreet Lakha { 79eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 80eced51f9SBhawanpreet Lakha uint32_t cur_value; 81eced51f9SBhawanpreet Lakha 82eced51f9SBhawanpreet Lakha REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); 83eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_group_vblank) 84eced51f9SBhawanpreet Lakha REG_SET(VBLANK_PARAMETERS_5, 0, 85eced51f9SBhawanpreet Lakha REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 86eced51f9SBhawanpreet Lakha 87eced51f9SBhawanpreet Lakha REG_GET(VBLANK_PARAMETERS_6, 88eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_VBLANK, 89eced51f9SBhawanpreet Lakha &cur_value); 90eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_req_vblank) 91eced51f9SBhawanpreet Lakha REG_SET(VBLANK_PARAMETERS_6, 0, 92eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 93eced51f9SBhawanpreet Lakha 94eced51f9SBhawanpreet Lakha REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); 95eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_group_flip) 96eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_3, 0, 97eced51f9SBhawanpreet Lakha REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 98eced51f9SBhawanpreet Lakha 99eced51f9SBhawanpreet Lakha REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); 100eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_req_flip) 101eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_4, 0, 102eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 103eced51f9SBhawanpreet Lakha 104eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_5, 0, 105eced51f9SBhawanpreet Lakha REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 106eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_6, 0, 107eced51f9SBhawanpreet Lakha REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 108eced51f9SBhawanpreet Lakha } 109eced51f9SBhawanpreet Lakha 110eced51f9SBhawanpreet Lakha void hubp21_program_deadline( 111eced51f9SBhawanpreet Lakha struct hubp *hubp, 112eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 113eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 114eced51f9SBhawanpreet Lakha { 115eced51f9SBhawanpreet Lakha hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 116eced51f9SBhawanpreet Lakha 117eced51f9SBhawanpreet Lakha apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 118eced51f9SBhawanpreet Lakha } 119eced51f9SBhawanpreet Lakha 120eced51f9SBhawanpreet Lakha void hubp21_program_requestor( 121eced51f9SBhawanpreet Lakha struct hubp *hubp, 122eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_rq_regs_st *rq_regs) 123eced51f9SBhawanpreet Lakha { 124eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 125eced51f9SBhawanpreet Lakha 126eced51f9SBhawanpreet Lakha REG_UPDATE(HUBPRET_CONTROL, 127eced51f9SBhawanpreet Lakha DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 128eced51f9SBhawanpreet Lakha REG_SET_4(DCN_EXPANSION_MODE, 0, 129eced51f9SBhawanpreet Lakha DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 130eced51f9SBhawanpreet Lakha PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 131eced51f9SBhawanpreet Lakha MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 132eced51f9SBhawanpreet Lakha CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 133eced51f9SBhawanpreet Lakha REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 134eced51f9SBhawanpreet Lakha CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 135eced51f9SBhawanpreet Lakha MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 136eced51f9SBhawanpreet Lakha META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 137eced51f9SBhawanpreet Lakha MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 138eced51f9SBhawanpreet Lakha DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 139eced51f9SBhawanpreet Lakha VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 140eced51f9SBhawanpreet Lakha SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 141eced51f9SBhawanpreet Lakha PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 142eced51f9SBhawanpreet Lakha REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 143eced51f9SBhawanpreet Lakha CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 144eced51f9SBhawanpreet Lakha MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 145eced51f9SBhawanpreet Lakha META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 146eced51f9SBhawanpreet Lakha MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 147eced51f9SBhawanpreet Lakha DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 148eced51f9SBhawanpreet Lakha SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 149eced51f9SBhawanpreet Lakha PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 150eced51f9SBhawanpreet Lakha } 151eced51f9SBhawanpreet Lakha 152eced51f9SBhawanpreet Lakha static void hubp21_setup( 153eced51f9SBhawanpreet Lakha struct hubp *hubp, 154eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 155eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 156eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_rq_regs_st *rq_regs, 157eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 158eced51f9SBhawanpreet Lakha { 159eced51f9SBhawanpreet Lakha /* otg is locked when this func is called. Register are double buffered. 160eced51f9SBhawanpreet Lakha * disable the requestors is not needed 161eced51f9SBhawanpreet Lakha */ 162eced51f9SBhawanpreet Lakha 163eced51f9SBhawanpreet Lakha hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 164eced51f9SBhawanpreet Lakha hubp21_program_requestor(hubp, rq_regs); 165eced51f9SBhawanpreet Lakha hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 166eced51f9SBhawanpreet Lakha 167eced51f9SBhawanpreet Lakha } 168eced51f9SBhawanpreet Lakha 1691cad8ff7SEric Yang void hubp21_set_viewport( 1701cad8ff7SEric Yang struct hubp *hubp, 1711cad8ff7SEric Yang const struct rect *viewport, 1721cad8ff7SEric Yang const struct rect *viewport_c) 1731cad8ff7SEric Yang { 1741cad8ff7SEric Yang struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 1751cad8ff7SEric Yang int patched_viewport_height = 0; 1761cad8ff7SEric Yang struct dc_debug_options *debug = &hubp->ctx->dc->debug; 1771cad8ff7SEric Yang 1781cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 1791cad8ff7SEric Yang PRI_VIEWPORT_WIDTH, viewport->width, 1801cad8ff7SEric Yang PRI_VIEWPORT_HEIGHT, viewport->height); 1811cad8ff7SEric Yang 1821cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 1831cad8ff7SEric Yang PRI_VIEWPORT_X_START, viewport->x, 1841cad8ff7SEric Yang PRI_VIEWPORT_Y_START, viewport->y); 1851cad8ff7SEric Yang 1861cad8ff7SEric Yang /*for stereo*/ 1871cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 1881cad8ff7SEric Yang SEC_VIEWPORT_WIDTH, viewport->width, 1891cad8ff7SEric Yang SEC_VIEWPORT_HEIGHT, viewport->height); 1901cad8ff7SEric Yang 1911cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 1921cad8ff7SEric Yang SEC_VIEWPORT_X_START, viewport->x, 1931cad8ff7SEric Yang SEC_VIEWPORT_Y_START, viewport->y); 1941cad8ff7SEric Yang 1951cad8ff7SEric Yang /* 1961cad8ff7SEric Yang * Work around for underflow issue with NV12 + rIOMMU translation 1971cad8ff7SEric Yang * + immediate flip. This will cause hubp underflow, but will not 1981cad8ff7SEric Yang * be user visible since underflow is in blank region 1991cad8ff7SEric Yang */ 2001cad8ff7SEric Yang patched_viewport_height = viewport_c->height; 2011cad8ff7SEric Yang if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa) { 2021cad8ff7SEric Yang int pte_row_height = 0; 2031cad8ff7SEric Yang int pte_rows = 0; 2041cad8ff7SEric Yang 205db8ff9d3SJoseph Gravenor REG_GET(DCHUBP_REQ_SIZE_CONFIG_C, 206db8ff9d3SJoseph Gravenor PTE_ROW_HEIGHT_LINEAR_C, &pte_row_height); 2071cad8ff7SEric Yang 2081cad8ff7SEric Yang pte_row_height = 1 << (pte_row_height + 3); 209e6b268ddSJoseph Gravenor pte_rows = (viewport_c->height / pte_row_height) + 1; 210e6b268ddSJoseph Gravenor patched_viewport_height = pte_rows * pte_row_height + 1; 2111cad8ff7SEric Yang } 2121cad8ff7SEric Yang 2131cad8ff7SEric Yang 2141cad8ff7SEric Yang /* DC supports NV12 only at the moment */ 2151cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 2161cad8ff7SEric Yang PRI_VIEWPORT_WIDTH_C, viewport_c->width, 2171cad8ff7SEric Yang PRI_VIEWPORT_HEIGHT_C, patched_viewport_height); 2181cad8ff7SEric Yang 2191cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 2201cad8ff7SEric Yang PRI_VIEWPORT_X_START_C, viewport_c->x, 2211cad8ff7SEric Yang PRI_VIEWPORT_Y_START_C, viewport_c->y); 2221cad8ff7SEric Yang 2231cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 2241cad8ff7SEric Yang SEC_VIEWPORT_WIDTH_C, viewport_c->width, 2251cad8ff7SEric Yang SEC_VIEWPORT_HEIGHT_C, patched_viewport_height); 2261cad8ff7SEric Yang 2271cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 2281cad8ff7SEric Yang SEC_VIEWPORT_X_START_C, viewport_c->x, 2291cad8ff7SEric Yang SEC_VIEWPORT_Y_START_C, viewport_c->y); 2301cad8ff7SEric Yang } 2311cad8ff7SEric Yang 232eced51f9SBhawanpreet Lakha void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 233eced51f9SBhawanpreet Lakha struct vm_system_aperture_param *apt) 234eced51f9SBhawanpreet Lakha { 235eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 236eced51f9SBhawanpreet Lakha 237eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 238eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 239eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 240eced51f9SBhawanpreet Lakha 241eced51f9SBhawanpreet Lakha // The format of default addr is 48:12 of the 48 bit addr 242eced51f9SBhawanpreet Lakha mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 243eced51f9SBhawanpreet Lakha 244eced51f9SBhawanpreet Lakha // The format of high/low are 48:18 of the 48 bit addr 245eced51f9SBhawanpreet Lakha mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 246eced51f9SBhawanpreet Lakha mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 247eced51f9SBhawanpreet Lakha 248eced51f9SBhawanpreet Lakha REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 249eced51f9SBhawanpreet Lakha MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 250eced51f9SBhawanpreet Lakha 251eced51f9SBhawanpreet Lakha REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 252eced51f9SBhawanpreet Lakha MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 253eced51f9SBhawanpreet Lakha 254eced51f9SBhawanpreet Lakha REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 255eced51f9SBhawanpreet Lakha ENABLE_L1_TLB, 1, 256eced51f9SBhawanpreet Lakha SYSTEM_ACCESS_MODE, 0x3); 257eced51f9SBhawanpreet Lakha } 258eced51f9SBhawanpreet Lakha 259b9fe5151SJaehyun Chung void hubp21_validate_dml_output(struct hubp *hubp, 260b9fe5151SJaehyun Chung struct dc_context *ctx, 261b9fe5151SJaehyun Chung struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 262b9fe5151SJaehyun Chung struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 263b9fe5151SJaehyun Chung struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 264b9fe5151SJaehyun Chung { 265b9fe5151SJaehyun Chung struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 266b9fe5151SJaehyun Chung struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 267b9fe5151SJaehyun Chung struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 268b9fe5151SJaehyun Chung struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 269b9fe5151SJaehyun Chung DC_LOGGER_INIT(ctx->logger); 270b9fe5151SJaehyun Chung 271b9fe5151SJaehyun Chung /* Requester - Per hubp */ 272b9fe5151SJaehyun Chung REG_GET(HUBPRET_CONTROL, 273b9fe5151SJaehyun Chung DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 274b9fe5151SJaehyun Chung REG_GET_4(DCN_EXPANSION_MODE, 275b9fe5151SJaehyun Chung DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 276b9fe5151SJaehyun Chung PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 277b9fe5151SJaehyun Chung MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 278b9fe5151SJaehyun Chung CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 279b9fe5151SJaehyun Chung REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 280b9fe5151SJaehyun Chung CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 281b9fe5151SJaehyun Chung MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 282b9fe5151SJaehyun Chung META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 283b9fe5151SJaehyun Chung MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 284b9fe5151SJaehyun Chung DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 285b9fe5151SJaehyun Chung VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 286b9fe5151SJaehyun Chung SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 287b9fe5151SJaehyun Chung PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 288b9fe5151SJaehyun Chung REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, 289b9fe5151SJaehyun Chung CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 290b9fe5151SJaehyun Chung MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 291b9fe5151SJaehyun Chung META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 292b9fe5151SJaehyun Chung MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 293b9fe5151SJaehyun Chung DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 294b9fe5151SJaehyun Chung SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 295b9fe5151SJaehyun Chung PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 296b9fe5151SJaehyun Chung 297b9fe5151SJaehyun Chung if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 298b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 299b9fe5151SJaehyun Chung dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 300b9fe5151SJaehyun Chung if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 301b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 302b9fe5151SJaehyun Chung dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 303b9fe5151SJaehyun Chung if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 304b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 305b9fe5151SJaehyun Chung dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 306b9fe5151SJaehyun Chung if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 307b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 308b9fe5151SJaehyun Chung dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 309b9fe5151SJaehyun Chung if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 310b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 311b9fe5151SJaehyun Chung dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 312b9fe5151SJaehyun Chung 313b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 314b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 315b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 316b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 317b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 318b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 319b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 320b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 321b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 322b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 323b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 324b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 325b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 326b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 327b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 328b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 329b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", 330b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 331b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 332b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 333b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 334b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 335b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 336b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 337b9fe5151SJaehyun Chung 338b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 339b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 340b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 341b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 342b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 343b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 344b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 345b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 346b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 347b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 348b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 349b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 350b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 351b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 352b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 353b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 354b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 355b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 356b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 357b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 358b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 359b9fe5151SJaehyun Chung 360b9fe5151SJaehyun Chung 361b9fe5151SJaehyun Chung /* DLG - Per hubp */ 362b9fe5151SJaehyun Chung REG_GET_2(BLANK_OFFSET_0, 363b9fe5151SJaehyun Chung REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 364b9fe5151SJaehyun Chung DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 365b9fe5151SJaehyun Chung REG_GET(BLANK_OFFSET_1, 366b9fe5151SJaehyun Chung MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 367b9fe5151SJaehyun Chung REG_GET(DST_DIMENSIONS, 368b9fe5151SJaehyun Chung REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 369b9fe5151SJaehyun Chung REG_GET_2(DST_AFTER_SCALER, 370b9fe5151SJaehyun Chung REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 371b9fe5151SJaehyun Chung DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 372b9fe5151SJaehyun Chung REG_GET(REF_FREQ_TO_PIX_FREQ, 373b9fe5151SJaehyun Chung REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 374b9fe5151SJaehyun Chung 375b9fe5151SJaehyun Chung if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 376b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 377b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 378b9fe5151SJaehyun Chung if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 379b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 380b9fe5151SJaehyun Chung dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 381b9fe5151SJaehyun Chung if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 382b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 383b9fe5151SJaehyun Chung dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 384b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 385b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 386b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 387b9fe5151SJaehyun Chung if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 388b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 389b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 390b9fe5151SJaehyun Chung if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 391b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 392b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 393b9fe5151SJaehyun Chung if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 394b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 395b9fe5151SJaehyun Chung dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 396b9fe5151SJaehyun Chung 397b9fe5151SJaehyun Chung /* DLG - Per luma/chroma */ 398b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_1, 399b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 400b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_0)) 401b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_0, 402b9fe5151SJaehyun Chung DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 403b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_1)) 404b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_1, 405b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 406b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_4, 407b9fe5151SJaehyun Chung DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 408b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_5, 409b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 410b9fe5151SJaehyun Chung REG_GET_2(PER_LINE_DELIVERY, 411b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 412b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 413b9fe5151SJaehyun Chung REG_GET_2(PER_LINE_DELIVERY_PRE, 414b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 415b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 416b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_2, 417b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 418b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_2)) 419b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_2, 420b9fe5151SJaehyun Chung DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 421b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_3)) 422b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_3, 423b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 424b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_6, 425b9fe5151SJaehyun Chung DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 426b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_7, 427b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 428b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_3, 429b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 430b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_4, 431b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 432b9fe5151SJaehyun Chung 433b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 434b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 435b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 436b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 437b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 438b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 439b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 440b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 441b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 442b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 443b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 444b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 445b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 446b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 447b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 448b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 449b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 450b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 451b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 452b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 453b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 454b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 455b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 456b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 457b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 458b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 459b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 460b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 461b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 462b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 463b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 464b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 465b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 466b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 467b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 468b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 469b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 470b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 471b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 472b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 473b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 474b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 475b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 476b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 477b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 478b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 479b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 480b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 481b9fe5151SJaehyun Chung 482b9fe5151SJaehyun Chung /* TTU - per hubp */ 483b9fe5151SJaehyun Chung REG_GET_2(DCN_TTU_QOS_WM, 484b9fe5151SJaehyun Chung QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 485b9fe5151SJaehyun Chung QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 486b9fe5151SJaehyun Chung 487b9fe5151SJaehyun Chung if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 488b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 489b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 490b9fe5151SJaehyun Chung if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 491b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 492b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 493b9fe5151SJaehyun Chung 494b9fe5151SJaehyun Chung /* TTU - per luma/chroma */ 495b9fe5151SJaehyun Chung /* Assumed surf0 is luma and 1 is chroma */ 496b9fe5151SJaehyun Chung REG_GET_3(DCN_SURF0_TTU_CNTL0, 497b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 498b9fe5151SJaehyun Chung QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 499b9fe5151SJaehyun Chung QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 500b9fe5151SJaehyun Chung REG_GET_3(DCN_SURF1_TTU_CNTL0, 501b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 502b9fe5151SJaehyun Chung QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 503b9fe5151SJaehyun Chung QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 504b9fe5151SJaehyun Chung REG_GET_3(DCN_CUR0_TTU_CNTL0, 505b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 506b9fe5151SJaehyun Chung QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 507b9fe5151SJaehyun Chung QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 508b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_1, 509b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 510b9fe5151SJaehyun Chung REG_GET(DCN_CUR0_TTU_CNTL1, 511b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 512b9fe5151SJaehyun Chung REG_GET(DCN_CUR1_TTU_CNTL1, 513b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 514b9fe5151SJaehyun Chung REG_GET(DCN_SURF0_TTU_CNTL1, 515b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 516b9fe5151SJaehyun Chung REG_GET(DCN_SURF1_TTU_CNTL1, 517b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 518b9fe5151SJaehyun Chung 519b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 520b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 521b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 522b9fe5151SJaehyun Chung if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 523b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 524b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 525b9fe5151SJaehyun Chung if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 526b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 527b9fe5151SJaehyun Chung dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 528b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 529b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 530b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 531b9fe5151SJaehyun Chung if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 532b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 533b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 534b9fe5151SJaehyun Chung if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 535b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 536b9fe5151SJaehyun Chung dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 537b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 538b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 539b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 540b9fe5151SJaehyun Chung if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 541b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 542b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 543b9fe5151SJaehyun Chung if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 544b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 545b9fe5151SJaehyun Chung dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 546b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 547b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 548b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 549b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 550b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 551b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 552b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 553b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 554b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 555b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 556b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 557b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 558b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 559b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 560b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 561b9fe5151SJaehyun Chung 562b9fe5151SJaehyun Chung /* Host VM deadline regs */ 563b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_5, 564b9fe5151SJaehyun Chung REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); 565b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_6, 566b9fe5151SJaehyun Chung REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); 567b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_3, 568b9fe5151SJaehyun Chung REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); 569b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_4, 570b9fe5151SJaehyun Chung REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); 571b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_5, 572b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); 573b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_6, 574b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); 575b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_2, 576b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); 577b9fe5151SJaehyun Chung 578b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) 579b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", 580b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); 581b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) 582b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", 583b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); 584b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) 585b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", 586b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); 587b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) 588b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", 589b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); 590b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) 591b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", 592b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); 593b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) 594b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", 595b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); 596b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) 597b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", 598b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); 599b9fe5151SJaehyun Chung } 600b9fe5151SJaehyun Chung 601eced51f9SBhawanpreet Lakha void hubp21_init(struct hubp *hubp) 602eced51f9SBhawanpreet Lakha { 603eced51f9SBhawanpreet Lakha // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 604eced51f9SBhawanpreet Lakha // This is a chicken bit to enable the ECO fix. 605eced51f9SBhawanpreet Lakha 606eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 607eced51f9SBhawanpreet Lakha //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 608eced51f9SBhawanpreet Lakha REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 609eced51f9SBhawanpreet Lakha } 610eced51f9SBhawanpreet Lakha static struct hubp_funcs dcn21_hubp_funcs = { 611eced51f9SBhawanpreet Lakha .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 612eced51f9SBhawanpreet Lakha .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 613eced51f9SBhawanpreet Lakha .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 61402981b28SEric Yang .hubp_program_surface_config = hubp1_program_surface_config, 615eced51f9SBhawanpreet Lakha .hubp_is_flip_pending = hubp1_is_flip_pending, 616eced51f9SBhawanpreet Lakha .hubp_setup = hubp21_setup, 617eced51f9SBhawanpreet Lakha .hubp_setup_interdependent = hubp2_setup_interdependent, 618eced51f9SBhawanpreet Lakha .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 619eced51f9SBhawanpreet Lakha .set_blank = hubp1_set_blank, 620eced51f9SBhawanpreet Lakha .dcc_control = hubp1_dcc_control, 6211cad8ff7SEric Yang .mem_program_viewport = hubp21_set_viewport, 622eced51f9SBhawanpreet Lakha .set_cursor_attributes = hubp2_cursor_set_attributes, 623eced51f9SBhawanpreet Lakha .set_cursor_position = hubp1_cursor_set_position, 624eced51f9SBhawanpreet Lakha .hubp_clk_cntl = hubp1_clk_cntl, 625eced51f9SBhawanpreet Lakha .hubp_vtg_sel = hubp1_vtg_sel, 626eced51f9SBhawanpreet Lakha .dmdata_set_attributes = hubp2_dmdata_set_attributes, 627eced51f9SBhawanpreet Lakha .dmdata_load = hubp2_dmdata_load, 628eced51f9SBhawanpreet Lakha .dmdata_status_done = hubp2_dmdata_status_done, 629eced51f9SBhawanpreet Lakha .hubp_read_state = hubp1_read_state, 630eced51f9SBhawanpreet Lakha .hubp_clear_underflow = hubp1_clear_underflow, 631eced51f9SBhawanpreet Lakha .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 632eced51f9SBhawanpreet Lakha .hubp_init = hubp21_init, 633b9fe5151SJaehyun Chung .validate_dml_output = hubp21_validate_dml_output, 634eced51f9SBhawanpreet Lakha }; 635eced51f9SBhawanpreet Lakha 636eced51f9SBhawanpreet Lakha bool hubp21_construct( 637eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21, 638eced51f9SBhawanpreet Lakha struct dc_context *ctx, 639eced51f9SBhawanpreet Lakha uint32_t inst, 640eced51f9SBhawanpreet Lakha const struct dcn_hubp2_registers *hubp_regs, 641eced51f9SBhawanpreet Lakha const struct dcn_hubp2_shift *hubp_shift, 642eced51f9SBhawanpreet Lakha const struct dcn_hubp2_mask *hubp_mask) 643eced51f9SBhawanpreet Lakha { 644eced51f9SBhawanpreet Lakha hubp21->base.funcs = &dcn21_hubp_funcs; 645eced51f9SBhawanpreet Lakha hubp21->base.ctx = ctx; 646eced51f9SBhawanpreet Lakha hubp21->hubp_regs = hubp_regs; 647eced51f9SBhawanpreet Lakha hubp21->hubp_shift = hubp_shift; 648eced51f9SBhawanpreet Lakha hubp21->hubp_mask = hubp_mask; 649eced51f9SBhawanpreet Lakha hubp21->base.inst = inst; 650eced51f9SBhawanpreet Lakha hubp21->base.opp_id = OPP_ID_INVALID; 651eced51f9SBhawanpreet Lakha hubp21->base.mpcc_id = 0xf; 652eced51f9SBhawanpreet Lakha 653eced51f9SBhawanpreet Lakha return true; 654eced51f9SBhawanpreet Lakha } 655