1eced51f9SBhawanpreet Lakha /* 2eced51f9SBhawanpreet Lakha * Copyright 2018 Advanced Micro Devices, Inc. 3eced51f9SBhawanpreet Lakha * 4eced51f9SBhawanpreet Lakha * Permission is hereby granted, free of charge, to any person obtaining a 5eced51f9SBhawanpreet Lakha * copy of this software and associated documentation files (the "Software"), 6eced51f9SBhawanpreet Lakha * to deal in the Software without restriction, including without limitation 7eced51f9SBhawanpreet Lakha * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8eced51f9SBhawanpreet Lakha * and/or sell copies of the Software, and to permit persons to whom the 9eced51f9SBhawanpreet Lakha * Software is furnished to do so, subject to the following conditions: 10eced51f9SBhawanpreet Lakha * 11eced51f9SBhawanpreet Lakha * The above copyright notice and this permission notice shall be included in 12eced51f9SBhawanpreet Lakha * all copies or substantial portions of the Software. 13eced51f9SBhawanpreet Lakha * 14eced51f9SBhawanpreet Lakha * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15eced51f9SBhawanpreet Lakha * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16eced51f9SBhawanpreet Lakha * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17eced51f9SBhawanpreet Lakha * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18eced51f9SBhawanpreet Lakha * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19eced51f9SBhawanpreet Lakha * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20eced51f9SBhawanpreet Lakha * OTHER DEALINGS IN THE SOFTWARE. 21eced51f9SBhawanpreet Lakha * 22eced51f9SBhawanpreet Lakha * Authors: AMD 23eced51f9SBhawanpreet Lakha * 24eced51f9SBhawanpreet Lakha */ 2502981b28SEric Yang 2602981b28SEric Yang #include "dcn10/dcn10_hubp.h" 27eced51f9SBhawanpreet Lakha #include "dcn21_hubp.h" 28eced51f9SBhawanpreet Lakha 29eced51f9SBhawanpreet Lakha #include "dm_services.h" 30eced51f9SBhawanpreet Lakha #include "reg_helper.h" 31eced51f9SBhawanpreet Lakha 328c019253SYongqiang Sun #include "dc_dmub_srv.h" 338c019253SYongqiang Sun 34b9fe5151SJaehyun Chung #define DC_LOGGER_INIT(logger) 35b9fe5151SJaehyun Chung 36eced51f9SBhawanpreet Lakha #define REG(reg)\ 37eced51f9SBhawanpreet Lakha hubp21->hubp_regs->reg 38eced51f9SBhawanpreet Lakha 39eced51f9SBhawanpreet Lakha #define CTX \ 40eced51f9SBhawanpreet Lakha hubp21->base.ctx 41eced51f9SBhawanpreet Lakha 42eced51f9SBhawanpreet Lakha #undef FN 43eced51f9SBhawanpreet Lakha #define FN(reg_name, field_name) \ 44eced51f9SBhawanpreet Lakha hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 45eced51f9SBhawanpreet Lakha 46eced51f9SBhawanpreet Lakha /* 47eced51f9SBhawanpreet Lakha * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 48eced51f9SBhawanpreet Lakha * As a result, if S/W updates any of these registers during a mode change, 49eced51f9SBhawanpreet Lakha * the current frame before the mode change will use the new value right away 50eced51f9SBhawanpreet Lakha * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 51eced51f9SBhawanpreet Lakha * 52eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_GROUP_FLIP[22:0] 53eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_GROUP_VBLANK[22:0] 54eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_REQ_FLIP[22:0] 55eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_REQ_VBLANK[22:0] 56eced51f9SBhawanpreet Lakha * 57eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 58eced51f9SBhawanpreet Lakha * when flipping to a new surface 59eced51f9SBhawanpreet Lakha * 60eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 61eced51f9SBhawanpreet Lakha * during prefetch period of a frame. The prefetch starts at a pre-determined 62eced51f9SBhawanpreet Lakha * number of lines before the display active per frame 63eced51f9SBhawanpreet Lakha * 64eced51f9SBhawanpreet Lakha * DCN may underflow due to incorrectly programming these registers 65eced51f9SBhawanpreet Lakha * during VM stage of prefetch/iflip. First lines of display active 66eced51f9SBhawanpreet Lakha * or a sub-region of active using a new surface will be corrupted 67eced51f9SBhawanpreet Lakha * until the VM data returns at flip/mode change transitions 68eced51f9SBhawanpreet Lakha * 69eced51f9SBhawanpreet Lakha * Work around: 70eced51f9SBhawanpreet Lakha * workaround is always opt to use the more aggressive settings. 71eced51f9SBhawanpreet Lakha * On any mode switch, if the new reg values are smaller than the current values, 72eced51f9SBhawanpreet Lakha * then update the regs with the new values. 73eced51f9SBhawanpreet Lakha * 74eced51f9SBhawanpreet Lakha * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 75eced51f9SBhawanpreet Lakha * 76eced51f9SBhawanpreet Lakha */ 77eced51f9SBhawanpreet Lakha void apply_DEDCN21_142_wa_for_hostvm_deadline( 78eced51f9SBhawanpreet Lakha struct hubp *hubp, 79eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 80eced51f9SBhawanpreet Lakha { 81eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 8285e148fbSTony Cheng uint32_t refcyc_per_vm_group_vblank; 8385e148fbSTony Cheng uint32_t refcyc_per_vm_req_vblank; 8485e148fbSTony Cheng uint32_t refcyc_per_vm_group_flip; 8585e148fbSTony Cheng uint32_t refcyc_per_vm_req_flip; 8685e148fbSTony Cheng const uint32_t uninitialized_hw_default = 0; 87eced51f9SBhawanpreet Lakha 8885e148fbSTony Cheng REG_GET(VBLANK_PARAMETERS_5, 8985e148fbSTony Cheng REFCYC_PER_VM_GROUP_VBLANK, &refcyc_per_vm_group_vblank); 9085e148fbSTony Cheng 9185e148fbSTony Cheng if (refcyc_per_vm_group_vblank == uninitialized_hw_default || 9285e148fbSTony Cheng refcyc_per_vm_group_vblank > dlg_attr->refcyc_per_vm_group_vblank) 93eced51f9SBhawanpreet Lakha REG_SET(VBLANK_PARAMETERS_5, 0, 94eced51f9SBhawanpreet Lakha REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 95eced51f9SBhawanpreet Lakha 96eced51f9SBhawanpreet Lakha REG_GET(VBLANK_PARAMETERS_6, 9785e148fbSTony Cheng REFCYC_PER_VM_REQ_VBLANK, &refcyc_per_vm_req_vblank); 9885e148fbSTony Cheng 9985e148fbSTony Cheng if (refcyc_per_vm_req_vblank == uninitialized_hw_default || 10085e148fbSTony Cheng refcyc_per_vm_req_vblank > dlg_attr->refcyc_per_vm_req_vblank) 101eced51f9SBhawanpreet Lakha REG_SET(VBLANK_PARAMETERS_6, 0, 102eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 103eced51f9SBhawanpreet Lakha 10485e148fbSTony Cheng REG_GET(FLIP_PARAMETERS_3, 10585e148fbSTony Cheng REFCYC_PER_VM_GROUP_FLIP, &refcyc_per_vm_group_flip); 10685e148fbSTony Cheng 10785e148fbSTony Cheng if (refcyc_per_vm_group_flip == uninitialized_hw_default || 10885e148fbSTony Cheng refcyc_per_vm_group_flip > dlg_attr->refcyc_per_vm_group_flip) 109eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_3, 0, 110eced51f9SBhawanpreet Lakha REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 111eced51f9SBhawanpreet Lakha 11285e148fbSTony Cheng REG_GET(FLIP_PARAMETERS_4, 11385e148fbSTony Cheng REFCYC_PER_VM_REQ_FLIP, &refcyc_per_vm_req_flip); 11485e148fbSTony Cheng 11585e148fbSTony Cheng if (refcyc_per_vm_req_flip == uninitialized_hw_default || 11685e148fbSTony Cheng refcyc_per_vm_req_flip > dlg_attr->refcyc_per_vm_req_flip) 117eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_4, 0, 118eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 119eced51f9SBhawanpreet Lakha 120eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_5, 0, 121eced51f9SBhawanpreet Lakha REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 12285e148fbSTony Cheng 123eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_6, 0, 124eced51f9SBhawanpreet Lakha REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 125eced51f9SBhawanpreet Lakha } 126eced51f9SBhawanpreet Lakha 127eced51f9SBhawanpreet Lakha void hubp21_program_deadline( 128eced51f9SBhawanpreet Lakha struct hubp *hubp, 129eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 130eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 131eced51f9SBhawanpreet Lakha { 132eced51f9SBhawanpreet Lakha hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 133eced51f9SBhawanpreet Lakha 134eced51f9SBhawanpreet Lakha apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 135eced51f9SBhawanpreet Lakha } 136eced51f9SBhawanpreet Lakha 137eced51f9SBhawanpreet Lakha void hubp21_program_requestor( 138eced51f9SBhawanpreet Lakha struct hubp *hubp, 139eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_rq_regs_st *rq_regs) 140eced51f9SBhawanpreet Lakha { 141eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 142eced51f9SBhawanpreet Lakha 143eced51f9SBhawanpreet Lakha REG_UPDATE(HUBPRET_CONTROL, 144eced51f9SBhawanpreet Lakha DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 145eced51f9SBhawanpreet Lakha REG_SET_4(DCN_EXPANSION_MODE, 0, 146eced51f9SBhawanpreet Lakha DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 147eced51f9SBhawanpreet Lakha PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 148eced51f9SBhawanpreet Lakha MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 149eced51f9SBhawanpreet Lakha CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 150eced51f9SBhawanpreet Lakha REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 151eced51f9SBhawanpreet Lakha CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 152eced51f9SBhawanpreet Lakha MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 153eced51f9SBhawanpreet Lakha META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 154eced51f9SBhawanpreet Lakha MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 155eced51f9SBhawanpreet Lakha DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 156eced51f9SBhawanpreet Lakha VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 157eced51f9SBhawanpreet Lakha SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 158eced51f9SBhawanpreet Lakha PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 159eced51f9SBhawanpreet Lakha REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 160eced51f9SBhawanpreet Lakha CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 161eced51f9SBhawanpreet Lakha MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 162eced51f9SBhawanpreet Lakha META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 163eced51f9SBhawanpreet Lakha MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 164eced51f9SBhawanpreet Lakha DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 165eced51f9SBhawanpreet Lakha SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 166eced51f9SBhawanpreet Lakha PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 167eced51f9SBhawanpreet Lakha } 168eced51f9SBhawanpreet Lakha 169eced51f9SBhawanpreet Lakha static void hubp21_setup( 170eced51f9SBhawanpreet Lakha struct hubp *hubp, 171eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 172eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 173eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_rq_regs_st *rq_regs, 174eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 175eced51f9SBhawanpreet Lakha { 176eced51f9SBhawanpreet Lakha /* otg is locked when this func is called. Register are double buffered. 177eced51f9SBhawanpreet Lakha * disable the requestors is not needed 178eced51f9SBhawanpreet Lakha */ 179eced51f9SBhawanpreet Lakha 180eced51f9SBhawanpreet Lakha hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 181eced51f9SBhawanpreet Lakha hubp21_program_requestor(hubp, rq_regs); 182eced51f9SBhawanpreet Lakha hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 183eced51f9SBhawanpreet Lakha 184eced51f9SBhawanpreet Lakha } 185eced51f9SBhawanpreet Lakha 1861cad8ff7SEric Yang void hubp21_set_viewport( 1871cad8ff7SEric Yang struct hubp *hubp, 1881cad8ff7SEric Yang const struct rect *viewport, 189cf27a6d1SEric Yang const struct rect *viewport_c) 1901cad8ff7SEric Yang { 1911cad8ff7SEric Yang struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 1921cad8ff7SEric Yang 1931cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 1941cad8ff7SEric Yang PRI_VIEWPORT_WIDTH, viewport->width, 1951cad8ff7SEric Yang PRI_VIEWPORT_HEIGHT, viewport->height); 1961cad8ff7SEric Yang 1971cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 1981cad8ff7SEric Yang PRI_VIEWPORT_X_START, viewport->x, 1991cad8ff7SEric Yang PRI_VIEWPORT_Y_START, viewport->y); 2001cad8ff7SEric Yang 2011cad8ff7SEric Yang /*for stereo*/ 2021cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 2031cad8ff7SEric Yang SEC_VIEWPORT_WIDTH, viewport->width, 2041cad8ff7SEric Yang SEC_VIEWPORT_HEIGHT, viewport->height); 2051cad8ff7SEric Yang 2061cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 2071cad8ff7SEric Yang SEC_VIEWPORT_X_START, viewport->x, 2081cad8ff7SEric Yang SEC_VIEWPORT_Y_START, viewport->y); 2091cad8ff7SEric Yang 2101cad8ff7SEric Yang /* DC supports NV12 only at the moment */ 2111cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 2121cad8ff7SEric Yang PRI_VIEWPORT_WIDTH_C, viewport_c->width, 213cf27a6d1SEric Yang PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 2141cad8ff7SEric Yang 2151cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 2161cad8ff7SEric Yang PRI_VIEWPORT_X_START_C, viewport_c->x, 2171cad8ff7SEric Yang PRI_VIEWPORT_Y_START_C, viewport_c->y); 2181cad8ff7SEric Yang 2191cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 2201cad8ff7SEric Yang SEC_VIEWPORT_WIDTH_C, viewport_c->width, 221cf27a6d1SEric Yang SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 2221cad8ff7SEric Yang 2231cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 2241cad8ff7SEric Yang SEC_VIEWPORT_X_START_C, viewport_c->x, 2251cad8ff7SEric Yang SEC_VIEWPORT_Y_START_C, viewport_c->y); 2261cad8ff7SEric Yang } 2271cad8ff7SEric Yang 228eced51f9SBhawanpreet Lakha void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 229eced51f9SBhawanpreet Lakha struct vm_system_aperture_param *apt) 230eced51f9SBhawanpreet Lakha { 231eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 232eced51f9SBhawanpreet Lakha 233eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 234eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 235eced51f9SBhawanpreet Lakha 236eced51f9SBhawanpreet Lakha // The format of high/low are 48:18 of the 48 bit addr 237eced51f9SBhawanpreet Lakha mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 238eced51f9SBhawanpreet Lakha mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 239eced51f9SBhawanpreet Lakha 240eced51f9SBhawanpreet Lakha REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 241eced51f9SBhawanpreet Lakha MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 242eced51f9SBhawanpreet Lakha 243eced51f9SBhawanpreet Lakha REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 244eced51f9SBhawanpreet Lakha MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 245eced51f9SBhawanpreet Lakha 246eced51f9SBhawanpreet Lakha REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 247eced51f9SBhawanpreet Lakha ENABLE_L1_TLB, 1, 248eced51f9SBhawanpreet Lakha SYSTEM_ACCESS_MODE, 0x3); 249eced51f9SBhawanpreet Lakha } 250eced51f9SBhawanpreet Lakha 251b9fe5151SJaehyun Chung void hubp21_validate_dml_output(struct hubp *hubp, 252b9fe5151SJaehyun Chung struct dc_context *ctx, 253b9fe5151SJaehyun Chung struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 254b9fe5151SJaehyun Chung struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 255b9fe5151SJaehyun Chung struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 256b9fe5151SJaehyun Chung { 257b9fe5151SJaehyun Chung struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 258b9fe5151SJaehyun Chung struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 259b9fe5151SJaehyun Chung struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 260b9fe5151SJaehyun Chung struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 261b9fe5151SJaehyun Chung DC_LOGGER_INIT(ctx->logger); 262a4cea116SJaehyun Chung DC_LOG_DEBUG("DML Validation | Running Validation"); 263b9fe5151SJaehyun Chung 264b9fe5151SJaehyun Chung /* Requester - Per hubp */ 265b9fe5151SJaehyun Chung REG_GET(HUBPRET_CONTROL, 266b9fe5151SJaehyun Chung DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 267b9fe5151SJaehyun Chung REG_GET_4(DCN_EXPANSION_MODE, 268b9fe5151SJaehyun Chung DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 269b9fe5151SJaehyun Chung PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 270b9fe5151SJaehyun Chung MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 271b9fe5151SJaehyun Chung CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 272b9fe5151SJaehyun Chung REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 273b9fe5151SJaehyun Chung CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 274b9fe5151SJaehyun Chung MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 275b9fe5151SJaehyun Chung META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 276b9fe5151SJaehyun Chung MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 277b9fe5151SJaehyun Chung DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 278b9fe5151SJaehyun Chung VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 279b9fe5151SJaehyun Chung SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 280b9fe5151SJaehyun Chung PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 281b9fe5151SJaehyun Chung REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, 282b9fe5151SJaehyun Chung CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 283b9fe5151SJaehyun Chung MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 284b9fe5151SJaehyun Chung META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 285b9fe5151SJaehyun Chung MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 286b9fe5151SJaehyun Chung DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 287b9fe5151SJaehyun Chung SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 288b9fe5151SJaehyun Chung PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 289b9fe5151SJaehyun Chung 290b9fe5151SJaehyun Chung if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 291b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 292b9fe5151SJaehyun Chung dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 293b9fe5151SJaehyun Chung if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 294b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 295b9fe5151SJaehyun Chung dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 296b9fe5151SJaehyun Chung if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 297b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 298b9fe5151SJaehyun Chung dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 299b9fe5151SJaehyun Chung if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 300b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 301b9fe5151SJaehyun Chung dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 302b9fe5151SJaehyun Chung if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 303b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 304b9fe5151SJaehyun Chung dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 305b9fe5151SJaehyun Chung 306b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 307b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 308b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 309b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 310b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 311b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 312b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 313b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 314b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 315b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 316b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 317b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 318b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 319b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 320b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 321b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 322b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", 323b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 324b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 325b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 326b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 327b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 328b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 329b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 330b9fe5151SJaehyun Chung 331b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 332b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 333b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 334b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 335b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 336b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 337b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 338b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 339b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 340b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 341b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 342b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 343b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 344b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 345b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 346b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 347b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 348b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 349b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 350b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 351b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 352b9fe5151SJaehyun Chung 353b9fe5151SJaehyun Chung 354b9fe5151SJaehyun Chung /* DLG - Per hubp */ 355b9fe5151SJaehyun Chung REG_GET_2(BLANK_OFFSET_0, 356b9fe5151SJaehyun Chung REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 357b9fe5151SJaehyun Chung DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 358b9fe5151SJaehyun Chung REG_GET(BLANK_OFFSET_1, 359b9fe5151SJaehyun Chung MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 360b9fe5151SJaehyun Chung REG_GET(DST_DIMENSIONS, 361b9fe5151SJaehyun Chung REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 362b9fe5151SJaehyun Chung REG_GET_2(DST_AFTER_SCALER, 363b9fe5151SJaehyun Chung REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 364b9fe5151SJaehyun Chung DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 365b9fe5151SJaehyun Chung REG_GET(REF_FREQ_TO_PIX_FREQ, 366b9fe5151SJaehyun Chung REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 367b9fe5151SJaehyun Chung 368b9fe5151SJaehyun Chung if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 369b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 370b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 371b9fe5151SJaehyun Chung if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 372b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 373b9fe5151SJaehyun Chung dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 374b9fe5151SJaehyun Chung if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 375b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 376b9fe5151SJaehyun Chung dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 377b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 378b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 379b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 380b9fe5151SJaehyun Chung if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 381b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 382b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 383b9fe5151SJaehyun Chung if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 384b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 385b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 386b9fe5151SJaehyun Chung if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 387b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 388b9fe5151SJaehyun Chung dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 389b9fe5151SJaehyun Chung 390b9fe5151SJaehyun Chung /* DLG - Per luma/chroma */ 391b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_1, 392b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 393b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_0)) 394b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_0, 395b9fe5151SJaehyun Chung DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 396b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_1)) 397b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_1, 398b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 399b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_4, 400b9fe5151SJaehyun Chung DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 401b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_5, 402b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 403b9fe5151SJaehyun Chung REG_GET_2(PER_LINE_DELIVERY, 404b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 405b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 406b9fe5151SJaehyun Chung REG_GET_2(PER_LINE_DELIVERY_PRE, 407b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 408b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 409b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_2, 410b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 411b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_2)) 412b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_2, 413b9fe5151SJaehyun Chung DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 414b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_3)) 415b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_3, 416b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 417b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_6, 418b9fe5151SJaehyun Chung DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 419b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_7, 420b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 421b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_3, 422b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 423b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_4, 424b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 425b9fe5151SJaehyun Chung 426b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 427b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 428b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 429b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 430b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 431b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 432b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 433b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 434b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 435b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 436b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 437b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 438b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 439b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 440b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 441b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 442b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 443b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 444b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 445b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 446b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 447b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 448b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 449b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 450b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 451b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 452b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 453b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 454b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 455b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 456b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 457b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 458b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 459b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 460b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 461b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 462b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 463b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 464b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 465b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 466b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 467b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 468b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 469b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 470b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 471b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 472b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 473b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 474b9fe5151SJaehyun Chung 475b9fe5151SJaehyun Chung /* TTU - per hubp */ 476b9fe5151SJaehyun Chung REG_GET_2(DCN_TTU_QOS_WM, 477b9fe5151SJaehyun Chung QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 478b9fe5151SJaehyun Chung QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 479b9fe5151SJaehyun Chung 480b9fe5151SJaehyun Chung if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 481b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 482b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 483b9fe5151SJaehyun Chung if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 484b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 485b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 486b9fe5151SJaehyun Chung 487b9fe5151SJaehyun Chung /* TTU - per luma/chroma */ 488b9fe5151SJaehyun Chung /* Assumed surf0 is luma and 1 is chroma */ 489b9fe5151SJaehyun Chung REG_GET_3(DCN_SURF0_TTU_CNTL0, 490b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 491b9fe5151SJaehyun Chung QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 492b9fe5151SJaehyun Chung QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 493b9fe5151SJaehyun Chung REG_GET_3(DCN_SURF1_TTU_CNTL0, 494b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 495b9fe5151SJaehyun Chung QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 496b9fe5151SJaehyun Chung QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 497b9fe5151SJaehyun Chung REG_GET_3(DCN_CUR0_TTU_CNTL0, 498b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 499b9fe5151SJaehyun Chung QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 500b9fe5151SJaehyun Chung QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 501b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_1, 502b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 503b9fe5151SJaehyun Chung REG_GET(DCN_CUR0_TTU_CNTL1, 504b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 505b9fe5151SJaehyun Chung REG_GET(DCN_CUR1_TTU_CNTL1, 506b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 507b9fe5151SJaehyun Chung REG_GET(DCN_SURF0_TTU_CNTL1, 508b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 509b9fe5151SJaehyun Chung REG_GET(DCN_SURF1_TTU_CNTL1, 510b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 511b9fe5151SJaehyun Chung 512b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 513b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 514b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 515b9fe5151SJaehyun Chung if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 516b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 517b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 518b9fe5151SJaehyun Chung if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 519b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 520b9fe5151SJaehyun Chung dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 521b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 522b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 523b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 524b9fe5151SJaehyun Chung if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 525b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 526b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 527b9fe5151SJaehyun Chung if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 528b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 529b9fe5151SJaehyun Chung dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 530b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 531b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 532b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 533b9fe5151SJaehyun Chung if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 534b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 535b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 536b9fe5151SJaehyun Chung if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 537b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 538b9fe5151SJaehyun Chung dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 539b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 540b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 541b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 542b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 543b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 544b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 545b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 546b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 547b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 548b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 549b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 550b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 551b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 552b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 553b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 554b9fe5151SJaehyun Chung 555b9fe5151SJaehyun Chung /* Host VM deadline regs */ 556b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_5, 557b9fe5151SJaehyun Chung REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); 558b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_6, 559b9fe5151SJaehyun Chung REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); 560b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_3, 561b9fe5151SJaehyun Chung REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); 562b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_4, 563b9fe5151SJaehyun Chung REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); 564b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_5, 565b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); 566b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_6, 567b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); 568b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_2, 569b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); 570b9fe5151SJaehyun Chung 571b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) 572b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", 573b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); 574b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) 575b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", 576b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); 577b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) 578b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", 579b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); 580b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) 581b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", 582b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); 583b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) 584b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", 585b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); 586b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) 587b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", 588b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); 589b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) 590b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", 591b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); 592b9fe5151SJaehyun Chung } 593b9fe5151SJaehyun Chung 594bae9c49bSYongqiang Sun static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs) 59522aa5614SYongqiang Sun { 59622aa5614SYongqiang Sun struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 59722aa5614SYongqiang Sun 59822aa5614SYongqiang Sun REG_UPDATE_3(DCSURF_FLIP_CONTROL, 599bae9c49bSYongqiang Sun SURFACE_FLIP_TYPE, flip_regs->immediate, 600bae9c49bSYongqiang Sun SURFACE_FLIP_MODE_FOR_STEREOSYNC, flip_regs->grph_stereo, 601bae9c49bSYongqiang Sun SURFACE_FLIP_IN_STEREOSYNC, flip_regs->grph_stereo); 60222aa5614SYongqiang Sun 60322aa5614SYongqiang Sun REG_UPDATE(VMID_SETTINGS_0, 604bae9c49bSYongqiang Sun VMID, flip_regs->vmid); 60522aa5614SYongqiang Sun 60622aa5614SYongqiang Sun REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 607bae9c49bSYongqiang Sun PRIMARY_SURFACE_TMZ, flip_regs->tmz_surface, 608bae9c49bSYongqiang Sun PRIMARY_SURFACE_TMZ_C, flip_regs->tmz_surface, 609bae9c49bSYongqiang Sun PRIMARY_META_SURFACE_TMZ, flip_regs->tmz_surface, 610bae9c49bSYongqiang Sun PRIMARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface, 611bae9c49bSYongqiang Sun SECONDARY_SURFACE_TMZ, flip_regs->tmz_surface, 612bae9c49bSYongqiang Sun SECONDARY_SURFACE_TMZ_C, flip_regs->tmz_surface, 613bae9c49bSYongqiang Sun SECONDARY_META_SURFACE_TMZ, flip_regs->tmz_surface, 614bae9c49bSYongqiang Sun SECONDARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface); 61522aa5614SYongqiang Sun 61622aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 61722aa5614SYongqiang Sun PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 618bae9c49bSYongqiang Sun flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C); 61922aa5614SYongqiang Sun 62022aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 62122aa5614SYongqiang Sun PRIMARY_META_SURFACE_ADDRESS_C, 622bae9c49bSYongqiang Sun flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_C); 62322aa5614SYongqiang Sun 62422aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 62522aa5614SYongqiang Sun PRIMARY_META_SURFACE_ADDRESS_HIGH, 626bae9c49bSYongqiang Sun flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH); 62722aa5614SYongqiang Sun 62822aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 62922aa5614SYongqiang Sun PRIMARY_META_SURFACE_ADDRESS, 630bae9c49bSYongqiang Sun flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS); 63122aa5614SYongqiang Sun 63222aa5614SYongqiang Sun REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 63322aa5614SYongqiang Sun SECONDARY_META_SURFACE_ADDRESS_HIGH, 634bae9c49bSYongqiang Sun flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH); 63522aa5614SYongqiang Sun 63622aa5614SYongqiang Sun REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 63722aa5614SYongqiang Sun SECONDARY_META_SURFACE_ADDRESS, 638bae9c49bSYongqiang Sun flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS); 63922aa5614SYongqiang Sun 64022aa5614SYongqiang Sun 64122aa5614SYongqiang Sun REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 64222aa5614SYongqiang Sun SECONDARY_SURFACE_ADDRESS_HIGH, 643bae9c49bSYongqiang Sun flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH); 64422aa5614SYongqiang Sun 64522aa5614SYongqiang Sun REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 64622aa5614SYongqiang Sun SECONDARY_SURFACE_ADDRESS, 647bae9c49bSYongqiang Sun flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS); 64822aa5614SYongqiang Sun 64922aa5614SYongqiang Sun 65022aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 65122aa5614SYongqiang Sun PRIMARY_SURFACE_ADDRESS_HIGH_C, 652bae9c49bSYongqiang Sun flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C); 65322aa5614SYongqiang Sun 65422aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 65522aa5614SYongqiang Sun PRIMARY_SURFACE_ADDRESS_C, 656bae9c49bSYongqiang Sun flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C); 65722aa5614SYongqiang Sun 65822aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 65922aa5614SYongqiang Sun PRIMARY_SURFACE_ADDRESS_HIGH, 660bae9c49bSYongqiang Sun flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH); 66122aa5614SYongqiang Sun 66222aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 66322aa5614SYongqiang Sun PRIMARY_SURFACE_ADDRESS, 664bae9c49bSYongqiang Sun flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS); 66522aa5614SYongqiang Sun } 66622aa5614SYongqiang Sun 667bae9c49bSYongqiang Sun void dmcub_PLAT_54186_wa(struct hubp *hubp, struct surface_flip_registers *flip_regs) 66822aa5614SYongqiang Sun { 66922aa5614SYongqiang Sun struct dc_dmub_srv *dmcub = hubp->ctx->dmub_srv; 67022aa5614SYongqiang Sun struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 6710ed3bcc4SNicholas Kazlauskas union dmub_rb_cmd cmd; 672bae9c49bSYongqiang Sun 6730ed3bcc4SNicholas Kazlauskas memset(&cmd, 0, sizeof(cmd)); 6740ed3bcc4SNicholas Kazlauskas 6750ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.header.type = DMUB_CMD__PLAT_54186_WA; 6760ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.header.payload_bytes = sizeof(cmd.PLAT_54186_wa.flip); 6770ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS = 6780ed3bcc4SNicholas Kazlauskas flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS; 6790ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 6800ed3bcc4SNicholas Kazlauskas flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C; 6810ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 6820ed3bcc4SNicholas Kazlauskas flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 6830ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 6840ed3bcc4SNicholas Kazlauskas flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 6850ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.flip.flip_params.grph_stereo = flip_regs->grph_stereo; 6860ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst; 6870ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.flip.flip_params.immediate = flip_regs->immediate; 6880ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.flip.flip_params.tmz_surface = flip_regs->tmz_surface; 6890ed3bcc4SNicholas Kazlauskas cmd.PLAT_54186_wa.flip.flip_params.vmid = flip_regs->vmid; 69022aa5614SYongqiang Sun 69122aa5614SYongqiang Sun PERF_TRACE(); // TODO: remove after performance is stable. 6920ed3bcc4SNicholas Kazlauskas dc_dmub_srv_cmd_queue(dmcub, &cmd); 69322aa5614SYongqiang Sun PERF_TRACE(); // TODO: remove after performance is stable. 69422aa5614SYongqiang Sun dc_dmub_srv_cmd_execute(dmcub); 69522aa5614SYongqiang Sun PERF_TRACE(); // TODO: remove after performance is stable. 69622aa5614SYongqiang Sun dc_dmub_srv_wait_idle(dmcub); 69722aa5614SYongqiang Sun PERF_TRACE(); // TODO: remove after performance is stable. 69822aa5614SYongqiang Sun } 69922aa5614SYongqiang Sun 70022aa5614SYongqiang Sun bool hubp21_program_surface_flip_and_addr( 7018c019253SYongqiang Sun struct hubp *hubp, 7028c019253SYongqiang Sun const struct dc_plane_address *address, 7038c019253SYongqiang Sun bool flip_immediate) 7048c019253SYongqiang Sun { 705bae9c49bSYongqiang Sun struct surface_flip_registers flip_regs = { 0 }; 7068c019253SYongqiang Sun 707bae9c49bSYongqiang Sun flip_regs.vmid = address->vmid; 7088c019253SYongqiang Sun 7098c019253SYongqiang Sun switch (address->type) { 7108c019253SYongqiang Sun case PLN_ADDR_TYPE_GRAPHICS: 71122aa5614SYongqiang Sun if (address->grph.addr.quad_part == 0) { 71222aa5614SYongqiang Sun BREAK_TO_DEBUGGER(); 71322aa5614SYongqiang Sun break; 71422aa5614SYongqiang Sun } 7158c019253SYongqiang Sun 7168c019253SYongqiang Sun if (address->grph.meta_addr.quad_part != 0) { 717bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 7188c019253SYongqiang Sun address->grph.meta_addr.low_part; 719bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 7208c019253SYongqiang Sun address->grph.meta_addr.high_part; 7218c019253SYongqiang Sun } 7228c019253SYongqiang Sun 723bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 7248c019253SYongqiang Sun address->grph.addr.low_part; 725bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 7268c019253SYongqiang Sun address->grph.addr.high_part; 7278c019253SYongqiang Sun break; 7288c019253SYongqiang Sun case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 7298c019253SYongqiang Sun if (address->video_progressive.luma_addr.quad_part == 0 7308c019253SYongqiang Sun || address->video_progressive.chroma_addr.quad_part == 0) 73122aa5614SYongqiang Sun break; 7328c019253SYongqiang Sun 7338c019253SYongqiang Sun if (address->video_progressive.luma_meta_addr.quad_part != 0) { 734bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 7358c019253SYongqiang Sun address->video_progressive.luma_meta_addr.low_part; 736bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 7378c019253SYongqiang Sun address->video_progressive.luma_meta_addr.high_part; 7388c019253SYongqiang Sun 739bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 7408c019253SYongqiang Sun address->video_progressive.chroma_meta_addr.low_part; 741bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 7428c019253SYongqiang Sun address->video_progressive.chroma_meta_addr.high_part; 7438c019253SYongqiang Sun } 7448c019253SYongqiang Sun 745bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 7468c019253SYongqiang Sun address->video_progressive.luma_addr.low_part; 747bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 7488c019253SYongqiang Sun address->video_progressive.luma_addr.high_part; 7498c019253SYongqiang Sun 750bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 7518c019253SYongqiang Sun address->video_progressive.chroma_addr.low_part; 75222aa5614SYongqiang Sun 753bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 7548c019253SYongqiang Sun address->video_progressive.chroma_addr.high_part; 7558c019253SYongqiang Sun 7568c019253SYongqiang Sun break; 7578c019253SYongqiang Sun case PLN_ADDR_TYPE_GRPH_STEREO: 7588c019253SYongqiang Sun if (address->grph_stereo.left_addr.quad_part == 0) 75922aa5614SYongqiang Sun break; 7608c019253SYongqiang Sun if (address->grph_stereo.right_addr.quad_part == 0) 76122aa5614SYongqiang Sun break; 7628c019253SYongqiang Sun 763bae9c49bSYongqiang Sun flip_regs.grph_stereo = true; 7648c019253SYongqiang Sun 7658c019253SYongqiang Sun if (address->grph_stereo.right_meta_addr.quad_part != 0) { 766bae9c49bSYongqiang Sun flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS = 7678c019253SYongqiang Sun address->grph_stereo.right_meta_addr.low_part; 768bae9c49bSYongqiang Sun flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 7698c019253SYongqiang Sun address->grph_stereo.right_meta_addr.high_part; 7708c019253SYongqiang Sun } 7718c019253SYongqiang Sun 7728c019253SYongqiang Sun if (address->grph_stereo.left_meta_addr.quad_part != 0) { 773bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 7748c019253SYongqiang Sun address->grph_stereo.left_meta_addr.low_part; 775bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 7768c019253SYongqiang Sun address->grph_stereo.left_meta_addr.high_part; 7778c019253SYongqiang Sun } 7788c019253SYongqiang Sun 779bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 7808c019253SYongqiang Sun address->grph_stereo.left_addr.low_part; 781bae9c49bSYongqiang Sun flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 7828c019253SYongqiang Sun address->grph_stereo.left_addr.high_part; 7838c019253SYongqiang Sun 784bae9c49bSYongqiang Sun flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS = 7858c019253SYongqiang Sun address->grph_stereo.right_addr.low_part; 786bae9c49bSYongqiang Sun flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 7878c019253SYongqiang Sun address->grph_stereo.right_addr.high_part; 7888c019253SYongqiang Sun 7898c019253SYongqiang Sun break; 790cf27a6d1SEric Yang default: 791cf27a6d1SEric Yang BREAK_TO_DEBUGGER(); 792cf27a6d1SEric Yang break; 793cf27a6d1SEric Yang } 794cf27a6d1SEric Yang 795bae9c49bSYongqiang Sun flip_regs.tmz_surface = address->tmz_surface; 796bae9c49bSYongqiang Sun flip_regs.immediate = flip_immediate; 79722aa5614SYongqiang Sun 798bae9c49bSYongqiang Sun if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 799bae9c49bSYongqiang Sun dmcub_PLAT_54186_wa(hubp, &flip_regs); 80022aa5614SYongqiang Sun else 801bae9c49bSYongqiang Sun program_surface_flip_and_addr(hubp, &flip_regs); 80222aa5614SYongqiang Sun 803cf27a6d1SEric Yang hubp->request_address = *address; 804cf27a6d1SEric Yang 805cf27a6d1SEric Yang return true; 806cf27a6d1SEric Yang } 807cf27a6d1SEric Yang 808eced51f9SBhawanpreet Lakha void hubp21_init(struct hubp *hubp) 809eced51f9SBhawanpreet Lakha { 810eced51f9SBhawanpreet Lakha // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 811eced51f9SBhawanpreet Lakha // This is a chicken bit to enable the ECO fix. 812eced51f9SBhawanpreet Lakha 813eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 814eced51f9SBhawanpreet Lakha //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 815eced51f9SBhawanpreet Lakha REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 816eced51f9SBhawanpreet Lakha } 817eced51f9SBhawanpreet Lakha static struct hubp_funcs dcn21_hubp_funcs = { 818eced51f9SBhawanpreet Lakha .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 819eced51f9SBhawanpreet Lakha .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 820cf27a6d1SEric Yang .hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr, 82102981b28SEric Yang .hubp_program_surface_config = hubp1_program_surface_config, 822eced51f9SBhawanpreet Lakha .hubp_is_flip_pending = hubp1_is_flip_pending, 823eced51f9SBhawanpreet Lakha .hubp_setup = hubp21_setup, 824eced51f9SBhawanpreet Lakha .hubp_setup_interdependent = hubp2_setup_interdependent, 825eced51f9SBhawanpreet Lakha .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 826eced51f9SBhawanpreet Lakha .set_blank = hubp1_set_blank, 827eced51f9SBhawanpreet Lakha .dcc_control = hubp1_dcc_control, 8281cad8ff7SEric Yang .mem_program_viewport = hubp21_set_viewport, 829eced51f9SBhawanpreet Lakha .set_cursor_attributes = hubp2_cursor_set_attributes, 830eced51f9SBhawanpreet Lakha .set_cursor_position = hubp1_cursor_set_position, 831eced51f9SBhawanpreet Lakha .hubp_clk_cntl = hubp1_clk_cntl, 832eced51f9SBhawanpreet Lakha .hubp_vtg_sel = hubp1_vtg_sel, 833eced51f9SBhawanpreet Lakha .dmdata_set_attributes = hubp2_dmdata_set_attributes, 834eced51f9SBhawanpreet Lakha .dmdata_load = hubp2_dmdata_load, 835eced51f9SBhawanpreet Lakha .dmdata_status_done = hubp2_dmdata_status_done, 836eced51f9SBhawanpreet Lakha .hubp_read_state = hubp1_read_state, 837eced51f9SBhawanpreet Lakha .hubp_clear_underflow = hubp1_clear_underflow, 838eced51f9SBhawanpreet Lakha .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 839eced51f9SBhawanpreet Lakha .hubp_init = hubp21_init, 840b9fe5151SJaehyun Chung .validate_dml_output = hubp21_validate_dml_output, 841*7afa0033SQingqing Zhuo .hubp_set_flip_int = hubp1_set_flip_int, 842eced51f9SBhawanpreet Lakha }; 843eced51f9SBhawanpreet Lakha 844eced51f9SBhawanpreet Lakha bool hubp21_construct( 845eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21, 846eced51f9SBhawanpreet Lakha struct dc_context *ctx, 847eced51f9SBhawanpreet Lakha uint32_t inst, 848eced51f9SBhawanpreet Lakha const struct dcn_hubp2_registers *hubp_regs, 849eced51f9SBhawanpreet Lakha const struct dcn_hubp2_shift *hubp_shift, 850eced51f9SBhawanpreet Lakha const struct dcn_hubp2_mask *hubp_mask) 851eced51f9SBhawanpreet Lakha { 852eced51f9SBhawanpreet Lakha hubp21->base.funcs = &dcn21_hubp_funcs; 853eced51f9SBhawanpreet Lakha hubp21->base.ctx = ctx; 854eced51f9SBhawanpreet Lakha hubp21->hubp_regs = hubp_regs; 855eced51f9SBhawanpreet Lakha hubp21->hubp_shift = hubp_shift; 856eced51f9SBhawanpreet Lakha hubp21->hubp_mask = hubp_mask; 857eced51f9SBhawanpreet Lakha hubp21->base.inst = inst; 858eced51f9SBhawanpreet Lakha hubp21->base.opp_id = OPP_ID_INVALID; 859eced51f9SBhawanpreet Lakha hubp21->base.mpcc_id = 0xf; 860eced51f9SBhawanpreet Lakha 861eced51f9SBhawanpreet Lakha return true; 862eced51f9SBhawanpreet Lakha } 863