1eced51f9SBhawanpreet Lakha /* 2eced51f9SBhawanpreet Lakha * Copyright 2018 Advanced Micro Devices, Inc. 3eced51f9SBhawanpreet Lakha * 4eced51f9SBhawanpreet Lakha * Permission is hereby granted, free of charge, to any person obtaining a 5eced51f9SBhawanpreet Lakha * copy of this software and associated documentation files (the "Software"), 6eced51f9SBhawanpreet Lakha * to deal in the Software without restriction, including without limitation 7eced51f9SBhawanpreet Lakha * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8eced51f9SBhawanpreet Lakha * and/or sell copies of the Software, and to permit persons to whom the 9eced51f9SBhawanpreet Lakha * Software is furnished to do so, subject to the following conditions: 10eced51f9SBhawanpreet Lakha * 11eced51f9SBhawanpreet Lakha * The above copyright notice and this permission notice shall be included in 12eced51f9SBhawanpreet Lakha * all copies or substantial portions of the Software. 13eced51f9SBhawanpreet Lakha * 14eced51f9SBhawanpreet Lakha * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15eced51f9SBhawanpreet Lakha * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16eced51f9SBhawanpreet Lakha * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17eced51f9SBhawanpreet Lakha * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18eced51f9SBhawanpreet Lakha * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19eced51f9SBhawanpreet Lakha * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20eced51f9SBhawanpreet Lakha * OTHER DEALINGS IN THE SOFTWARE. 21eced51f9SBhawanpreet Lakha * 22eced51f9SBhawanpreet Lakha * Authors: AMD 23eced51f9SBhawanpreet Lakha * 24eced51f9SBhawanpreet Lakha */ 2502981b28SEric Yang 2602981b28SEric Yang #include "dcn10/dcn10_hubp.h" 27eced51f9SBhawanpreet Lakha #include "dcn21_hubp.h" 28eced51f9SBhawanpreet Lakha 29eced51f9SBhawanpreet Lakha #include "dm_services.h" 30eced51f9SBhawanpreet Lakha #include "reg_helper.h" 31eced51f9SBhawanpreet Lakha 328c019253SYongqiang Sun #include "dc_dmub_srv.h" 338c019253SYongqiang Sun 34b9fe5151SJaehyun Chung #define DC_LOGGER_INIT(logger) 35b9fe5151SJaehyun Chung 36eced51f9SBhawanpreet Lakha #define REG(reg)\ 37eced51f9SBhawanpreet Lakha hubp21->hubp_regs->reg 38eced51f9SBhawanpreet Lakha 39eced51f9SBhawanpreet Lakha #define CTX \ 40eced51f9SBhawanpreet Lakha hubp21->base.ctx 41eced51f9SBhawanpreet Lakha 42eced51f9SBhawanpreet Lakha #undef FN 43eced51f9SBhawanpreet Lakha #define FN(reg_name, field_name) \ 44eced51f9SBhawanpreet Lakha hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 45eced51f9SBhawanpreet Lakha 46eced51f9SBhawanpreet Lakha /* 47eced51f9SBhawanpreet Lakha * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 48eced51f9SBhawanpreet Lakha * As a result, if S/W updates any of these registers during a mode change, 49eced51f9SBhawanpreet Lakha * the current frame before the mode change will use the new value right away 50eced51f9SBhawanpreet Lakha * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 51eced51f9SBhawanpreet Lakha * 52eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_GROUP_FLIP[22:0] 53eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_GROUP_VBLANK[22:0] 54eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_REQ_FLIP[22:0] 55eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_REQ_VBLANK[22:0] 56eced51f9SBhawanpreet Lakha * 57eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 58eced51f9SBhawanpreet Lakha * when flipping to a new surface 59eced51f9SBhawanpreet Lakha * 60eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 61eced51f9SBhawanpreet Lakha * during prefetch period of a frame. The prefetch starts at a pre-determined 62eced51f9SBhawanpreet Lakha * number of lines before the display active per frame 63eced51f9SBhawanpreet Lakha * 64eced51f9SBhawanpreet Lakha * DCN may underflow due to incorrectly programming these registers 65eced51f9SBhawanpreet Lakha * during VM stage of prefetch/iflip. First lines of display active 66eced51f9SBhawanpreet Lakha * or a sub-region of active using a new surface will be corrupted 67eced51f9SBhawanpreet Lakha * until the VM data returns at flip/mode change transitions 68eced51f9SBhawanpreet Lakha * 69eced51f9SBhawanpreet Lakha * Work around: 70eced51f9SBhawanpreet Lakha * workaround is always opt to use the more aggressive settings. 71eced51f9SBhawanpreet Lakha * On any mode switch, if the new reg values are smaller than the current values, 72eced51f9SBhawanpreet Lakha * then update the regs with the new values. 73eced51f9SBhawanpreet Lakha * 74eced51f9SBhawanpreet Lakha * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 75eced51f9SBhawanpreet Lakha * 76eced51f9SBhawanpreet Lakha */ 77eced51f9SBhawanpreet Lakha void apply_DEDCN21_142_wa_for_hostvm_deadline( 78eced51f9SBhawanpreet Lakha struct hubp *hubp, 79eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 80eced51f9SBhawanpreet Lakha { 81eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 82eced51f9SBhawanpreet Lakha uint32_t cur_value; 83eced51f9SBhawanpreet Lakha 84eced51f9SBhawanpreet Lakha REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); 85eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_group_vblank) 86eced51f9SBhawanpreet Lakha REG_SET(VBLANK_PARAMETERS_5, 0, 87eced51f9SBhawanpreet Lakha REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 88eced51f9SBhawanpreet Lakha 89eced51f9SBhawanpreet Lakha REG_GET(VBLANK_PARAMETERS_6, 90eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_VBLANK, 91eced51f9SBhawanpreet Lakha &cur_value); 92eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_req_vblank) 93eced51f9SBhawanpreet Lakha REG_SET(VBLANK_PARAMETERS_6, 0, 94eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 95eced51f9SBhawanpreet Lakha 96eced51f9SBhawanpreet Lakha REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); 97eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_group_flip) 98eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_3, 0, 99eced51f9SBhawanpreet Lakha REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 100eced51f9SBhawanpreet Lakha 101eced51f9SBhawanpreet Lakha REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); 102eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_req_flip) 103eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_4, 0, 104eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 105eced51f9SBhawanpreet Lakha 106eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_5, 0, 107eced51f9SBhawanpreet Lakha REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 108eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_6, 0, 109eced51f9SBhawanpreet Lakha REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 110eced51f9SBhawanpreet Lakha } 111eced51f9SBhawanpreet Lakha 112eced51f9SBhawanpreet Lakha void hubp21_program_deadline( 113eced51f9SBhawanpreet Lakha struct hubp *hubp, 114eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 115eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 116eced51f9SBhawanpreet Lakha { 117eced51f9SBhawanpreet Lakha hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 118eced51f9SBhawanpreet Lakha 119eced51f9SBhawanpreet Lakha apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 120eced51f9SBhawanpreet Lakha } 121eced51f9SBhawanpreet Lakha 122eced51f9SBhawanpreet Lakha void hubp21_program_requestor( 123eced51f9SBhawanpreet Lakha struct hubp *hubp, 124eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_rq_regs_st *rq_regs) 125eced51f9SBhawanpreet Lakha { 126eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 127eced51f9SBhawanpreet Lakha 128eced51f9SBhawanpreet Lakha REG_UPDATE(HUBPRET_CONTROL, 129eced51f9SBhawanpreet Lakha DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 130eced51f9SBhawanpreet Lakha REG_SET_4(DCN_EXPANSION_MODE, 0, 131eced51f9SBhawanpreet Lakha DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 132eced51f9SBhawanpreet Lakha PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 133eced51f9SBhawanpreet Lakha MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 134eced51f9SBhawanpreet Lakha CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 135eced51f9SBhawanpreet Lakha REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 136eced51f9SBhawanpreet Lakha CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 137eced51f9SBhawanpreet Lakha MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 138eced51f9SBhawanpreet Lakha META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 139eced51f9SBhawanpreet Lakha MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 140eced51f9SBhawanpreet Lakha DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 141eced51f9SBhawanpreet Lakha VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 142eced51f9SBhawanpreet Lakha SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 143eced51f9SBhawanpreet Lakha PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 144eced51f9SBhawanpreet Lakha REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 145eced51f9SBhawanpreet Lakha CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 146eced51f9SBhawanpreet Lakha MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 147eced51f9SBhawanpreet Lakha META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 148eced51f9SBhawanpreet Lakha MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 149eced51f9SBhawanpreet Lakha DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 150eced51f9SBhawanpreet Lakha SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 151eced51f9SBhawanpreet Lakha PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 152eced51f9SBhawanpreet Lakha } 153eced51f9SBhawanpreet Lakha 154eced51f9SBhawanpreet Lakha static void hubp21_setup( 155eced51f9SBhawanpreet Lakha struct hubp *hubp, 156eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 157eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 158eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_rq_regs_st *rq_regs, 159eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 160eced51f9SBhawanpreet Lakha { 161eced51f9SBhawanpreet Lakha /* otg is locked when this func is called. Register are double buffered. 162eced51f9SBhawanpreet Lakha * disable the requestors is not needed 163eced51f9SBhawanpreet Lakha */ 164eced51f9SBhawanpreet Lakha 165eced51f9SBhawanpreet Lakha hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 166eced51f9SBhawanpreet Lakha hubp21_program_requestor(hubp, rq_regs); 167eced51f9SBhawanpreet Lakha hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 168eced51f9SBhawanpreet Lakha 169eced51f9SBhawanpreet Lakha } 170eced51f9SBhawanpreet Lakha 1711cad8ff7SEric Yang void hubp21_set_viewport( 1721cad8ff7SEric Yang struct hubp *hubp, 1731cad8ff7SEric Yang const struct rect *viewport, 174cf27a6d1SEric Yang const struct rect *viewport_c) 1751cad8ff7SEric Yang { 1761cad8ff7SEric Yang struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 1771cad8ff7SEric Yang 1781cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 1791cad8ff7SEric Yang PRI_VIEWPORT_WIDTH, viewport->width, 1801cad8ff7SEric Yang PRI_VIEWPORT_HEIGHT, viewport->height); 1811cad8ff7SEric Yang 1821cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 1831cad8ff7SEric Yang PRI_VIEWPORT_X_START, viewport->x, 1841cad8ff7SEric Yang PRI_VIEWPORT_Y_START, viewport->y); 1851cad8ff7SEric Yang 1861cad8ff7SEric Yang /*for stereo*/ 1871cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 1881cad8ff7SEric Yang SEC_VIEWPORT_WIDTH, viewport->width, 1891cad8ff7SEric Yang SEC_VIEWPORT_HEIGHT, viewport->height); 1901cad8ff7SEric Yang 1911cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 1921cad8ff7SEric Yang SEC_VIEWPORT_X_START, viewport->x, 1931cad8ff7SEric Yang SEC_VIEWPORT_Y_START, viewport->y); 1941cad8ff7SEric Yang 1951cad8ff7SEric Yang /* DC supports NV12 only at the moment */ 1961cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 1971cad8ff7SEric Yang PRI_VIEWPORT_WIDTH_C, viewport_c->width, 198cf27a6d1SEric Yang PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 1991cad8ff7SEric Yang 2001cad8ff7SEric Yang REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 2011cad8ff7SEric Yang PRI_VIEWPORT_X_START_C, viewport_c->x, 2021cad8ff7SEric Yang PRI_VIEWPORT_Y_START_C, viewport_c->y); 2031cad8ff7SEric Yang 2041cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 2051cad8ff7SEric Yang SEC_VIEWPORT_WIDTH_C, viewport_c->width, 206cf27a6d1SEric Yang SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 2071cad8ff7SEric Yang 2081cad8ff7SEric Yang REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 2091cad8ff7SEric Yang SEC_VIEWPORT_X_START_C, viewport_c->x, 2101cad8ff7SEric Yang SEC_VIEWPORT_Y_START_C, viewport_c->y); 2111cad8ff7SEric Yang } 2121cad8ff7SEric Yang 213cf27a6d1SEric Yang static void hubp21_apply_PLAT_54186_wa( 214cf27a6d1SEric Yang struct hubp *hubp, 215cf27a6d1SEric Yang const struct dc_plane_address *address) 216cf27a6d1SEric Yang { 217cf27a6d1SEric Yang struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 218cf27a6d1SEric Yang struct dc_debug_options *debug = &hubp->ctx->dc->debug; 219cf27a6d1SEric Yang unsigned int chroma_bpe = 2; 220cf27a6d1SEric Yang unsigned int luma_addr_high_part = 0; 221cf27a6d1SEric Yang unsigned int row_height = 0; 222cf27a6d1SEric Yang unsigned int chroma_pitch = 0; 223cf27a6d1SEric Yang unsigned int viewport_c_height = 0; 224cf27a6d1SEric Yang unsigned int viewport_c_width = 0; 225cf27a6d1SEric Yang unsigned int patched_viewport_height = 0; 226cf27a6d1SEric Yang unsigned int patched_viewport_width = 0; 227cf27a6d1SEric Yang unsigned int rotation_angle = 0; 228cf27a6d1SEric Yang unsigned int pix_format = 0; 229cf27a6d1SEric Yang unsigned int h_mirror_en = 0; 230cf27a6d1SEric Yang unsigned int tile_blk_size = 64 * 1024; /* 64KB for 64KB SW, 4KB for 4KB SW */ 231cf27a6d1SEric Yang 232cf27a6d1SEric Yang 233cf27a6d1SEric Yang if (!debug->nv12_iflip_vm_wa) 234cf27a6d1SEric Yang return; 235cf27a6d1SEric Yang 236cf27a6d1SEric Yang REG_GET(DCHUBP_REQ_SIZE_CONFIG_C, 237cf27a6d1SEric Yang PTE_ROW_HEIGHT_LINEAR_C, &row_height); 238cf27a6d1SEric Yang 239cf27a6d1SEric Yang REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 240cf27a6d1SEric Yang PRI_VIEWPORT_WIDTH_C, &viewport_c_width, 241cf27a6d1SEric Yang PRI_VIEWPORT_HEIGHT_C, &viewport_c_height); 242cf27a6d1SEric Yang 243cf27a6d1SEric Yang REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 244cf27a6d1SEric Yang PRIMARY_SURFACE_ADDRESS_HIGH_C, &luma_addr_high_part); 245cf27a6d1SEric Yang 246cf27a6d1SEric Yang REG_GET(DCSURF_SURFACE_PITCH_C, 247cf27a6d1SEric Yang PITCH_C, &chroma_pitch); 248cf27a6d1SEric Yang 249cf27a6d1SEric Yang chroma_pitch += 1; 250cf27a6d1SEric Yang 251cf27a6d1SEric Yang REG_GET_3(DCSURF_SURFACE_CONFIG, 252cf27a6d1SEric Yang SURFACE_PIXEL_FORMAT, &pix_format, 253cf27a6d1SEric Yang ROTATION_ANGLE, &rotation_angle, 254cf27a6d1SEric Yang H_MIRROR_EN, &h_mirror_en); 255cf27a6d1SEric Yang 25693a8955bSEric Yang /* reset persistent cached data */ 25793a8955bSEric Yang hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 25893a8955bSEric Yang /* apply wa only for NV12 surface with scatter gather enabled with viewport > 512 along 25993a8955bSEric Yang * the vertical direction*/ 260cf27a6d1SEric Yang if (address->type != PLN_ADDR_TYPE_VIDEO_PROGRESSIVE || 26193a8955bSEric Yang address->video_progressive.luma_addr.high_part == 0xf4) 26293a8955bSEric Yang return; 26393a8955bSEric Yang 26493a8955bSEric Yang if ((rotation_angle == 0 || rotation_angle == 180) 26593a8955bSEric Yang && viewport_c_height <= 512) 26693a8955bSEric Yang return; 26793a8955bSEric Yang 26893a8955bSEric Yang if ((rotation_angle == 90 || rotation_angle == 270) 26993a8955bSEric Yang && viewport_c_width <= 512) 270cf27a6d1SEric Yang return; 271cf27a6d1SEric Yang 272cf27a6d1SEric Yang switch (rotation_angle) { 273cf27a6d1SEric Yang case 0: /* 0 degree rotation */ 274cf27a6d1SEric Yang row_height = 128; 275cf27a6d1SEric Yang patched_viewport_height = (viewport_c_height / row_height + 1) * row_height + 1; 276cf27a6d1SEric Yang patched_viewport_width = viewport_c_width; 277cf27a6d1SEric Yang hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 278cf27a6d1SEric Yang break; 279cf27a6d1SEric Yang case 2: /* 180 degree rotation */ 280cf27a6d1SEric Yang row_height = 128; 281cf27a6d1SEric Yang patched_viewport_height = viewport_c_height + row_height; 282cf27a6d1SEric Yang patched_viewport_width = viewport_c_width; 283cf27a6d1SEric Yang hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - chroma_pitch * row_height * chroma_bpe; 284cf27a6d1SEric Yang break; 285cf27a6d1SEric Yang case 1: /* 90 degree rotation */ 286cf27a6d1SEric Yang row_height = 256; 287cf27a6d1SEric Yang if (h_mirror_en) { 288cf27a6d1SEric Yang patched_viewport_height = viewport_c_height; 289cf27a6d1SEric Yang patched_viewport_width = viewport_c_width + row_height; 290cf27a6d1SEric Yang hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 291cf27a6d1SEric Yang } else { 292cf27a6d1SEric Yang patched_viewport_height = viewport_c_height; 293cf27a6d1SEric Yang patched_viewport_width = viewport_c_width + row_height; 294cf27a6d1SEric Yang hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size; 295cf27a6d1SEric Yang } 296cf27a6d1SEric Yang break; 297cf27a6d1SEric Yang case 3: /* 270 degree rotation */ 298cf27a6d1SEric Yang row_height = 256; 299cf27a6d1SEric Yang if (h_mirror_en) { 300cf27a6d1SEric Yang patched_viewport_height = viewport_c_height; 301cf27a6d1SEric Yang patched_viewport_width = viewport_c_width + row_height; 302cf27a6d1SEric Yang hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size; 303cf27a6d1SEric Yang } else { 304cf27a6d1SEric Yang patched_viewport_height = viewport_c_height; 305cf27a6d1SEric Yang patched_viewport_width = viewport_c_width + row_height; 306cf27a6d1SEric Yang hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 307cf27a6d1SEric Yang } 308cf27a6d1SEric Yang break; 309cf27a6d1SEric Yang default: 310cf27a6d1SEric Yang ASSERT(0); 311cf27a6d1SEric Yang break; 312cf27a6d1SEric Yang } 313cf27a6d1SEric Yang 314cf27a6d1SEric Yang /* catch cases where viewport keep growing */ 315cf27a6d1SEric Yang ASSERT(patched_viewport_height && patched_viewport_height < 5000); 316cf27a6d1SEric Yang ASSERT(patched_viewport_width && patched_viewport_width < 5000); 317cf27a6d1SEric Yang 318cf27a6d1SEric Yang REG_UPDATE_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 319cf27a6d1SEric Yang PRI_VIEWPORT_WIDTH_C, patched_viewport_width, 320cf27a6d1SEric Yang PRI_VIEWPORT_HEIGHT_C, patched_viewport_height); 321cf27a6d1SEric Yang } 322cf27a6d1SEric Yang 323eced51f9SBhawanpreet Lakha void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 324eced51f9SBhawanpreet Lakha struct vm_system_aperture_param *apt) 325eced51f9SBhawanpreet Lakha { 326eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 327eced51f9SBhawanpreet Lakha 328eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 329eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 330eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 331eced51f9SBhawanpreet Lakha 332eced51f9SBhawanpreet Lakha // The format of default addr is 48:12 of the 48 bit addr 333eced51f9SBhawanpreet Lakha mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 334eced51f9SBhawanpreet Lakha 335eced51f9SBhawanpreet Lakha // The format of high/low are 48:18 of the 48 bit addr 336eced51f9SBhawanpreet Lakha mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 337eced51f9SBhawanpreet Lakha mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 338eced51f9SBhawanpreet Lakha 339eced51f9SBhawanpreet Lakha REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 340eced51f9SBhawanpreet Lakha MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 341eced51f9SBhawanpreet Lakha 342eced51f9SBhawanpreet Lakha REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 343eced51f9SBhawanpreet Lakha MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 344eced51f9SBhawanpreet Lakha 345eced51f9SBhawanpreet Lakha REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 346eced51f9SBhawanpreet Lakha ENABLE_L1_TLB, 1, 347eced51f9SBhawanpreet Lakha SYSTEM_ACCESS_MODE, 0x3); 348eced51f9SBhawanpreet Lakha } 349eced51f9SBhawanpreet Lakha 350b9fe5151SJaehyun Chung void hubp21_validate_dml_output(struct hubp *hubp, 351b9fe5151SJaehyun Chung struct dc_context *ctx, 352b9fe5151SJaehyun Chung struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 353b9fe5151SJaehyun Chung struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 354b9fe5151SJaehyun Chung struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 355b9fe5151SJaehyun Chung { 356b9fe5151SJaehyun Chung struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 357b9fe5151SJaehyun Chung struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 358b9fe5151SJaehyun Chung struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 359b9fe5151SJaehyun Chung struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 360b9fe5151SJaehyun Chung DC_LOGGER_INIT(ctx->logger); 361a4cea116SJaehyun Chung DC_LOG_DEBUG("DML Validation | Running Validation"); 362b9fe5151SJaehyun Chung 363b9fe5151SJaehyun Chung /* Requester - Per hubp */ 364b9fe5151SJaehyun Chung REG_GET(HUBPRET_CONTROL, 365b9fe5151SJaehyun Chung DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 366b9fe5151SJaehyun Chung REG_GET_4(DCN_EXPANSION_MODE, 367b9fe5151SJaehyun Chung DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 368b9fe5151SJaehyun Chung PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 369b9fe5151SJaehyun Chung MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 370b9fe5151SJaehyun Chung CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 371b9fe5151SJaehyun Chung REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 372b9fe5151SJaehyun Chung CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 373b9fe5151SJaehyun Chung MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 374b9fe5151SJaehyun Chung META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 375b9fe5151SJaehyun Chung MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 376b9fe5151SJaehyun Chung DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 377b9fe5151SJaehyun Chung VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 378b9fe5151SJaehyun Chung SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 379b9fe5151SJaehyun Chung PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 380b9fe5151SJaehyun Chung REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, 381b9fe5151SJaehyun Chung CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 382b9fe5151SJaehyun Chung MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 383b9fe5151SJaehyun Chung META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 384b9fe5151SJaehyun Chung MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 385b9fe5151SJaehyun Chung DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 386b9fe5151SJaehyun Chung SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 387b9fe5151SJaehyun Chung PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 388b9fe5151SJaehyun Chung 389b9fe5151SJaehyun Chung if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 390b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 391b9fe5151SJaehyun Chung dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 392b9fe5151SJaehyun Chung if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 393b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 394b9fe5151SJaehyun Chung dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 395b9fe5151SJaehyun Chung if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 396b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 397b9fe5151SJaehyun Chung dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 398b9fe5151SJaehyun Chung if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 399b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 400b9fe5151SJaehyun Chung dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 401b9fe5151SJaehyun Chung if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 402b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 403b9fe5151SJaehyun Chung dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 404b9fe5151SJaehyun Chung 405b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 406b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 407b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 408b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 409b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 410b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 411b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 412b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 413b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 414b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 415b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 416b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 417b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 418b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 419b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 420b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 421b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", 422b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 423b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 424b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 425b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 426b9fe5151SJaehyun Chung if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 427b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 428b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 429b9fe5151SJaehyun Chung 430b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 431b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 432b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 433b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 434b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 435b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 436b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 437b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 438b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 439b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 440b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 441b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 442b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 443b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 444b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 445b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 446b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 447b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 448b9fe5151SJaehyun Chung if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 449b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 450b9fe5151SJaehyun Chung dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 451b9fe5151SJaehyun Chung 452b9fe5151SJaehyun Chung 453b9fe5151SJaehyun Chung /* DLG - Per hubp */ 454b9fe5151SJaehyun Chung REG_GET_2(BLANK_OFFSET_0, 455b9fe5151SJaehyun Chung REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 456b9fe5151SJaehyun Chung DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 457b9fe5151SJaehyun Chung REG_GET(BLANK_OFFSET_1, 458b9fe5151SJaehyun Chung MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 459b9fe5151SJaehyun Chung REG_GET(DST_DIMENSIONS, 460b9fe5151SJaehyun Chung REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 461b9fe5151SJaehyun Chung REG_GET_2(DST_AFTER_SCALER, 462b9fe5151SJaehyun Chung REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 463b9fe5151SJaehyun Chung DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 464b9fe5151SJaehyun Chung REG_GET(REF_FREQ_TO_PIX_FREQ, 465b9fe5151SJaehyun Chung REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 466b9fe5151SJaehyun Chung 467b9fe5151SJaehyun Chung if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 468b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 469b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 470b9fe5151SJaehyun Chung if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 471b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 472b9fe5151SJaehyun Chung dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 473b9fe5151SJaehyun Chung if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 474b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 475b9fe5151SJaehyun Chung dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 476b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 477b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 478b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 479b9fe5151SJaehyun Chung if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 480b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 481b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 482b9fe5151SJaehyun Chung if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 483b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 484b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 485b9fe5151SJaehyun Chung if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 486b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 487b9fe5151SJaehyun Chung dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 488b9fe5151SJaehyun Chung 489b9fe5151SJaehyun Chung /* DLG - Per luma/chroma */ 490b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_1, 491b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 492b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_0)) 493b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_0, 494b9fe5151SJaehyun Chung DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 495b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_1)) 496b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_1, 497b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 498b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_4, 499b9fe5151SJaehyun Chung DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 500b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_5, 501b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 502b9fe5151SJaehyun Chung REG_GET_2(PER_LINE_DELIVERY, 503b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 504b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 505b9fe5151SJaehyun Chung REG_GET_2(PER_LINE_DELIVERY_PRE, 506b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 507b9fe5151SJaehyun Chung REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 508b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_2, 509b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 510b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_2)) 511b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_2, 512b9fe5151SJaehyun Chung DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 513b9fe5151SJaehyun Chung if (REG(NOM_PARAMETERS_3)) 514b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_3, 515b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 516b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_6, 517b9fe5151SJaehyun Chung DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 518b9fe5151SJaehyun Chung REG_GET(NOM_PARAMETERS_7, 519b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 520b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_3, 521b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 522b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_4, 523b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 524b9fe5151SJaehyun Chung 525b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 526b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 527b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 528b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 529b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 530b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 531b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 532b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 533b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 534b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 535b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 536b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 537b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 538b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 539b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 540b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 541b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 542b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 543b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 544b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 545b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 546b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 547b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 548b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 549b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 550b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 551b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 552b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 553b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 554b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 555b9fe5151SJaehyun Chung if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 556b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 557b9fe5151SJaehyun Chung dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 558b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 559b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 560b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 561b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 562b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 563b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 564b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 565b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 566b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 567b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 568b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 569b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 570b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 571b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 572b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 573b9fe5151SJaehyun Chung 574b9fe5151SJaehyun Chung /* TTU - per hubp */ 575b9fe5151SJaehyun Chung REG_GET_2(DCN_TTU_QOS_WM, 576b9fe5151SJaehyun Chung QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 577b9fe5151SJaehyun Chung QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 578b9fe5151SJaehyun Chung 579b9fe5151SJaehyun Chung if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 580b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 581b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 582b9fe5151SJaehyun Chung if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 583b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 584b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 585b9fe5151SJaehyun Chung 586b9fe5151SJaehyun Chung /* TTU - per luma/chroma */ 587b9fe5151SJaehyun Chung /* Assumed surf0 is luma and 1 is chroma */ 588b9fe5151SJaehyun Chung REG_GET_3(DCN_SURF0_TTU_CNTL0, 589b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 590b9fe5151SJaehyun Chung QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 591b9fe5151SJaehyun Chung QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 592b9fe5151SJaehyun Chung REG_GET_3(DCN_SURF1_TTU_CNTL0, 593b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 594b9fe5151SJaehyun Chung QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 595b9fe5151SJaehyun Chung QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 596b9fe5151SJaehyun Chung REG_GET_3(DCN_CUR0_TTU_CNTL0, 597b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 598b9fe5151SJaehyun Chung QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 599b9fe5151SJaehyun Chung QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 600b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_1, 601b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 602b9fe5151SJaehyun Chung REG_GET(DCN_CUR0_TTU_CNTL1, 603b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 604b9fe5151SJaehyun Chung REG_GET(DCN_CUR1_TTU_CNTL1, 605b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 606b9fe5151SJaehyun Chung REG_GET(DCN_SURF0_TTU_CNTL1, 607b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 608b9fe5151SJaehyun Chung REG_GET(DCN_SURF1_TTU_CNTL1, 609b9fe5151SJaehyun Chung REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 610b9fe5151SJaehyun Chung 611b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 612b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 613b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 614b9fe5151SJaehyun Chung if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 615b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 616b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 617b9fe5151SJaehyun Chung if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 618b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 619b9fe5151SJaehyun Chung dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 620b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 621b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 622b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 623b9fe5151SJaehyun Chung if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 624b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 625b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 626b9fe5151SJaehyun Chung if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 627b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 628b9fe5151SJaehyun Chung dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 629b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 630b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 631b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 632b9fe5151SJaehyun Chung if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 633b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 634b9fe5151SJaehyun Chung dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 635b9fe5151SJaehyun Chung if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 636b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 637b9fe5151SJaehyun Chung dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 638b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 639b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 640b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 641b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 642b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 643b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 644b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 645b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 646b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 647b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 648b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 649b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 650b9fe5151SJaehyun Chung if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 651b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 652b9fe5151SJaehyun Chung dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 653b9fe5151SJaehyun Chung 654b9fe5151SJaehyun Chung /* Host VM deadline regs */ 655b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_5, 656b9fe5151SJaehyun Chung REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); 657b9fe5151SJaehyun Chung REG_GET(VBLANK_PARAMETERS_6, 658b9fe5151SJaehyun Chung REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); 659b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_3, 660b9fe5151SJaehyun Chung REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); 661b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_4, 662b9fe5151SJaehyun Chung REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); 663b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_5, 664b9fe5151SJaehyun Chung REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); 665b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_6, 666b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); 667b9fe5151SJaehyun Chung REG_GET(FLIP_PARAMETERS_2, 668b9fe5151SJaehyun Chung REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); 669b9fe5151SJaehyun Chung 670b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) 671b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", 672b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); 673b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) 674b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", 675b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); 676b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) 677b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", 678b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); 679b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) 680b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", 681b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); 682b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) 683b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", 684b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); 685b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) 686b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", 687b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); 688b9fe5151SJaehyun Chung if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) 689b9fe5151SJaehyun Chung DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", 690b9fe5151SJaehyun Chung dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); 691b9fe5151SJaehyun Chung } 692b9fe5151SJaehyun Chung 69322aa5614SYongqiang Sun static void program_surface_flip_and_addr(struct hubp *hubp, struct dmub_rb_cmd_flip *surface_flip) 69422aa5614SYongqiang Sun { 69522aa5614SYongqiang Sun struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 69622aa5614SYongqiang Sun 69722aa5614SYongqiang Sun REG_UPDATE_3(DCSURF_FLIP_CONTROL, 69822aa5614SYongqiang Sun SURFACE_FLIP_TYPE, surface_flip->flip.flip_params.immediate, 69922aa5614SYongqiang Sun SURFACE_FLIP_MODE_FOR_STEREOSYNC, surface_flip->flip.flip_params.grph_stereo, 70022aa5614SYongqiang Sun SURFACE_FLIP_IN_STEREOSYNC, surface_flip->flip.flip_params.grph_stereo); 70122aa5614SYongqiang Sun 70222aa5614SYongqiang Sun REG_UPDATE(VMID_SETTINGS_0, 70322aa5614SYongqiang Sun VMID, surface_flip->flip.flip_params.vmid); 70422aa5614SYongqiang Sun 70522aa5614SYongqiang Sun REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 70622aa5614SYongqiang Sun PRIMARY_SURFACE_TMZ, surface_flip->flip.flip_params.tmz_surface, 70722aa5614SYongqiang Sun PRIMARY_SURFACE_TMZ_C, surface_flip->flip.flip_params.tmz_surface, 70822aa5614SYongqiang Sun PRIMARY_META_SURFACE_TMZ, surface_flip->flip.flip_params.tmz_surface, 70922aa5614SYongqiang Sun PRIMARY_META_SURFACE_TMZ_C, surface_flip->flip.flip_params.tmz_surface, 71022aa5614SYongqiang Sun SECONDARY_SURFACE_TMZ, surface_flip->flip.flip_params.tmz_surface, 71122aa5614SYongqiang Sun SECONDARY_SURFACE_TMZ_C, surface_flip->flip.flip_params.tmz_surface, 71222aa5614SYongqiang Sun SECONDARY_META_SURFACE_TMZ, surface_flip->flip.flip_params.tmz_surface, 71322aa5614SYongqiang Sun SECONDARY_META_SURFACE_TMZ_C, surface_flip->flip.flip_params.tmz_surface); 71422aa5614SYongqiang Sun 71522aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 71622aa5614SYongqiang Sun PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 71722aa5614SYongqiang Sun surface_flip->flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C); 71822aa5614SYongqiang Sun 71922aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 72022aa5614SYongqiang Sun PRIMARY_META_SURFACE_ADDRESS_C, 72122aa5614SYongqiang Sun surface_flip->flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C); 72222aa5614SYongqiang Sun 72322aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 72422aa5614SYongqiang Sun PRIMARY_META_SURFACE_ADDRESS_HIGH, 72522aa5614SYongqiang Sun surface_flip->flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH); 72622aa5614SYongqiang Sun 72722aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 72822aa5614SYongqiang Sun PRIMARY_META_SURFACE_ADDRESS, 72922aa5614SYongqiang Sun surface_flip->flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS); 73022aa5614SYongqiang Sun 73122aa5614SYongqiang Sun REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 73222aa5614SYongqiang Sun SECONDARY_META_SURFACE_ADDRESS_HIGH, 73322aa5614SYongqiang Sun surface_flip->flip.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH); 73422aa5614SYongqiang Sun 73522aa5614SYongqiang Sun REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 73622aa5614SYongqiang Sun SECONDARY_META_SURFACE_ADDRESS, 73722aa5614SYongqiang Sun surface_flip->flip.DCSURF_SECONDARY_META_SURFACE_ADDRESS); 73822aa5614SYongqiang Sun 73922aa5614SYongqiang Sun 74022aa5614SYongqiang Sun REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 74122aa5614SYongqiang Sun SECONDARY_SURFACE_ADDRESS_HIGH, 74222aa5614SYongqiang Sun surface_flip->flip.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH); 74322aa5614SYongqiang Sun 74422aa5614SYongqiang Sun REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 74522aa5614SYongqiang Sun SECONDARY_SURFACE_ADDRESS, 74622aa5614SYongqiang Sun surface_flip->flip.DCSURF_SECONDARY_SURFACE_ADDRESS); 74722aa5614SYongqiang Sun 74822aa5614SYongqiang Sun 74922aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 75022aa5614SYongqiang Sun PRIMARY_SURFACE_ADDRESS_HIGH_C, 75122aa5614SYongqiang Sun surface_flip->flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C); 75222aa5614SYongqiang Sun 75322aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 75422aa5614SYongqiang Sun PRIMARY_SURFACE_ADDRESS_C, 75522aa5614SYongqiang Sun surface_flip->flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C); 75622aa5614SYongqiang Sun 75722aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 75822aa5614SYongqiang Sun PRIMARY_SURFACE_ADDRESS_HIGH, 75922aa5614SYongqiang Sun surface_flip->flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH); 76022aa5614SYongqiang Sun 76122aa5614SYongqiang Sun REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 76222aa5614SYongqiang Sun PRIMARY_SURFACE_ADDRESS, 76322aa5614SYongqiang Sun surface_flip->flip.DCSURF_PRIMARY_SURFACE_ADDRESS); 76422aa5614SYongqiang Sun } 76522aa5614SYongqiang Sun 76622aa5614SYongqiang Sun void program_surface_flip_and_addr_dmcub(struct hubp *hubp, struct dmub_rb_cmd_flip *surface_flip) 76722aa5614SYongqiang Sun { 76822aa5614SYongqiang Sun struct dc_dmub_srv *dmcub = hubp->ctx->dmub_srv; 76922aa5614SYongqiang Sun struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 77022aa5614SYongqiang Sun 77122aa5614SYongqiang Sun PERF_TRACE(); // TODO: remove after performance is stable. 77222aa5614SYongqiang Sun dc_dmub_srv_cmd_queue(dmcub, &surface_flip->header); 77322aa5614SYongqiang Sun PERF_TRACE(); // TODO: remove after performance is stable. 77422aa5614SYongqiang Sun dc_dmub_srv_cmd_execute(dmcub); 77522aa5614SYongqiang Sun PERF_TRACE(); // TODO: remove after performance is stable. 77622aa5614SYongqiang Sun dc_dmub_srv_wait_idle(dmcub); 77722aa5614SYongqiang Sun PERF_TRACE(); // TODO: remove after performance is stable. 77822aa5614SYongqiang Sun } 77922aa5614SYongqiang Sun 78022aa5614SYongqiang Sun bool hubp21_program_surface_flip_and_addr( 7818c019253SYongqiang Sun struct hubp *hubp, 7828c019253SYongqiang Sun const struct dc_plane_address *address, 7838c019253SYongqiang Sun bool flip_immediate) 7848c019253SYongqiang Sun { 7858c019253SYongqiang Sun struct dmub_rb_cmd_flip surface_flip = { 0 }; 78622aa5614SYongqiang Sun bool grph_stereo = false; 78722aa5614SYongqiang Sun struct dc_debug_options *debug = &hubp->ctx->dc->debug; 78822aa5614SYongqiang Sun struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 7898c019253SYongqiang Sun 7908c019253SYongqiang Sun surface_flip.header.type = DMUB_CMD__SURFACE_FLIP; 7918c019253SYongqiang Sun 79222aa5614SYongqiang Sun surface_flip.flip.flip_params.vmid = address->vmid; 79322aa5614SYongqiang Sun surface_flip.flip.flip_params.hubp_inst = hubp->inst; 7948c019253SYongqiang Sun 7958c019253SYongqiang Sun switch (address->type) { 7968c019253SYongqiang Sun case PLN_ADDR_TYPE_GRAPHICS: 79722aa5614SYongqiang Sun if (address->grph.addr.quad_part == 0) { 79822aa5614SYongqiang Sun BREAK_TO_DEBUGGER(); 79922aa5614SYongqiang Sun break; 80022aa5614SYongqiang Sun } 8018c019253SYongqiang Sun 8028c019253SYongqiang Sun if (address->grph.meta_addr.quad_part != 0) { 8038c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 8048c019253SYongqiang Sun address->grph.meta_addr.low_part; 8058c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 8068c019253SYongqiang Sun address->grph.meta_addr.high_part; 8078c019253SYongqiang Sun } 8088c019253SYongqiang Sun 8098c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_SURFACE_ADDRESS = 8108c019253SYongqiang Sun address->grph.addr.low_part; 8118c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 8128c019253SYongqiang Sun address->grph.addr.high_part; 8138c019253SYongqiang Sun break; 8148c019253SYongqiang Sun case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 8158c019253SYongqiang Sun if (address->video_progressive.luma_addr.quad_part == 0 8168c019253SYongqiang Sun || address->video_progressive.chroma_addr.quad_part == 0) 81722aa5614SYongqiang Sun break; 8188c019253SYongqiang Sun 8198c019253SYongqiang Sun if (address->video_progressive.luma_meta_addr.quad_part != 0) { 8208c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 8218c019253SYongqiang Sun address->video_progressive.luma_meta_addr.low_part; 8228c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 8238c019253SYongqiang Sun address->video_progressive.luma_meta_addr.high_part; 8248c019253SYongqiang Sun 8258c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 8268c019253SYongqiang Sun address->video_progressive.chroma_meta_addr.low_part; 8278c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 8288c019253SYongqiang Sun address->video_progressive.chroma_meta_addr.high_part; 8298c019253SYongqiang Sun } 8308c019253SYongqiang Sun 8318c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_SURFACE_ADDRESS = 8328c019253SYongqiang Sun address->video_progressive.luma_addr.low_part; 8338c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 8348c019253SYongqiang Sun address->video_progressive.luma_addr.high_part; 8358c019253SYongqiang Sun 83622aa5614SYongqiang Sun if (debug->nv12_iflip_vm_wa) { 83722aa5614SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 83822aa5614SYongqiang Sun address->video_progressive.chroma_addr.low_part + hubp21->PLAT_54186_wa_chroma_addr_offset; 83922aa5614SYongqiang Sun } else 8408c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 8418c019253SYongqiang Sun address->video_progressive.chroma_addr.low_part; 84222aa5614SYongqiang Sun 8438c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 8448c019253SYongqiang Sun address->video_progressive.chroma_addr.high_part; 8458c019253SYongqiang Sun 8468c019253SYongqiang Sun break; 8478c019253SYongqiang Sun case PLN_ADDR_TYPE_GRPH_STEREO: 8488c019253SYongqiang Sun if (address->grph_stereo.left_addr.quad_part == 0) 84922aa5614SYongqiang Sun break; 8508c019253SYongqiang Sun if (address->grph_stereo.right_addr.quad_part == 0) 85122aa5614SYongqiang Sun break; 8528c019253SYongqiang Sun 85322aa5614SYongqiang Sun grph_stereo = true; 8548c019253SYongqiang Sun 8558c019253SYongqiang Sun if (address->grph_stereo.right_meta_addr.quad_part != 0) { 8568c019253SYongqiang Sun surface_flip.flip.DCSURF_SECONDARY_META_SURFACE_ADDRESS = 8578c019253SYongqiang Sun address->grph_stereo.right_meta_addr.low_part; 8588c019253SYongqiang Sun surface_flip.flip.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 8598c019253SYongqiang Sun address->grph_stereo.right_meta_addr.high_part; 8608c019253SYongqiang Sun } 8618c019253SYongqiang Sun 8628c019253SYongqiang Sun if (address->grph_stereo.left_meta_addr.quad_part != 0) { 8638c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 8648c019253SYongqiang Sun address->grph_stereo.left_meta_addr.low_part; 8658c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 8668c019253SYongqiang Sun address->grph_stereo.left_meta_addr.high_part; 8678c019253SYongqiang Sun } 8688c019253SYongqiang Sun 8698c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_SURFACE_ADDRESS = 8708c019253SYongqiang Sun address->grph_stereo.left_addr.low_part; 8718c019253SYongqiang Sun surface_flip.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 8728c019253SYongqiang Sun address->grph_stereo.left_addr.high_part; 8738c019253SYongqiang Sun 8748c019253SYongqiang Sun surface_flip.flip.DCSURF_SECONDARY_SURFACE_ADDRESS = 8758c019253SYongqiang Sun address->grph_stereo.right_addr.low_part; 8768c019253SYongqiang Sun surface_flip.flip.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 8778c019253SYongqiang Sun address->grph_stereo.right_addr.high_part; 8788c019253SYongqiang Sun 8798c019253SYongqiang Sun break; 880cf27a6d1SEric Yang default: 881cf27a6d1SEric Yang BREAK_TO_DEBUGGER(); 882cf27a6d1SEric Yang break; 883cf27a6d1SEric Yang } 884cf27a6d1SEric Yang 88522aa5614SYongqiang Sun surface_flip.flip.flip_params.vmid = address->vmid; 88622aa5614SYongqiang Sun surface_flip.flip.flip_params.grph_stereo = grph_stereo; 88722aa5614SYongqiang Sun surface_flip.flip.flip_params.tmz_surface = address->tmz_surface; 88822aa5614SYongqiang Sun surface_flip.flip.flip_params.immediate = flip_immediate; 88922aa5614SYongqiang Sun 89022aa5614SYongqiang Sun if (hubp->ctx->dc->debug.enable_dmcub_surface_flip) 89122aa5614SYongqiang Sun program_surface_flip_and_addr_dmcub(hubp, &surface_flip); 89222aa5614SYongqiang Sun else 89322aa5614SYongqiang Sun program_surface_flip_and_addr(hubp, &surface_flip); 89422aa5614SYongqiang Sun 895cf27a6d1SEric Yang hubp->request_address = *address; 896cf27a6d1SEric Yang 897cf27a6d1SEric Yang return true; 898cf27a6d1SEric Yang } 899cf27a6d1SEric Yang 900eced51f9SBhawanpreet Lakha void hubp21_init(struct hubp *hubp) 901eced51f9SBhawanpreet Lakha { 902eced51f9SBhawanpreet Lakha // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 903eced51f9SBhawanpreet Lakha // This is a chicken bit to enable the ECO fix. 904eced51f9SBhawanpreet Lakha 905eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 906eced51f9SBhawanpreet Lakha //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 907eced51f9SBhawanpreet Lakha REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 908eced51f9SBhawanpreet Lakha } 909eced51f9SBhawanpreet Lakha static struct hubp_funcs dcn21_hubp_funcs = { 910eced51f9SBhawanpreet Lakha .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 911eced51f9SBhawanpreet Lakha .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 912cf27a6d1SEric Yang .hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr, 91302981b28SEric Yang .hubp_program_surface_config = hubp1_program_surface_config, 914eced51f9SBhawanpreet Lakha .hubp_is_flip_pending = hubp1_is_flip_pending, 915eced51f9SBhawanpreet Lakha .hubp_setup = hubp21_setup, 916eced51f9SBhawanpreet Lakha .hubp_setup_interdependent = hubp2_setup_interdependent, 917eced51f9SBhawanpreet Lakha .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 918eced51f9SBhawanpreet Lakha .set_blank = hubp1_set_blank, 919eced51f9SBhawanpreet Lakha .dcc_control = hubp1_dcc_control, 9201cad8ff7SEric Yang .mem_program_viewport = hubp21_set_viewport, 921cf27a6d1SEric Yang .apply_PLAT_54186_wa = hubp21_apply_PLAT_54186_wa, 922eced51f9SBhawanpreet Lakha .set_cursor_attributes = hubp2_cursor_set_attributes, 923eced51f9SBhawanpreet Lakha .set_cursor_position = hubp1_cursor_set_position, 924eced51f9SBhawanpreet Lakha .hubp_clk_cntl = hubp1_clk_cntl, 925eced51f9SBhawanpreet Lakha .hubp_vtg_sel = hubp1_vtg_sel, 926eced51f9SBhawanpreet Lakha .dmdata_set_attributes = hubp2_dmdata_set_attributes, 927eced51f9SBhawanpreet Lakha .dmdata_load = hubp2_dmdata_load, 928eced51f9SBhawanpreet Lakha .dmdata_status_done = hubp2_dmdata_status_done, 929eced51f9SBhawanpreet Lakha .hubp_read_state = hubp1_read_state, 930eced51f9SBhawanpreet Lakha .hubp_clear_underflow = hubp1_clear_underflow, 931eced51f9SBhawanpreet Lakha .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 932eced51f9SBhawanpreet Lakha .hubp_init = hubp21_init, 933b9fe5151SJaehyun Chung .validate_dml_output = hubp21_validate_dml_output, 934eced51f9SBhawanpreet Lakha }; 935eced51f9SBhawanpreet Lakha 936eced51f9SBhawanpreet Lakha bool hubp21_construct( 937eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21, 938eced51f9SBhawanpreet Lakha struct dc_context *ctx, 939eced51f9SBhawanpreet Lakha uint32_t inst, 940eced51f9SBhawanpreet Lakha const struct dcn_hubp2_registers *hubp_regs, 941eced51f9SBhawanpreet Lakha const struct dcn_hubp2_shift *hubp_shift, 942eced51f9SBhawanpreet Lakha const struct dcn_hubp2_mask *hubp_mask) 943eced51f9SBhawanpreet Lakha { 944eced51f9SBhawanpreet Lakha hubp21->base.funcs = &dcn21_hubp_funcs; 945eced51f9SBhawanpreet Lakha hubp21->base.ctx = ctx; 946eced51f9SBhawanpreet Lakha hubp21->hubp_regs = hubp_regs; 947eced51f9SBhawanpreet Lakha hubp21->hubp_shift = hubp_shift; 948eced51f9SBhawanpreet Lakha hubp21->hubp_mask = hubp_mask; 949eced51f9SBhawanpreet Lakha hubp21->base.inst = inst; 950eced51f9SBhawanpreet Lakha hubp21->base.opp_id = OPP_ID_INVALID; 951eced51f9SBhawanpreet Lakha hubp21->base.mpcc_id = 0xf; 952eced51f9SBhawanpreet Lakha 953eced51f9SBhawanpreet Lakha return true; 954eced51f9SBhawanpreet Lakha } 955