1eced51f9SBhawanpreet Lakha /* 2eced51f9SBhawanpreet Lakha * Copyright 2018 Advanced Micro Devices, Inc. 3eced51f9SBhawanpreet Lakha * 4eced51f9SBhawanpreet Lakha * Permission is hereby granted, free of charge, to any person obtaining a 5eced51f9SBhawanpreet Lakha * copy of this software and associated documentation files (the "Software"), 6eced51f9SBhawanpreet Lakha * to deal in the Software without restriction, including without limitation 7eced51f9SBhawanpreet Lakha * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8eced51f9SBhawanpreet Lakha * and/or sell copies of the Software, and to permit persons to whom the 9eced51f9SBhawanpreet Lakha * Software is furnished to do so, subject to the following conditions: 10eced51f9SBhawanpreet Lakha * 11eced51f9SBhawanpreet Lakha * The above copyright notice and this permission notice shall be included in 12eced51f9SBhawanpreet Lakha * all copies or substantial portions of the Software. 13eced51f9SBhawanpreet Lakha * 14eced51f9SBhawanpreet Lakha * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15eced51f9SBhawanpreet Lakha * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16eced51f9SBhawanpreet Lakha * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17eced51f9SBhawanpreet Lakha * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18eced51f9SBhawanpreet Lakha * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19eced51f9SBhawanpreet Lakha * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20eced51f9SBhawanpreet Lakha * OTHER DEALINGS IN THE SOFTWARE. 21eced51f9SBhawanpreet Lakha * 22eced51f9SBhawanpreet Lakha * Authors: AMD 23eced51f9SBhawanpreet Lakha * 24eced51f9SBhawanpreet Lakha */ 2502981b28SEric Yang 2602981b28SEric Yang #include "dcn10/dcn10_hubp.h" 27eced51f9SBhawanpreet Lakha #include "dcn21_hubp.h" 28eced51f9SBhawanpreet Lakha 29eced51f9SBhawanpreet Lakha #include "dm_services.h" 30eced51f9SBhawanpreet Lakha #include "reg_helper.h" 31eced51f9SBhawanpreet Lakha 32eced51f9SBhawanpreet Lakha #define REG(reg)\ 33eced51f9SBhawanpreet Lakha hubp21->hubp_regs->reg 34eced51f9SBhawanpreet Lakha 35eced51f9SBhawanpreet Lakha #define CTX \ 36eced51f9SBhawanpreet Lakha hubp21->base.ctx 37eced51f9SBhawanpreet Lakha 38eced51f9SBhawanpreet Lakha #undef FN 39eced51f9SBhawanpreet Lakha #define FN(reg_name, field_name) \ 40eced51f9SBhawanpreet Lakha hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 41eced51f9SBhawanpreet Lakha 42eced51f9SBhawanpreet Lakha /* 43eced51f9SBhawanpreet Lakha * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 44eced51f9SBhawanpreet Lakha * As a result, if S/W updates any of these registers during a mode change, 45eced51f9SBhawanpreet Lakha * the current frame before the mode change will use the new value right away 46eced51f9SBhawanpreet Lakha * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 47eced51f9SBhawanpreet Lakha * 48eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_GROUP_FLIP[22:0] 49eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_GROUP_VBLANK[22:0] 50eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_REQ_FLIP[22:0] 51eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_REQ_VBLANK[22:0] 52eced51f9SBhawanpreet Lakha * 53eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 54eced51f9SBhawanpreet Lakha * when flipping to a new surface 55eced51f9SBhawanpreet Lakha * 56eced51f9SBhawanpreet Lakha * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 57eced51f9SBhawanpreet Lakha * during prefetch period of a frame. The prefetch starts at a pre-determined 58eced51f9SBhawanpreet Lakha * number of lines before the display active per frame 59eced51f9SBhawanpreet Lakha * 60eced51f9SBhawanpreet Lakha * DCN may underflow due to incorrectly programming these registers 61eced51f9SBhawanpreet Lakha * during VM stage of prefetch/iflip. First lines of display active 62eced51f9SBhawanpreet Lakha * or a sub-region of active using a new surface will be corrupted 63eced51f9SBhawanpreet Lakha * until the VM data returns at flip/mode change transitions 64eced51f9SBhawanpreet Lakha * 65eced51f9SBhawanpreet Lakha * Work around: 66eced51f9SBhawanpreet Lakha * workaround is always opt to use the more aggressive settings. 67eced51f9SBhawanpreet Lakha * On any mode switch, if the new reg values are smaller than the current values, 68eced51f9SBhawanpreet Lakha * then update the regs with the new values. 69eced51f9SBhawanpreet Lakha * 70eced51f9SBhawanpreet Lakha * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 71eced51f9SBhawanpreet Lakha * 72eced51f9SBhawanpreet Lakha */ 73eced51f9SBhawanpreet Lakha void apply_DEDCN21_142_wa_for_hostvm_deadline( 74eced51f9SBhawanpreet Lakha struct hubp *hubp, 75eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 76eced51f9SBhawanpreet Lakha { 77eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 78eced51f9SBhawanpreet Lakha uint32_t cur_value; 79eced51f9SBhawanpreet Lakha 80eced51f9SBhawanpreet Lakha REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); 81eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_group_vblank) 82eced51f9SBhawanpreet Lakha REG_SET(VBLANK_PARAMETERS_5, 0, 83eced51f9SBhawanpreet Lakha REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 84eced51f9SBhawanpreet Lakha 85eced51f9SBhawanpreet Lakha REG_GET(VBLANK_PARAMETERS_6, 86eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_VBLANK, 87eced51f9SBhawanpreet Lakha &cur_value); 88eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_req_vblank) 89eced51f9SBhawanpreet Lakha REG_SET(VBLANK_PARAMETERS_6, 0, 90eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 91eced51f9SBhawanpreet Lakha 92eced51f9SBhawanpreet Lakha REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); 93eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_group_flip) 94eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_3, 0, 95eced51f9SBhawanpreet Lakha REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 96eced51f9SBhawanpreet Lakha 97eced51f9SBhawanpreet Lakha REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); 98eced51f9SBhawanpreet Lakha if (cur_value > dlg_attr->refcyc_per_vm_req_flip) 99eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_4, 0, 100eced51f9SBhawanpreet Lakha REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 101eced51f9SBhawanpreet Lakha 102eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_5, 0, 103eced51f9SBhawanpreet Lakha REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 104eced51f9SBhawanpreet Lakha REG_SET(FLIP_PARAMETERS_6, 0, 105eced51f9SBhawanpreet Lakha REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 106eced51f9SBhawanpreet Lakha } 107eced51f9SBhawanpreet Lakha 108eced51f9SBhawanpreet Lakha void hubp21_program_deadline( 109eced51f9SBhawanpreet Lakha struct hubp *hubp, 110eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 111eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 112eced51f9SBhawanpreet Lakha { 113eced51f9SBhawanpreet Lakha hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 114eced51f9SBhawanpreet Lakha 115eced51f9SBhawanpreet Lakha apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 116eced51f9SBhawanpreet Lakha } 117eced51f9SBhawanpreet Lakha 118eced51f9SBhawanpreet Lakha void hubp21_program_requestor( 119eced51f9SBhawanpreet Lakha struct hubp *hubp, 120eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_rq_regs_st *rq_regs) 121eced51f9SBhawanpreet Lakha { 122eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 123eced51f9SBhawanpreet Lakha 124eced51f9SBhawanpreet Lakha REG_UPDATE(HUBPRET_CONTROL, 125eced51f9SBhawanpreet Lakha DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 126eced51f9SBhawanpreet Lakha REG_SET_4(DCN_EXPANSION_MODE, 0, 127eced51f9SBhawanpreet Lakha DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 128eced51f9SBhawanpreet Lakha PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 129eced51f9SBhawanpreet Lakha MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 130eced51f9SBhawanpreet Lakha CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 131eced51f9SBhawanpreet Lakha REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 132eced51f9SBhawanpreet Lakha CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 133eced51f9SBhawanpreet Lakha MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 134eced51f9SBhawanpreet Lakha META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 135eced51f9SBhawanpreet Lakha MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 136eced51f9SBhawanpreet Lakha DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 137eced51f9SBhawanpreet Lakha VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 138eced51f9SBhawanpreet Lakha SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 139eced51f9SBhawanpreet Lakha PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 140eced51f9SBhawanpreet Lakha REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 141eced51f9SBhawanpreet Lakha CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 142eced51f9SBhawanpreet Lakha MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 143eced51f9SBhawanpreet Lakha META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 144eced51f9SBhawanpreet Lakha MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 145eced51f9SBhawanpreet Lakha DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 146eced51f9SBhawanpreet Lakha SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 147eced51f9SBhawanpreet Lakha PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 148eced51f9SBhawanpreet Lakha } 149eced51f9SBhawanpreet Lakha 150eced51f9SBhawanpreet Lakha static void hubp21_setup( 151eced51f9SBhawanpreet Lakha struct hubp *hubp, 152eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 153eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 154eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_rq_regs_st *rq_regs, 155eced51f9SBhawanpreet Lakha struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 156eced51f9SBhawanpreet Lakha { 157eced51f9SBhawanpreet Lakha /* otg is locked when this func is called. Register are double buffered. 158eced51f9SBhawanpreet Lakha * disable the requestors is not needed 159eced51f9SBhawanpreet Lakha */ 160eced51f9SBhawanpreet Lakha 161eced51f9SBhawanpreet Lakha hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 162eced51f9SBhawanpreet Lakha hubp21_program_requestor(hubp, rq_regs); 163eced51f9SBhawanpreet Lakha hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 164eced51f9SBhawanpreet Lakha 165eced51f9SBhawanpreet Lakha } 166eced51f9SBhawanpreet Lakha 167eced51f9SBhawanpreet Lakha void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 168eced51f9SBhawanpreet Lakha struct vm_system_aperture_param *apt) 169eced51f9SBhawanpreet Lakha { 170eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 171eced51f9SBhawanpreet Lakha 172eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 173eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 174eced51f9SBhawanpreet Lakha PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 175eced51f9SBhawanpreet Lakha 176eced51f9SBhawanpreet Lakha // The format of default addr is 48:12 of the 48 bit addr 177eced51f9SBhawanpreet Lakha mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 178eced51f9SBhawanpreet Lakha 179eced51f9SBhawanpreet Lakha // The format of high/low are 48:18 of the 48 bit addr 180eced51f9SBhawanpreet Lakha mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 181eced51f9SBhawanpreet Lakha mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 182eced51f9SBhawanpreet Lakha 183eced51f9SBhawanpreet Lakha REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 184eced51f9SBhawanpreet Lakha MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 185eced51f9SBhawanpreet Lakha 186eced51f9SBhawanpreet Lakha REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 187eced51f9SBhawanpreet Lakha MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 188eced51f9SBhawanpreet Lakha 189eced51f9SBhawanpreet Lakha REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 190eced51f9SBhawanpreet Lakha ENABLE_L1_TLB, 1, 191eced51f9SBhawanpreet Lakha SYSTEM_ACCESS_MODE, 0x3); 192eced51f9SBhawanpreet Lakha } 193eced51f9SBhawanpreet Lakha 194eced51f9SBhawanpreet Lakha void hubp21_init(struct hubp *hubp) 195eced51f9SBhawanpreet Lakha { 196eced51f9SBhawanpreet Lakha // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 197eced51f9SBhawanpreet Lakha // This is a chicken bit to enable the ECO fix. 198eced51f9SBhawanpreet Lakha 199eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 200eced51f9SBhawanpreet Lakha //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 201eced51f9SBhawanpreet Lakha REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 202eced51f9SBhawanpreet Lakha } 203eced51f9SBhawanpreet Lakha static struct hubp_funcs dcn21_hubp_funcs = { 204eced51f9SBhawanpreet Lakha .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 205eced51f9SBhawanpreet Lakha .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 206eced51f9SBhawanpreet Lakha .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 20702981b28SEric Yang .hubp_program_surface_config = hubp1_program_surface_config, 208eced51f9SBhawanpreet Lakha .hubp_is_flip_pending = hubp1_is_flip_pending, 209eced51f9SBhawanpreet Lakha .hubp_setup = hubp21_setup, 210eced51f9SBhawanpreet Lakha .hubp_setup_interdependent = hubp2_setup_interdependent, 211eced51f9SBhawanpreet Lakha .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 212eced51f9SBhawanpreet Lakha .set_blank = hubp1_set_blank, 213eced51f9SBhawanpreet Lakha .dcc_control = hubp1_dcc_control, 214eced51f9SBhawanpreet Lakha .mem_program_viewport = min_set_viewport, 215eced51f9SBhawanpreet Lakha .set_cursor_attributes = hubp2_cursor_set_attributes, 216eced51f9SBhawanpreet Lakha .set_cursor_position = hubp1_cursor_set_position, 217eced51f9SBhawanpreet Lakha .hubp_clk_cntl = hubp1_clk_cntl, 218eced51f9SBhawanpreet Lakha .hubp_vtg_sel = hubp1_vtg_sel, 219eced51f9SBhawanpreet Lakha .dmdata_set_attributes = hubp2_dmdata_set_attributes, 220eced51f9SBhawanpreet Lakha .dmdata_load = hubp2_dmdata_load, 221eced51f9SBhawanpreet Lakha .dmdata_status_done = hubp2_dmdata_status_done, 222eced51f9SBhawanpreet Lakha .hubp_read_state = hubp1_read_state, 223eced51f9SBhawanpreet Lakha .hubp_clear_underflow = hubp1_clear_underflow, 224eced51f9SBhawanpreet Lakha .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 225eced51f9SBhawanpreet Lakha .hubp_init = hubp21_init, 226eced51f9SBhawanpreet Lakha }; 227eced51f9SBhawanpreet Lakha 228eced51f9SBhawanpreet Lakha bool hubp21_construct( 229eced51f9SBhawanpreet Lakha struct dcn21_hubp *hubp21, 230eced51f9SBhawanpreet Lakha struct dc_context *ctx, 231eced51f9SBhawanpreet Lakha uint32_t inst, 232eced51f9SBhawanpreet Lakha const struct dcn_hubp2_registers *hubp_regs, 233eced51f9SBhawanpreet Lakha const struct dcn_hubp2_shift *hubp_shift, 234eced51f9SBhawanpreet Lakha const struct dcn_hubp2_mask *hubp_mask) 235eced51f9SBhawanpreet Lakha { 236eced51f9SBhawanpreet Lakha hubp21->base.funcs = &dcn21_hubp_funcs; 237eced51f9SBhawanpreet Lakha hubp21->base.ctx = ctx; 238eced51f9SBhawanpreet Lakha hubp21->hubp_regs = hubp_regs; 239eced51f9SBhawanpreet Lakha hubp21->hubp_shift = hubp_shift; 240eced51f9SBhawanpreet Lakha hubp21->hubp_mask = hubp_mask; 241eced51f9SBhawanpreet Lakha hubp21->base.inst = inst; 242eced51f9SBhawanpreet Lakha hubp21->base.opp_id = OPP_ID_INVALID; 243eced51f9SBhawanpreet Lakha hubp21->base.mpcc_id = 0xf; 244eced51f9SBhawanpreet Lakha 245eced51f9SBhawanpreet Lakha return true; 246eced51f9SBhawanpreet Lakha } 247