17c15fd86SMauro Rossi /*
27c15fd86SMauro Rossi * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
37c15fd86SMauro Rossi *
47c15fd86SMauro Rossi * Permission is hereby granted, free of charge, to any person obtaining a
57c15fd86SMauro Rossi * copy of this software and associated documentation files (the "Software"),
67c15fd86SMauro Rossi * to deal in the Software without restriction, including without limitation
77c15fd86SMauro Rossi * the rights to use, copy, modify, merge, publish, distribute, sublicense,
87c15fd86SMauro Rossi * and/or sell copies of the Software, and to permit persons to whom the
97c15fd86SMauro Rossi * Software is furnished to do so, subject to the following conditions:
107c15fd86SMauro Rossi *
117c15fd86SMauro Rossi * The above copyright notice and this permission notice shall be included in
127c15fd86SMauro Rossi * all copies or substantial portions of the Software.
137c15fd86SMauro Rossi *
147c15fd86SMauro Rossi * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
157c15fd86SMauro Rossi * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
167c15fd86SMauro Rossi * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
177c15fd86SMauro Rossi * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
187c15fd86SMauro Rossi * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
197c15fd86SMauro Rossi * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
207c15fd86SMauro Rossi * OTHER DEALINGS IN THE SOFTWARE.
217c15fd86SMauro Rossi *
227c15fd86SMauro Rossi * Authors: AMD
237c15fd86SMauro Rossi *
247c15fd86SMauro Rossi */
257c15fd86SMauro Rossi
267c15fd86SMauro Rossi #include "dm_services.h"
277c15fd86SMauro Rossi #include "dc.h"
287c15fd86SMauro Rossi #include "core_types.h"
297c15fd86SMauro Rossi #include "dce60_hw_sequencer.h"
307c15fd86SMauro Rossi
317c15fd86SMauro Rossi #include "dce/dce_hwseq.h"
327c15fd86SMauro Rossi #include "dce110/dce110_hw_sequencer.h"
337c15fd86SMauro Rossi #include "dce100/dce100_hw_sequencer.h"
347c15fd86SMauro Rossi
35167d74fdSMauro Rossi /* include DCE6 register header files */
367c15fd86SMauro Rossi #include "dce/dce_6_0_d.h"
377c15fd86SMauro Rossi #include "dce/dce_6_0_sh_mask.h"
387c15fd86SMauro Rossi
39167d74fdSMauro Rossi #define DC_LOGGER_INIT()
40167d74fdSMauro Rossi
417c15fd86SMauro Rossi /*******************************************************************************
427c15fd86SMauro Rossi * Private definitions
437c15fd86SMauro Rossi ******************************************************************************/
447c15fd86SMauro Rossi
457c15fd86SMauro Rossi /***************************PIPE_CONTROL***********************************/
467c15fd86SMauro Rossi
47167d74fdSMauro Rossi /*
48167d74fdSMauro Rossi * Check if FBC can be enabled
49167d74fdSMauro Rossi */
dce60_should_enable_fbc(struct dc * dc,struct dc_state * context,uint32_t * pipe_idx)50167d74fdSMauro Rossi static bool dce60_should_enable_fbc(struct dc *dc,
51167d74fdSMauro Rossi struct dc_state *context,
52167d74fdSMauro Rossi uint32_t *pipe_idx)
53167d74fdSMauro Rossi {
54167d74fdSMauro Rossi uint32_t i;
55167d74fdSMauro Rossi struct pipe_ctx *pipe_ctx = NULL;
56167d74fdSMauro Rossi struct resource_context *res_ctx = &context->res_ctx;
57167d74fdSMauro Rossi unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
58167d74fdSMauro Rossi
59167d74fdSMauro Rossi
60167d74fdSMauro Rossi ASSERT(dc->fbc_compressor);
61167d74fdSMauro Rossi
62167d74fdSMauro Rossi /* FBC memory should be allocated */
63167d74fdSMauro Rossi if (!dc->ctx->fbc_gpu_addr)
64167d74fdSMauro Rossi return false;
65167d74fdSMauro Rossi
66167d74fdSMauro Rossi /* Only supports single display */
67167d74fdSMauro Rossi if (context->stream_count != 1)
68167d74fdSMauro Rossi return false;
69167d74fdSMauro Rossi
70167d74fdSMauro Rossi for (i = 0; i < dc->res_pool->pipe_count; i++) {
71167d74fdSMauro Rossi if (res_ctx->pipe_ctx[i].stream) {
72167d74fdSMauro Rossi
73167d74fdSMauro Rossi pipe_ctx = &res_ctx->pipe_ctx[i];
74167d74fdSMauro Rossi
75167d74fdSMauro Rossi if (!pipe_ctx)
76167d74fdSMauro Rossi continue;
77167d74fdSMauro Rossi
78167d74fdSMauro Rossi /* fbc not applicable on underlay pipe */
79167d74fdSMauro Rossi if (pipe_ctx->pipe_idx != underlay_idx) {
80167d74fdSMauro Rossi *pipe_idx = i;
81167d74fdSMauro Rossi break;
82167d74fdSMauro Rossi }
83167d74fdSMauro Rossi }
84167d74fdSMauro Rossi }
85167d74fdSMauro Rossi
86167d74fdSMauro Rossi if (i == dc->res_pool->pipe_count)
87167d74fdSMauro Rossi return false;
88167d74fdSMauro Rossi
89167d74fdSMauro Rossi if (!pipe_ctx->stream->link)
90167d74fdSMauro Rossi return false;
91167d74fdSMauro Rossi
92167d74fdSMauro Rossi /* Only supports eDP */
93167d74fdSMauro Rossi if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
94167d74fdSMauro Rossi return false;
95167d74fdSMauro Rossi
96167d74fdSMauro Rossi /* PSR should not be enabled */
97167d74fdSMauro Rossi if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
98167d74fdSMauro Rossi return false;
99167d74fdSMauro Rossi
100167d74fdSMauro Rossi /* Nothing to compress */
101167d74fdSMauro Rossi if (!pipe_ctx->plane_state)
102167d74fdSMauro Rossi return false;
103167d74fdSMauro Rossi
104167d74fdSMauro Rossi /* Only for non-linear tiling */
105167d74fdSMauro Rossi if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
106167d74fdSMauro Rossi return false;
107167d74fdSMauro Rossi
108167d74fdSMauro Rossi return true;
109167d74fdSMauro Rossi }
110167d74fdSMauro Rossi
111167d74fdSMauro Rossi /*
112167d74fdSMauro Rossi * Enable FBC
113167d74fdSMauro Rossi */
dce60_enable_fbc(struct dc * dc,struct dc_state * context)114167d74fdSMauro Rossi static void dce60_enable_fbc(
115167d74fdSMauro Rossi struct dc *dc,
116167d74fdSMauro Rossi struct dc_state *context)
117167d74fdSMauro Rossi {
118167d74fdSMauro Rossi uint32_t pipe_idx = 0;
119167d74fdSMauro Rossi
120167d74fdSMauro Rossi if (dce60_should_enable_fbc(dc, context, &pipe_idx)) {
121167d74fdSMauro Rossi /* Program GRPH COMPRESSED ADDRESS and PITCH */
122167d74fdSMauro Rossi struct compr_addr_and_pitch_params params = {0, 0, 0};
123167d74fdSMauro Rossi struct compressor *compr = dc->fbc_compressor;
124167d74fdSMauro Rossi struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
125167d74fdSMauro Rossi
126167d74fdSMauro Rossi params.source_view_width = pipe_ctx->stream->timing.h_addressable;
127167d74fdSMauro Rossi params.source_view_height = pipe_ctx->stream->timing.v_addressable;
128167d74fdSMauro Rossi params.inst = pipe_ctx->stream_res.tg->inst;
129167d74fdSMauro Rossi compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
130167d74fdSMauro Rossi
131167d74fdSMauro Rossi compr->funcs->surface_address_and_pitch(compr, ¶ms);
132167d74fdSMauro Rossi compr->funcs->set_fbc_invalidation_triggers(compr, 1);
133167d74fdSMauro Rossi
134167d74fdSMauro Rossi compr->funcs->enable_fbc(compr, ¶ms);
135167d74fdSMauro Rossi }
136167d74fdSMauro Rossi }
137167d74fdSMauro Rossi
138167d74fdSMauro Rossi
139167d74fdSMauro Rossi /*******************************************************************************
140167d74fdSMauro Rossi * Front End programming
141167d74fdSMauro Rossi ******************************************************************************/
142167d74fdSMauro Rossi
dce60_set_default_colors(struct pipe_ctx * pipe_ctx)143167d74fdSMauro Rossi static void dce60_set_default_colors(struct pipe_ctx *pipe_ctx)
144167d74fdSMauro Rossi {
145167d74fdSMauro Rossi struct default_adjustment default_adjust = { 0 };
146167d74fdSMauro Rossi
147167d74fdSMauro Rossi default_adjust.force_hw_default = false;
148167d74fdSMauro Rossi default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
149167d74fdSMauro Rossi default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
150167d74fdSMauro Rossi default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
151167d74fdSMauro Rossi default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
152167d74fdSMauro Rossi
153167d74fdSMauro Rossi /* display color depth */
154167d74fdSMauro Rossi default_adjust.color_depth =
155167d74fdSMauro Rossi pipe_ctx->stream->timing.display_color_depth;
156167d74fdSMauro Rossi
157167d74fdSMauro Rossi /* Lb color depth */
158167d74fdSMauro Rossi default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
159167d74fdSMauro Rossi
160167d74fdSMauro Rossi pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
161167d74fdSMauro Rossi pipe_ctx->plane_res.xfm, &default_adjust);
162167d74fdSMauro Rossi }
163167d74fdSMauro Rossi
164167d74fdSMauro Rossi /*******************************************************************************
165167d74fdSMauro Rossi * In order to turn on surface we will program
166167d74fdSMauro Rossi * CRTC
167167d74fdSMauro Rossi *
168167d74fdSMauro Rossi * DCE6 has no bottom_pipe and no Blender HW
169167d74fdSMauro Rossi * We need to set 'blank_target' to false in order to turn on the display
170167d74fdSMauro Rossi *
171167d74fdSMauro Rossi * |-----------|------------|---------|
172167d74fdSMauro Rossi * |curr pipe | set_blank | |
173167d74fdSMauro Rossi * |Surface |blank_target| CRCT |
174167d74fdSMauro Rossi * |visibility | argument | |
175167d74fdSMauro Rossi * |-----------|------------|---------|
176167d74fdSMauro Rossi * | off | true | blank |
177167d74fdSMauro Rossi * | on | false | unblank |
178167d74fdSMauro Rossi * |-----------|------------|---------|
179167d74fdSMauro Rossi *
180167d74fdSMauro Rossi ******************************************************************************/
dce60_program_surface_visibility(const struct dc * dc,struct pipe_ctx * pipe_ctx)181167d74fdSMauro Rossi static void dce60_program_surface_visibility(const struct dc *dc,
182167d74fdSMauro Rossi struct pipe_ctx *pipe_ctx)
183167d74fdSMauro Rossi {
184167d74fdSMauro Rossi bool blank_target = false;
185167d74fdSMauro Rossi
186167d74fdSMauro Rossi /* DCE6 has no bottom_pipe and no Blender HW */
187167d74fdSMauro Rossi
188167d74fdSMauro Rossi if (!pipe_ctx->plane_state->visible)
189167d74fdSMauro Rossi blank_target = true;
190167d74fdSMauro Rossi
191167d74fdSMauro Rossi /* DCE6 skip dce_set_blender_mode() but then proceed to 'unblank' CRTC */
192167d74fdSMauro Rossi pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
193167d74fdSMauro Rossi
194167d74fdSMauro Rossi }
195167d74fdSMauro Rossi
196167d74fdSMauro Rossi
dce60_get_surface_visual_confirm_color(const struct pipe_ctx * pipe_ctx,struct tg_color * color)197167d74fdSMauro Rossi static void dce60_get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
198167d74fdSMauro Rossi struct tg_color *color)
199167d74fdSMauro Rossi {
200167d74fdSMauro Rossi uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
201167d74fdSMauro Rossi
202167d74fdSMauro Rossi switch (pipe_ctx->plane_res.scl_data.format) {
203167d74fdSMauro Rossi case PIXEL_FORMAT_ARGB8888:
204167d74fdSMauro Rossi /* set boarder color to red */
205167d74fdSMauro Rossi color->color_r_cr = color_value;
206167d74fdSMauro Rossi break;
207167d74fdSMauro Rossi
208167d74fdSMauro Rossi case PIXEL_FORMAT_ARGB2101010:
209167d74fdSMauro Rossi /* set boarder color to blue */
210167d74fdSMauro Rossi color->color_b_cb = color_value;
211167d74fdSMauro Rossi break;
212167d74fdSMauro Rossi case PIXEL_FORMAT_420BPP8:
213167d74fdSMauro Rossi /* set boarder color to green */
214167d74fdSMauro Rossi color->color_g_y = color_value;
215167d74fdSMauro Rossi break;
216167d74fdSMauro Rossi case PIXEL_FORMAT_420BPP10:
217167d74fdSMauro Rossi /* set boarder color to yellow */
218167d74fdSMauro Rossi color->color_g_y = color_value;
219167d74fdSMauro Rossi color->color_r_cr = color_value;
220167d74fdSMauro Rossi break;
221167d74fdSMauro Rossi case PIXEL_FORMAT_FP16:
222167d74fdSMauro Rossi /* set boarder color to white */
223167d74fdSMauro Rossi color->color_r_cr = color_value;
224167d74fdSMauro Rossi color->color_b_cb = color_value;
225167d74fdSMauro Rossi color->color_g_y = color_value;
226167d74fdSMauro Rossi break;
227167d74fdSMauro Rossi default:
228167d74fdSMauro Rossi break;
229167d74fdSMauro Rossi }
230167d74fdSMauro Rossi }
231167d74fdSMauro Rossi
dce60_program_scaler(const struct dc * dc,const struct pipe_ctx * pipe_ctx)232167d74fdSMauro Rossi static void dce60_program_scaler(const struct dc *dc,
233167d74fdSMauro Rossi const struct pipe_ctx *pipe_ctx)
234167d74fdSMauro Rossi {
235167d74fdSMauro Rossi struct tg_color color = {0};
236167d74fdSMauro Rossi
237167d74fdSMauro Rossi /* DCE6 skips DCN TOFPGA check for transform_set_pixel_storage_depth == NULL */
238167d74fdSMauro Rossi
239167d74fdSMauro Rossi if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
240167d74fdSMauro Rossi dce60_get_surface_visual_confirm_color(pipe_ctx, &color);
241167d74fdSMauro Rossi else
242167d74fdSMauro Rossi color_space_to_black_color(dc,
243167d74fdSMauro Rossi pipe_ctx->stream->output_color_space,
244167d74fdSMauro Rossi &color);
245167d74fdSMauro Rossi
246167d74fdSMauro Rossi pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
247167d74fdSMauro Rossi pipe_ctx->plane_res.xfm,
248167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.lb_params.depth,
249167d74fdSMauro Rossi &pipe_ctx->stream->bit_depth_params);
250167d74fdSMauro Rossi
251167d74fdSMauro Rossi if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
252167d74fdSMauro Rossi /*
253167d74fdSMauro Rossi * The way 420 is packed, 2 channels carry Y component, 1 channel
254167d74fdSMauro Rossi * alternate between Cb and Cr, so both channels need the pixel
255167d74fdSMauro Rossi * value for Y
256167d74fdSMauro Rossi */
257167d74fdSMauro Rossi if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
258167d74fdSMauro Rossi color.color_r_cr = color.color_g_y;
259167d74fdSMauro Rossi
260167d74fdSMauro Rossi pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
261167d74fdSMauro Rossi pipe_ctx->stream_res.tg,
262167d74fdSMauro Rossi &color);
263167d74fdSMauro Rossi }
264167d74fdSMauro Rossi
265167d74fdSMauro Rossi pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
266167d74fdSMauro Rossi &pipe_ctx->plane_res.scl_data);
267167d74fdSMauro Rossi }
268167d74fdSMauro Rossi
269167d74fdSMauro Rossi static void
dce60_program_front_end_for_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx)270167d74fdSMauro Rossi dce60_program_front_end_for_pipe(
271167d74fdSMauro Rossi struct dc *dc, struct pipe_ctx *pipe_ctx)
272167d74fdSMauro Rossi {
273167d74fdSMauro Rossi struct mem_input *mi = pipe_ctx->plane_res.mi;
274167d74fdSMauro Rossi struct dc_plane_state *plane_state = pipe_ctx->plane_state;
275167d74fdSMauro Rossi struct xfm_grph_csc_adjustment adjust;
276167d74fdSMauro Rossi struct out_csc_color_matrix tbl_entry;
277167d74fdSMauro Rossi unsigned int i;
278167d74fdSMauro Rossi struct dce_hwseq *hws = dc->hwseq;
279167d74fdSMauro Rossi
280167d74fdSMauro Rossi DC_LOGGER_INIT();
281167d74fdSMauro Rossi memset(&tbl_entry, 0, sizeof(tbl_entry));
282167d74fdSMauro Rossi
283167d74fdSMauro Rossi memset(&adjust, 0, sizeof(adjust));
284167d74fdSMauro Rossi adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
285167d74fdSMauro Rossi
286167d74fdSMauro Rossi dce_enable_fe_clock(dc->hwseq, mi->inst, true);
287167d74fdSMauro Rossi
288167d74fdSMauro Rossi dce60_set_default_colors(pipe_ctx);
289167d74fdSMauro Rossi if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
290167d74fdSMauro Rossi == true) {
291167d74fdSMauro Rossi tbl_entry.color_space =
292167d74fdSMauro Rossi pipe_ctx->stream->output_color_space;
293167d74fdSMauro Rossi
294167d74fdSMauro Rossi for (i = 0; i < 12; i++)
295167d74fdSMauro Rossi tbl_entry.regval[i] =
296167d74fdSMauro Rossi pipe_ctx->stream->csc_color_matrix.matrix[i];
297167d74fdSMauro Rossi
298167d74fdSMauro Rossi pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
299167d74fdSMauro Rossi (pipe_ctx->plane_res.xfm, &tbl_entry);
300167d74fdSMauro Rossi }
301167d74fdSMauro Rossi
302167d74fdSMauro Rossi if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
303167d74fdSMauro Rossi adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
304167d74fdSMauro Rossi
305167d74fdSMauro Rossi for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
306167d74fdSMauro Rossi adjust.temperature_matrix[i] =
307167d74fdSMauro Rossi pipe_ctx->stream->gamut_remap_matrix.matrix[i];
308167d74fdSMauro Rossi }
309167d74fdSMauro Rossi
310167d74fdSMauro Rossi pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
311167d74fdSMauro Rossi
312167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
313167d74fdSMauro Rossi
314167d74fdSMauro Rossi dce60_program_scaler(dc, pipe_ctx);
315167d74fdSMauro Rossi
316167d74fdSMauro Rossi mi->funcs->mem_input_program_surface_config(
317167d74fdSMauro Rossi mi,
318167d74fdSMauro Rossi plane_state->format,
319167d74fdSMauro Rossi &plane_state->tiling_info,
320167d74fdSMauro Rossi &plane_state->plane_size,
321167d74fdSMauro Rossi plane_state->rotation,
322167d74fdSMauro Rossi NULL,
323167d74fdSMauro Rossi false);
324167d74fdSMauro Rossi if (mi->funcs->set_blank)
325167d74fdSMauro Rossi mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
326167d74fdSMauro Rossi
327167d74fdSMauro Rossi if (dc->config.gpu_vm_support)
328167d74fdSMauro Rossi mi->funcs->mem_input_program_pte_vm(
329167d74fdSMauro Rossi pipe_ctx->plane_res.mi,
330167d74fdSMauro Rossi plane_state->format,
331167d74fdSMauro Rossi &plane_state->tiling_info,
332167d74fdSMauro Rossi plane_state->rotation);
333167d74fdSMauro Rossi
334167d74fdSMauro Rossi /* Moved programming gamma from dc to hwss */
335167d74fdSMauro Rossi if (pipe_ctx->plane_state->update_flags.bits.full_update ||
336167d74fdSMauro Rossi pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
337167d74fdSMauro Rossi pipe_ctx->plane_state->update_flags.bits.gamma_change)
338167d74fdSMauro Rossi hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
339167d74fdSMauro Rossi
340167d74fdSMauro Rossi if (pipe_ctx->plane_state->update_flags.bits.full_update)
341167d74fdSMauro Rossi hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
342167d74fdSMauro Rossi
343167d74fdSMauro Rossi DC_LOG_SURFACE(
344167d74fdSMauro Rossi "Pipe:%d %p: addr hi:0x%x, "
345167d74fdSMauro Rossi "addr low:0x%x, "
346167d74fdSMauro Rossi "src: %d, %d, %d,"
347167d74fdSMauro Rossi " %d; dst: %d, %d, %d, %d;"
348167d74fdSMauro Rossi "clip: %d, %d, %d, %d\n",
349167d74fdSMauro Rossi pipe_ctx->pipe_idx,
350167d74fdSMauro Rossi (void *) pipe_ctx->plane_state,
351167d74fdSMauro Rossi pipe_ctx->plane_state->address.grph.addr.high_part,
352167d74fdSMauro Rossi pipe_ctx->plane_state->address.grph.addr.low_part,
353167d74fdSMauro Rossi pipe_ctx->plane_state->src_rect.x,
354167d74fdSMauro Rossi pipe_ctx->plane_state->src_rect.y,
355167d74fdSMauro Rossi pipe_ctx->plane_state->src_rect.width,
356167d74fdSMauro Rossi pipe_ctx->plane_state->src_rect.height,
357167d74fdSMauro Rossi pipe_ctx->plane_state->dst_rect.x,
358167d74fdSMauro Rossi pipe_ctx->plane_state->dst_rect.y,
359167d74fdSMauro Rossi pipe_ctx->plane_state->dst_rect.width,
360167d74fdSMauro Rossi pipe_ctx->plane_state->dst_rect.height,
361167d74fdSMauro Rossi pipe_ctx->plane_state->clip_rect.x,
362167d74fdSMauro Rossi pipe_ctx->plane_state->clip_rect.y,
363167d74fdSMauro Rossi pipe_ctx->plane_state->clip_rect.width,
364167d74fdSMauro Rossi pipe_ctx->plane_state->clip_rect.height);
365167d74fdSMauro Rossi
366167d74fdSMauro Rossi DC_LOG_SURFACE(
367167d74fdSMauro Rossi "Pipe %d: width, height, x, y\n"
368167d74fdSMauro Rossi "viewport:%d, %d, %d, %d\n"
369167d74fdSMauro Rossi "recout: %d, %d, %d, %d\n",
370167d74fdSMauro Rossi pipe_ctx->pipe_idx,
371167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.viewport.width,
372167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.viewport.height,
373167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.viewport.x,
374167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.viewport.y,
375167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.recout.width,
376167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.recout.height,
377167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.recout.x,
378167d74fdSMauro Rossi pipe_ctx->plane_res.scl_data.recout.y);
379167d74fdSMauro Rossi }
380167d74fdSMauro Rossi
dce60_apply_ctx_for_surface(struct dc * dc,const struct dc_stream_state * stream,int num_planes,struct dc_state * context)381167d74fdSMauro Rossi static void dce60_apply_ctx_for_surface(
382167d74fdSMauro Rossi struct dc *dc,
383167d74fdSMauro Rossi const struct dc_stream_state *stream,
384167d74fdSMauro Rossi int num_planes,
385167d74fdSMauro Rossi struct dc_state *context)
386167d74fdSMauro Rossi {
387167d74fdSMauro Rossi int i;
388167d74fdSMauro Rossi
389167d74fdSMauro Rossi if (num_planes == 0)
390167d74fdSMauro Rossi return;
391167d74fdSMauro Rossi
392167d74fdSMauro Rossi if (dc->fbc_compressor)
393167d74fdSMauro Rossi dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
394167d74fdSMauro Rossi
395167d74fdSMauro Rossi for (i = 0; i < dc->res_pool->pipe_count; i++) {
396167d74fdSMauro Rossi struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
397167d74fdSMauro Rossi
398167d74fdSMauro Rossi if (pipe_ctx->stream != stream)
399167d74fdSMauro Rossi continue;
400167d74fdSMauro Rossi
401167d74fdSMauro Rossi /* Need to allocate mem before program front end for Fiji */
402167d74fdSMauro Rossi pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
403167d74fdSMauro Rossi pipe_ctx->plane_res.mi,
404167d74fdSMauro Rossi pipe_ctx->stream->timing.h_total,
405167d74fdSMauro Rossi pipe_ctx->stream->timing.v_total,
406167d74fdSMauro Rossi pipe_ctx->stream->timing.pix_clk_100hz / 10,
407167d74fdSMauro Rossi context->stream_count);
408167d74fdSMauro Rossi
409167d74fdSMauro Rossi dce60_program_front_end_for_pipe(dc, pipe_ctx);
410167d74fdSMauro Rossi
411167d74fdSMauro Rossi dc->hwss.update_plane_addr(dc, pipe_ctx);
412167d74fdSMauro Rossi
413167d74fdSMauro Rossi dce60_program_surface_visibility(dc, pipe_ctx);
414167d74fdSMauro Rossi
415167d74fdSMauro Rossi }
416167d74fdSMauro Rossi
417167d74fdSMauro Rossi if (dc->fbc_compressor)
418167d74fdSMauro Rossi dce60_enable_fbc(dc, context);
419167d74fdSMauro Rossi }
420167d74fdSMauro Rossi
dce60_hw_sequencer_construct(struct dc * dc)4217c15fd86SMauro Rossi void dce60_hw_sequencer_construct(struct dc *dc)
4227c15fd86SMauro Rossi {
4237c15fd86SMauro Rossi dce110_hw_sequencer_construct(dc);
4247c15fd86SMauro Rossi
4257c15fd86SMauro Rossi dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
426167d74fdSMauro Rossi dc->hwss.apply_ctx_for_surface = dce60_apply_ctx_for_surface;
4271bd26c7dSMauro Rossi dc->hwss.cursor_lock = dce60_pipe_control_lock;
428167d74fdSMauro Rossi dc->hwss.pipe_control_lock = dce60_pipe_control_lock;
4297c15fd86SMauro Rossi dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
4307c15fd86SMauro Rossi dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
4317c15fd86SMauro Rossi }
4327c15fd86SMauro Rossi
433