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Revision tags: v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9 |
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| #
1bd26c7d |
| 12-Jul-2020 |
Mauro Rossi <issor.oruam@gmail.com> |
drm/amd/display: dce60_hw_sequencer: add DCE6 specific .cursor_lock
[Why]
kernel WARNING due to use of .cursor_lock = dce_pipe_control_lock inherited by dce110
[How]
DCE6 set .cursor_lock = dce60_p
drm/amd/display: dce60_hw_sequencer: add DCE6 specific .cursor_lock
[Why]
kernel WARNING due to use of .cursor_lock = dce_pipe_control_lock inherited by dce110
[How]
DCE6 set .cursor_lock = dce60_pipe_control_lock
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
167d74fd |
| 10-Jul-2020 |
Mauro Rossi <issor.oruam@gmail.com> |
drm/amd/display: dce60_hw_sequencer: add DCE6 specific functions (v2)
[Why]
DCE6 has no bottom_pipe and no Blender HW
DCE6 needs 'blank_target' set to false in order to turn on the display
DCE6 has
drm/amd/display: dce60_hw_sequencer: add DCE6 specific functions (v2)
[Why]
DCE6 has no bottom_pipe and no Blender HW
DCE6 needs 'blank_target' set to false in order to turn on the display
DCE6 has a specific dce60_pipe_control_lock() fuction that is a no op
[How]
Add DCE6 specific functions with needed private dce60_* dependent fuctions
Comment DCE6 specific CTRC program visibility implementation
Fix a typo in the initial header includes comment 's/DCE8/DCE6/g'
Use dce60_apply_ctx_for_surface() in dce60_hw_sequencer_construct
Use dce60_pipe_control_lock() in dce60_hw_sequencer_construct
v2: add missing return type (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
7c15fd86 |
| 11-Jul-2020 |
Mauro Rossi <issor.oruam@gmail.com> |
drm/amd/display: dc/dce: add initial DCE6 support (v10)
[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this
[How]
DCE6 targets are added replicating existing DCE8 implementati
drm/amd/display: dc/dce: add initial DCE6 support (v10)
[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this
[How]
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
initial build prototype due to missing DCE6 macros/registers/masks
DCE6 specific macros/registers/masks will be added with later commits
(v2b) removed dce_version cases in dc/dce/dce_clock_source.c and
updated dce60 due to following kernel 5.0 commits:
24f7dd7 ("drm/amd/display: move pplib/smu notification to dccg block")
9566b67 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead")
4244381 ("drm/amd/display: clean up base dccg struct")
4c5e8b5 ("drm/amd/display: split dccg clock manager into asic folders")
84e7fc0 ("drm/amd/display: rename dccg to clk_mgr")
77f6916 ("drm/amd/display: Remove duplicate header")
9f7ddbe ("drm/amd/display: fix optimize_bandwidth func pointer for dce80")
4ece61a ("drm/amd/display: set clocks to 0 on suspend on dce80")
(v3b) updated dce60 due to following kernel 5.1 commits:
380604e ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks")
32e6136 ("drm/amd/display: Fix 64-bit division for 32-bit builds")
1877ccf ("drm/amd/display: Change from aux_engine to dce_aux")
c69dffa ("drm/amd/display: fix eDP fast bootup for pre-raven asic")
(v4b) updated dce60 due to following kernel 5.2 commits:
e5c4197 ("drm/amd/display: Add plane capabilities to dc_caps")
813d20d ("drm/amd/display: Fix multi-thread writing to 1 state")
ea36ad3 ("drm/amd/display: expand plane caps to include fp16 and scaling capability")
afcd526 ("drm/amd/display: Add fast_validate parameter")
(v5b) updated dce60 due to following kernel 5.3 commits:
e7e10c4 ("drm/amd/display: stop external access to internal optc sync params")
78cc70b ("drm/amd/display: Engine-specific encoder allocation")
dc88b4a ("drm/amd/display: make clk mgr soc specific")
4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")
(v6b) updated dce60 due to following kernel 5.4 commits:
54a9bcb ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask")
9adc805 ("drm/amd/display: make firmware info only load once during dc_bios create")
(v7b) updated dce60 due to following kernel 5.5 commits:
cabe144 ("drm/amd/display: memory leak")
8276dd8 ("drm/amd/display: update register field access mechanism")
f6040a4 ("drm/amd/display: configurable aux timeout support")
bf7f5ac ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x")
(v8b) updated dce60 due to following kernel 5.6 commits:
d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")
f42ea55 ("drm/amd/display: add separate of private hwss functions")
(v9b) updated dce60 due to following kernel 5.8 commits:
bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
904fb6e ("drm/amd/display: move panel power seq to new panel struct")
d4caa72 ("drm/amd/display: change from panel to panel cntl")
(v10) Fix up PLL handling for DCE6:
DCE6.0 supports 2 PLLs. DCE6.1 supports 3 PLLs. (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
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|
Revision tags: v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9 |
|
| #
1bd26c7d |
| 12-Jul-2020 |
Mauro Rossi <issor.oruam@gmail.com> |
drm/amd/display: dce60_hw_sequencer: add DCE6 specific .cursor_lock
[Why]
kernel WARNING due to use of .cursor_lock = dce_pipe_control_lock inherited by dce110
[How]
DCE6 se
drm/amd/display: dce60_hw_sequencer: add DCE6 specific .cursor_lock
[Why]
kernel WARNING due to use of .cursor_lock = dce_pipe_control_lock inherited by dce110
[How]
DCE6 set .cursor_lock = dce60_pipe_control_lock
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
167d74fd |
| 10-Jul-2020 |
Mauro Rossi <issor.oruam@gmail.com> |
drm/amd/display: dce60_hw_sequencer: add DCE6 specific functions (v2)
[Why]
DCE6 has no bottom_pipe and no Blender HW
DCE6 needs 'blank_target' set to false in order to turn on the d
drm/amd/display: dce60_hw_sequencer: add DCE6 specific functions (v2)
[Why]
DCE6 has no bottom_pipe and no Blender HW
DCE6 needs 'blank_target' set to false in order to turn on the display
DCE6 has a specific dce60_pipe_control_lock() fuction that is a no op
[How]
Add DCE6 specific functions with needed private dce60_* dependent fuctions
Comment DCE6 specific CTRC program visibility implementation
Fix a typo in the initial header includes comment 's/DCE8/DCE6/g'
Use dce60_apply_ctx_for_surface() in dce60_hw_sequencer_construct
Use dce60_pipe_control_lock() in dce60_hw_sequencer_construct
v2: add missing return type (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
7c15fd86 |
| 11-Jul-2020 |
Mauro Rossi <issor.oruam@gmail.com> |
drm/amd/display: dc/dce: add initial DCE6 support (v10)
[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this
[How]
DCE6 targets are added replicating ex
drm/amd/display: dc/dce: add initial DCE6 support (v10)
[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this
[How]
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
initial build prototype due to missing DCE6 macros/registers/masks
DCE6 specific macros/registers/masks will be added with later commits
(v2b) removed dce_version cases in dc/dce/dce_clock_source.c and
updated dce60 due to following kernel 5.0 commits:
24f7dd7 ("drm/amd/display: move pplib/smu notification to dccg block")
9566b67 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead")
4244381 ("drm/amd/display: clean up base dccg struct")
4c5e8b5 ("drm/amd/display: split dccg clock manager into asic folders")
84e7fc0 ("drm/amd/display: rename dccg to clk_mgr")
77f6916 ("drm/amd/display: Remove duplicate header")
9f7ddbe ("drm/amd/display: fix optimize_bandwidth func pointer for dce80")
4ece61a ("drm/amd/display: set clocks to 0 on suspend on dce80")
(v3b) updated dce60 due to following kernel 5.1 commits:
380604e ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks")
32e6136 ("drm/amd/display: Fix 64-bit division for 32-bit builds")
1877ccf ("drm/amd/display: Change from aux_engine to dce_aux")
c69dffa ("drm/amd/display: fix eDP fast bootup for pre-raven asic")
(v4b) updated dce60 due to following kernel 5.2 commits:
e5c4197 ("drm/amd/display: Add plane capabilities to dc_caps")
813d20d ("drm/amd/display: Fix multi-thread writing to 1 state")
ea36ad3 ("drm/amd/display: expand plane caps to include fp16 and scaling capability")
afcd526 ("drm/amd/display: Add fast_validate parameter")
(v5b) updated dce60 due to following kernel 5.3 commits:
e7e10c4 ("drm/amd/display: stop external access to internal optc sync params")
78cc70b ("drm/amd/display: Engine-specific encoder allocation")
dc88b4a ("drm/amd/display: make clk mgr soc specific")
4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")
(v6b) updated dce60 due to following kernel 5.4 commits:
54a9bcb ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask")
9adc805 ("drm/amd/display: make firmware info only load once during dc_bios create")
(v7b) updated dce60 due to following kernel 5.5 commits:
cabe144 ("drm/amd/display: memory leak")
8276dd8 ("drm/amd/display: update register field access mechanism")
f6040a4 ("drm/amd/display: configurable aux timeout support")
bf7f5ac ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x")
(v8b) updated dce60 due to following kernel 5.6 commits:
d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")
f42ea55 ("drm/amd/display: add separate of private hwss functions")
(v9b) updated dce60 due to following kernel 5.8 commits:
bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
904fb6e ("drm/amd/display: move panel power seq to new panel struct")
d4caa72 ("drm/amd/display: change from panel to panel cntl")
(v10) Fix up PLL handling for DCE6:
DCE6.0 supports 2 PLLs. DCE6.1 supports 3 PLLs. (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|