1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 #include "dc_bios_types.h" 31 #include "core_types.h" 32 #include "core_status.h" 33 #include "resource.h" 34 #include "dm_helpers.h" 35 #include "dce110_hw_sequencer.h" 36 #include "dce110_timing_generator.h" 37 #include "dce/dce_hwseq.h" 38 #include "gpio_service_interface.h" 39 40 #include "dce110_compressor.h" 41 42 #include "bios/bios_parser_helper.h" 43 #include "timing_generator.h" 44 #include "mem_input.h" 45 #include "opp.h" 46 #include "ipp.h" 47 #include "transform.h" 48 #include "stream_encoder.h" 49 #include "link_encoder.h" 50 #include "link_hwss.h" 51 #include "clock_source.h" 52 #include "clk_mgr.h" 53 #include "abm.h" 54 #include "audio.h" 55 #include "reg_helper.h" 56 #include "panel_cntl.h" 57 58 /* include DCE11 register header files */ 59 #include "dce/dce_11_0_d.h" 60 #include "dce/dce_11_0_sh_mask.h" 61 #include "custom_float.h" 62 63 #include "atomfirmware.h" 64 65 #define GAMMA_HW_POINTS_NUM 256 66 67 /* 68 * All values are in milliseconds; 69 * For eDP, after power-up/power/down, 70 * 300/500 msec max. delay from LCDVCC to black video generation 71 */ 72 #define PANEL_POWER_UP_TIMEOUT 300 73 #define PANEL_POWER_DOWN_TIMEOUT 500 74 #define HPD_CHECK_INTERVAL 10 75 #define OLED_POST_T7_DELAY 100 76 #define OLED_PRE_T11_DELAY 150 77 78 #define CTX \ 79 hws->ctx 80 81 #define DC_LOGGER_INIT() 82 83 #define REG(reg)\ 84 hws->regs->reg 85 86 #undef FN 87 #define FN(reg_name, field_name) \ 88 hws->shifts->field_name, hws->masks->field_name 89 90 struct dce110_hw_seq_reg_offsets { 91 uint32_t crtc; 92 }; 93 94 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 95 { 96 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 97 }, 98 { 99 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 100 }, 101 { 102 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 103 }, 104 { 105 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 106 } 107 }; 108 109 #define HW_REG_BLND(reg, id)\ 110 (reg + reg_offsets[id].blnd) 111 112 #define HW_REG_CRTC(reg, id)\ 113 (reg + reg_offsets[id].crtc) 114 115 #define MAX_WATERMARK 0xFFFF 116 #define SAFE_NBP_MARK 0x7FFF 117 118 /******************************************************************************* 119 * Private definitions 120 ******************************************************************************/ 121 /***************************PIPE_CONTROL***********************************/ 122 static void dce110_init_pte(struct dc_context *ctx) 123 { 124 uint32_t addr; 125 uint32_t value = 0; 126 uint32_t chunk_int = 0; 127 uint32_t chunk_mul = 0; 128 129 addr = mmUNP_DVMM_PTE_CONTROL; 130 value = dm_read_reg(ctx, addr); 131 132 set_reg_field_value( 133 value, 134 0, 135 DVMM_PTE_CONTROL, 136 DVMM_USE_SINGLE_PTE); 137 138 set_reg_field_value( 139 value, 140 1, 141 DVMM_PTE_CONTROL, 142 DVMM_PTE_BUFFER_MODE0); 143 144 set_reg_field_value( 145 value, 146 1, 147 DVMM_PTE_CONTROL, 148 DVMM_PTE_BUFFER_MODE1); 149 150 dm_write_reg(ctx, addr, value); 151 152 addr = mmDVMM_PTE_REQ; 153 value = dm_read_reg(ctx, addr); 154 155 chunk_int = get_reg_field_value( 156 value, 157 DVMM_PTE_REQ, 158 HFLIP_PTEREQ_PER_CHUNK_INT); 159 160 chunk_mul = get_reg_field_value( 161 value, 162 DVMM_PTE_REQ, 163 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 164 165 if (chunk_int != 0x4 || chunk_mul != 0x4) { 166 167 set_reg_field_value( 168 value, 169 255, 170 DVMM_PTE_REQ, 171 MAX_PTEREQ_TO_ISSUE); 172 173 set_reg_field_value( 174 value, 175 4, 176 DVMM_PTE_REQ, 177 HFLIP_PTEREQ_PER_CHUNK_INT); 178 179 set_reg_field_value( 180 value, 181 4, 182 DVMM_PTE_REQ, 183 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 184 185 dm_write_reg(ctx, addr, value); 186 } 187 } 188 /**************************************************************************/ 189 190 static void enable_display_pipe_clock_gating( 191 struct dc_context *ctx, 192 bool clock_gating) 193 { 194 /*TODO*/ 195 } 196 197 static bool dce110_enable_display_power_gating( 198 struct dc *dc, 199 uint8_t controller_id, 200 struct dc_bios *dcb, 201 enum pipe_gating_control power_gating) 202 { 203 enum bp_result bp_result = BP_RESULT_OK; 204 enum bp_pipe_control_action cntl; 205 struct dc_context *ctx = dc->ctx; 206 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 207 208 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 209 return true; 210 211 if (power_gating == PIPE_GATING_CONTROL_INIT) 212 cntl = ASIC_PIPE_INIT; 213 else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 214 cntl = ASIC_PIPE_ENABLE; 215 else 216 cntl = ASIC_PIPE_DISABLE; 217 218 if (controller_id == underlay_idx) 219 controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 220 221 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 222 223 bp_result = dcb->funcs->enable_disp_power_gating( 224 dcb, controller_id + 1, cntl); 225 226 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 227 * by default when command table is called 228 * 229 * Bios parser accepts controller_id = 6 as indicative of 230 * underlay pipe in dce110. But we do not support more 231 * than 3. 232 */ 233 if (controller_id < CONTROLLER_ID_MAX - 1) 234 dm_write_reg(ctx, 235 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 236 0); 237 } 238 239 if (power_gating != PIPE_GATING_CONTROL_ENABLE) 240 dce110_init_pte(ctx); 241 242 if (bp_result == BP_RESULT_OK) 243 return true; 244 else 245 return false; 246 } 247 248 static void build_prescale_params(struct ipp_prescale_params *prescale_params, 249 const struct dc_plane_state *plane_state) 250 { 251 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 252 253 switch (plane_state->format) { 254 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 255 prescale_params->scale = 0x2082; 256 break; 257 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 258 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 259 prescale_params->scale = 0x2020; 260 break; 261 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 262 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 263 prescale_params->scale = 0x2008; 264 break; 265 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 266 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 267 prescale_params->scale = 0x2000; 268 break; 269 default: 270 ASSERT(false); 271 break; 272 } 273 } 274 275 static bool 276 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 277 const struct dc_plane_state *plane_state) 278 { 279 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 280 const struct dc_transfer_func *tf = NULL; 281 struct ipp_prescale_params prescale_params = { 0 }; 282 bool result = true; 283 284 if (ipp == NULL) 285 return false; 286 287 if (plane_state->in_transfer_func) 288 tf = plane_state->in_transfer_func; 289 290 build_prescale_params(&prescale_params, plane_state); 291 ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 292 293 if (plane_state->gamma_correction && 294 !plane_state->gamma_correction->is_identity && 295 dce_use_lut(plane_state->format)) 296 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 297 298 if (tf == NULL) { 299 /* Default case if no input transfer function specified */ 300 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 301 } else if (tf->type == TF_TYPE_PREDEFINED) { 302 switch (tf->tf) { 303 case TRANSFER_FUNCTION_SRGB: 304 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 305 break; 306 case TRANSFER_FUNCTION_BT709: 307 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 308 break; 309 case TRANSFER_FUNCTION_LINEAR: 310 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 311 break; 312 case TRANSFER_FUNCTION_PQ: 313 default: 314 result = false; 315 break; 316 } 317 } else if (tf->type == TF_TYPE_BYPASS) { 318 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 319 } else { 320 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 321 result = false; 322 } 323 324 return result; 325 } 326 327 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 328 struct curve_points *arr_points, 329 uint32_t hw_points_num) 330 { 331 struct custom_float_format fmt; 332 333 struct pwl_result_data *rgb = rgb_resulted; 334 335 uint32_t i = 0; 336 337 fmt.exponenta_bits = 6; 338 fmt.mantissa_bits = 12; 339 fmt.sign = true; 340 341 if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 342 &arr_points[0].custom_float_x)) { 343 BREAK_TO_DEBUGGER(); 344 return false; 345 } 346 347 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 348 &arr_points[0].custom_float_offset)) { 349 BREAK_TO_DEBUGGER(); 350 return false; 351 } 352 353 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 354 &arr_points[0].custom_float_slope)) { 355 BREAK_TO_DEBUGGER(); 356 return false; 357 } 358 359 fmt.mantissa_bits = 10; 360 fmt.sign = false; 361 362 if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 363 &arr_points[1].custom_float_x)) { 364 BREAK_TO_DEBUGGER(); 365 return false; 366 } 367 368 if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 369 &arr_points[1].custom_float_y)) { 370 BREAK_TO_DEBUGGER(); 371 return false; 372 } 373 374 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 375 &arr_points[1].custom_float_slope)) { 376 BREAK_TO_DEBUGGER(); 377 return false; 378 } 379 380 fmt.mantissa_bits = 12; 381 fmt.sign = true; 382 383 while (i != hw_points_num) { 384 if (!convert_to_custom_float_format(rgb->red, &fmt, 385 &rgb->red_reg)) { 386 BREAK_TO_DEBUGGER(); 387 return false; 388 } 389 390 if (!convert_to_custom_float_format(rgb->green, &fmt, 391 &rgb->green_reg)) { 392 BREAK_TO_DEBUGGER(); 393 return false; 394 } 395 396 if (!convert_to_custom_float_format(rgb->blue, &fmt, 397 &rgb->blue_reg)) { 398 BREAK_TO_DEBUGGER(); 399 return false; 400 } 401 402 if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 403 &rgb->delta_red_reg)) { 404 BREAK_TO_DEBUGGER(); 405 return false; 406 } 407 408 if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 409 &rgb->delta_green_reg)) { 410 BREAK_TO_DEBUGGER(); 411 return false; 412 } 413 414 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 415 &rgb->delta_blue_reg)) { 416 BREAK_TO_DEBUGGER(); 417 return false; 418 } 419 420 ++rgb; 421 ++i; 422 } 423 424 return true; 425 } 426 427 #define MAX_LOW_POINT 25 428 #define NUMBER_REGIONS 16 429 #define NUMBER_SW_SEGMENTS 16 430 431 static bool 432 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 433 struct pwl_params *regamma_params) 434 { 435 struct curve_points *arr_points; 436 struct pwl_result_data *rgb_resulted; 437 struct pwl_result_data *rgb; 438 struct pwl_result_data *rgb_plus_1; 439 struct fixed31_32 y_r; 440 struct fixed31_32 y_g; 441 struct fixed31_32 y_b; 442 struct fixed31_32 y1_min; 443 struct fixed31_32 y3_max; 444 445 int32_t region_start, region_end; 446 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 447 448 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 449 return false; 450 451 arr_points = regamma_params->arr_points; 452 rgb_resulted = regamma_params->rgb_resulted; 453 hw_points = 0; 454 455 memset(regamma_params, 0, sizeof(struct pwl_params)); 456 457 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 458 /* 16 segments 459 * segments are from 2^-11 to 2^5 460 */ 461 region_start = -11; 462 region_end = region_start + NUMBER_REGIONS; 463 464 for (i = 0; i < NUMBER_REGIONS; i++) 465 seg_distr[i] = 4; 466 467 } else { 468 /* 10 segments 469 * segment is from 2^-10 to 2^1 470 * We include an extra segment for range [2^0, 2^1). This is to 471 * ensure that colors with normalized values of 1 don't miss the 472 * LUT. 473 */ 474 region_start = -10; 475 region_end = 1; 476 477 seg_distr[0] = 4; 478 seg_distr[1] = 4; 479 seg_distr[2] = 4; 480 seg_distr[3] = 4; 481 seg_distr[4] = 4; 482 seg_distr[5] = 4; 483 seg_distr[6] = 4; 484 seg_distr[7] = 4; 485 seg_distr[8] = 4; 486 seg_distr[9] = 4; 487 seg_distr[10] = 0; 488 seg_distr[11] = -1; 489 seg_distr[12] = -1; 490 seg_distr[13] = -1; 491 seg_distr[14] = -1; 492 seg_distr[15] = -1; 493 } 494 495 for (k = 0; k < 16; k++) { 496 if (seg_distr[k] != -1) 497 hw_points += (1 << seg_distr[k]); 498 } 499 500 j = 0; 501 for (k = 0; k < (region_end - region_start); k++) { 502 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 503 start_index = (region_start + k + MAX_LOW_POINT) * 504 NUMBER_SW_SEGMENTS; 505 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 506 i += increment) { 507 if (j == hw_points - 1) 508 break; 509 rgb_resulted[j].red = output_tf->tf_pts.red[i]; 510 rgb_resulted[j].green = output_tf->tf_pts.green[i]; 511 rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 512 j++; 513 } 514 } 515 516 /* last point */ 517 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 518 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 519 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 520 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 521 522 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 523 dc_fixpt_from_int(region_start)); 524 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 525 dc_fixpt_from_int(region_end)); 526 527 y_r = rgb_resulted[0].red; 528 y_g = rgb_resulted[0].green; 529 y_b = rgb_resulted[0].blue; 530 531 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 532 533 arr_points[0].y = y1_min; 534 arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 535 arr_points[0].x); 536 537 y_r = rgb_resulted[hw_points - 1].red; 538 y_g = rgb_resulted[hw_points - 1].green; 539 y_b = rgb_resulted[hw_points - 1].blue; 540 541 /* see comment above, m_arrPoints[1].y should be the Y value for the 542 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 543 */ 544 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 545 546 arr_points[1].y = y3_max; 547 548 arr_points[1].slope = dc_fixpt_zero; 549 550 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 551 /* for PQ, we want to have a straight line from last HW X point, 552 * and the slope to be such that we hit 1.0 at 10000 nits. 553 */ 554 const struct fixed31_32 end_value = dc_fixpt_from_int(125); 555 556 arr_points[1].slope = dc_fixpt_div( 557 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 558 dc_fixpt_sub(end_value, arr_points[1].x)); 559 } 560 561 regamma_params->hw_points_num = hw_points; 562 563 k = 0; 564 for (i = 1; i < 16; i++) { 565 if (seg_distr[k] != -1) { 566 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 567 regamma_params->arr_curve_points[i].offset = 568 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 569 } 570 k++; 571 } 572 573 if (seg_distr[k] != -1) 574 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 575 576 rgb = rgb_resulted; 577 rgb_plus_1 = rgb_resulted + 1; 578 579 i = 1; 580 581 while (i != hw_points + 1) { 582 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 583 rgb_plus_1->red = rgb->red; 584 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 585 rgb_plus_1->green = rgb->green; 586 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 587 rgb_plus_1->blue = rgb->blue; 588 589 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 590 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 591 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 592 593 ++rgb_plus_1; 594 ++rgb; 595 ++i; 596 } 597 598 convert_to_custom_float(rgb_resulted, arr_points, hw_points); 599 600 return true; 601 } 602 603 static bool 604 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 605 const struct dc_stream_state *stream) 606 { 607 struct transform *xfm = pipe_ctx->plane_res.xfm; 608 609 xfm->funcs->opp_power_on_regamma_lut(xfm, true); 610 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 611 612 if (stream->out_transfer_func && 613 stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 614 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 615 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 616 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 617 &xfm->regamma_params)) { 618 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 619 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 620 } else { 621 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 622 } 623 624 xfm->funcs->opp_power_on_regamma_lut(xfm, false); 625 626 return true; 627 } 628 629 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 630 { 631 bool is_hdmi_tmds; 632 bool is_dp; 633 634 ASSERT(pipe_ctx->stream); 635 636 if (pipe_ctx->stream_res.stream_enc == NULL) 637 return; /* this is not root pipe */ 638 639 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 640 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 641 642 if (!is_hdmi_tmds && !is_dp) 643 return; 644 645 if (is_hdmi_tmds) 646 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 647 pipe_ctx->stream_res.stream_enc, 648 &pipe_ctx->stream_res.encoder_info_frame); 649 else 650 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 651 pipe_ctx->stream_res.stream_enc, 652 &pipe_ctx->stream_res.encoder_info_frame); 653 } 654 655 void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 656 { 657 enum dc_lane_count lane_count = 658 pipe_ctx->stream->link->cur_link_settings.lane_count; 659 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 660 struct dc_link *link = pipe_ctx->stream->link; 661 const struct dc *dc = link->dc; 662 663 uint32_t active_total_with_borders; 664 uint32_t early_control = 0; 665 struct timing_generator *tg = pipe_ctx->stream_res.tg; 666 667 /* For MST, there are multiply stream go to only one link. 668 * connect DIG back_end to front_end while enable_stream and 669 * disconnect them during disable_stream 670 * BY this, it is logic clean to separate stream and link */ 671 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 672 pipe_ctx->stream_res.stream_enc->id, true); 673 674 dc->hwss.update_info_frame(pipe_ctx); 675 676 /* enable early control to avoid corruption on DP monitor*/ 677 active_total_with_borders = 678 timing->h_addressable 679 + timing->h_border_left 680 + timing->h_border_right; 681 682 if (lane_count != 0) 683 early_control = active_total_with_borders % lane_count; 684 685 if (early_control == 0) 686 early_control = lane_count; 687 688 tg->funcs->set_early_control(tg, early_control); 689 690 /* enable audio only within mode set */ 691 if (pipe_ctx->stream_res.audio != NULL) { 692 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 693 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 694 } 695 696 697 698 699 } 700 701 static enum bp_result link_transmitter_control( 702 struct dc_bios *bios, 703 struct bp_transmitter_control *cntl) 704 { 705 enum bp_result result; 706 707 result = bios->funcs->transmitter_control(bios, cntl); 708 709 return result; 710 } 711 712 /* 713 * @brief 714 * eDP only. 715 */ 716 void dce110_edp_wait_for_hpd_ready( 717 struct dc_link *link, 718 bool power_up) 719 { 720 struct dc_context *ctx = link->ctx; 721 struct graphics_object_id connector = link->link_enc->connector; 722 struct gpio *hpd; 723 bool edp_hpd_high = false; 724 uint32_t time_elapsed = 0; 725 uint32_t timeout = power_up ? 726 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 727 728 if (dal_graphics_object_id_get_connector_id(connector) 729 != CONNECTOR_ID_EDP) { 730 BREAK_TO_DEBUGGER(); 731 return; 732 } 733 734 if (!power_up) 735 /* 736 * From KV, we will not HPD low after turning off VCC - 737 * instead, we will check the SW timer in power_up(). 738 */ 739 return; 740 741 /* 742 * When we power on/off the eDP panel, 743 * we need to wait until SENSE bit is high/low. 744 */ 745 746 /* obtain HPD */ 747 /* TODO what to do with this? */ 748 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 749 750 if (!hpd) { 751 BREAK_TO_DEBUGGER(); 752 return; 753 } 754 755 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 756 757 /* wait until timeout or panel detected */ 758 759 do { 760 uint32_t detected = 0; 761 762 dal_gpio_get_value(hpd, &detected); 763 764 if (!(detected ^ power_up)) { 765 edp_hpd_high = true; 766 break; 767 } 768 769 msleep(HPD_CHECK_INTERVAL); 770 771 time_elapsed += HPD_CHECK_INTERVAL; 772 } while (time_elapsed < timeout); 773 774 dal_gpio_close(hpd); 775 776 dal_gpio_destroy_irq(&hpd); 777 778 if (false == edp_hpd_high) { 779 DC_LOG_ERROR( 780 "%s: wait timed out!\n", __func__); 781 } 782 } 783 784 void dce110_edp_power_control( 785 struct dc_link *link, 786 bool power_up) 787 { 788 struct dc_context *ctx = link->ctx; 789 struct bp_transmitter_control cntl = { 0 }; 790 enum bp_result bp_result; 791 792 793 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 794 != CONNECTOR_ID_EDP) { 795 BREAK_TO_DEBUGGER(); 796 return; 797 } 798 799 if (!link->panel_cntl) 800 return; 801 802 if (power_up != 803 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 804 /* Send VBIOS command to prompt eDP panel power */ 805 if (power_up) { 806 unsigned long long current_ts = dm_get_timestamp(ctx); 807 unsigned long long duration_in_ms = 808 div64_u64(dm_get_elapse_time_in_ns( 809 ctx, 810 current_ts, 811 link->link_trace.time_stamp.edp_poweroff), 1000000); 812 unsigned long long wait_time_ms = 0; 813 814 /* max 500ms from LCDVDD off to on */ 815 unsigned long long edp_poweroff_time_ms = 500; 816 817 if (link->local_sink != NULL) 818 edp_poweroff_time_ms = 819 500 + link->local_sink->edid_caps.panel_patch.extra_t12_ms; 820 if (link->link_trace.time_stamp.edp_poweroff == 0) 821 wait_time_ms = edp_poweroff_time_ms; 822 else if (duration_in_ms < edp_poweroff_time_ms) 823 wait_time_ms = edp_poweroff_time_ms - duration_in_ms; 824 825 if (wait_time_ms) { 826 msleep(wait_time_ms); 827 dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 828 __func__, wait_time_ms); 829 } 830 831 } 832 833 DC_LOG_HW_RESUME_S3( 834 "%s: Panel Power action: %s\n", 835 __func__, (power_up ? "On":"Off")); 836 837 cntl.action = power_up ? 838 TRANSMITTER_CONTROL_POWER_ON : 839 TRANSMITTER_CONTROL_POWER_OFF; 840 cntl.transmitter = link->link_enc->transmitter; 841 cntl.connector_obj_id = link->link_enc->connector; 842 cntl.coherent = false; 843 cntl.lanes_number = LANE_COUNT_FOUR; 844 cntl.hpd_sel = link->link_enc->hpd_source; 845 bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 846 847 if (!power_up) 848 /*save driver power off time stamp*/ 849 link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 850 else 851 link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 852 853 if (bp_result != BP_RESULT_OK) 854 DC_LOG_ERROR( 855 "%s: Panel Power bp_result: %d\n", 856 __func__, bp_result); 857 } else { 858 DC_LOG_HW_RESUME_S3( 859 "%s: Skipping Panel Power action: %s\n", 860 __func__, (power_up ? "On":"Off")); 861 } 862 } 863 864 /*todo: cloned in stream enc, fix*/ 865 /* 866 * @brief 867 * eDP only. Control the backlight of the eDP panel 868 */ 869 void dce110_edp_backlight_control( 870 struct dc_link *link, 871 bool enable) 872 { 873 struct dc_context *ctx = link->ctx; 874 struct bp_transmitter_control cntl = { 0 }; 875 876 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 877 != CONNECTOR_ID_EDP) { 878 BREAK_TO_DEBUGGER(); 879 return; 880 } 881 882 if (enable && link->panel_cntl && 883 link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl)) { 884 DC_LOG_HW_RESUME_S3( 885 "%s: panel already powered up. Do nothing.\n", 886 __func__); 887 return; 888 } 889 890 /* Send VBIOS command to control eDP panel backlight */ 891 892 DC_LOG_HW_RESUME_S3( 893 "%s: backlight action: %s\n", 894 __func__, (enable ? "On":"Off")); 895 896 cntl.action = enable ? 897 TRANSMITTER_CONTROL_BACKLIGHT_ON : 898 TRANSMITTER_CONTROL_BACKLIGHT_OFF; 899 900 /*cntl.engine_id = ctx->engine;*/ 901 cntl.transmitter = link->link_enc->transmitter; 902 cntl.connector_obj_id = link->link_enc->connector; 903 /*todo: unhardcode*/ 904 cntl.lanes_number = LANE_COUNT_FOUR; 905 cntl.hpd_sel = link->link_enc->hpd_source; 906 cntl.signal = SIGNAL_TYPE_EDP; 907 908 /* For eDP, the following delays might need to be considered 909 * after link training completed: 910 * idle period - min. accounts for required BS-Idle pattern, 911 * max. allows for source frame synchronization); 912 * 50 msec max. delay from valid video data from source 913 * to video on dislpay or backlight enable. 914 * 915 * Disable the delay for now. 916 * Enable it in the future if necessary. 917 */ 918 /* dc_service_sleep_in_milliseconds(50); */ 919 /*edp 1.2*/ 920 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 921 edp_receiver_ready_T7(link); 922 link_transmitter_control(ctx->dc_bios, &cntl); 923 924 if (enable && link->dpcd_sink_ext_caps.bits.oled) 925 msleep(OLED_POST_T7_DELAY); 926 927 if (link->dpcd_sink_ext_caps.bits.oled || 928 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 929 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 930 dc_link_backlight_enable_aux(link, enable); 931 932 /*edp 1.2*/ 933 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) 934 edp_receiver_ready_T9(link); 935 936 if (!enable && link->dpcd_sink_ext_caps.bits.oled) 937 msleep(OLED_PRE_T11_DELAY); 938 } 939 940 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 941 { 942 /* notify audio driver for audio modes of monitor */ 943 struct dc *dc; 944 struct clk_mgr *clk_mgr; 945 unsigned int i, num_audio = 1; 946 947 if (!pipe_ctx->stream) 948 return; 949 950 dc = pipe_ctx->stream->ctx->dc; 951 clk_mgr = dc->clk_mgr; 952 953 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 954 return; 955 956 if (pipe_ctx->stream_res.audio) { 957 for (i = 0; i < MAX_PIPES; i++) { 958 /*current_state not updated yet*/ 959 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 960 num_audio++; 961 } 962 963 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 964 965 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 966 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 967 clk_mgr->funcs->enable_pme_wa(clk_mgr); 968 /* un-mute audio */ 969 /* TODO: audio should be per stream rather than per link */ 970 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 971 pipe_ctx->stream_res.stream_enc, false); 972 if (pipe_ctx->stream_res.audio) 973 pipe_ctx->stream_res.audio->enabled = true; 974 } 975 } 976 977 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 978 { 979 struct dc *dc; 980 struct clk_mgr *clk_mgr; 981 982 if (!pipe_ctx || !pipe_ctx->stream) 983 return; 984 985 dc = pipe_ctx->stream->ctx->dc; 986 clk_mgr = dc->clk_mgr; 987 988 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 989 return; 990 991 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 992 pipe_ctx->stream_res.stream_enc, true); 993 if (pipe_ctx->stream_res.audio) { 994 pipe_ctx->stream_res.audio->enabled = false; 995 996 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 997 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 998 pipe_ctx->stream_res.stream_enc); 999 else 1000 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 1001 pipe_ctx->stream_res.stream_enc); 1002 1003 if (clk_mgr->funcs->enable_pme_wa) 1004 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1005 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1006 1007 /* TODO: notify audio driver for if audio modes list changed 1008 * add audio mode list change flag */ 1009 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 1010 * stream->stream_engine_id); 1011 */ 1012 } 1013 } 1014 1015 void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 1016 { 1017 struct dc_stream_state *stream = pipe_ctx->stream; 1018 struct dc_link *link = stream->link; 1019 struct dc *dc = pipe_ctx->stream->ctx->dc; 1020 1021 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 1022 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 1023 pipe_ctx->stream_res.stream_enc); 1024 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1025 pipe_ctx->stream_res.stream_enc); 1026 } 1027 1028 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1029 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 1030 pipe_ctx->stream_res.stream_enc); 1031 1032 dc->hwss.disable_audio_stream(pipe_ctx); 1033 1034 link->link_enc->funcs->connect_dig_be_to_fe( 1035 link->link_enc, 1036 pipe_ctx->stream_res.stream_enc->id, 1037 false); 1038 1039 } 1040 1041 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 1042 struct dc_link_settings *link_settings) 1043 { 1044 struct encoder_unblank_param params = { { 0 } }; 1045 struct dc_stream_state *stream = pipe_ctx->stream; 1046 struct dc_link *link = stream->link; 1047 struct dce_hwseq *hws = link->dc->hwseq; 1048 1049 /* only 3 items below are used by unblank */ 1050 params.timing = pipe_ctx->stream->timing; 1051 params.link_settings.link_rate = link_settings->link_rate; 1052 1053 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1054 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 1055 1056 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1057 hws->funcs.edp_backlight_control(link, true); 1058 } 1059 } 1060 1061 void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 1062 { 1063 struct dc_stream_state *stream = pipe_ctx->stream; 1064 struct dc_link *link = stream->link; 1065 struct dce_hwseq *hws = link->dc->hwseq; 1066 1067 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1068 hws->funcs.edp_backlight_control(link, false); 1069 link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1070 } 1071 1072 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1073 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 1074 } 1075 1076 1077 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 1078 { 1079 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 1080 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 1081 } 1082 1083 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 1084 { 1085 switch (crtc_id) { 1086 case CONTROLLER_ID_D0: 1087 return DTO_SOURCE_ID0; 1088 case CONTROLLER_ID_D1: 1089 return DTO_SOURCE_ID1; 1090 case CONTROLLER_ID_D2: 1091 return DTO_SOURCE_ID2; 1092 case CONTROLLER_ID_D3: 1093 return DTO_SOURCE_ID3; 1094 case CONTROLLER_ID_D4: 1095 return DTO_SOURCE_ID4; 1096 case CONTROLLER_ID_D5: 1097 return DTO_SOURCE_ID5; 1098 default: 1099 return DTO_SOURCE_UNKNOWN; 1100 } 1101 } 1102 1103 static void build_audio_output( 1104 struct dc_state *state, 1105 const struct pipe_ctx *pipe_ctx, 1106 struct audio_output *audio_output) 1107 { 1108 const struct dc_stream_state *stream = pipe_ctx->stream; 1109 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 1110 1111 audio_output->signal = pipe_ctx->stream->signal; 1112 1113 /* audio_crtc_info */ 1114 1115 audio_output->crtc_info.h_total = 1116 stream->timing.h_total; 1117 1118 /* 1119 * Audio packets are sent during actual CRTC blank physical signal, we 1120 * need to specify actual active signal portion 1121 */ 1122 audio_output->crtc_info.h_active = 1123 stream->timing.h_addressable 1124 + stream->timing.h_border_left 1125 + stream->timing.h_border_right; 1126 1127 audio_output->crtc_info.v_active = 1128 stream->timing.v_addressable 1129 + stream->timing.v_border_top 1130 + stream->timing.v_border_bottom; 1131 1132 audio_output->crtc_info.pixel_repetition = 1; 1133 1134 audio_output->crtc_info.interlaced = 1135 stream->timing.flags.INTERLACE; 1136 1137 audio_output->crtc_info.refresh_rate = 1138 (stream->timing.pix_clk_100hz*100)/ 1139 (stream->timing.h_total*stream->timing.v_total); 1140 1141 audio_output->crtc_info.color_depth = 1142 stream->timing.display_color_depth; 1143 1144 audio_output->crtc_info.requested_pixel_clock_100Hz = 1145 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1146 1147 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1148 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1149 1150 /*for HDMI, audio ACR is with deep color ratio factor*/ 1151 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && 1152 audio_output->crtc_info.requested_pixel_clock_100Hz == 1153 (stream->timing.pix_clk_100hz)) { 1154 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1155 audio_output->crtc_info.requested_pixel_clock_100Hz = 1156 audio_output->crtc_info.requested_pixel_clock_100Hz/2; 1157 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1158 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 1159 1160 } 1161 } 1162 1163 if (state->clk_mgr && 1164 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1165 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 1166 audio_output->pll_info.dp_dto_source_clock_in_khz = 1167 state->clk_mgr->funcs->get_dp_ref_clk_frequency( 1168 state->clk_mgr); 1169 } 1170 1171 audio_output->pll_info.feed_back_divider = 1172 pipe_ctx->pll_settings.feedback_divider; 1173 1174 audio_output->pll_info.dto_source = 1175 translate_to_dto_source( 1176 pipe_ctx->stream_res.tg->inst + 1); 1177 1178 /* TODO hard code to enable for now. Need get from stream */ 1179 audio_output->pll_info.ss_enabled = true; 1180 1181 audio_output->pll_info.ss_percentage = 1182 pipe_ctx->pll_settings.ss_percentage; 1183 } 1184 1185 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 1186 struct tg_color *color) 1187 { 1188 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; 1189 1190 switch (pipe_ctx->plane_res.scl_data.format) { 1191 case PIXEL_FORMAT_ARGB8888: 1192 /* set boarder color to red */ 1193 color->color_r_cr = color_value; 1194 break; 1195 1196 case PIXEL_FORMAT_ARGB2101010: 1197 /* set boarder color to blue */ 1198 color->color_b_cb = color_value; 1199 break; 1200 case PIXEL_FORMAT_420BPP8: 1201 /* set boarder color to green */ 1202 color->color_g_y = color_value; 1203 break; 1204 case PIXEL_FORMAT_420BPP10: 1205 /* set boarder color to yellow */ 1206 color->color_g_y = color_value; 1207 color->color_r_cr = color_value; 1208 break; 1209 case PIXEL_FORMAT_FP16: 1210 /* set boarder color to white */ 1211 color->color_r_cr = color_value; 1212 color->color_b_cb = color_value; 1213 color->color_g_y = color_value; 1214 break; 1215 default: 1216 break; 1217 } 1218 } 1219 1220 static void program_scaler(const struct dc *dc, 1221 const struct pipe_ctx *pipe_ctx) 1222 { 1223 struct tg_color color = {0}; 1224 1225 #if defined(CONFIG_DRM_AMD_DC_DCN) 1226 /* TOFPGA */ 1227 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1228 return; 1229 #endif 1230 1231 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 1232 get_surface_visual_confirm_color(pipe_ctx, &color); 1233 else 1234 color_space_to_black_color(dc, 1235 pipe_ctx->stream->output_color_space, 1236 &color); 1237 1238 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 1239 pipe_ctx->plane_res.xfm, 1240 pipe_ctx->plane_res.scl_data.lb_params.depth, 1241 &pipe_ctx->stream->bit_depth_params); 1242 1243 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 1244 /* 1245 * The way 420 is packed, 2 channels carry Y component, 1 channel 1246 * alternate between Cb and Cr, so both channels need the pixel 1247 * value for Y 1248 */ 1249 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1250 color.color_r_cr = color.color_g_y; 1251 1252 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 1253 pipe_ctx->stream_res.tg, 1254 &color); 1255 } 1256 1257 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 1258 &pipe_ctx->plane_res.scl_data); 1259 } 1260 1261 static enum dc_status dce110_enable_stream_timing( 1262 struct pipe_ctx *pipe_ctx, 1263 struct dc_state *context, 1264 struct dc *dc) 1265 { 1266 struct dc_stream_state *stream = pipe_ctx->stream; 1267 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 1268 pipe_ctx[pipe_ctx->pipe_idx]; 1269 struct tg_color black_color = {0}; 1270 1271 if (!pipe_ctx_old->stream) { 1272 1273 /* program blank color */ 1274 color_space_to_black_color(dc, 1275 stream->output_color_space, &black_color); 1276 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1277 pipe_ctx->stream_res.tg, 1278 &black_color); 1279 1280 /* 1281 * Must blank CRTC after disabling power gating and before any 1282 * programming, otherwise CRTC will be hung in bad state 1283 */ 1284 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 1285 1286 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 1287 pipe_ctx->clock_source, 1288 &pipe_ctx->stream_res.pix_clk_params, 1289 &pipe_ctx->pll_settings)) { 1290 BREAK_TO_DEBUGGER(); 1291 return DC_ERROR_UNEXPECTED; 1292 } 1293 1294 pipe_ctx->stream_res.tg->funcs->program_timing( 1295 pipe_ctx->stream_res.tg, 1296 &stream->timing, 1297 0, 1298 0, 1299 0, 1300 0, 1301 pipe_ctx->stream->signal, 1302 true); 1303 } 1304 1305 if (!pipe_ctx_old->stream) { 1306 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 1307 pipe_ctx->stream_res.tg)) { 1308 BREAK_TO_DEBUGGER(); 1309 return DC_ERROR_UNEXPECTED; 1310 } 1311 } 1312 1313 return DC_OK; 1314 } 1315 1316 static enum dc_status apply_single_controller_ctx_to_hw( 1317 struct pipe_ctx *pipe_ctx, 1318 struct dc_state *context, 1319 struct dc *dc) 1320 { 1321 struct dc_stream_state *stream = pipe_ctx->stream; 1322 struct drr_params params = {0}; 1323 unsigned int event_triggers = 0; 1324 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1325 struct dce_hwseq *hws = dc->hwseq; 1326 1327 if (hws->funcs.disable_stream_gating) { 1328 hws->funcs.disable_stream_gating(dc, pipe_ctx); 1329 } 1330 1331 if (pipe_ctx->stream_res.audio != NULL) { 1332 struct audio_output audio_output; 1333 1334 build_audio_output(context, pipe_ctx, &audio_output); 1335 1336 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1337 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 1338 pipe_ctx->stream_res.stream_enc, 1339 pipe_ctx->stream_res.audio->inst, 1340 &pipe_ctx->stream->audio_info); 1341 else 1342 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 1343 pipe_ctx->stream_res.stream_enc, 1344 pipe_ctx->stream_res.audio->inst, 1345 &pipe_ctx->stream->audio_info, 1346 &audio_output.crtc_info); 1347 1348 pipe_ctx->stream_res.audio->funcs->az_configure( 1349 pipe_ctx->stream_res.audio, 1350 pipe_ctx->stream->signal, 1351 &audio_output.crtc_info, 1352 &pipe_ctx->stream->audio_info); 1353 } 1354 1355 /* */ 1356 /* Do not touch stream timing on seamless boot optimization. */ 1357 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1358 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1359 1360 if (hws->funcs.setup_vupdate_interrupt) 1361 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1362 1363 params.vertical_total_min = stream->adjust.v_total_min; 1364 params.vertical_total_max = stream->adjust.v_total_max; 1365 if (pipe_ctx->stream_res.tg->funcs->set_drr) 1366 pipe_ctx->stream_res.tg->funcs->set_drr( 1367 pipe_ctx->stream_res.tg, ¶ms); 1368 1369 // DRR should set trigger event to monitor surface update event 1370 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 1371 event_triggers = 0x80; 1372 /* Event triggers and num frames initialized for DRR, but can be 1373 * later updated for PSR use. Note DRR trigger events are generated 1374 * regardless of whether num frames met. 1375 */ 1376 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 1377 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 1378 pipe_ctx->stream_res.tg, event_triggers, 2); 1379 1380 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1381 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1382 pipe_ctx->stream_res.stream_enc, 1383 pipe_ctx->stream_res.tg->inst); 1384 1385 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1386 pipe_ctx->stream_res.opp, 1387 COLOR_SPACE_YCBCR601, 1388 stream->timing.display_color_depth, 1389 stream->signal); 1390 1391 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1392 pipe_ctx->stream_res.opp, 1393 &stream->bit_depth_params, 1394 &stream->clamping); 1395 while (odm_pipe) { 1396 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 1397 odm_pipe->stream_res.opp, 1398 COLOR_SPACE_YCBCR601, 1399 stream->timing.display_color_depth, 1400 stream->signal); 1401 1402 odm_pipe->stream_res.opp->funcs->opp_program_fmt( 1403 odm_pipe->stream_res.opp, 1404 &stream->bit_depth_params, 1405 &stream->clamping); 1406 odm_pipe = odm_pipe->next_odm_pipe; 1407 } 1408 1409 if (!stream->dpms_off) 1410 core_link_enable_stream(context, pipe_ctx); 1411 1412 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 1413 1414 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 1415 1416 return DC_OK; 1417 } 1418 1419 /******************************************************************************/ 1420 1421 static void power_down_encoders(struct dc *dc) 1422 { 1423 int i; 1424 1425 /* do not know BIOS back-front mapping, simply blank all. It will not 1426 * hurt for non-DP 1427 */ 1428 for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1429 dc->res_pool->stream_enc[i]->funcs->dp_blank( 1430 dc->res_pool->stream_enc[i]); 1431 } 1432 1433 for (i = 0; i < dc->link_count; i++) { 1434 enum signal_type signal = dc->links[i]->connector_signal; 1435 1436 if ((signal == SIGNAL_TYPE_EDP) || 1437 (signal == SIGNAL_TYPE_DISPLAY_PORT)) 1438 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) 1439 dp_receiver_power_ctrl(dc->links[i], false); 1440 1441 if (signal != SIGNAL_TYPE_EDP) 1442 signal = SIGNAL_TYPE_NONE; 1443 1444 dc->links[i]->link_enc->funcs->disable_output( 1445 dc->links[i]->link_enc, signal); 1446 } 1447 } 1448 1449 static void power_down_controllers(struct dc *dc) 1450 { 1451 int i; 1452 1453 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1454 dc->res_pool->timing_generators[i]->funcs->disable_crtc( 1455 dc->res_pool->timing_generators[i]); 1456 } 1457 } 1458 1459 static void power_down_clock_sources(struct dc *dc) 1460 { 1461 int i; 1462 1463 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 1464 dc->res_pool->dp_clock_source) == false) 1465 dm_error("Failed to power down pll! (dp clk src)\n"); 1466 1467 for (i = 0; i < dc->res_pool->clk_src_count; i++) { 1468 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 1469 dc->res_pool->clock_sources[i]) == false) 1470 dm_error("Failed to power down pll! (clk src index=%d)\n", i); 1471 } 1472 } 1473 1474 static void power_down_all_hw_blocks(struct dc *dc) 1475 { 1476 power_down_encoders(dc); 1477 1478 power_down_controllers(dc); 1479 1480 power_down_clock_sources(dc); 1481 1482 if (dc->fbc_compressor) 1483 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 1484 } 1485 1486 static void disable_vga_and_power_gate_all_controllers( 1487 struct dc *dc) 1488 { 1489 int i; 1490 struct timing_generator *tg; 1491 struct dc_context *ctx = dc->ctx; 1492 1493 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1494 tg = dc->res_pool->timing_generators[i]; 1495 1496 if (tg->funcs->disable_vga) 1497 tg->funcs->disable_vga(tg); 1498 } 1499 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1500 /* Enable CLOCK gating for each pipe BEFORE controller 1501 * powergating. */ 1502 enable_display_pipe_clock_gating(ctx, 1503 true); 1504 1505 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 1506 dc->hwss.disable_plane(dc, 1507 &dc->current_state->res_ctx.pipe_ctx[i]); 1508 } 1509 } 1510 1511 1512 static struct dc_stream_state *get_edp_stream(struct dc_state *context) 1513 { 1514 int i; 1515 1516 for (i = 0; i < context->stream_count; i++) { 1517 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) 1518 return context->streams[i]; 1519 } 1520 return NULL; 1521 } 1522 1523 static struct dc_link *get_edp_link_with_sink( 1524 struct dc *dc, 1525 struct dc_state *context) 1526 { 1527 int i; 1528 struct dc_link *link = NULL; 1529 1530 /* check if there is an eDP panel not in use */ 1531 for (i = 0; i < dc->link_count; i++) { 1532 if (dc->links[i]->local_sink && 1533 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1534 link = dc->links[i]; 1535 break; 1536 } 1537 } 1538 1539 return link; 1540 } 1541 1542 /** 1543 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 1544 * 1. Power down all DC HW blocks 1545 * 2. Disable VGA engine on all controllers 1546 * 3. Enable power gating for controller 1547 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 1548 */ 1549 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 1550 { 1551 int i; 1552 struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context); 1553 struct dc_link *edp_link = get_edp_link(dc); 1554 struct dc_stream_state *edp_stream = NULL; 1555 bool can_apply_edp_fast_boot = false; 1556 bool can_apply_seamless_boot = false; 1557 bool keep_edp_vdd_on = false; 1558 struct dce_hwseq *hws = dc->hwseq; 1559 1560 if (hws->funcs.init_pipes) 1561 hws->funcs.init_pipes(dc, context); 1562 1563 edp_stream = get_edp_stream(context); 1564 1565 // Check fastboot support, disable on DCE8 because of blank screens 1566 if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 && 1567 dc->ctx->dce_version != DCE_VERSION_8_1 && 1568 dc->ctx->dce_version != DCE_VERSION_8_3) { 1569 1570 // enable fastboot if backend is enabled on eDP 1571 if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) { 1572 /* Set optimization flag on eDP stream*/ 1573 if (edp_stream) { 1574 edp_stream->apply_edp_fast_boot_optimization = true; 1575 can_apply_edp_fast_boot = true; 1576 } 1577 } 1578 1579 // We are trying to enable eDP, don't power down VDD 1580 if (edp_stream) 1581 keep_edp_vdd_on = true; 1582 } 1583 1584 // Check seamless boot support 1585 for (i = 0; i < context->stream_count; i++) { 1586 if (context->streams[i]->apply_seamless_boot_optimization) { 1587 can_apply_seamless_boot = true; 1588 break; 1589 } 1590 } 1591 1592 /* eDP should not have stream in resume from S4 and so even with VBios post 1593 * it should get turned off 1594 */ 1595 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 1596 if (edp_link_with_sink && !keep_edp_vdd_on) { 1597 /*turn off backlight before DP_blank and encoder powered down*/ 1598 hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1599 } 1600 /*resume from S3, no vbios posting, no need to power down again*/ 1601 power_down_all_hw_blocks(dc); 1602 disable_vga_and_power_gate_all_controllers(dc); 1603 if (edp_link_with_sink && !keep_edp_vdd_on) 1604 dc->hwss.edp_power_control(edp_link_with_sink, false); 1605 } 1606 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 1607 } 1608 1609 static uint32_t compute_pstate_blackout_duration( 1610 struct bw_fixed blackout_duration, 1611 const struct dc_stream_state *stream) 1612 { 1613 uint32_t total_dest_line_time_ns; 1614 uint32_t pstate_blackout_duration_ns; 1615 1616 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 1617 1618 total_dest_line_time_ns = 1000000UL * 1619 (stream->timing.h_total * 10) / 1620 stream->timing.pix_clk_100hz + 1621 pstate_blackout_duration_ns; 1622 1623 return total_dest_line_time_ns; 1624 } 1625 1626 static void dce110_set_displaymarks( 1627 const struct dc *dc, 1628 struct dc_state *context) 1629 { 1630 uint8_t i, num_pipes; 1631 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1632 1633 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 1634 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1635 uint32_t total_dest_line_time_ns; 1636 1637 if (pipe_ctx->stream == NULL) 1638 continue; 1639 1640 total_dest_line_time_ns = compute_pstate_blackout_duration( 1641 dc->bw_vbios->blackout_duration, pipe_ctx->stream); 1642 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 1643 pipe_ctx->plane_res.mi, 1644 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1645 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1646 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1647 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1648 total_dest_line_time_ns); 1649 if (i == underlay_idx) { 1650 num_pipes++; 1651 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1652 pipe_ctx->plane_res.mi, 1653 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1654 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1655 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1656 total_dest_line_time_ns); 1657 } 1658 num_pipes++; 1659 } 1660 } 1661 1662 void dce110_set_safe_displaymarks( 1663 struct resource_context *res_ctx, 1664 const struct resource_pool *pool) 1665 { 1666 int i; 1667 int underlay_idx = pool->underlay_pipe_index; 1668 struct dce_watermarks max_marks = { 1669 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 1670 struct dce_watermarks nbp_marks = { 1671 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 1672 struct dce_watermarks min_marks = { 0, 0, 0, 0}; 1673 1674 for (i = 0; i < MAX_PIPES; i++) { 1675 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 1676 continue; 1677 1678 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 1679 res_ctx->pipe_ctx[i].plane_res.mi, 1680 nbp_marks, 1681 max_marks, 1682 min_marks, 1683 max_marks, 1684 MAX_WATERMARK); 1685 1686 if (i == underlay_idx) 1687 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1688 res_ctx->pipe_ctx[i].plane_res.mi, 1689 nbp_marks, 1690 max_marks, 1691 max_marks, 1692 MAX_WATERMARK); 1693 1694 } 1695 } 1696 1697 /******************************************************************************* 1698 * Public functions 1699 ******************************************************************************/ 1700 1701 static void set_drr(struct pipe_ctx **pipe_ctx, 1702 int num_pipes, unsigned int vmin, unsigned int vmax, 1703 unsigned int vmid, unsigned int vmid_frame_number) 1704 { 1705 int i = 0; 1706 struct drr_params params = {0}; 1707 // DRR should set trigger event to monitor surface update event 1708 unsigned int event_triggers = 0x80; 1709 // Note DRR trigger events are generated regardless of whether num frames met. 1710 unsigned int num_frames = 2; 1711 1712 params.vertical_total_max = vmax; 1713 params.vertical_total_min = vmin; 1714 1715 /* TODO: If multiple pipes are to be supported, you need 1716 * some GSL stuff. Static screen triggers may be programmed differently 1717 * as well. 1718 */ 1719 for (i = 0; i < num_pipes; i++) { 1720 pipe_ctx[i]->stream_res.tg->funcs->set_drr( 1721 pipe_ctx[i]->stream_res.tg, ¶ms); 1722 1723 if (vmax != 0 && vmin != 0) 1724 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 1725 pipe_ctx[i]->stream_res.tg, 1726 event_triggers, num_frames); 1727 } 1728 } 1729 1730 static void get_position(struct pipe_ctx **pipe_ctx, 1731 int num_pipes, 1732 struct crtc_position *position) 1733 { 1734 int i = 0; 1735 1736 /* TODO: handle pipes > 1 1737 */ 1738 for (i = 0; i < num_pipes; i++) 1739 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 1740 } 1741 1742 static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 1743 int num_pipes, const struct dc_static_screen_params *params) 1744 { 1745 unsigned int i; 1746 unsigned int triggers = 0; 1747 1748 if (params->triggers.overlay_update) 1749 triggers |= 0x100; 1750 if (params->triggers.surface_update) 1751 triggers |= 0x80; 1752 if (params->triggers.cursor_update) 1753 triggers |= 0x2; 1754 if (params->triggers.force_trigger) 1755 triggers |= 0x1; 1756 1757 if (num_pipes) { 1758 struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1759 1760 if (dc->fbc_compressor) 1761 triggers |= 0x84; 1762 } 1763 1764 for (i = 0; i < num_pipes; i++) 1765 pipe_ctx[i]->stream_res.tg->funcs-> 1766 set_static_screen_control(pipe_ctx[i]->stream_res.tg, 1767 triggers, params->num_frames); 1768 } 1769 1770 /* 1771 * Check if FBC can be enabled 1772 */ 1773 static bool should_enable_fbc(struct dc *dc, 1774 struct dc_state *context, 1775 uint32_t *pipe_idx) 1776 { 1777 uint32_t i; 1778 struct pipe_ctx *pipe_ctx = NULL; 1779 struct resource_context *res_ctx = &context->res_ctx; 1780 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1781 1782 1783 ASSERT(dc->fbc_compressor); 1784 1785 /* FBC memory should be allocated */ 1786 if (!dc->ctx->fbc_gpu_addr) 1787 return false; 1788 1789 /* Only supports single display */ 1790 if (context->stream_count != 1) 1791 return false; 1792 1793 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1794 if (res_ctx->pipe_ctx[i].stream) { 1795 1796 pipe_ctx = &res_ctx->pipe_ctx[i]; 1797 1798 if (!pipe_ctx) 1799 continue; 1800 1801 /* fbc not applicable on underlay pipe */ 1802 if (pipe_ctx->pipe_idx != underlay_idx) { 1803 *pipe_idx = i; 1804 break; 1805 } 1806 } 1807 } 1808 1809 if (i == dc->res_pool->pipe_count) 1810 return false; 1811 1812 if (!pipe_ctx->stream->link) 1813 return false; 1814 1815 /* Only supports eDP */ 1816 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 1817 return false; 1818 1819 /* PSR should not be enabled */ 1820 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 1821 return false; 1822 1823 /* Nothing to compress */ 1824 if (!pipe_ctx->plane_state) 1825 return false; 1826 1827 /* Only for non-linear tiling */ 1828 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 1829 return false; 1830 1831 return true; 1832 } 1833 1834 /* 1835 * Enable FBC 1836 */ 1837 static void enable_fbc( 1838 struct dc *dc, 1839 struct dc_state *context) 1840 { 1841 uint32_t pipe_idx = 0; 1842 1843 if (should_enable_fbc(dc, context, &pipe_idx)) { 1844 /* Program GRPH COMPRESSED ADDRESS and PITCH */ 1845 struct compr_addr_and_pitch_params params = {0, 0, 0}; 1846 struct compressor *compr = dc->fbc_compressor; 1847 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 1848 1849 params.source_view_width = pipe_ctx->stream->timing.h_addressable; 1850 params.source_view_height = pipe_ctx->stream->timing.v_addressable; 1851 params.inst = pipe_ctx->stream_res.tg->inst; 1852 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 1853 1854 compr->funcs->surface_address_and_pitch(compr, ¶ms); 1855 compr->funcs->set_fbc_invalidation_triggers(compr, 1); 1856 1857 compr->funcs->enable_fbc(compr, ¶ms); 1858 } 1859 } 1860 1861 static void dce110_reset_hw_ctx_wrap( 1862 struct dc *dc, 1863 struct dc_state *context) 1864 { 1865 int i; 1866 1867 /* Reset old context */ 1868 /* look up the targets that have been removed since last commit */ 1869 for (i = 0; i < MAX_PIPES; i++) { 1870 struct pipe_ctx *pipe_ctx_old = 1871 &dc->current_state->res_ctx.pipe_ctx[i]; 1872 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1873 1874 /* Note: We need to disable output if clock sources change, 1875 * since bios does optimization and doesn't apply if changing 1876 * PHY when not already disabled. 1877 */ 1878 1879 /* Skip underlay pipe since it will be handled in commit surface*/ 1880 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 1881 continue; 1882 1883 if (!pipe_ctx->stream || 1884 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 1885 struct clock_source *old_clk = pipe_ctx_old->clock_source; 1886 1887 /* Disable if new stream is null. O/w, if stream is 1888 * disabled already, no need to disable again. 1889 */ 1890 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 1891 core_link_disable_stream(pipe_ctx_old); 1892 1893 /* free acquired resources*/ 1894 if (pipe_ctx_old->stream_res.audio) { 1895 /*disable az_endpoint*/ 1896 pipe_ctx_old->stream_res.audio->funcs-> 1897 az_disable(pipe_ctx_old->stream_res.audio); 1898 1899 /*free audio*/ 1900 if (dc->caps.dynamic_audio == true) { 1901 /*we have to dynamic arbitrate the audio endpoints*/ 1902 /*we free the resource, need reset is_audio_acquired*/ 1903 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 1904 pipe_ctx_old->stream_res.audio, false); 1905 pipe_ctx_old->stream_res.audio = NULL; 1906 } 1907 } 1908 } 1909 1910 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 1911 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 1912 dm_error("DC: failed to blank crtc!\n"); 1913 BREAK_TO_DEBUGGER(); 1914 } 1915 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 1916 pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 1917 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 1918 1919 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 1920 dc->res_pool, 1921 old_clk)) 1922 old_clk->funcs->cs_power_down(old_clk); 1923 1924 dc->hwss.disable_plane(dc, pipe_ctx_old); 1925 1926 pipe_ctx_old->stream = NULL; 1927 } 1928 } 1929 } 1930 1931 static void dce110_setup_audio_dto( 1932 struct dc *dc, 1933 struct dc_state *context) 1934 { 1935 int i; 1936 1937 /* program audio wall clock. use HDMI as clock source if HDMI 1938 * audio active. Otherwise, use DP as clock source 1939 * first, loop to find any HDMI audio, if not, loop find DP audio 1940 */ 1941 /* Setup audio rate clock source */ 1942 /* Issue: 1943 * Audio lag happened on DP monitor when unplug a HDMI monitor 1944 * 1945 * Cause: 1946 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 1947 * is set to either dto0 or dto1, audio should work fine. 1948 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 1949 * set to dto0 will cause audio lag. 1950 * 1951 * Solution: 1952 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 1953 * find first available pipe with audio, setup audio wall DTO per topology 1954 * instead of per pipe. 1955 */ 1956 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1957 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1958 1959 if (pipe_ctx->stream == NULL) 1960 continue; 1961 1962 if (pipe_ctx->top_pipe) 1963 continue; 1964 1965 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 1966 continue; 1967 1968 if (pipe_ctx->stream_res.audio != NULL) { 1969 struct audio_output audio_output; 1970 1971 build_audio_output(context, pipe_ctx, &audio_output); 1972 1973 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 1974 pipe_ctx->stream_res.audio, 1975 pipe_ctx->stream->signal, 1976 &audio_output.crtc_info, 1977 &audio_output.pll_info); 1978 break; 1979 } 1980 } 1981 1982 /* no HDMI audio is found, try DP audio */ 1983 if (i == dc->res_pool->pipe_count) { 1984 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1985 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1986 1987 if (pipe_ctx->stream == NULL) 1988 continue; 1989 1990 if (pipe_ctx->top_pipe) 1991 continue; 1992 1993 if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 1994 continue; 1995 1996 if (pipe_ctx->stream_res.audio != NULL) { 1997 struct audio_output audio_output; 1998 1999 build_audio_output(context, pipe_ctx, &audio_output); 2000 2001 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2002 pipe_ctx->stream_res.audio, 2003 pipe_ctx->stream->signal, 2004 &audio_output.crtc_info, 2005 &audio_output.pll_info); 2006 break; 2007 } 2008 } 2009 } 2010 } 2011 2012 enum dc_status dce110_apply_ctx_to_hw( 2013 struct dc *dc, 2014 struct dc_state *context) 2015 { 2016 struct dce_hwseq *hws = dc->hwseq; 2017 struct dc_bios *dcb = dc->ctx->dc_bios; 2018 enum dc_status status; 2019 int i; 2020 2021 /* Reset old context */ 2022 /* look up the targets that have been removed since last commit */ 2023 hws->funcs.reset_hw_ctx_wrap(dc, context); 2024 2025 /* Skip applying if no targets */ 2026 if (context->stream_count <= 0) 2027 return DC_OK; 2028 2029 /* Apply new context */ 2030 dcb->funcs->set_scratch_critical_state(dcb, true); 2031 2032 /* below is for real asic only */ 2033 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2034 struct pipe_ctx *pipe_ctx_old = 2035 &dc->current_state->res_ctx.pipe_ctx[i]; 2036 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2037 2038 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 2039 continue; 2040 2041 if (pipe_ctx->stream == pipe_ctx_old->stream) { 2042 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 2043 dce_crtc_switch_to_clk_src(dc->hwseq, 2044 pipe_ctx->clock_source, i); 2045 continue; 2046 } 2047 2048 hws->funcs.enable_display_power_gating( 2049 dc, i, dc->ctx->dc_bios, 2050 PIPE_GATING_CONTROL_DISABLE); 2051 } 2052 2053 if (dc->fbc_compressor) 2054 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2055 2056 dce110_setup_audio_dto(dc, context); 2057 2058 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2059 struct pipe_ctx *pipe_ctx_old = 2060 &dc->current_state->res_ctx.pipe_ctx[i]; 2061 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2062 2063 if (pipe_ctx->stream == NULL) 2064 continue; 2065 2066 if (pipe_ctx->stream == pipe_ctx_old->stream && 2067 pipe_ctx->stream->link->link_state_valid) { 2068 continue; 2069 } 2070 2071 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2072 continue; 2073 2074 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2075 continue; 2076 2077 status = apply_single_controller_ctx_to_hw( 2078 pipe_ctx, 2079 context, 2080 dc); 2081 2082 if (DC_OK != status) 2083 return status; 2084 } 2085 2086 if (dc->fbc_compressor) 2087 enable_fbc(dc, dc->current_state); 2088 2089 dcb->funcs->set_scratch_critical_state(dcb, false); 2090 2091 return DC_OK; 2092 } 2093 2094 /******************************************************************************* 2095 * Front End programming 2096 ******************************************************************************/ 2097 static void set_default_colors(struct pipe_ctx *pipe_ctx) 2098 { 2099 struct default_adjustment default_adjust = { 0 }; 2100 2101 default_adjust.force_hw_default = false; 2102 default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 2103 default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 2104 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 2105 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 2106 2107 /* display color depth */ 2108 default_adjust.color_depth = 2109 pipe_ctx->stream->timing.display_color_depth; 2110 2111 /* Lb color depth */ 2112 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 2113 2114 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 2115 pipe_ctx->plane_res.xfm, &default_adjust); 2116 } 2117 2118 2119 /******************************************************************************* 2120 * In order to turn on/off specific surface we will program 2121 * Blender + CRTC 2122 * 2123 * In case that we have two surfaces and they have a different visibility 2124 * we can't turn off the CRTC since it will turn off the entire display 2125 * 2126 * |----------------------------------------------- | 2127 * |bottom pipe|curr pipe | | | 2128 * |Surface |Surface | Blender | CRCT | 2129 * |visibility |visibility | Configuration| | 2130 * |------------------------------------------------| 2131 * | off | off | CURRENT_PIPE | blank | 2132 * | off | on | CURRENT_PIPE | unblank | 2133 * | on | off | OTHER_PIPE | unblank | 2134 * | on | on | BLENDING | unblank | 2135 * -------------------------------------------------| 2136 * 2137 ******************************************************************************/ 2138 static void program_surface_visibility(const struct dc *dc, 2139 struct pipe_ctx *pipe_ctx) 2140 { 2141 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2142 bool blank_target = false; 2143 2144 if (pipe_ctx->bottom_pipe) { 2145 2146 /* For now we are supporting only two pipes */ 2147 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2148 2149 if (pipe_ctx->bottom_pipe->plane_state->visible) { 2150 if (pipe_ctx->plane_state->visible) 2151 blender_mode = BLND_MODE_BLENDING; 2152 else 2153 blender_mode = BLND_MODE_OTHER_PIPE; 2154 2155 } else if (!pipe_ctx->plane_state->visible) 2156 blank_target = true; 2157 2158 } else if (!pipe_ctx->plane_state->visible) 2159 blank_target = true; 2160 2161 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 2162 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2163 2164 } 2165 2166 static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 2167 { 2168 int i = 0; 2169 struct xfm_grph_csc_adjustment adjust; 2170 memset(&adjust, 0, sizeof(adjust)); 2171 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2172 2173 2174 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2175 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2176 2177 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2178 adjust.temperature_matrix[i] = 2179 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2180 } 2181 2182 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2183 } 2184 static void update_plane_addr(const struct dc *dc, 2185 struct pipe_ctx *pipe_ctx) 2186 { 2187 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2188 2189 if (plane_state == NULL) 2190 return; 2191 2192 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 2193 pipe_ctx->plane_res.mi, 2194 &plane_state->address, 2195 plane_state->flip_immediate); 2196 2197 plane_state->status.requested_address = plane_state->address; 2198 } 2199 2200 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 2201 { 2202 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2203 2204 if (plane_state == NULL) 2205 return; 2206 2207 plane_state->status.is_flip_pending = 2208 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 2209 pipe_ctx->plane_res.mi); 2210 2211 if (plane_state->status.is_flip_pending && !plane_state->visible) 2212 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 2213 2214 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 2215 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2216 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 2217 plane_state->status.is_right_eye =\ 2218 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 2219 } 2220 } 2221 2222 void dce110_power_down(struct dc *dc) 2223 { 2224 power_down_all_hw_blocks(dc); 2225 disable_vga_and_power_gate_all_controllers(dc); 2226 } 2227 2228 static bool wait_for_reset_trigger_to_occur( 2229 struct dc_context *dc_ctx, 2230 struct timing_generator *tg) 2231 { 2232 bool rc = false; 2233 2234 /* To avoid endless loop we wait at most 2235 * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 2236 const uint32_t frames_to_wait_on_triggered_reset = 10; 2237 uint32_t i; 2238 2239 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 2240 2241 if (!tg->funcs->is_counter_moving(tg)) { 2242 DC_ERROR("TG counter is not moving!\n"); 2243 break; 2244 } 2245 2246 if (tg->funcs->did_triggered_reset_occur(tg)) { 2247 rc = true; 2248 /* usually occurs at i=1 */ 2249 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 2250 i); 2251 break; 2252 } 2253 2254 /* Wait for one frame. */ 2255 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 2256 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 2257 } 2258 2259 if (false == rc) 2260 DC_ERROR("GSL: Timeout on reset trigger!\n"); 2261 2262 return rc; 2263 } 2264 2265 /* Enable timing synchronization for a group of Timing Generators. */ 2266 static void dce110_enable_timing_synchronization( 2267 struct dc *dc, 2268 int group_index, 2269 int group_size, 2270 struct pipe_ctx *grouped_pipes[]) 2271 { 2272 struct dc_context *dc_ctx = dc->ctx; 2273 struct dcp_gsl_params gsl_params = { 0 }; 2274 int i; 2275 2276 DC_SYNC_INFO("GSL: Setting-up...\n"); 2277 2278 /* Designate a single TG in the group as a master. 2279 * Since HW doesn't care which one, we always assign 2280 * the 1st one in the group. */ 2281 gsl_params.gsl_group = 0; 2282 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 2283 2284 for (i = 0; i < group_size; i++) 2285 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2286 grouped_pipes[i]->stream_res.tg, &gsl_params); 2287 2288 /* Reset slave controllers on master VSync */ 2289 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2290 2291 for (i = 1 /* skip the master */; i < group_size; i++) 2292 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2293 grouped_pipes[i]->stream_res.tg, 2294 gsl_params.gsl_group); 2295 2296 for (i = 1 /* skip the master */; i < group_size; i++) { 2297 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2298 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2299 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2300 grouped_pipes[i]->stream_res.tg); 2301 } 2302 2303 /* GSL Vblank synchronization is a one time sync mechanism, assumption 2304 * is that the sync'ed displays will not drift out of sync over time*/ 2305 DC_SYNC_INFO("GSL: Restoring register states.\n"); 2306 for (i = 0; i < group_size; i++) 2307 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2308 2309 DC_SYNC_INFO("GSL: Set-up complete.\n"); 2310 } 2311 2312 static void dce110_enable_per_frame_crtc_position_reset( 2313 struct dc *dc, 2314 int group_size, 2315 struct pipe_ctx *grouped_pipes[]) 2316 { 2317 struct dc_context *dc_ctx = dc->ctx; 2318 struct dcp_gsl_params gsl_params = { 0 }; 2319 int i; 2320 2321 gsl_params.gsl_group = 0; 2322 gsl_params.gsl_master = 0; 2323 2324 for (i = 0; i < group_size; i++) 2325 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2326 grouped_pipes[i]->stream_res.tg, &gsl_params); 2327 2328 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2329 2330 for (i = 1; i < group_size; i++) 2331 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2332 grouped_pipes[i]->stream_res.tg, 2333 gsl_params.gsl_master, 2334 &grouped_pipes[i]->stream->triggered_crtc_reset); 2335 2336 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2337 for (i = 1; i < group_size; i++) 2338 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2339 2340 for (i = 0; i < group_size; i++) 2341 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2342 2343 } 2344 2345 static void init_pipes(struct dc *dc, struct dc_state *context) 2346 { 2347 // Do nothing 2348 } 2349 2350 static void init_hw(struct dc *dc) 2351 { 2352 int i; 2353 struct dc_bios *bp; 2354 struct transform *xfm; 2355 struct abm *abm; 2356 struct dmcu *dmcu; 2357 struct dce_hwseq *hws = dc->hwseq; 2358 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 2359 2360 bp = dc->ctx->dc_bios; 2361 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2362 xfm = dc->res_pool->transforms[i]; 2363 xfm->funcs->transform_reset(xfm); 2364 2365 hws->funcs.enable_display_power_gating( 2366 dc, i, bp, 2367 PIPE_GATING_CONTROL_INIT); 2368 hws->funcs.enable_display_power_gating( 2369 dc, i, bp, 2370 PIPE_GATING_CONTROL_DISABLE); 2371 hws->funcs.enable_display_pipe_clock_gating( 2372 dc->ctx, 2373 true); 2374 } 2375 2376 dce_clock_gating_power_up(dc->hwseq, false); 2377 /***************************************/ 2378 2379 for (i = 0; i < dc->link_count; i++) { 2380 /****************************************/ 2381 /* Power up AND update implementation according to the 2382 * required signal (which may be different from the 2383 * default signal on connector). */ 2384 struct dc_link *link = dc->links[i]; 2385 2386 link->link_enc->funcs->hw_init(link->link_enc); 2387 } 2388 2389 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2390 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2391 2392 tg->funcs->disable_vga(tg); 2393 2394 /* Blank controller using driver code instead of 2395 * command table. */ 2396 tg->funcs->set_blank(tg, true); 2397 hwss_wait_for_blank_complete(tg); 2398 } 2399 2400 for (i = 0; i < dc->res_pool->audio_count; i++) { 2401 struct audio *audio = dc->res_pool->audios[i]; 2402 audio->funcs->hw_init(audio); 2403 } 2404 2405 for (i = 0; i < dc->link_count; i++) { 2406 struct dc_link *link = dc->links[i]; 2407 2408 if (link->panel_cntl) 2409 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 2410 } 2411 2412 abm = dc->res_pool->abm; 2413 if (abm != NULL) 2414 abm->funcs->abm_init(abm, backlight); 2415 2416 dmcu = dc->res_pool->dmcu; 2417 if (dmcu != NULL && abm != NULL) 2418 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 2419 2420 if (dc->fbc_compressor) 2421 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2422 2423 } 2424 2425 2426 void dce110_prepare_bandwidth( 2427 struct dc *dc, 2428 struct dc_state *context) 2429 { 2430 struct clk_mgr *dccg = dc->clk_mgr; 2431 2432 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2433 2434 dccg->funcs->update_clocks( 2435 dccg, 2436 context, 2437 false); 2438 } 2439 2440 void dce110_optimize_bandwidth( 2441 struct dc *dc, 2442 struct dc_state *context) 2443 { 2444 struct clk_mgr *dccg = dc->clk_mgr; 2445 2446 dce110_set_displaymarks(dc, context); 2447 2448 dccg->funcs->update_clocks( 2449 dccg, 2450 context, 2451 true); 2452 } 2453 2454 static void dce110_program_front_end_for_pipe( 2455 struct dc *dc, struct pipe_ctx *pipe_ctx) 2456 { 2457 struct mem_input *mi = pipe_ctx->plane_res.mi; 2458 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2459 struct xfm_grph_csc_adjustment adjust; 2460 struct out_csc_color_matrix tbl_entry; 2461 unsigned int i; 2462 struct dce_hwseq *hws = dc->hwseq; 2463 2464 DC_LOGGER_INIT(); 2465 memset(&tbl_entry, 0, sizeof(tbl_entry)); 2466 2467 memset(&adjust, 0, sizeof(adjust)); 2468 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2469 2470 dce_enable_fe_clock(dc->hwseq, mi->inst, true); 2471 2472 set_default_colors(pipe_ctx); 2473 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 2474 == true) { 2475 tbl_entry.color_space = 2476 pipe_ctx->stream->output_color_space; 2477 2478 for (i = 0; i < 12; i++) 2479 tbl_entry.regval[i] = 2480 pipe_ctx->stream->csc_color_matrix.matrix[i]; 2481 2482 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 2483 (pipe_ctx->plane_res.xfm, &tbl_entry); 2484 } 2485 2486 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2487 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2488 2489 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2490 adjust.temperature_matrix[i] = 2491 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2492 } 2493 2494 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2495 2496 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2497 2498 program_scaler(dc, pipe_ctx); 2499 2500 mi->funcs->mem_input_program_surface_config( 2501 mi, 2502 plane_state->format, 2503 &plane_state->tiling_info, 2504 &plane_state->plane_size, 2505 plane_state->rotation, 2506 NULL, 2507 false); 2508 if (mi->funcs->set_blank) 2509 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 2510 2511 if (dc->config.gpu_vm_support) 2512 mi->funcs->mem_input_program_pte_vm( 2513 pipe_ctx->plane_res.mi, 2514 plane_state->format, 2515 &plane_state->tiling_info, 2516 plane_state->rotation); 2517 2518 /* Moved programming gamma from dc to hwss */ 2519 if (pipe_ctx->plane_state->update_flags.bits.full_update || 2520 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2521 pipe_ctx->plane_state->update_flags.bits.gamma_change) 2522 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2523 2524 if (pipe_ctx->plane_state->update_flags.bits.full_update) 2525 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2526 2527 DC_LOG_SURFACE( 2528 "Pipe:%d %p: addr hi:0x%x, " 2529 "addr low:0x%x, " 2530 "src: %d, %d, %d," 2531 " %d; dst: %d, %d, %d, %d;" 2532 "clip: %d, %d, %d, %d\n", 2533 pipe_ctx->pipe_idx, 2534 (void *) pipe_ctx->plane_state, 2535 pipe_ctx->plane_state->address.grph.addr.high_part, 2536 pipe_ctx->plane_state->address.grph.addr.low_part, 2537 pipe_ctx->plane_state->src_rect.x, 2538 pipe_ctx->plane_state->src_rect.y, 2539 pipe_ctx->plane_state->src_rect.width, 2540 pipe_ctx->plane_state->src_rect.height, 2541 pipe_ctx->plane_state->dst_rect.x, 2542 pipe_ctx->plane_state->dst_rect.y, 2543 pipe_ctx->plane_state->dst_rect.width, 2544 pipe_ctx->plane_state->dst_rect.height, 2545 pipe_ctx->plane_state->clip_rect.x, 2546 pipe_ctx->plane_state->clip_rect.y, 2547 pipe_ctx->plane_state->clip_rect.width, 2548 pipe_ctx->plane_state->clip_rect.height); 2549 2550 DC_LOG_SURFACE( 2551 "Pipe %d: width, height, x, y\n" 2552 "viewport:%d, %d, %d, %d\n" 2553 "recout: %d, %d, %d, %d\n", 2554 pipe_ctx->pipe_idx, 2555 pipe_ctx->plane_res.scl_data.viewport.width, 2556 pipe_ctx->plane_res.scl_data.viewport.height, 2557 pipe_ctx->plane_res.scl_data.viewport.x, 2558 pipe_ctx->plane_res.scl_data.viewport.y, 2559 pipe_ctx->plane_res.scl_data.recout.width, 2560 pipe_ctx->plane_res.scl_data.recout.height, 2561 pipe_ctx->plane_res.scl_data.recout.x, 2562 pipe_ctx->plane_res.scl_data.recout.y); 2563 } 2564 2565 static void dce110_apply_ctx_for_surface( 2566 struct dc *dc, 2567 const struct dc_stream_state *stream, 2568 int num_planes, 2569 struct dc_state *context) 2570 { 2571 int i; 2572 2573 if (num_planes == 0) 2574 return; 2575 2576 if (dc->fbc_compressor) 2577 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2578 2579 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2580 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2581 2582 if (pipe_ctx->stream != stream) 2583 continue; 2584 2585 /* Need to allocate mem before program front end for Fiji */ 2586 pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 2587 pipe_ctx->plane_res.mi, 2588 pipe_ctx->stream->timing.h_total, 2589 pipe_ctx->stream->timing.v_total, 2590 pipe_ctx->stream->timing.pix_clk_100hz / 10, 2591 context->stream_count); 2592 2593 dce110_program_front_end_for_pipe(dc, pipe_ctx); 2594 2595 dc->hwss.update_plane_addr(dc, pipe_ctx); 2596 2597 program_surface_visibility(dc, pipe_ctx); 2598 2599 } 2600 2601 if (dc->fbc_compressor) 2602 enable_fbc(dc, context); 2603 } 2604 2605 static void dce110_post_unlock_program_front_end( 2606 struct dc *dc, 2607 struct dc_state *context) 2608 { 2609 } 2610 2611 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 2612 { 2613 struct dce_hwseq *hws = dc->hwseq; 2614 int fe_idx = pipe_ctx->plane_res.mi ? 2615 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2616 2617 /* Do not power down fe when stream is active on dce*/ 2618 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 2619 return; 2620 2621 hws->funcs.enable_display_power_gating( 2622 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2623 2624 dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2625 dc->res_pool->transforms[fe_idx]); 2626 } 2627 2628 static void dce110_wait_for_mpcc_disconnect( 2629 struct dc *dc, 2630 struct resource_pool *res_pool, 2631 struct pipe_ctx *pipe_ctx) 2632 { 2633 /* do nothing*/ 2634 } 2635 2636 static void program_output_csc(struct dc *dc, 2637 struct pipe_ctx *pipe_ctx, 2638 enum dc_color_space colorspace, 2639 uint16_t *matrix, 2640 int opp_id) 2641 { 2642 int i; 2643 struct out_csc_color_matrix tbl_entry; 2644 2645 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 2646 enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 2647 2648 for (i = 0; i < 12; i++) 2649 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 2650 2651 tbl_entry.color_space = color_space; 2652 2653 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 2654 pipe_ctx->plane_res.xfm, &tbl_entry); 2655 } 2656 } 2657 2658 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 2659 { 2660 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 2661 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2662 struct mem_input *mi = pipe_ctx->plane_res.mi; 2663 struct dc_cursor_mi_param param = { 2664 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 2665 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 2666 .viewport = pipe_ctx->plane_res.scl_data.viewport, 2667 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 2668 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 2669 .rotation = pipe_ctx->plane_state->rotation, 2670 .mirror = pipe_ctx->plane_state->horizontal_mirror 2671 }; 2672 2673 /** 2674 * If the cursor's source viewport is clipped then we need to 2675 * translate the cursor to appear in the correct position on 2676 * the screen. 2677 * 2678 * This translation isn't affected by scaling so it needs to be 2679 * done *after* we adjust the position for the scale factor. 2680 * 2681 * This is only done by opt-in for now since there are still 2682 * some usecases like tiled display that might enable the 2683 * cursor on both streams while expecting dc to clip it. 2684 */ 2685 if (pos_cpy.translate_by_source) { 2686 pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 2687 pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2688 } 2689 2690 if (pipe_ctx->plane_state->address.type 2691 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2692 pos_cpy.enable = false; 2693 2694 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 2695 pos_cpy.enable = false; 2696 2697 if (ipp->funcs->ipp_cursor_set_position) 2698 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2699 if (mi->funcs->set_cursor_position) 2700 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 2701 } 2702 2703 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 2704 { 2705 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 2706 2707 if (pipe_ctx->plane_res.ipp && 2708 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 2709 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 2710 pipe_ctx->plane_res.ipp, attributes); 2711 2712 if (pipe_ctx->plane_res.mi && 2713 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 2714 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 2715 pipe_ctx->plane_res.mi, attributes); 2716 2717 if (pipe_ctx->plane_res.xfm && 2718 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 2719 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 2720 pipe_ctx->plane_res.xfm, attributes); 2721 } 2722 2723 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 2724 uint32_t backlight_pwm_u16_16, 2725 uint32_t frame_ramp) 2726 { 2727 struct dc_link *link = pipe_ctx->stream->link; 2728 struct dc *dc = link->ctx->dc; 2729 struct abm *abm = pipe_ctx->stream_res.abm; 2730 struct panel_cntl *panel_cntl = link->panel_cntl; 2731 struct dmcu *dmcu = dc->res_pool->dmcu; 2732 bool fw_set_brightness = true; 2733 /* DMCU -1 for all controller id values, 2734 * therefore +1 here 2735 */ 2736 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 2737 2738 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 2739 return false; 2740 2741 if (dmcu) 2742 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 2743 2744 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 2745 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 2746 else 2747 abm->funcs->set_backlight_level_pwm( 2748 abm, 2749 backlight_pwm_u16_16, 2750 frame_ramp, 2751 controller_id, 2752 link->panel_cntl->inst); 2753 2754 return true; 2755 } 2756 2757 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 2758 { 2759 struct abm *abm = pipe_ctx->stream_res.abm; 2760 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 2761 2762 if (abm) 2763 abm->funcs->set_abm_immediate_disable(abm, 2764 pipe_ctx->stream->link->panel_cntl->inst); 2765 2766 if (panel_cntl) 2767 panel_cntl->funcs->store_backlight_level(panel_cntl); 2768 } 2769 2770 static const struct hw_sequencer_funcs dce110_funcs = { 2771 .program_gamut_remap = program_gamut_remap, 2772 .program_output_csc = program_output_csc, 2773 .init_hw = init_hw, 2774 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 2775 .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 2776 .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 2777 .update_plane_addr = update_plane_addr, 2778 .update_pending_status = dce110_update_pending_status, 2779 .enable_accelerated_mode = dce110_enable_accelerated_mode, 2780 .enable_timing_synchronization = dce110_enable_timing_synchronization, 2781 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 2782 .update_info_frame = dce110_update_info_frame, 2783 .enable_stream = dce110_enable_stream, 2784 .disable_stream = dce110_disable_stream, 2785 .unblank_stream = dce110_unblank_stream, 2786 .blank_stream = dce110_blank_stream, 2787 .enable_audio_stream = dce110_enable_audio_stream, 2788 .disable_audio_stream = dce110_disable_audio_stream, 2789 .disable_plane = dce110_power_down_fe, 2790 .pipe_control_lock = dce_pipe_control_lock, 2791 .interdependent_update_lock = NULL, 2792 .cursor_lock = dce_pipe_control_lock, 2793 .prepare_bandwidth = dce110_prepare_bandwidth, 2794 .optimize_bandwidth = dce110_optimize_bandwidth, 2795 .set_drr = set_drr, 2796 .get_position = get_position, 2797 .set_static_screen_control = set_static_screen_control, 2798 .setup_stereo = NULL, 2799 .set_avmute = dce110_set_avmute, 2800 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 2801 .edp_power_control = dce110_edp_power_control, 2802 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 2803 .set_cursor_position = dce110_set_cursor_position, 2804 .set_cursor_attribute = dce110_set_cursor_attribute, 2805 .set_backlight_level = dce110_set_backlight_level, 2806 .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 2807 }; 2808 2809 static const struct hwseq_private_funcs dce110_private_funcs = { 2810 .init_pipes = init_pipes, 2811 .update_plane_addr = update_plane_addr, 2812 .set_input_transfer_func = dce110_set_input_transfer_func, 2813 .set_output_transfer_func = dce110_set_output_transfer_func, 2814 .power_down = dce110_power_down, 2815 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 2816 .enable_display_power_gating = dce110_enable_display_power_gating, 2817 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 2818 .enable_stream_timing = dce110_enable_stream_timing, 2819 .disable_stream_gating = NULL, 2820 .enable_stream_gating = NULL, 2821 .edp_backlight_control = dce110_edp_backlight_control, 2822 }; 2823 2824 void dce110_hw_sequencer_construct(struct dc *dc) 2825 { 2826 dc->hwss = dce110_funcs; 2827 dc->hwseq->funcs = dce110_private_funcs; 2828 } 2829 2830