1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 #include "dc_bios_types.h" 29 #include "core_types.h" 30 #include "core_status.h" 31 #include "resource.h" 32 #include "dm_helpers.h" 33 #include "dce110_timing_generator.h" 34 #include "dce/dce_hwseq.h" 35 #include "gpio_service_interface.h" 36 37 #include "dce110_compressor.h" 38 39 #include "bios/bios_parser_helper.h" 40 #include "timing_generator.h" 41 #include "mem_input.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "transform.h" 45 #include "stream_encoder.h" 46 #include "link_encoder.h" 47 #include "link_enc_cfg.h" 48 #include "link_hwss.h" 49 #include "dc_link_dp.h" 50 #include "dccg.h" 51 #include "clock_source.h" 52 #include "clk_mgr.h" 53 #include "abm.h" 54 #include "audio.h" 55 #include "reg_helper.h" 56 #include "panel_cntl.h" 57 #include "inc/link_dpcd.h" 58 #include "dpcd_defs.h" 59 /* include DCE11 register header files */ 60 #include "dce/dce_11_0_d.h" 61 #include "dce/dce_11_0_sh_mask.h" 62 #include "custom_float.h" 63 64 #include "atomfirmware.h" 65 66 #include "dcn10/dcn10_hw_sequencer.h" 67 68 #include "link/link_dp_trace.h" 69 #include "dce110_hw_sequencer.h" 70 71 #define GAMMA_HW_POINTS_NUM 256 72 73 /* 74 * All values are in milliseconds; 75 * For eDP, after power-up/power/down, 76 * 300/500 msec max. delay from LCDVCC to black video generation 77 */ 78 #define PANEL_POWER_UP_TIMEOUT 300 79 #define PANEL_POWER_DOWN_TIMEOUT 500 80 #define HPD_CHECK_INTERVAL 10 81 #define OLED_POST_T7_DELAY 100 82 #define OLED_PRE_T11_DELAY 150 83 84 #define CTX \ 85 hws->ctx 86 87 #define DC_LOGGER_INIT() 88 89 #define REG(reg)\ 90 hws->regs->reg 91 92 #undef FN 93 #define FN(reg_name, field_name) \ 94 hws->shifts->field_name, hws->masks->field_name 95 96 struct dce110_hw_seq_reg_offsets { 97 uint32_t crtc; 98 }; 99 100 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 101 { 102 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 103 }, 104 { 105 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 106 }, 107 { 108 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 109 }, 110 { 111 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 112 } 113 }; 114 115 #define HW_REG_BLND(reg, id)\ 116 (reg + reg_offsets[id].blnd) 117 118 #define HW_REG_CRTC(reg, id)\ 119 (reg + reg_offsets[id].crtc) 120 121 #define MAX_WATERMARK 0xFFFF 122 #define SAFE_NBP_MARK 0x7FFF 123 124 /******************************************************************************* 125 * Private definitions 126 ******************************************************************************/ 127 /***************************PIPE_CONTROL***********************************/ 128 static void dce110_init_pte(struct dc_context *ctx) 129 { 130 uint32_t addr; 131 uint32_t value = 0; 132 uint32_t chunk_int = 0; 133 uint32_t chunk_mul = 0; 134 135 addr = mmUNP_DVMM_PTE_CONTROL; 136 value = dm_read_reg(ctx, addr); 137 138 set_reg_field_value( 139 value, 140 0, 141 DVMM_PTE_CONTROL, 142 DVMM_USE_SINGLE_PTE); 143 144 set_reg_field_value( 145 value, 146 1, 147 DVMM_PTE_CONTROL, 148 DVMM_PTE_BUFFER_MODE0); 149 150 set_reg_field_value( 151 value, 152 1, 153 DVMM_PTE_CONTROL, 154 DVMM_PTE_BUFFER_MODE1); 155 156 dm_write_reg(ctx, addr, value); 157 158 addr = mmDVMM_PTE_REQ; 159 value = dm_read_reg(ctx, addr); 160 161 chunk_int = get_reg_field_value( 162 value, 163 DVMM_PTE_REQ, 164 HFLIP_PTEREQ_PER_CHUNK_INT); 165 166 chunk_mul = get_reg_field_value( 167 value, 168 DVMM_PTE_REQ, 169 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 170 171 if (chunk_int != 0x4 || chunk_mul != 0x4) { 172 173 set_reg_field_value( 174 value, 175 255, 176 DVMM_PTE_REQ, 177 MAX_PTEREQ_TO_ISSUE); 178 179 set_reg_field_value( 180 value, 181 4, 182 DVMM_PTE_REQ, 183 HFLIP_PTEREQ_PER_CHUNK_INT); 184 185 set_reg_field_value( 186 value, 187 4, 188 DVMM_PTE_REQ, 189 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 190 191 dm_write_reg(ctx, addr, value); 192 } 193 } 194 /**************************************************************************/ 195 196 static void enable_display_pipe_clock_gating( 197 struct dc_context *ctx, 198 bool clock_gating) 199 { 200 /*TODO*/ 201 } 202 203 static bool dce110_enable_display_power_gating( 204 struct dc *dc, 205 uint8_t controller_id, 206 struct dc_bios *dcb, 207 enum pipe_gating_control power_gating) 208 { 209 enum bp_result bp_result = BP_RESULT_OK; 210 enum bp_pipe_control_action cntl; 211 struct dc_context *ctx = dc->ctx; 212 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 213 214 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 215 return true; 216 217 if (power_gating == PIPE_GATING_CONTROL_INIT) 218 cntl = ASIC_PIPE_INIT; 219 else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 220 cntl = ASIC_PIPE_ENABLE; 221 else 222 cntl = ASIC_PIPE_DISABLE; 223 224 if (controller_id == underlay_idx) 225 controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 226 227 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 228 229 bp_result = dcb->funcs->enable_disp_power_gating( 230 dcb, controller_id + 1, cntl); 231 232 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 233 * by default when command table is called 234 * 235 * Bios parser accepts controller_id = 6 as indicative of 236 * underlay pipe in dce110. But we do not support more 237 * than 3. 238 */ 239 if (controller_id < CONTROLLER_ID_MAX - 1) 240 dm_write_reg(ctx, 241 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 242 0); 243 } 244 245 if (power_gating != PIPE_GATING_CONTROL_ENABLE) 246 dce110_init_pte(ctx); 247 248 if (bp_result == BP_RESULT_OK) 249 return true; 250 else 251 return false; 252 } 253 254 static void build_prescale_params(struct ipp_prescale_params *prescale_params, 255 const struct dc_plane_state *plane_state) 256 { 257 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 258 259 switch (plane_state->format) { 260 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 261 prescale_params->scale = 0x2082; 262 break; 263 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 264 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 265 prescale_params->scale = 0x2020; 266 break; 267 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 268 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 269 prescale_params->scale = 0x2008; 270 break; 271 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 272 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 273 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 274 prescale_params->scale = 0x2000; 275 break; 276 default: 277 ASSERT(false); 278 break; 279 } 280 } 281 282 static bool 283 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 284 const struct dc_plane_state *plane_state) 285 { 286 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 287 const struct dc_transfer_func *tf = NULL; 288 struct ipp_prescale_params prescale_params = { 0 }; 289 bool result = true; 290 291 if (ipp == NULL) 292 return false; 293 294 if (plane_state->in_transfer_func) 295 tf = plane_state->in_transfer_func; 296 297 build_prescale_params(&prescale_params, plane_state); 298 ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 299 300 if (plane_state->gamma_correction && 301 !plane_state->gamma_correction->is_identity && 302 dce_use_lut(plane_state->format)) 303 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 304 305 if (tf == NULL) { 306 /* Default case if no input transfer function specified */ 307 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 308 } else if (tf->type == TF_TYPE_PREDEFINED) { 309 switch (tf->tf) { 310 case TRANSFER_FUNCTION_SRGB: 311 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 312 break; 313 case TRANSFER_FUNCTION_BT709: 314 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 315 break; 316 case TRANSFER_FUNCTION_LINEAR: 317 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 318 break; 319 case TRANSFER_FUNCTION_PQ: 320 default: 321 result = false; 322 break; 323 } 324 } else if (tf->type == TF_TYPE_BYPASS) { 325 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 326 } else { 327 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 328 result = false; 329 } 330 331 return result; 332 } 333 334 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 335 struct curve_points *arr_points, 336 uint32_t hw_points_num) 337 { 338 struct custom_float_format fmt; 339 340 struct pwl_result_data *rgb = rgb_resulted; 341 342 uint32_t i = 0; 343 344 fmt.exponenta_bits = 6; 345 fmt.mantissa_bits = 12; 346 fmt.sign = true; 347 348 if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 349 &arr_points[0].custom_float_x)) { 350 BREAK_TO_DEBUGGER(); 351 return false; 352 } 353 354 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 355 &arr_points[0].custom_float_offset)) { 356 BREAK_TO_DEBUGGER(); 357 return false; 358 } 359 360 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 361 &arr_points[0].custom_float_slope)) { 362 BREAK_TO_DEBUGGER(); 363 return false; 364 } 365 366 fmt.mantissa_bits = 10; 367 fmt.sign = false; 368 369 if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 370 &arr_points[1].custom_float_x)) { 371 BREAK_TO_DEBUGGER(); 372 return false; 373 } 374 375 if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 376 &arr_points[1].custom_float_y)) { 377 BREAK_TO_DEBUGGER(); 378 return false; 379 } 380 381 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 382 &arr_points[1].custom_float_slope)) { 383 BREAK_TO_DEBUGGER(); 384 return false; 385 } 386 387 fmt.mantissa_bits = 12; 388 fmt.sign = true; 389 390 while (i != hw_points_num) { 391 if (!convert_to_custom_float_format(rgb->red, &fmt, 392 &rgb->red_reg)) { 393 BREAK_TO_DEBUGGER(); 394 return false; 395 } 396 397 if (!convert_to_custom_float_format(rgb->green, &fmt, 398 &rgb->green_reg)) { 399 BREAK_TO_DEBUGGER(); 400 return false; 401 } 402 403 if (!convert_to_custom_float_format(rgb->blue, &fmt, 404 &rgb->blue_reg)) { 405 BREAK_TO_DEBUGGER(); 406 return false; 407 } 408 409 if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 410 &rgb->delta_red_reg)) { 411 BREAK_TO_DEBUGGER(); 412 return false; 413 } 414 415 if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 416 &rgb->delta_green_reg)) { 417 BREAK_TO_DEBUGGER(); 418 return false; 419 } 420 421 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 422 &rgb->delta_blue_reg)) { 423 BREAK_TO_DEBUGGER(); 424 return false; 425 } 426 427 ++rgb; 428 ++i; 429 } 430 431 return true; 432 } 433 434 #define MAX_LOW_POINT 25 435 #define NUMBER_REGIONS 16 436 #define NUMBER_SW_SEGMENTS 16 437 438 static bool 439 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 440 struct pwl_params *regamma_params) 441 { 442 struct curve_points *arr_points; 443 struct pwl_result_data *rgb_resulted; 444 struct pwl_result_data *rgb; 445 struct pwl_result_data *rgb_plus_1; 446 struct fixed31_32 y_r; 447 struct fixed31_32 y_g; 448 struct fixed31_32 y_b; 449 struct fixed31_32 y1_min; 450 struct fixed31_32 y3_max; 451 452 int32_t region_start, region_end; 453 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 454 455 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 456 return false; 457 458 arr_points = regamma_params->arr_points; 459 rgb_resulted = regamma_params->rgb_resulted; 460 hw_points = 0; 461 462 memset(regamma_params, 0, sizeof(struct pwl_params)); 463 464 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 465 /* 16 segments 466 * segments are from 2^-11 to 2^5 467 */ 468 region_start = -11; 469 region_end = region_start + NUMBER_REGIONS; 470 471 for (i = 0; i < NUMBER_REGIONS; i++) 472 seg_distr[i] = 4; 473 474 } else { 475 /* 10 segments 476 * segment is from 2^-10 to 2^1 477 * We include an extra segment for range [2^0, 2^1). This is to 478 * ensure that colors with normalized values of 1 don't miss the 479 * LUT. 480 */ 481 region_start = -10; 482 region_end = 1; 483 484 seg_distr[0] = 4; 485 seg_distr[1] = 4; 486 seg_distr[2] = 4; 487 seg_distr[3] = 4; 488 seg_distr[4] = 4; 489 seg_distr[5] = 4; 490 seg_distr[6] = 4; 491 seg_distr[7] = 4; 492 seg_distr[8] = 4; 493 seg_distr[9] = 4; 494 seg_distr[10] = 0; 495 seg_distr[11] = -1; 496 seg_distr[12] = -1; 497 seg_distr[13] = -1; 498 seg_distr[14] = -1; 499 seg_distr[15] = -1; 500 } 501 502 for (k = 0; k < 16; k++) { 503 if (seg_distr[k] != -1) 504 hw_points += (1 << seg_distr[k]); 505 } 506 507 j = 0; 508 for (k = 0; k < (region_end - region_start); k++) { 509 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 510 start_index = (region_start + k + MAX_LOW_POINT) * 511 NUMBER_SW_SEGMENTS; 512 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 513 i += increment) { 514 if (j == hw_points - 1) 515 break; 516 rgb_resulted[j].red = output_tf->tf_pts.red[i]; 517 rgb_resulted[j].green = output_tf->tf_pts.green[i]; 518 rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 519 j++; 520 } 521 } 522 523 /* last point */ 524 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 525 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 526 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 527 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 528 529 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 530 dc_fixpt_from_int(region_start)); 531 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 532 dc_fixpt_from_int(region_end)); 533 534 y_r = rgb_resulted[0].red; 535 y_g = rgb_resulted[0].green; 536 y_b = rgb_resulted[0].blue; 537 538 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 539 540 arr_points[0].y = y1_min; 541 arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 542 arr_points[0].x); 543 544 y_r = rgb_resulted[hw_points - 1].red; 545 y_g = rgb_resulted[hw_points - 1].green; 546 y_b = rgb_resulted[hw_points - 1].blue; 547 548 /* see comment above, m_arrPoints[1].y should be the Y value for the 549 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 550 */ 551 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 552 553 arr_points[1].y = y3_max; 554 555 arr_points[1].slope = dc_fixpt_zero; 556 557 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 558 /* for PQ, we want to have a straight line from last HW X point, 559 * and the slope to be such that we hit 1.0 at 10000 nits. 560 */ 561 const struct fixed31_32 end_value = dc_fixpt_from_int(125); 562 563 arr_points[1].slope = dc_fixpt_div( 564 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 565 dc_fixpt_sub(end_value, arr_points[1].x)); 566 } 567 568 regamma_params->hw_points_num = hw_points; 569 570 k = 0; 571 for (i = 1; i < 16; i++) { 572 if (seg_distr[k] != -1) { 573 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 574 regamma_params->arr_curve_points[i].offset = 575 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 576 } 577 k++; 578 } 579 580 if (seg_distr[k] != -1) 581 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 582 583 rgb = rgb_resulted; 584 rgb_plus_1 = rgb_resulted + 1; 585 586 i = 1; 587 588 while (i != hw_points + 1) { 589 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 590 rgb_plus_1->red = rgb->red; 591 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 592 rgb_plus_1->green = rgb->green; 593 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 594 rgb_plus_1->blue = rgb->blue; 595 596 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 597 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 598 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 599 600 ++rgb_plus_1; 601 ++rgb; 602 ++i; 603 } 604 605 convert_to_custom_float(rgb_resulted, arr_points, hw_points); 606 607 return true; 608 } 609 610 static bool 611 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 612 const struct dc_stream_state *stream) 613 { 614 struct transform *xfm = pipe_ctx->plane_res.xfm; 615 616 xfm->funcs->opp_power_on_regamma_lut(xfm, true); 617 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 618 619 if (stream->out_transfer_func && 620 stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 621 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 622 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 623 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 624 &xfm->regamma_params)) { 625 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 626 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 627 } else { 628 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 629 } 630 631 xfm->funcs->opp_power_on_regamma_lut(xfm, false); 632 633 return true; 634 } 635 636 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 637 { 638 bool is_hdmi_tmds; 639 bool is_dp; 640 641 ASSERT(pipe_ctx->stream); 642 643 if (pipe_ctx->stream_res.stream_enc == NULL) 644 return; /* this is not root pipe */ 645 646 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 647 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 648 649 if (!is_hdmi_tmds && !is_dp) 650 return; 651 652 if (is_hdmi_tmds) 653 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 654 pipe_ctx->stream_res.stream_enc, 655 &pipe_ctx->stream_res.encoder_info_frame); 656 else 657 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 658 pipe_ctx->stream_res.stream_enc, 659 &pipe_ctx->stream_res.encoder_info_frame); 660 } 661 662 void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 663 { 664 enum dc_lane_count lane_count = 665 pipe_ctx->stream->link->cur_link_settings.lane_count; 666 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 667 struct dc_link *link = pipe_ctx->stream->link; 668 const struct dc *dc = link->dc; 669 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 670 uint32_t active_total_with_borders; 671 uint32_t early_control = 0; 672 struct timing_generator *tg = pipe_ctx->stream_res.tg; 673 674 link_hwss->setup_stream_encoder(pipe_ctx); 675 676 dc->hwss.update_info_frame(pipe_ctx); 677 678 /* enable early control to avoid corruption on DP monitor*/ 679 active_total_with_borders = 680 timing->h_addressable 681 + timing->h_border_left 682 + timing->h_border_right; 683 684 if (lane_count != 0) 685 early_control = active_total_with_borders % lane_count; 686 687 if (early_control == 0) 688 early_control = lane_count; 689 690 tg->funcs->set_early_control(tg, early_control); 691 692 /* enable audio only within mode set */ 693 if (pipe_ctx->stream_res.audio != NULL) { 694 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 695 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 696 } 697 698 699 700 701 } 702 703 static enum bp_result link_transmitter_control( 704 struct dc_bios *bios, 705 struct bp_transmitter_control *cntl) 706 { 707 enum bp_result result; 708 709 result = bios->funcs->transmitter_control(bios, cntl); 710 711 return result; 712 } 713 714 /* 715 * @brief 716 * eDP only. 717 */ 718 void dce110_edp_wait_for_hpd_ready( 719 struct dc_link *link, 720 bool power_up) 721 { 722 struct dc_context *ctx = link->ctx; 723 struct graphics_object_id connector = link->link_enc->connector; 724 struct gpio *hpd; 725 struct dc_sink *sink = link->local_sink; 726 bool edp_hpd_high = false; 727 uint32_t time_elapsed = 0; 728 uint32_t timeout = power_up ? 729 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 730 731 if (dal_graphics_object_id_get_connector_id(connector) 732 != CONNECTOR_ID_EDP) { 733 BREAK_TO_DEBUGGER(); 734 return; 735 } 736 737 if (!power_up) 738 /* 739 * From KV, we will not HPD low after turning off VCC - 740 * instead, we will check the SW timer in power_up(). 741 */ 742 return; 743 744 /* 745 * When we power on/off the eDP panel, 746 * we need to wait until SENSE bit is high/low. 747 */ 748 749 /* obtain HPD */ 750 /* TODO what to do with this? */ 751 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 752 753 if (!hpd) { 754 BREAK_TO_DEBUGGER(); 755 return; 756 } 757 758 if (sink != NULL) { 759 if (sink->edid_caps.panel_patch.extra_t3_ms > 0) { 760 int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms; 761 762 msleep(extra_t3_in_ms); 763 } 764 } 765 766 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 767 768 /* wait until timeout or panel detected */ 769 770 do { 771 uint32_t detected = 0; 772 773 dal_gpio_get_value(hpd, &detected); 774 775 if (!(detected ^ power_up)) { 776 edp_hpd_high = true; 777 break; 778 } 779 780 msleep(HPD_CHECK_INTERVAL); 781 782 time_elapsed += HPD_CHECK_INTERVAL; 783 } while (time_elapsed < timeout); 784 785 dal_gpio_close(hpd); 786 787 dal_gpio_destroy_irq(&hpd); 788 789 if (false == edp_hpd_high) { 790 DC_LOG_WARNING( 791 "%s: wait timed out!\n", __func__); 792 } 793 } 794 795 void dce110_edp_power_control( 796 struct dc_link *link, 797 bool power_up) 798 { 799 struct dc_context *ctx = link->ctx; 800 struct bp_transmitter_control cntl = { 0 }; 801 enum bp_result bp_result; 802 uint8_t panel_instance; 803 804 805 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 806 != CONNECTOR_ID_EDP) { 807 BREAK_TO_DEBUGGER(); 808 return; 809 } 810 811 if (!link->panel_cntl) 812 return; 813 if (power_up != 814 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 815 816 unsigned long long current_ts = dm_get_timestamp(ctx); 817 unsigned long long time_since_edp_poweroff_ms = 818 div64_u64(dm_get_elapse_time_in_ns( 819 ctx, 820 current_ts, 821 dp_trace_get_edp_poweroff_timestamp(link)), 1000000); 822 unsigned long long time_since_edp_poweron_ms = 823 div64_u64(dm_get_elapse_time_in_ns( 824 ctx, 825 current_ts, 826 dp_trace_get_edp_poweron_timestamp(link)), 1000000); 827 DC_LOG_HW_RESUME_S3( 828 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 829 __func__, 830 power_up, 831 current_ts, 832 dp_trace_get_edp_poweroff_timestamp(link), 833 dp_trace_get_edp_poweron_timestamp(link), 834 time_since_edp_poweroff_ms, 835 time_since_edp_poweron_ms); 836 837 /* Send VBIOS command to prompt eDP panel power */ 838 if (power_up) { 839 /* edp requires a min of 500ms from LCDVDD off to on */ 840 unsigned long long remaining_min_edp_poweroff_time_ms = 500; 841 842 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 843 if (link->local_sink != NULL) 844 remaining_min_edp_poweroff_time_ms += 845 link->local_sink->edid_caps.panel_patch.extra_t12_ms; 846 847 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 848 if (dp_trace_get_edp_poweroff_timestamp(link) != 0) { 849 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 850 remaining_min_edp_poweroff_time_ms = 851 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 852 else 853 remaining_min_edp_poweroff_time_ms = 0; 854 } 855 856 if (remaining_min_edp_poweroff_time_ms) { 857 DC_LOG_HW_RESUME_S3( 858 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 859 __func__, remaining_min_edp_poweroff_time_ms); 860 msleep(remaining_min_edp_poweroff_time_ms); 861 DC_LOG_HW_RESUME_S3( 862 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 863 __func__, remaining_min_edp_poweroff_time_ms); 864 dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 865 __func__, remaining_min_edp_poweroff_time_ms); 866 } else { 867 DC_LOG_HW_RESUME_S3( 868 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 869 __func__, remaining_min_edp_poweroff_time_ms); 870 } 871 } 872 873 DC_LOG_HW_RESUME_S3( 874 "%s: BEGIN: Panel Power action: %s\n", 875 __func__, (power_up ? "On":"Off")); 876 877 cntl.action = power_up ? 878 TRANSMITTER_CONTROL_POWER_ON : 879 TRANSMITTER_CONTROL_POWER_OFF; 880 cntl.transmitter = link->link_enc->transmitter; 881 cntl.connector_obj_id = link->link_enc->connector; 882 cntl.coherent = false; 883 cntl.lanes_number = LANE_COUNT_FOUR; 884 cntl.hpd_sel = link->link_enc->hpd_source; 885 panel_instance = link->panel_cntl->inst; 886 887 if (ctx->dc->ctx->dmub_srv && 888 ctx->dc->debug.dmub_command_table) { 889 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) 890 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 891 LVTMA_CONTROL_POWER_ON, 892 panel_instance); 893 else 894 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 895 LVTMA_CONTROL_POWER_OFF, 896 panel_instance); 897 } 898 899 bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 900 901 DC_LOG_HW_RESUME_S3( 902 "%s: END: Panel Power action: %s bp_result=%u\n", 903 __func__, (power_up ? "On":"Off"), 904 bp_result); 905 906 dp_trace_set_edp_power_timestamp(link, power_up); 907 908 DC_LOG_HW_RESUME_S3( 909 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 910 __func__, 911 dp_trace_get_edp_poweroff_timestamp(link), 912 dp_trace_get_edp_poweron_timestamp(link)); 913 914 if (bp_result != BP_RESULT_OK) 915 DC_LOG_ERROR( 916 "%s: Panel Power bp_result: %d\n", 917 __func__, bp_result); 918 } else { 919 DC_LOG_HW_RESUME_S3( 920 "%s: Skipping Panel Power action: %s\n", 921 __func__, (power_up ? "On":"Off")); 922 } 923 } 924 925 void dce110_edp_wait_for_T12( 926 struct dc_link *link) 927 { 928 struct dc_context *ctx = link->ctx; 929 930 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 931 != CONNECTOR_ID_EDP) { 932 BREAK_TO_DEBUGGER(); 933 return; 934 } 935 936 if (!link->panel_cntl) 937 return; 938 939 if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 940 dp_trace_get_edp_poweroff_timestamp(link) != 0) { 941 unsigned int t12_duration = 500; // Default T12 as per spec 942 unsigned long long current_ts = dm_get_timestamp(ctx); 943 unsigned long long time_since_edp_poweroff_ms = 944 div64_u64(dm_get_elapse_time_in_ns( 945 ctx, 946 current_ts, 947 dp_trace_get_edp_poweroff_timestamp(link)), 1000000); 948 949 t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12 950 951 if (time_since_edp_poweroff_ms < t12_duration) 952 msleep(t12_duration - time_since_edp_poweroff_ms); 953 } 954 } 955 956 /*todo: cloned in stream enc, fix*/ 957 /* 958 * @brief 959 * eDP only. Control the backlight of the eDP panel 960 */ 961 void dce110_edp_backlight_control( 962 struct dc_link *link, 963 bool enable) 964 { 965 struct dc_context *ctx = link->ctx; 966 struct bp_transmitter_control cntl = { 0 }; 967 uint8_t panel_instance; 968 969 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 970 != CONNECTOR_ID_EDP) { 971 BREAK_TO_DEBUGGER(); 972 return; 973 } 974 975 if (link->panel_cntl) { 976 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 977 978 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 979 DC_LOG_HW_RESUME_S3( 980 "%s: panel already powered up/off. Do nothing.\n", 981 __func__); 982 return; 983 } 984 } 985 986 /* Send VBIOS command to control eDP panel backlight */ 987 988 DC_LOG_HW_RESUME_S3( 989 "%s: backlight action: %s\n", 990 __func__, (enable ? "On":"Off")); 991 992 cntl.action = enable ? 993 TRANSMITTER_CONTROL_BACKLIGHT_ON : 994 TRANSMITTER_CONTROL_BACKLIGHT_OFF; 995 996 /*cntl.engine_id = ctx->engine;*/ 997 cntl.transmitter = link->link_enc->transmitter; 998 cntl.connector_obj_id = link->link_enc->connector; 999 /*todo: unhardcode*/ 1000 cntl.lanes_number = LANE_COUNT_FOUR; 1001 cntl.hpd_sel = link->link_enc->hpd_source; 1002 cntl.signal = SIGNAL_TYPE_EDP; 1003 1004 /* For eDP, the following delays might need to be considered 1005 * after link training completed: 1006 * idle period - min. accounts for required BS-Idle pattern, 1007 * max. allows for source frame synchronization); 1008 * 50 msec max. delay from valid video data from source 1009 * to video on dislpay or backlight enable. 1010 * 1011 * Disable the delay for now. 1012 * Enable it in the future if necessary. 1013 */ 1014 /* dc_service_sleep_in_milliseconds(50); */ 1015 /*edp 1.2*/ 1016 panel_instance = link->panel_cntl->inst; 1017 1018 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { 1019 if (!link->dc->config.edp_no_power_sequencing) 1020 /* 1021 * Sometimes, DP receiver chip power-controlled externally by an 1022 * Embedded Controller could be treated and used as eDP, 1023 * if it drives mobile display. In this case, 1024 * we shouldn't be doing power-sequencing, hence we can skip 1025 * waiting for T7-ready. 1026 */ 1027 edp_receiver_ready_T7(link); 1028 else 1029 DC_LOG_DC("edp_receiver_ready_T7 skipped\n"); 1030 } 1031 1032 if (ctx->dc->ctx->dmub_srv && 1033 ctx->dc->debug.dmub_command_table) { 1034 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 1035 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1036 LVTMA_CONTROL_LCD_BLON, 1037 panel_instance); 1038 else 1039 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1040 LVTMA_CONTROL_LCD_BLOFF, 1041 panel_instance); 1042 } 1043 1044 link_transmitter_control(ctx->dc_bios, &cntl); 1045 1046 if (enable && link->dpcd_sink_ext_caps.bits.oled) 1047 msleep(OLED_POST_T7_DELAY); 1048 1049 if (link->dpcd_sink_ext_caps.bits.oled || 1050 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 1051 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 1052 dc_link_backlight_enable_aux(link, enable); 1053 1054 /*edp 1.2*/ 1055 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) { 1056 if (!link->dc->config.edp_no_power_sequencing) 1057 /* 1058 * Sometimes, DP receiver chip power-controlled externally by an 1059 * Embedded Controller could be treated and used as eDP, 1060 * if it drives mobile display. In this case, 1061 * we shouldn't be doing power-sequencing, hence we can skip 1062 * waiting for T9-ready. 1063 */ 1064 edp_add_delay_for_T9(link); 1065 else 1066 DC_LOG_DC("edp_receiver_ready_T9 skipped\n"); 1067 } 1068 1069 if (!enable && link->dpcd_sink_ext_caps.bits.oled) 1070 msleep(OLED_PRE_T11_DELAY); 1071 } 1072 1073 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 1074 { 1075 /* notify audio driver for audio modes of monitor */ 1076 struct dc *dc; 1077 struct clk_mgr *clk_mgr; 1078 unsigned int i, num_audio = 1; 1079 1080 if (!pipe_ctx->stream) 1081 return; 1082 1083 dc = pipe_ctx->stream->ctx->dc; 1084 clk_mgr = dc->clk_mgr; 1085 1086 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 1087 return; 1088 1089 if (pipe_ctx->stream_res.audio) { 1090 for (i = 0; i < MAX_PIPES; i++) { 1091 /*current_state not updated yet*/ 1092 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 1093 num_audio++; 1094 } 1095 1096 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 1097 1098 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 1099 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1100 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1101 /* un-mute audio */ 1102 /* TODO: audio should be per stream rather than per link */ 1103 if (is_dp_128b_132b_signal(pipe_ctx)) 1104 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( 1105 pipe_ctx->stream_res.hpo_dp_stream_enc, false); 1106 else 1107 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 1108 pipe_ctx->stream_res.stream_enc, false); 1109 if (pipe_ctx->stream_res.audio) 1110 pipe_ctx->stream_res.audio->enabled = true; 1111 } 1112 1113 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1114 dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM); 1115 } 1116 1117 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 1118 { 1119 struct dc *dc; 1120 struct clk_mgr *clk_mgr; 1121 1122 if (!pipe_ctx || !pipe_ctx->stream) 1123 return; 1124 1125 dc = pipe_ctx->stream->ctx->dc; 1126 clk_mgr = dc->clk_mgr; 1127 1128 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 1129 return; 1130 1131 if (is_dp_128b_132b_signal(pipe_ctx)) 1132 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( 1133 pipe_ctx->stream_res.hpo_dp_stream_enc, true); 1134 else 1135 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 1136 pipe_ctx->stream_res.stream_enc, true); 1137 if (pipe_ctx->stream_res.audio) { 1138 pipe_ctx->stream_res.audio->enabled = false; 1139 1140 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1141 if (is_dp_128b_132b_signal(pipe_ctx)) 1142 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable( 1143 pipe_ctx->stream_res.hpo_dp_stream_enc); 1144 else 1145 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 1146 pipe_ctx->stream_res.stream_enc); 1147 else 1148 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 1149 pipe_ctx->stream_res.stream_enc); 1150 1151 if (clk_mgr->funcs->enable_pme_wa) 1152 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1153 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1154 1155 /* TODO: notify audio driver for if audio modes list changed 1156 * add audio mode list change flag */ 1157 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 1158 * stream->stream_engine_id); 1159 */ 1160 } 1161 1162 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1163 dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM); 1164 } 1165 1166 void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 1167 { 1168 struct dc_stream_state *stream = pipe_ctx->stream; 1169 struct dc_link *link = stream->link; 1170 struct dc *dc = pipe_ctx->stream->ctx->dc; 1171 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1172 1173 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 1174 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 1175 pipe_ctx->stream_res.stream_enc); 1176 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1177 pipe_ctx->stream_res.stream_enc); 1178 } 1179 1180 if (is_dp_128b_132b_signal(pipe_ctx)) { 1181 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets( 1182 pipe_ctx->stream_res.hpo_dp_stream_enc); 1183 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1184 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 1185 pipe_ctx->stream_res.stream_enc); 1186 1187 dc->hwss.disable_audio_stream(pipe_ctx); 1188 1189 link_hwss->reset_stream_encoder(pipe_ctx); 1190 1191 if (is_dp_128b_132b_signal(pipe_ctx)) { 1192 /* TODO: This looks like a bug to me as we are disabling HPO IO when 1193 * we are just disabling a single HPO stream. Shouldn't we disable HPO 1194 * HW control only when HPOs for all streams are disabled? 1195 */ 1196 if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control) 1197 pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control( 1198 pipe_ctx->stream->ctx->dc->hwseq, false); 1199 } 1200 } 1201 1202 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 1203 struct dc_link_settings *link_settings) 1204 { 1205 struct encoder_unblank_param params = { { 0 } }; 1206 struct dc_stream_state *stream = pipe_ctx->stream; 1207 struct dc_link *link = stream->link; 1208 struct dce_hwseq *hws = link->dc->hwseq; 1209 1210 /* only 3 items below are used by unblank */ 1211 params.timing = pipe_ctx->stream->timing; 1212 params.link_settings.link_rate = link_settings->link_rate; 1213 1214 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1215 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1216 1217 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1218 hws->funcs.edp_backlight_control(link, true); 1219 } 1220 } 1221 1222 void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 1223 { 1224 struct dc_stream_state *stream = pipe_ctx->stream; 1225 struct dc_link *link = stream->link; 1226 struct dce_hwseq *hws = link->dc->hwseq; 1227 1228 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1229 hws->funcs.edp_backlight_control(link, false); 1230 link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1231 } 1232 1233 if (is_dp_128b_132b_signal(pipe_ctx)) { 1234 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1235 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank( 1236 pipe_ctx->stream_res.hpo_dp_stream_enc); 1237 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1238 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc); 1239 1240 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1241 /* 1242 * After output is idle pattern some sinks need time to recognize the stream 1243 * has changed or they enter protection state and hang. 1244 */ 1245 msleep(60); 1246 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 1247 if (!link->dc->config.edp_no_power_sequencing) { 1248 /* 1249 * Sometimes, DP receiver chip power-controlled externally by an 1250 * Embedded Controller could be treated and used as eDP, 1251 * if it drives mobile display. In this case, 1252 * we shouldn't be doing power-sequencing, hence we can skip 1253 * waiting for T9-ready. 1254 */ 1255 edp_receiver_ready_T9(link); 1256 } 1257 } 1258 } 1259 1260 } 1261 1262 1263 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 1264 { 1265 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 1266 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 1267 } 1268 1269 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 1270 { 1271 switch (crtc_id) { 1272 case CONTROLLER_ID_D0: 1273 return DTO_SOURCE_ID0; 1274 case CONTROLLER_ID_D1: 1275 return DTO_SOURCE_ID1; 1276 case CONTROLLER_ID_D2: 1277 return DTO_SOURCE_ID2; 1278 case CONTROLLER_ID_D3: 1279 return DTO_SOURCE_ID3; 1280 case CONTROLLER_ID_D4: 1281 return DTO_SOURCE_ID4; 1282 case CONTROLLER_ID_D5: 1283 return DTO_SOURCE_ID5; 1284 default: 1285 return DTO_SOURCE_UNKNOWN; 1286 } 1287 } 1288 1289 static void build_audio_output( 1290 struct dc_state *state, 1291 const struct pipe_ctx *pipe_ctx, 1292 struct audio_output *audio_output) 1293 { 1294 const struct dc_stream_state *stream = pipe_ctx->stream; 1295 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 1296 1297 audio_output->signal = pipe_ctx->stream->signal; 1298 1299 /* audio_crtc_info */ 1300 1301 audio_output->crtc_info.h_total = 1302 stream->timing.h_total; 1303 1304 /* 1305 * Audio packets are sent during actual CRTC blank physical signal, we 1306 * need to specify actual active signal portion 1307 */ 1308 audio_output->crtc_info.h_active = 1309 stream->timing.h_addressable 1310 + stream->timing.h_border_left 1311 + stream->timing.h_border_right; 1312 1313 audio_output->crtc_info.v_active = 1314 stream->timing.v_addressable 1315 + stream->timing.v_border_top 1316 + stream->timing.v_border_bottom; 1317 1318 audio_output->crtc_info.pixel_repetition = 1; 1319 1320 audio_output->crtc_info.interlaced = 1321 stream->timing.flags.INTERLACE; 1322 1323 audio_output->crtc_info.refresh_rate = 1324 (stream->timing.pix_clk_100hz*100)/ 1325 (stream->timing.h_total*stream->timing.v_total); 1326 1327 audio_output->crtc_info.color_depth = 1328 stream->timing.display_color_depth; 1329 1330 audio_output->crtc_info.requested_pixel_clock_100Hz = 1331 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1332 1333 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1334 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1335 1336 /*for HDMI, audio ACR is with deep color ratio factor*/ 1337 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 1338 audio_output->crtc_info.requested_pixel_clock_100Hz == 1339 (stream->timing.pix_clk_100hz)) { 1340 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1341 audio_output->crtc_info.requested_pixel_clock_100Hz = 1342 audio_output->crtc_info.requested_pixel_clock_100Hz/2; 1343 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1344 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 1345 1346 } 1347 } 1348 1349 if (state->clk_mgr && 1350 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1351 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 1352 audio_output->pll_info.dp_dto_source_clock_in_khz = 1353 state->clk_mgr->funcs->get_dp_ref_clk_frequency( 1354 state->clk_mgr); 1355 } 1356 1357 audio_output->pll_info.feed_back_divider = 1358 pipe_ctx->pll_settings.feedback_divider; 1359 1360 audio_output->pll_info.dto_source = 1361 translate_to_dto_source( 1362 pipe_ctx->stream_res.tg->inst + 1); 1363 1364 /* TODO hard code to enable for now. Need get from stream */ 1365 audio_output->pll_info.ss_enabled = true; 1366 1367 audio_output->pll_info.ss_percentage = 1368 pipe_ctx->pll_settings.ss_percentage; 1369 } 1370 1371 static void program_scaler(const struct dc *dc, 1372 const struct pipe_ctx *pipe_ctx) 1373 { 1374 struct tg_color color = {0}; 1375 1376 /* TOFPGA */ 1377 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1378 return; 1379 1380 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 1381 get_surface_visual_confirm_color(pipe_ctx, &color); 1382 else 1383 color_space_to_black_color(dc, 1384 pipe_ctx->stream->output_color_space, 1385 &color); 1386 1387 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 1388 pipe_ctx->plane_res.xfm, 1389 pipe_ctx->plane_res.scl_data.lb_params.depth, 1390 &pipe_ctx->stream->bit_depth_params); 1391 1392 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 1393 /* 1394 * The way 420 is packed, 2 channels carry Y component, 1 channel 1395 * alternate between Cb and Cr, so both channels need the pixel 1396 * value for Y 1397 */ 1398 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1399 color.color_r_cr = color.color_g_y; 1400 1401 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 1402 pipe_ctx->stream_res.tg, 1403 &color); 1404 } 1405 1406 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 1407 &pipe_ctx->plane_res.scl_data); 1408 } 1409 1410 static enum dc_status dce110_enable_stream_timing( 1411 struct pipe_ctx *pipe_ctx, 1412 struct dc_state *context, 1413 struct dc *dc) 1414 { 1415 struct dc_stream_state *stream = pipe_ctx->stream; 1416 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 1417 pipe_ctx[pipe_ctx->pipe_idx]; 1418 struct tg_color black_color = {0}; 1419 1420 if (!pipe_ctx_old->stream) { 1421 1422 /* program blank color */ 1423 color_space_to_black_color(dc, 1424 stream->output_color_space, &black_color); 1425 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1426 pipe_ctx->stream_res.tg, 1427 &black_color); 1428 1429 /* 1430 * Must blank CRTC after disabling power gating and before any 1431 * programming, otherwise CRTC will be hung in bad state 1432 */ 1433 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 1434 1435 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 1436 pipe_ctx->clock_source, 1437 &pipe_ctx->stream_res.pix_clk_params, 1438 dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings), 1439 &pipe_ctx->pll_settings)) { 1440 BREAK_TO_DEBUGGER(); 1441 return DC_ERROR_UNEXPECTED; 1442 } 1443 1444 pipe_ctx->stream_res.tg->funcs->program_timing( 1445 pipe_ctx->stream_res.tg, 1446 &stream->timing, 1447 0, 1448 0, 1449 0, 1450 0, 1451 pipe_ctx->stream->signal, 1452 true); 1453 } 1454 1455 if (!pipe_ctx_old->stream) { 1456 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 1457 pipe_ctx->stream_res.tg)) { 1458 BREAK_TO_DEBUGGER(); 1459 return DC_ERROR_UNEXPECTED; 1460 } 1461 } 1462 1463 return DC_OK; 1464 } 1465 1466 static enum dc_status apply_single_controller_ctx_to_hw( 1467 struct pipe_ctx *pipe_ctx, 1468 struct dc_state *context, 1469 struct dc *dc) 1470 { 1471 struct dc_stream_state *stream = pipe_ctx->stream; 1472 struct dc_link *link = stream->link; 1473 struct drr_params params = {0}; 1474 unsigned int event_triggers = 0; 1475 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1476 struct dce_hwseq *hws = dc->hwseq; 1477 1478 if (hws->funcs.disable_stream_gating) { 1479 hws->funcs.disable_stream_gating(dc, pipe_ctx); 1480 } 1481 1482 if (pipe_ctx->stream_res.audio != NULL) { 1483 struct audio_output audio_output; 1484 1485 build_audio_output(context, pipe_ctx, &audio_output); 1486 1487 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1488 if (is_dp_128b_132b_signal(pipe_ctx)) 1489 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( 1490 pipe_ctx->stream_res.hpo_dp_stream_enc, 1491 pipe_ctx->stream_res.audio->inst, 1492 &pipe_ctx->stream->audio_info); 1493 else 1494 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 1495 pipe_ctx->stream_res.stream_enc, 1496 pipe_ctx->stream_res.audio->inst, 1497 &pipe_ctx->stream->audio_info); 1498 else 1499 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 1500 pipe_ctx->stream_res.stream_enc, 1501 pipe_ctx->stream_res.audio->inst, 1502 &pipe_ctx->stream->audio_info, 1503 &audio_output.crtc_info); 1504 1505 pipe_ctx->stream_res.audio->funcs->az_configure( 1506 pipe_ctx->stream_res.audio, 1507 pipe_ctx->stream->signal, 1508 &audio_output.crtc_info, 1509 &pipe_ctx->stream->audio_info); 1510 } 1511 1512 /* make sure no pipes syncd to the pipe being enabled */ 1513 if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic) 1514 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); 1515 1516 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1517 pipe_ctx->stream_res.opp, 1518 &stream->bit_depth_params, 1519 &stream->clamping); 1520 1521 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1522 pipe_ctx->stream_res.opp, 1523 COLOR_SPACE_YCBCR601, 1524 stream->timing.display_color_depth, 1525 stream->signal); 1526 1527 while (odm_pipe) { 1528 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 1529 odm_pipe->stream_res.opp, 1530 COLOR_SPACE_YCBCR601, 1531 stream->timing.display_color_depth, 1532 stream->signal); 1533 1534 odm_pipe->stream_res.opp->funcs->opp_program_fmt( 1535 odm_pipe->stream_res.opp, 1536 &stream->bit_depth_params, 1537 &stream->clamping); 1538 odm_pipe = odm_pipe->next_odm_pipe; 1539 } 1540 1541 /* DCN3.1 FPGA Workaround 1542 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1543 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1544 * function core_link_enable_stream 1545 */ 1546 if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx))) 1547 /* */ 1548 /* Do not touch stream timing on seamless boot optimization. */ 1549 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1550 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1551 1552 if (hws->funcs.setup_vupdate_interrupt) 1553 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1554 1555 params.vertical_total_min = stream->adjust.v_total_min; 1556 params.vertical_total_max = stream->adjust.v_total_max; 1557 if (pipe_ctx->stream_res.tg->funcs->set_drr) 1558 pipe_ctx->stream_res.tg->funcs->set_drr( 1559 pipe_ctx->stream_res.tg, ¶ms); 1560 1561 // DRR should set trigger event to monitor surface update event 1562 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 1563 event_triggers = 0x80; 1564 /* Event triggers and num frames initialized for DRR, but can be 1565 * later updated for PSR use. Note DRR trigger events are generated 1566 * regardless of whether num frames met. 1567 */ 1568 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 1569 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 1570 pipe_ctx->stream_res.tg, event_triggers, 2); 1571 1572 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1573 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1574 pipe_ctx->stream_res.stream_enc, 1575 pipe_ctx->stream_res.tg->inst); 1576 1577 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1578 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG); 1579 1580 if (!stream->dpms_off) 1581 core_link_enable_stream(context, pipe_ctx); 1582 1583 /* DCN3.1 FPGA Workaround 1584 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1585 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1586 * function core_link_enable_stream 1587 */ 1588 if (hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)) { 1589 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1590 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1591 } 1592 1593 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; 1594 1595 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 1596 1597 return DC_OK; 1598 } 1599 1600 /******************************************************************************/ 1601 1602 static void power_down_encoders(struct dc *dc) 1603 { 1604 int i; 1605 1606 for (i = 0; i < dc->link_count; i++) { 1607 enum signal_type signal = dc->links[i]->connector_signal; 1608 1609 dc_link_blank_dp_stream(dc->links[i], false); 1610 1611 if (signal != SIGNAL_TYPE_EDP) 1612 signal = SIGNAL_TYPE_NONE; 1613 1614 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY) 1615 dc->links[i]->link_enc->funcs->disable_output( 1616 dc->links[i]->link_enc, signal); 1617 1618 dc->links[i]->link_status.link_active = false; 1619 memset(&dc->links[i]->cur_link_settings, 0, 1620 sizeof(dc->links[i]->cur_link_settings)); 1621 } 1622 } 1623 1624 static void power_down_controllers(struct dc *dc) 1625 { 1626 int i; 1627 1628 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1629 dc->res_pool->timing_generators[i]->funcs->disable_crtc( 1630 dc->res_pool->timing_generators[i]); 1631 } 1632 } 1633 1634 static void power_down_clock_sources(struct dc *dc) 1635 { 1636 int i; 1637 1638 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 1639 dc->res_pool->dp_clock_source) == false) 1640 dm_error("Failed to power down pll! (dp clk src)\n"); 1641 1642 for (i = 0; i < dc->res_pool->clk_src_count; i++) { 1643 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 1644 dc->res_pool->clock_sources[i]) == false) 1645 dm_error("Failed to power down pll! (clk src index=%d)\n", i); 1646 } 1647 } 1648 1649 static void power_down_all_hw_blocks(struct dc *dc) 1650 { 1651 power_down_encoders(dc); 1652 1653 power_down_controllers(dc); 1654 1655 power_down_clock_sources(dc); 1656 1657 if (dc->fbc_compressor) 1658 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 1659 } 1660 1661 static void disable_vga_and_power_gate_all_controllers( 1662 struct dc *dc) 1663 { 1664 int i; 1665 struct timing_generator *tg; 1666 struct dc_context *ctx = dc->ctx; 1667 1668 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1669 tg = dc->res_pool->timing_generators[i]; 1670 1671 if (tg->funcs->disable_vga) 1672 tg->funcs->disable_vga(tg); 1673 } 1674 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1675 /* Enable CLOCK gating for each pipe BEFORE controller 1676 * powergating. */ 1677 enable_display_pipe_clock_gating(ctx, 1678 true); 1679 1680 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 1681 dc->hwss.disable_plane(dc, 1682 &dc->current_state->res_ctx.pipe_ctx[i]); 1683 } 1684 } 1685 1686 1687 static void get_edp_streams(struct dc_state *context, 1688 struct dc_stream_state **edp_streams, 1689 int *edp_stream_num) 1690 { 1691 int i; 1692 1693 *edp_stream_num = 0; 1694 for (i = 0; i < context->stream_count; i++) { 1695 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 1696 edp_streams[*edp_stream_num] = context->streams[i]; 1697 if (++(*edp_stream_num) == MAX_NUM_EDP) 1698 return; 1699 } 1700 } 1701 } 1702 1703 static void get_edp_links_with_sink( 1704 struct dc *dc, 1705 struct dc_link **edp_links_with_sink, 1706 int *edp_with_sink_num) 1707 { 1708 int i; 1709 1710 /* check if there is an eDP panel not in use */ 1711 *edp_with_sink_num = 0; 1712 for (i = 0; i < dc->link_count; i++) { 1713 if (dc->links[i]->local_sink && 1714 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1715 edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; 1716 if (++(*edp_with_sink_num) == MAX_NUM_EDP) 1717 return; 1718 } 1719 } 1720 } 1721 1722 /* 1723 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 1724 * 1. Power down all DC HW blocks 1725 * 2. Disable VGA engine on all controllers 1726 * 3. Enable power gating for controller 1727 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 1728 */ 1729 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 1730 { 1731 struct dc_link *edp_links_with_sink[MAX_NUM_EDP]; 1732 struct dc_link *edp_links[MAX_NUM_EDP]; 1733 struct dc_stream_state *edp_streams[MAX_NUM_EDP]; 1734 struct dc_link *edp_link_with_sink = NULL; 1735 struct dc_link *edp_link = NULL; 1736 struct dce_hwseq *hws = dc->hwseq; 1737 int edp_with_sink_num; 1738 int edp_num; 1739 int edp_stream_num; 1740 int i; 1741 bool can_apply_edp_fast_boot = false; 1742 bool can_apply_seamless_boot = false; 1743 bool keep_edp_vdd_on = false; 1744 DC_LOGGER_INIT(); 1745 1746 1747 get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); 1748 get_edp_links(dc, edp_links, &edp_num); 1749 1750 if (hws->funcs.init_pipes) 1751 hws->funcs.init_pipes(dc, context); 1752 1753 get_edp_streams(context, edp_streams, &edp_stream_num); 1754 1755 // Check fastboot support, disable on DCE8 because of blank screens 1756 if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 && 1757 dc->ctx->dce_version != DCE_VERSION_8_1 && 1758 dc->ctx->dce_version != DCE_VERSION_8_3) { 1759 for (i = 0; i < edp_num; i++) { 1760 edp_link = edp_links[i]; 1761 if (edp_link != edp_streams[0]->link) 1762 continue; 1763 // enable fastboot if backend is enabled on eDP 1764 if (edp_link->link_enc->funcs->is_dig_enabled && 1765 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 1766 edp_link->link_status.link_active) { 1767 struct dc_stream_state *edp_stream = edp_streams[0]; 1768 1769 can_apply_edp_fast_boot = dc_validate_boot_timing(dc, 1770 edp_stream->sink, &edp_stream->timing); 1771 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot; 1772 if (can_apply_edp_fast_boot) 1773 DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n"); 1774 1775 break; 1776 } 1777 } 1778 // We are trying to enable eDP, don't power down VDD 1779 if (can_apply_edp_fast_boot) 1780 keep_edp_vdd_on = true; 1781 } 1782 1783 // Check seamless boot support 1784 for (i = 0; i < context->stream_count; i++) { 1785 if (context->streams[i]->apply_seamless_boot_optimization) { 1786 can_apply_seamless_boot = true; 1787 break; 1788 } 1789 } 1790 1791 /* eDP should not have stream in resume from S4 and so even with VBios post 1792 * it should get turned off 1793 */ 1794 if (edp_with_sink_num) 1795 edp_link_with_sink = edp_links_with_sink[0]; 1796 1797 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 1798 if (edp_link_with_sink && !keep_edp_vdd_on) { 1799 /*turn off backlight before DP_blank and encoder powered down*/ 1800 hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1801 } 1802 /*resume from S3, no vbios posting, no need to power down again*/ 1803 power_down_all_hw_blocks(dc); 1804 disable_vga_and_power_gate_all_controllers(dc); 1805 if (edp_link_with_sink && !keep_edp_vdd_on) 1806 dc->hwss.edp_power_control(edp_link_with_sink, false); 1807 } 1808 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); 1809 } 1810 1811 static uint32_t compute_pstate_blackout_duration( 1812 struct bw_fixed blackout_duration, 1813 const struct dc_stream_state *stream) 1814 { 1815 uint32_t total_dest_line_time_ns; 1816 uint32_t pstate_blackout_duration_ns; 1817 1818 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 1819 1820 total_dest_line_time_ns = 1000000UL * 1821 (stream->timing.h_total * 10) / 1822 stream->timing.pix_clk_100hz + 1823 pstate_blackout_duration_ns; 1824 1825 return total_dest_line_time_ns; 1826 } 1827 1828 static void dce110_set_displaymarks( 1829 const struct dc *dc, 1830 struct dc_state *context) 1831 { 1832 uint8_t i, num_pipes; 1833 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1834 1835 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 1836 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1837 uint32_t total_dest_line_time_ns; 1838 1839 if (pipe_ctx->stream == NULL) 1840 continue; 1841 1842 total_dest_line_time_ns = compute_pstate_blackout_duration( 1843 dc->bw_vbios->blackout_duration, pipe_ctx->stream); 1844 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 1845 pipe_ctx->plane_res.mi, 1846 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1847 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1848 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1849 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1850 total_dest_line_time_ns); 1851 if (i == underlay_idx) { 1852 num_pipes++; 1853 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1854 pipe_ctx->plane_res.mi, 1855 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1856 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1857 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1858 total_dest_line_time_ns); 1859 } 1860 num_pipes++; 1861 } 1862 } 1863 1864 void dce110_set_safe_displaymarks( 1865 struct resource_context *res_ctx, 1866 const struct resource_pool *pool) 1867 { 1868 int i; 1869 int underlay_idx = pool->underlay_pipe_index; 1870 struct dce_watermarks max_marks = { 1871 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 1872 struct dce_watermarks nbp_marks = { 1873 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 1874 struct dce_watermarks min_marks = { 0, 0, 0, 0}; 1875 1876 for (i = 0; i < MAX_PIPES; i++) { 1877 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 1878 continue; 1879 1880 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 1881 res_ctx->pipe_ctx[i].plane_res.mi, 1882 nbp_marks, 1883 max_marks, 1884 min_marks, 1885 max_marks, 1886 MAX_WATERMARK); 1887 1888 if (i == underlay_idx) 1889 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1890 res_ctx->pipe_ctx[i].plane_res.mi, 1891 nbp_marks, 1892 max_marks, 1893 max_marks, 1894 MAX_WATERMARK); 1895 1896 } 1897 } 1898 1899 /******************************************************************************* 1900 * Public functions 1901 ******************************************************************************/ 1902 1903 static void set_drr(struct pipe_ctx **pipe_ctx, 1904 int num_pipes, struct dc_crtc_timing_adjust adjust) 1905 { 1906 int i = 0; 1907 struct drr_params params = {0}; 1908 // DRR should set trigger event to monitor surface update event 1909 unsigned int event_triggers = 0x80; 1910 // Note DRR trigger events are generated regardless of whether num frames met. 1911 unsigned int num_frames = 2; 1912 1913 params.vertical_total_max = adjust.v_total_max; 1914 params.vertical_total_min = adjust.v_total_min; 1915 1916 /* TODO: If multiple pipes are to be supported, you need 1917 * some GSL stuff. Static screen triggers may be programmed differently 1918 * as well. 1919 */ 1920 for (i = 0; i < num_pipes; i++) { 1921 pipe_ctx[i]->stream_res.tg->funcs->set_drr( 1922 pipe_ctx[i]->stream_res.tg, ¶ms); 1923 1924 if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 1925 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 1926 pipe_ctx[i]->stream_res.tg, 1927 event_triggers, num_frames); 1928 } 1929 } 1930 1931 static void get_position(struct pipe_ctx **pipe_ctx, 1932 int num_pipes, 1933 struct crtc_position *position) 1934 { 1935 int i = 0; 1936 1937 /* TODO: handle pipes > 1 1938 */ 1939 for (i = 0; i < num_pipes; i++) 1940 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 1941 } 1942 1943 static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 1944 int num_pipes, const struct dc_static_screen_params *params) 1945 { 1946 unsigned int i; 1947 unsigned int triggers = 0; 1948 1949 if (params->triggers.overlay_update) 1950 triggers |= 0x100; 1951 if (params->triggers.surface_update) 1952 triggers |= 0x80; 1953 if (params->triggers.cursor_update) 1954 triggers |= 0x2; 1955 if (params->triggers.force_trigger) 1956 triggers |= 0x1; 1957 1958 if (num_pipes) { 1959 struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1960 1961 if (dc->fbc_compressor) 1962 triggers |= 0x84; 1963 } 1964 1965 for (i = 0; i < num_pipes; i++) 1966 pipe_ctx[i]->stream_res.tg->funcs-> 1967 set_static_screen_control(pipe_ctx[i]->stream_res.tg, 1968 triggers, params->num_frames); 1969 } 1970 1971 /* 1972 * Check if FBC can be enabled 1973 */ 1974 static bool should_enable_fbc(struct dc *dc, 1975 struct dc_state *context, 1976 uint32_t *pipe_idx) 1977 { 1978 uint32_t i; 1979 struct pipe_ctx *pipe_ctx = NULL; 1980 struct resource_context *res_ctx = &context->res_ctx; 1981 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1982 1983 1984 ASSERT(dc->fbc_compressor); 1985 1986 /* FBC memory should be allocated */ 1987 if (!dc->ctx->fbc_gpu_addr) 1988 return false; 1989 1990 /* Only supports single display */ 1991 if (context->stream_count != 1) 1992 return false; 1993 1994 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1995 if (res_ctx->pipe_ctx[i].stream) { 1996 1997 pipe_ctx = &res_ctx->pipe_ctx[i]; 1998 1999 if (!pipe_ctx) 2000 continue; 2001 2002 /* fbc not applicable on underlay pipe */ 2003 if (pipe_ctx->pipe_idx != underlay_idx) { 2004 *pipe_idx = i; 2005 break; 2006 } 2007 } 2008 } 2009 2010 if (i == dc->res_pool->pipe_count) 2011 return false; 2012 2013 if (!pipe_ctx->stream->link) 2014 return false; 2015 2016 /* Only supports eDP */ 2017 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 2018 return false; 2019 2020 /* PSR should not be enabled */ 2021 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 2022 return false; 2023 2024 /* Nothing to compress */ 2025 if (!pipe_ctx->plane_state) 2026 return false; 2027 2028 /* Only for non-linear tiling */ 2029 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 2030 return false; 2031 2032 return true; 2033 } 2034 2035 /* 2036 * Enable FBC 2037 */ 2038 static void enable_fbc( 2039 struct dc *dc, 2040 struct dc_state *context) 2041 { 2042 uint32_t pipe_idx = 0; 2043 2044 if (should_enable_fbc(dc, context, &pipe_idx)) { 2045 /* Program GRPH COMPRESSED ADDRESS and PITCH */ 2046 struct compr_addr_and_pitch_params params = {0, 0, 0}; 2047 struct compressor *compr = dc->fbc_compressor; 2048 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2049 2050 params.source_view_width = pipe_ctx->stream->timing.h_addressable; 2051 params.source_view_height = pipe_ctx->stream->timing.v_addressable; 2052 params.inst = pipe_ctx->stream_res.tg->inst; 2053 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 2054 2055 compr->funcs->surface_address_and_pitch(compr, ¶ms); 2056 compr->funcs->set_fbc_invalidation_triggers(compr, 1); 2057 2058 compr->funcs->enable_fbc(compr, ¶ms); 2059 } 2060 } 2061 2062 static void dce110_reset_hw_ctx_wrap( 2063 struct dc *dc, 2064 struct dc_state *context) 2065 { 2066 int i; 2067 2068 /* Reset old context */ 2069 /* look up the targets that have been removed since last commit */ 2070 for (i = 0; i < MAX_PIPES; i++) { 2071 struct pipe_ctx *pipe_ctx_old = 2072 &dc->current_state->res_ctx.pipe_ctx[i]; 2073 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2074 2075 /* Note: We need to disable output if clock sources change, 2076 * since bios does optimization and doesn't apply if changing 2077 * PHY when not already disabled. 2078 */ 2079 2080 /* Skip underlay pipe since it will be handled in commit surface*/ 2081 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 2082 continue; 2083 2084 if (!pipe_ctx->stream || 2085 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2086 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2087 2088 /* Disable if new stream is null. O/w, if stream is 2089 * disabled already, no need to disable again. 2090 */ 2091 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 2092 core_link_disable_stream(pipe_ctx_old); 2093 2094 /* free acquired resources*/ 2095 if (pipe_ctx_old->stream_res.audio) { 2096 /*disable az_endpoint*/ 2097 pipe_ctx_old->stream_res.audio->funcs-> 2098 az_disable(pipe_ctx_old->stream_res.audio); 2099 2100 /*free audio*/ 2101 if (dc->caps.dynamic_audio == true) { 2102 /*we have to dynamic arbitrate the audio endpoints*/ 2103 /*we free the resource, need reset is_audio_acquired*/ 2104 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2105 pipe_ctx_old->stream_res.audio, false); 2106 pipe_ctx_old->stream_res.audio = NULL; 2107 } 2108 } 2109 } 2110 2111 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 2112 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 2113 dm_error("DC: failed to blank crtc!\n"); 2114 BREAK_TO_DEBUGGER(); 2115 } 2116 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 2117 pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2118 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 2119 2120 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2121 dc->res_pool, 2122 old_clk)) 2123 old_clk->funcs->cs_power_down(old_clk); 2124 2125 dc->hwss.disable_plane(dc, pipe_ctx_old); 2126 2127 pipe_ctx_old->stream = NULL; 2128 } 2129 } 2130 } 2131 2132 static void dce110_setup_audio_dto( 2133 struct dc *dc, 2134 struct dc_state *context) 2135 { 2136 int i; 2137 2138 /* program audio wall clock. use HDMI as clock source if HDMI 2139 * audio active. Otherwise, use DP as clock source 2140 * first, loop to find any HDMI audio, if not, loop find DP audio 2141 */ 2142 /* Setup audio rate clock source */ 2143 /* Issue: 2144 * Audio lag happened on DP monitor when unplug a HDMI monitor 2145 * 2146 * Cause: 2147 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 2148 * is set to either dto0 or dto1, audio should work fine. 2149 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 2150 * set to dto0 will cause audio lag. 2151 * 2152 * Solution: 2153 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 2154 * find first available pipe with audio, setup audio wall DTO per topology 2155 * instead of per pipe. 2156 */ 2157 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2158 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2159 2160 if (pipe_ctx->stream == NULL) 2161 continue; 2162 2163 if (pipe_ctx->top_pipe) 2164 continue; 2165 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 2166 continue; 2167 if (pipe_ctx->stream_res.audio != NULL) { 2168 struct audio_output audio_output; 2169 2170 build_audio_output(context, pipe_ctx, &audio_output); 2171 2172 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 2173 struct dtbclk_dto_params dto_params = {0}; 2174 2175 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 2176 dc->res_pool->dccg, &dto_params); 2177 2178 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2179 pipe_ctx->stream_res.audio, 2180 pipe_ctx->stream->signal, 2181 &audio_output.crtc_info, 2182 &audio_output.pll_info); 2183 } else 2184 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2185 pipe_ctx->stream_res.audio, 2186 pipe_ctx->stream->signal, 2187 &audio_output.crtc_info, 2188 &audio_output.pll_info); 2189 break; 2190 } 2191 } 2192 2193 /* no HDMI audio is found, try DP audio */ 2194 if (i == dc->res_pool->pipe_count) { 2195 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2196 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2197 2198 if (pipe_ctx->stream == NULL) 2199 continue; 2200 2201 if (pipe_ctx->top_pipe) 2202 continue; 2203 2204 if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 2205 continue; 2206 2207 if (pipe_ctx->stream_res.audio != NULL) { 2208 struct audio_output audio_output; 2209 2210 build_audio_output(context, pipe_ctx, &audio_output); 2211 2212 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2213 pipe_ctx->stream_res.audio, 2214 pipe_ctx->stream->signal, 2215 &audio_output.crtc_info, 2216 &audio_output.pll_info); 2217 break; 2218 } 2219 } 2220 } 2221 } 2222 2223 enum dc_status dce110_apply_ctx_to_hw( 2224 struct dc *dc, 2225 struct dc_state *context) 2226 { 2227 struct dce_hwseq *hws = dc->hwseq; 2228 struct dc_bios *dcb = dc->ctx->dc_bios; 2229 enum dc_status status; 2230 int i; 2231 2232 /* reset syncd pipes from disabled pipes */ 2233 if (dc->config.use_pipe_ctx_sync_logic) 2234 reset_syncd_pipes_from_disabled_pipes(dc, context); 2235 2236 /* Reset old context */ 2237 /* look up the targets that have been removed since last commit */ 2238 hws->funcs.reset_hw_ctx_wrap(dc, context); 2239 2240 /* Skip applying if no targets */ 2241 if (context->stream_count <= 0) 2242 return DC_OK; 2243 2244 /* Apply new context */ 2245 dcb->funcs->set_scratch_critical_state(dcb, true); 2246 2247 /* below is for real asic only */ 2248 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2249 struct pipe_ctx *pipe_ctx_old = 2250 &dc->current_state->res_ctx.pipe_ctx[i]; 2251 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2252 2253 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 2254 continue; 2255 2256 if (pipe_ctx->stream == pipe_ctx_old->stream) { 2257 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 2258 dce_crtc_switch_to_clk_src(dc->hwseq, 2259 pipe_ctx->clock_source, i); 2260 continue; 2261 } 2262 2263 hws->funcs.enable_display_power_gating( 2264 dc, i, dc->ctx->dc_bios, 2265 PIPE_GATING_CONTROL_DISABLE); 2266 } 2267 2268 if (dc->fbc_compressor) 2269 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2270 2271 dce110_setup_audio_dto(dc, context); 2272 2273 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2274 struct pipe_ctx *pipe_ctx_old = 2275 &dc->current_state->res_ctx.pipe_ctx[i]; 2276 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2277 2278 if (pipe_ctx->stream == NULL) 2279 continue; 2280 2281 if (pipe_ctx->stream == pipe_ctx_old->stream && 2282 pipe_ctx->stream->link->link_state_valid) { 2283 continue; 2284 } 2285 2286 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2287 continue; 2288 2289 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2290 continue; 2291 2292 status = apply_single_controller_ctx_to_hw( 2293 pipe_ctx, 2294 context, 2295 dc); 2296 2297 if (DC_OK != status) 2298 return status; 2299 } 2300 2301 if (dc->fbc_compressor) 2302 enable_fbc(dc, dc->current_state); 2303 2304 dcb->funcs->set_scratch_critical_state(dcb, false); 2305 2306 return DC_OK; 2307 } 2308 2309 /******************************************************************************* 2310 * Front End programming 2311 ******************************************************************************/ 2312 static void set_default_colors(struct pipe_ctx *pipe_ctx) 2313 { 2314 struct default_adjustment default_adjust = { 0 }; 2315 2316 default_adjust.force_hw_default = false; 2317 default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 2318 default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 2319 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 2320 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 2321 2322 /* display color depth */ 2323 default_adjust.color_depth = 2324 pipe_ctx->stream->timing.display_color_depth; 2325 2326 /* Lb color depth */ 2327 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 2328 2329 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 2330 pipe_ctx->plane_res.xfm, &default_adjust); 2331 } 2332 2333 2334 /******************************************************************************* 2335 * In order to turn on/off specific surface we will program 2336 * Blender + CRTC 2337 * 2338 * In case that we have two surfaces and they have a different visibility 2339 * we can't turn off the CRTC since it will turn off the entire display 2340 * 2341 * |----------------------------------------------- | 2342 * |bottom pipe|curr pipe | | | 2343 * |Surface |Surface | Blender | CRCT | 2344 * |visibility |visibility | Configuration| | 2345 * |------------------------------------------------| 2346 * | off | off | CURRENT_PIPE | blank | 2347 * | off | on | CURRENT_PIPE | unblank | 2348 * | on | off | OTHER_PIPE | unblank | 2349 * | on | on | BLENDING | unblank | 2350 * -------------------------------------------------| 2351 * 2352 ******************************************************************************/ 2353 static void program_surface_visibility(const struct dc *dc, 2354 struct pipe_ctx *pipe_ctx) 2355 { 2356 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2357 bool blank_target = false; 2358 2359 if (pipe_ctx->bottom_pipe) { 2360 2361 /* For now we are supporting only two pipes */ 2362 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2363 2364 if (pipe_ctx->bottom_pipe->plane_state->visible) { 2365 if (pipe_ctx->plane_state->visible) 2366 blender_mode = BLND_MODE_BLENDING; 2367 else 2368 blender_mode = BLND_MODE_OTHER_PIPE; 2369 2370 } else if (!pipe_ctx->plane_state->visible) 2371 blank_target = true; 2372 2373 } else if (!pipe_ctx->plane_state->visible) 2374 blank_target = true; 2375 2376 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 2377 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2378 2379 } 2380 2381 static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 2382 { 2383 int i = 0; 2384 struct xfm_grph_csc_adjustment adjust; 2385 memset(&adjust, 0, sizeof(adjust)); 2386 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2387 2388 2389 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2390 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2391 2392 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2393 adjust.temperature_matrix[i] = 2394 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2395 } 2396 2397 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2398 } 2399 static void update_plane_addr(const struct dc *dc, 2400 struct pipe_ctx *pipe_ctx) 2401 { 2402 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2403 2404 if (plane_state == NULL) 2405 return; 2406 2407 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 2408 pipe_ctx->plane_res.mi, 2409 &plane_state->address, 2410 plane_state->flip_immediate); 2411 2412 plane_state->status.requested_address = plane_state->address; 2413 } 2414 2415 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 2416 { 2417 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2418 2419 if (plane_state == NULL) 2420 return; 2421 2422 plane_state->status.is_flip_pending = 2423 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 2424 pipe_ctx->plane_res.mi); 2425 2426 if (plane_state->status.is_flip_pending && !plane_state->visible) 2427 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 2428 2429 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 2430 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2431 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 2432 plane_state->status.is_right_eye =\ 2433 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 2434 } 2435 } 2436 2437 void dce110_power_down(struct dc *dc) 2438 { 2439 power_down_all_hw_blocks(dc); 2440 disable_vga_and_power_gate_all_controllers(dc); 2441 } 2442 2443 static bool wait_for_reset_trigger_to_occur( 2444 struct dc_context *dc_ctx, 2445 struct timing_generator *tg) 2446 { 2447 bool rc = false; 2448 2449 /* To avoid endless loop we wait at most 2450 * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 2451 const uint32_t frames_to_wait_on_triggered_reset = 10; 2452 uint32_t i; 2453 2454 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 2455 2456 if (!tg->funcs->is_counter_moving(tg)) { 2457 DC_ERROR("TG counter is not moving!\n"); 2458 break; 2459 } 2460 2461 if (tg->funcs->did_triggered_reset_occur(tg)) { 2462 rc = true; 2463 /* usually occurs at i=1 */ 2464 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 2465 i); 2466 break; 2467 } 2468 2469 /* Wait for one frame. */ 2470 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 2471 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 2472 } 2473 2474 if (false == rc) 2475 DC_ERROR("GSL: Timeout on reset trigger!\n"); 2476 2477 return rc; 2478 } 2479 2480 /* Enable timing synchronization for a group of Timing Generators. */ 2481 static void dce110_enable_timing_synchronization( 2482 struct dc *dc, 2483 int group_index, 2484 int group_size, 2485 struct pipe_ctx *grouped_pipes[]) 2486 { 2487 struct dc_context *dc_ctx = dc->ctx; 2488 struct dcp_gsl_params gsl_params = { 0 }; 2489 int i; 2490 2491 DC_SYNC_INFO("GSL: Setting-up...\n"); 2492 2493 /* Designate a single TG in the group as a master. 2494 * Since HW doesn't care which one, we always assign 2495 * the 1st one in the group. */ 2496 gsl_params.gsl_group = 0; 2497 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 2498 2499 for (i = 0; i < group_size; i++) 2500 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2501 grouped_pipes[i]->stream_res.tg, &gsl_params); 2502 2503 /* Reset slave controllers on master VSync */ 2504 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2505 2506 for (i = 1 /* skip the master */; i < group_size; i++) 2507 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2508 grouped_pipes[i]->stream_res.tg, 2509 gsl_params.gsl_group); 2510 2511 for (i = 1 /* skip the master */; i < group_size; i++) { 2512 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2513 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2514 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2515 grouped_pipes[i]->stream_res.tg); 2516 } 2517 2518 /* GSL Vblank synchronization is a one time sync mechanism, assumption 2519 * is that the sync'ed displays will not drift out of sync over time*/ 2520 DC_SYNC_INFO("GSL: Restoring register states.\n"); 2521 for (i = 0; i < group_size; i++) 2522 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2523 2524 DC_SYNC_INFO("GSL: Set-up complete.\n"); 2525 } 2526 2527 static void dce110_enable_per_frame_crtc_position_reset( 2528 struct dc *dc, 2529 int group_size, 2530 struct pipe_ctx *grouped_pipes[]) 2531 { 2532 struct dc_context *dc_ctx = dc->ctx; 2533 struct dcp_gsl_params gsl_params = { 0 }; 2534 int i; 2535 2536 gsl_params.gsl_group = 0; 2537 gsl_params.gsl_master = 0; 2538 2539 for (i = 0; i < group_size; i++) 2540 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2541 grouped_pipes[i]->stream_res.tg, &gsl_params); 2542 2543 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2544 2545 for (i = 1; i < group_size; i++) 2546 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2547 grouped_pipes[i]->stream_res.tg, 2548 gsl_params.gsl_master, 2549 &grouped_pipes[i]->stream->triggered_crtc_reset); 2550 2551 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2552 for (i = 1; i < group_size; i++) 2553 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2554 2555 for (i = 0; i < group_size; i++) 2556 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2557 2558 } 2559 2560 static void init_pipes(struct dc *dc, struct dc_state *context) 2561 { 2562 // Do nothing 2563 } 2564 2565 static void init_hw(struct dc *dc) 2566 { 2567 int i; 2568 struct dc_bios *bp; 2569 struct transform *xfm; 2570 struct abm *abm; 2571 struct dmcu *dmcu; 2572 struct dce_hwseq *hws = dc->hwseq; 2573 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 2574 2575 bp = dc->ctx->dc_bios; 2576 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2577 xfm = dc->res_pool->transforms[i]; 2578 xfm->funcs->transform_reset(xfm); 2579 2580 hws->funcs.enable_display_power_gating( 2581 dc, i, bp, 2582 PIPE_GATING_CONTROL_INIT); 2583 hws->funcs.enable_display_power_gating( 2584 dc, i, bp, 2585 PIPE_GATING_CONTROL_DISABLE); 2586 hws->funcs.enable_display_pipe_clock_gating( 2587 dc->ctx, 2588 true); 2589 } 2590 2591 dce_clock_gating_power_up(dc->hwseq, false); 2592 /***************************************/ 2593 2594 for (i = 0; i < dc->link_count; i++) { 2595 /****************************************/ 2596 /* Power up AND update implementation according to the 2597 * required signal (which may be different from the 2598 * default signal on connector). */ 2599 struct dc_link *link = dc->links[i]; 2600 2601 link->link_enc->funcs->hw_init(link->link_enc); 2602 } 2603 2604 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2605 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2606 2607 tg->funcs->disable_vga(tg); 2608 2609 /* Blank controller using driver code instead of 2610 * command table. */ 2611 tg->funcs->set_blank(tg, true); 2612 hwss_wait_for_blank_complete(tg); 2613 } 2614 2615 for (i = 0; i < dc->res_pool->audio_count; i++) { 2616 struct audio *audio = dc->res_pool->audios[i]; 2617 audio->funcs->hw_init(audio); 2618 } 2619 2620 for (i = 0; i < dc->link_count; i++) { 2621 struct dc_link *link = dc->links[i]; 2622 2623 if (link->panel_cntl) 2624 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 2625 } 2626 2627 abm = dc->res_pool->abm; 2628 if (abm != NULL) 2629 abm->funcs->abm_init(abm, backlight); 2630 2631 dmcu = dc->res_pool->dmcu; 2632 if (dmcu != NULL && abm != NULL) 2633 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 2634 2635 if (dc->fbc_compressor) 2636 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2637 2638 } 2639 2640 2641 void dce110_prepare_bandwidth( 2642 struct dc *dc, 2643 struct dc_state *context) 2644 { 2645 struct clk_mgr *dccg = dc->clk_mgr; 2646 2647 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2648 2649 dccg->funcs->update_clocks( 2650 dccg, 2651 context, 2652 false); 2653 } 2654 2655 void dce110_optimize_bandwidth( 2656 struct dc *dc, 2657 struct dc_state *context) 2658 { 2659 struct clk_mgr *dccg = dc->clk_mgr; 2660 2661 dce110_set_displaymarks(dc, context); 2662 2663 dccg->funcs->update_clocks( 2664 dccg, 2665 context, 2666 true); 2667 } 2668 2669 static void dce110_program_front_end_for_pipe( 2670 struct dc *dc, struct pipe_ctx *pipe_ctx) 2671 { 2672 struct mem_input *mi = pipe_ctx->plane_res.mi; 2673 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2674 struct xfm_grph_csc_adjustment adjust; 2675 struct out_csc_color_matrix tbl_entry; 2676 unsigned int i; 2677 struct dce_hwseq *hws = dc->hwseq; 2678 2679 DC_LOGGER_INIT(); 2680 memset(&tbl_entry, 0, sizeof(tbl_entry)); 2681 2682 memset(&adjust, 0, sizeof(adjust)); 2683 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2684 2685 dce_enable_fe_clock(dc->hwseq, mi->inst, true); 2686 2687 set_default_colors(pipe_ctx); 2688 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 2689 == true) { 2690 tbl_entry.color_space = 2691 pipe_ctx->stream->output_color_space; 2692 2693 for (i = 0; i < 12; i++) 2694 tbl_entry.regval[i] = 2695 pipe_ctx->stream->csc_color_matrix.matrix[i]; 2696 2697 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 2698 (pipe_ctx->plane_res.xfm, &tbl_entry); 2699 } 2700 2701 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2702 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2703 2704 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2705 adjust.temperature_matrix[i] = 2706 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2707 } 2708 2709 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2710 2711 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; 2712 2713 program_scaler(dc, pipe_ctx); 2714 2715 mi->funcs->mem_input_program_surface_config( 2716 mi, 2717 plane_state->format, 2718 &plane_state->tiling_info, 2719 &plane_state->plane_size, 2720 plane_state->rotation, 2721 NULL, 2722 false); 2723 if (mi->funcs->set_blank) 2724 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 2725 2726 if (dc->config.gpu_vm_support) 2727 mi->funcs->mem_input_program_pte_vm( 2728 pipe_ctx->plane_res.mi, 2729 plane_state->format, 2730 &plane_state->tiling_info, 2731 plane_state->rotation); 2732 2733 /* Moved programming gamma from dc to hwss */ 2734 if (pipe_ctx->plane_state->update_flags.bits.full_update || 2735 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2736 pipe_ctx->plane_state->update_flags.bits.gamma_change) 2737 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2738 2739 if (pipe_ctx->plane_state->update_flags.bits.full_update) 2740 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2741 2742 DC_LOG_SURFACE( 2743 "Pipe:%d %p: addr hi:0x%x, " 2744 "addr low:0x%x, " 2745 "src: %d, %d, %d," 2746 " %d; dst: %d, %d, %d, %d;" 2747 "clip: %d, %d, %d, %d\n", 2748 pipe_ctx->pipe_idx, 2749 (void *) pipe_ctx->plane_state, 2750 pipe_ctx->plane_state->address.grph.addr.high_part, 2751 pipe_ctx->plane_state->address.grph.addr.low_part, 2752 pipe_ctx->plane_state->src_rect.x, 2753 pipe_ctx->plane_state->src_rect.y, 2754 pipe_ctx->plane_state->src_rect.width, 2755 pipe_ctx->plane_state->src_rect.height, 2756 pipe_ctx->plane_state->dst_rect.x, 2757 pipe_ctx->plane_state->dst_rect.y, 2758 pipe_ctx->plane_state->dst_rect.width, 2759 pipe_ctx->plane_state->dst_rect.height, 2760 pipe_ctx->plane_state->clip_rect.x, 2761 pipe_ctx->plane_state->clip_rect.y, 2762 pipe_ctx->plane_state->clip_rect.width, 2763 pipe_ctx->plane_state->clip_rect.height); 2764 2765 DC_LOG_SURFACE( 2766 "Pipe %d: width, height, x, y\n" 2767 "viewport:%d, %d, %d, %d\n" 2768 "recout: %d, %d, %d, %d\n", 2769 pipe_ctx->pipe_idx, 2770 pipe_ctx->plane_res.scl_data.viewport.width, 2771 pipe_ctx->plane_res.scl_data.viewport.height, 2772 pipe_ctx->plane_res.scl_data.viewport.x, 2773 pipe_ctx->plane_res.scl_data.viewport.y, 2774 pipe_ctx->plane_res.scl_data.recout.width, 2775 pipe_ctx->plane_res.scl_data.recout.height, 2776 pipe_ctx->plane_res.scl_data.recout.x, 2777 pipe_ctx->plane_res.scl_data.recout.y); 2778 } 2779 2780 static void dce110_apply_ctx_for_surface( 2781 struct dc *dc, 2782 const struct dc_stream_state *stream, 2783 int num_planes, 2784 struct dc_state *context) 2785 { 2786 int i; 2787 2788 if (num_planes == 0) 2789 return; 2790 2791 if (dc->fbc_compressor) 2792 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2793 2794 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2795 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2796 2797 if (pipe_ctx->stream != stream) 2798 continue; 2799 2800 /* Need to allocate mem before program front end for Fiji */ 2801 pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 2802 pipe_ctx->plane_res.mi, 2803 pipe_ctx->stream->timing.h_total, 2804 pipe_ctx->stream->timing.v_total, 2805 pipe_ctx->stream->timing.pix_clk_100hz / 10, 2806 context->stream_count); 2807 2808 dce110_program_front_end_for_pipe(dc, pipe_ctx); 2809 2810 dc->hwss.update_plane_addr(dc, pipe_ctx); 2811 2812 program_surface_visibility(dc, pipe_ctx); 2813 2814 } 2815 2816 if (dc->fbc_compressor) 2817 enable_fbc(dc, context); 2818 } 2819 2820 static void dce110_post_unlock_program_front_end( 2821 struct dc *dc, 2822 struct dc_state *context) 2823 { 2824 } 2825 2826 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 2827 { 2828 struct dce_hwseq *hws = dc->hwseq; 2829 int fe_idx = pipe_ctx->plane_res.mi ? 2830 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2831 2832 /* Do not power down fe when stream is active on dce*/ 2833 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 2834 return; 2835 2836 hws->funcs.enable_display_power_gating( 2837 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2838 2839 dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2840 dc->res_pool->transforms[fe_idx]); 2841 } 2842 2843 static void dce110_wait_for_mpcc_disconnect( 2844 struct dc *dc, 2845 struct resource_pool *res_pool, 2846 struct pipe_ctx *pipe_ctx) 2847 { 2848 /* do nothing*/ 2849 } 2850 2851 static void program_output_csc(struct dc *dc, 2852 struct pipe_ctx *pipe_ctx, 2853 enum dc_color_space colorspace, 2854 uint16_t *matrix, 2855 int opp_id) 2856 { 2857 int i; 2858 struct out_csc_color_matrix tbl_entry; 2859 2860 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 2861 enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 2862 2863 for (i = 0; i < 12; i++) 2864 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 2865 2866 tbl_entry.color_space = color_space; 2867 2868 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 2869 pipe_ctx->plane_res.xfm, &tbl_entry); 2870 } 2871 } 2872 2873 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 2874 { 2875 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 2876 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2877 struct mem_input *mi = pipe_ctx->plane_res.mi; 2878 struct dc_cursor_mi_param param = { 2879 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 2880 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 2881 .viewport = pipe_ctx->plane_res.scl_data.viewport, 2882 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 2883 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 2884 .rotation = pipe_ctx->plane_state->rotation, 2885 .mirror = pipe_ctx->plane_state->horizontal_mirror 2886 }; 2887 2888 /** 2889 * If the cursor's source viewport is clipped then we need to 2890 * translate the cursor to appear in the correct position on 2891 * the screen. 2892 * 2893 * This translation isn't affected by scaling so it needs to be 2894 * done *after* we adjust the position for the scale factor. 2895 * 2896 * This is only done by opt-in for now since there are still 2897 * some usecases like tiled display that might enable the 2898 * cursor on both streams while expecting dc to clip it. 2899 */ 2900 if (pos_cpy.translate_by_source) { 2901 pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 2902 pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2903 } 2904 2905 if (pipe_ctx->plane_state->address.type 2906 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2907 pos_cpy.enable = false; 2908 2909 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 2910 pos_cpy.enable = false; 2911 2912 if (ipp->funcs->ipp_cursor_set_position) 2913 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2914 if (mi->funcs->set_cursor_position) 2915 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 2916 } 2917 2918 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 2919 { 2920 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 2921 2922 if (pipe_ctx->plane_res.ipp && 2923 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 2924 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 2925 pipe_ctx->plane_res.ipp, attributes); 2926 2927 if (pipe_ctx->plane_res.mi && 2928 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 2929 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 2930 pipe_ctx->plane_res.mi, attributes); 2931 2932 if (pipe_ctx->plane_res.xfm && 2933 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 2934 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 2935 pipe_ctx->plane_res.xfm, attributes); 2936 } 2937 2938 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 2939 uint32_t backlight_pwm_u16_16, 2940 uint32_t frame_ramp) 2941 { 2942 struct dc_link *link = pipe_ctx->stream->link; 2943 struct dc *dc = link->ctx->dc; 2944 struct abm *abm = pipe_ctx->stream_res.abm; 2945 struct panel_cntl *panel_cntl = link->panel_cntl; 2946 struct dmcu *dmcu = dc->res_pool->dmcu; 2947 bool fw_set_brightness = true; 2948 /* DMCU -1 for all controller id values, 2949 * therefore +1 here 2950 */ 2951 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 2952 2953 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 2954 return false; 2955 2956 if (dmcu) 2957 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 2958 2959 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 2960 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 2961 else 2962 abm->funcs->set_backlight_level_pwm( 2963 abm, 2964 backlight_pwm_u16_16, 2965 frame_ramp, 2966 controller_id, 2967 link->panel_cntl->inst); 2968 2969 return true; 2970 } 2971 2972 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 2973 { 2974 struct abm *abm = pipe_ctx->stream_res.abm; 2975 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 2976 2977 if (abm) 2978 abm->funcs->set_abm_immediate_disable(abm, 2979 pipe_ctx->stream->link->panel_cntl->inst); 2980 2981 if (panel_cntl) 2982 panel_cntl->funcs->store_backlight_level(panel_cntl); 2983 } 2984 2985 void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 2986 { 2987 struct abm *abm = pipe_ctx->stream_res.abm; 2988 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 2989 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 2990 2991 if (abm && panel_cntl) 2992 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 2993 } 2994 2995 static const struct hw_sequencer_funcs dce110_funcs = { 2996 .program_gamut_remap = program_gamut_remap, 2997 .program_output_csc = program_output_csc, 2998 .init_hw = init_hw, 2999 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 3000 .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 3001 .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 3002 .update_plane_addr = update_plane_addr, 3003 .update_pending_status = dce110_update_pending_status, 3004 .enable_accelerated_mode = dce110_enable_accelerated_mode, 3005 .enable_timing_synchronization = dce110_enable_timing_synchronization, 3006 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 3007 .update_info_frame = dce110_update_info_frame, 3008 .enable_stream = dce110_enable_stream, 3009 .disable_stream = dce110_disable_stream, 3010 .unblank_stream = dce110_unblank_stream, 3011 .blank_stream = dce110_blank_stream, 3012 .enable_audio_stream = dce110_enable_audio_stream, 3013 .disable_audio_stream = dce110_disable_audio_stream, 3014 .disable_plane = dce110_power_down_fe, 3015 .pipe_control_lock = dce_pipe_control_lock, 3016 .interdependent_update_lock = NULL, 3017 .cursor_lock = dce_pipe_control_lock, 3018 .prepare_bandwidth = dce110_prepare_bandwidth, 3019 .optimize_bandwidth = dce110_optimize_bandwidth, 3020 .set_drr = set_drr, 3021 .get_position = get_position, 3022 .set_static_screen_control = set_static_screen_control, 3023 .setup_stereo = NULL, 3024 .set_avmute = dce110_set_avmute, 3025 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 3026 .edp_backlight_control = dce110_edp_backlight_control, 3027 .edp_power_control = dce110_edp_power_control, 3028 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 3029 .set_cursor_position = dce110_set_cursor_position, 3030 .set_cursor_attribute = dce110_set_cursor_attribute, 3031 .set_backlight_level = dce110_set_backlight_level, 3032 .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 3033 .set_pipe = dce110_set_pipe, 3034 }; 3035 3036 static const struct hwseq_private_funcs dce110_private_funcs = { 3037 .init_pipes = init_pipes, 3038 .update_plane_addr = update_plane_addr, 3039 .set_input_transfer_func = dce110_set_input_transfer_func, 3040 .set_output_transfer_func = dce110_set_output_transfer_func, 3041 .power_down = dce110_power_down, 3042 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 3043 .enable_display_power_gating = dce110_enable_display_power_gating, 3044 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 3045 .enable_stream_timing = dce110_enable_stream_timing, 3046 .disable_stream_gating = NULL, 3047 .enable_stream_gating = NULL, 3048 .edp_backlight_control = dce110_edp_backlight_control, 3049 }; 3050 3051 void dce110_hw_sequencer_construct(struct dc *dc) 3052 { 3053 dc->hwss = dce110_funcs; 3054 dc->hwseq->funcs = dce110_private_funcs; 3055 } 3056 3057