1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 #include "dc_bios_types.h" 31 #include "core_types.h" 32 #include "core_status.h" 33 #include "resource.h" 34 #include "dm_helpers.h" 35 #include "dce110_hw_sequencer.h" 36 #include "dce110_timing_generator.h" 37 #include "dce/dce_hwseq.h" 38 #include "gpio_service_interface.h" 39 40 #include "dce110_compressor.h" 41 42 #include "bios/bios_parser_helper.h" 43 #include "timing_generator.h" 44 #include "mem_input.h" 45 #include "opp.h" 46 #include "ipp.h" 47 #include "transform.h" 48 #include "stream_encoder.h" 49 #include "link_encoder.h" 50 #include "link_hwss.h" 51 #include "clock_source.h" 52 #include "clk_mgr.h" 53 #include "abm.h" 54 #include "audio.h" 55 #include "reg_helper.h" 56 #include "panel_cntl.h" 57 58 /* include DCE11 register header files */ 59 #include "dce/dce_11_0_d.h" 60 #include "dce/dce_11_0_sh_mask.h" 61 #include "custom_float.h" 62 63 #include "atomfirmware.h" 64 65 #define GAMMA_HW_POINTS_NUM 256 66 67 /* 68 * All values are in milliseconds; 69 * For eDP, after power-up/power/down, 70 * 300/500 msec max. delay from LCDVCC to black video generation 71 */ 72 #define PANEL_POWER_UP_TIMEOUT 300 73 #define PANEL_POWER_DOWN_TIMEOUT 500 74 #define HPD_CHECK_INTERVAL 10 75 #define OLED_POST_T7_DELAY 100 76 #define OLED_PRE_T11_DELAY 150 77 78 #define CTX \ 79 hws->ctx 80 81 #define DC_LOGGER_INIT() 82 83 #define REG(reg)\ 84 hws->regs->reg 85 86 #undef FN 87 #define FN(reg_name, field_name) \ 88 hws->shifts->field_name, hws->masks->field_name 89 90 struct dce110_hw_seq_reg_offsets { 91 uint32_t crtc; 92 }; 93 94 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 95 { 96 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 97 }, 98 { 99 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 100 }, 101 { 102 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 103 }, 104 { 105 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 106 } 107 }; 108 109 #define HW_REG_BLND(reg, id)\ 110 (reg + reg_offsets[id].blnd) 111 112 #define HW_REG_CRTC(reg, id)\ 113 (reg + reg_offsets[id].crtc) 114 115 #define MAX_WATERMARK 0xFFFF 116 #define SAFE_NBP_MARK 0x7FFF 117 118 /******************************************************************************* 119 * Private definitions 120 ******************************************************************************/ 121 /***************************PIPE_CONTROL***********************************/ 122 static void dce110_init_pte(struct dc_context *ctx) 123 { 124 uint32_t addr; 125 uint32_t value = 0; 126 uint32_t chunk_int = 0; 127 uint32_t chunk_mul = 0; 128 129 addr = mmUNP_DVMM_PTE_CONTROL; 130 value = dm_read_reg(ctx, addr); 131 132 set_reg_field_value( 133 value, 134 0, 135 DVMM_PTE_CONTROL, 136 DVMM_USE_SINGLE_PTE); 137 138 set_reg_field_value( 139 value, 140 1, 141 DVMM_PTE_CONTROL, 142 DVMM_PTE_BUFFER_MODE0); 143 144 set_reg_field_value( 145 value, 146 1, 147 DVMM_PTE_CONTROL, 148 DVMM_PTE_BUFFER_MODE1); 149 150 dm_write_reg(ctx, addr, value); 151 152 addr = mmDVMM_PTE_REQ; 153 value = dm_read_reg(ctx, addr); 154 155 chunk_int = get_reg_field_value( 156 value, 157 DVMM_PTE_REQ, 158 HFLIP_PTEREQ_PER_CHUNK_INT); 159 160 chunk_mul = get_reg_field_value( 161 value, 162 DVMM_PTE_REQ, 163 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 164 165 if (chunk_int != 0x4 || chunk_mul != 0x4) { 166 167 set_reg_field_value( 168 value, 169 255, 170 DVMM_PTE_REQ, 171 MAX_PTEREQ_TO_ISSUE); 172 173 set_reg_field_value( 174 value, 175 4, 176 DVMM_PTE_REQ, 177 HFLIP_PTEREQ_PER_CHUNK_INT); 178 179 set_reg_field_value( 180 value, 181 4, 182 DVMM_PTE_REQ, 183 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 184 185 dm_write_reg(ctx, addr, value); 186 } 187 } 188 /**************************************************************************/ 189 190 static void enable_display_pipe_clock_gating( 191 struct dc_context *ctx, 192 bool clock_gating) 193 { 194 /*TODO*/ 195 } 196 197 static bool dce110_enable_display_power_gating( 198 struct dc *dc, 199 uint8_t controller_id, 200 struct dc_bios *dcb, 201 enum pipe_gating_control power_gating) 202 { 203 enum bp_result bp_result = BP_RESULT_OK; 204 enum bp_pipe_control_action cntl; 205 struct dc_context *ctx = dc->ctx; 206 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 207 208 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 209 return true; 210 211 if (power_gating == PIPE_GATING_CONTROL_INIT) 212 cntl = ASIC_PIPE_INIT; 213 else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 214 cntl = ASIC_PIPE_ENABLE; 215 else 216 cntl = ASIC_PIPE_DISABLE; 217 218 if (controller_id == underlay_idx) 219 controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 220 221 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 222 223 bp_result = dcb->funcs->enable_disp_power_gating( 224 dcb, controller_id + 1, cntl); 225 226 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 227 * by default when command table is called 228 * 229 * Bios parser accepts controller_id = 6 as indicative of 230 * underlay pipe in dce110. But we do not support more 231 * than 3. 232 */ 233 if (controller_id < CONTROLLER_ID_MAX - 1) 234 dm_write_reg(ctx, 235 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 236 0); 237 } 238 239 if (power_gating != PIPE_GATING_CONTROL_ENABLE) 240 dce110_init_pte(ctx); 241 242 if (bp_result == BP_RESULT_OK) 243 return true; 244 else 245 return false; 246 } 247 248 static void build_prescale_params(struct ipp_prescale_params *prescale_params, 249 const struct dc_plane_state *plane_state) 250 { 251 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 252 253 switch (plane_state->format) { 254 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 255 prescale_params->scale = 0x2082; 256 break; 257 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 258 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 259 prescale_params->scale = 0x2020; 260 break; 261 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 262 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 263 prescale_params->scale = 0x2008; 264 break; 265 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 266 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 267 prescale_params->scale = 0x2000; 268 break; 269 default: 270 ASSERT(false); 271 break; 272 } 273 } 274 275 static bool 276 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 277 const struct dc_plane_state *plane_state) 278 { 279 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 280 const struct dc_transfer_func *tf = NULL; 281 struct ipp_prescale_params prescale_params = { 0 }; 282 bool result = true; 283 284 if (ipp == NULL) 285 return false; 286 287 if (plane_state->in_transfer_func) 288 tf = plane_state->in_transfer_func; 289 290 build_prescale_params(&prescale_params, plane_state); 291 ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 292 293 if (plane_state->gamma_correction && 294 !plane_state->gamma_correction->is_identity && 295 dce_use_lut(plane_state->format)) 296 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 297 298 if (tf == NULL) { 299 /* Default case if no input transfer function specified */ 300 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 301 } else if (tf->type == TF_TYPE_PREDEFINED) { 302 switch (tf->tf) { 303 case TRANSFER_FUNCTION_SRGB: 304 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 305 break; 306 case TRANSFER_FUNCTION_BT709: 307 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 308 break; 309 case TRANSFER_FUNCTION_LINEAR: 310 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 311 break; 312 case TRANSFER_FUNCTION_PQ: 313 default: 314 result = false; 315 break; 316 } 317 } else if (tf->type == TF_TYPE_BYPASS) { 318 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 319 } else { 320 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 321 result = false; 322 } 323 324 return result; 325 } 326 327 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 328 struct curve_points *arr_points, 329 uint32_t hw_points_num) 330 { 331 struct custom_float_format fmt; 332 333 struct pwl_result_data *rgb = rgb_resulted; 334 335 uint32_t i = 0; 336 337 fmt.exponenta_bits = 6; 338 fmt.mantissa_bits = 12; 339 fmt.sign = true; 340 341 if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 342 &arr_points[0].custom_float_x)) { 343 BREAK_TO_DEBUGGER(); 344 return false; 345 } 346 347 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 348 &arr_points[0].custom_float_offset)) { 349 BREAK_TO_DEBUGGER(); 350 return false; 351 } 352 353 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 354 &arr_points[0].custom_float_slope)) { 355 BREAK_TO_DEBUGGER(); 356 return false; 357 } 358 359 fmt.mantissa_bits = 10; 360 fmt.sign = false; 361 362 if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 363 &arr_points[1].custom_float_x)) { 364 BREAK_TO_DEBUGGER(); 365 return false; 366 } 367 368 if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 369 &arr_points[1].custom_float_y)) { 370 BREAK_TO_DEBUGGER(); 371 return false; 372 } 373 374 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 375 &arr_points[1].custom_float_slope)) { 376 BREAK_TO_DEBUGGER(); 377 return false; 378 } 379 380 fmt.mantissa_bits = 12; 381 fmt.sign = true; 382 383 while (i != hw_points_num) { 384 if (!convert_to_custom_float_format(rgb->red, &fmt, 385 &rgb->red_reg)) { 386 BREAK_TO_DEBUGGER(); 387 return false; 388 } 389 390 if (!convert_to_custom_float_format(rgb->green, &fmt, 391 &rgb->green_reg)) { 392 BREAK_TO_DEBUGGER(); 393 return false; 394 } 395 396 if (!convert_to_custom_float_format(rgb->blue, &fmt, 397 &rgb->blue_reg)) { 398 BREAK_TO_DEBUGGER(); 399 return false; 400 } 401 402 if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 403 &rgb->delta_red_reg)) { 404 BREAK_TO_DEBUGGER(); 405 return false; 406 } 407 408 if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 409 &rgb->delta_green_reg)) { 410 BREAK_TO_DEBUGGER(); 411 return false; 412 } 413 414 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 415 &rgb->delta_blue_reg)) { 416 BREAK_TO_DEBUGGER(); 417 return false; 418 } 419 420 ++rgb; 421 ++i; 422 } 423 424 return true; 425 } 426 427 #define MAX_LOW_POINT 25 428 #define NUMBER_REGIONS 16 429 #define NUMBER_SW_SEGMENTS 16 430 431 static bool 432 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 433 struct pwl_params *regamma_params) 434 { 435 struct curve_points *arr_points; 436 struct pwl_result_data *rgb_resulted; 437 struct pwl_result_data *rgb; 438 struct pwl_result_data *rgb_plus_1; 439 struct fixed31_32 y_r; 440 struct fixed31_32 y_g; 441 struct fixed31_32 y_b; 442 struct fixed31_32 y1_min; 443 struct fixed31_32 y3_max; 444 445 int32_t region_start, region_end; 446 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 447 448 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 449 return false; 450 451 arr_points = regamma_params->arr_points; 452 rgb_resulted = regamma_params->rgb_resulted; 453 hw_points = 0; 454 455 memset(regamma_params, 0, sizeof(struct pwl_params)); 456 457 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 458 /* 16 segments 459 * segments are from 2^-11 to 2^5 460 */ 461 region_start = -11; 462 region_end = region_start + NUMBER_REGIONS; 463 464 for (i = 0; i < NUMBER_REGIONS; i++) 465 seg_distr[i] = 4; 466 467 } else { 468 /* 10 segments 469 * segment is from 2^-10 to 2^1 470 * We include an extra segment for range [2^0, 2^1). This is to 471 * ensure that colors with normalized values of 1 don't miss the 472 * LUT. 473 */ 474 region_start = -10; 475 region_end = 1; 476 477 seg_distr[0] = 4; 478 seg_distr[1] = 4; 479 seg_distr[2] = 4; 480 seg_distr[3] = 4; 481 seg_distr[4] = 4; 482 seg_distr[5] = 4; 483 seg_distr[6] = 4; 484 seg_distr[7] = 4; 485 seg_distr[8] = 4; 486 seg_distr[9] = 4; 487 seg_distr[10] = 0; 488 seg_distr[11] = -1; 489 seg_distr[12] = -1; 490 seg_distr[13] = -1; 491 seg_distr[14] = -1; 492 seg_distr[15] = -1; 493 } 494 495 for (k = 0; k < 16; k++) { 496 if (seg_distr[k] != -1) 497 hw_points += (1 << seg_distr[k]); 498 } 499 500 j = 0; 501 for (k = 0; k < (region_end - region_start); k++) { 502 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 503 start_index = (region_start + k + MAX_LOW_POINT) * 504 NUMBER_SW_SEGMENTS; 505 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 506 i += increment) { 507 if (j == hw_points - 1) 508 break; 509 rgb_resulted[j].red = output_tf->tf_pts.red[i]; 510 rgb_resulted[j].green = output_tf->tf_pts.green[i]; 511 rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 512 j++; 513 } 514 } 515 516 /* last point */ 517 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 518 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 519 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 520 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 521 522 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 523 dc_fixpt_from_int(region_start)); 524 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 525 dc_fixpt_from_int(region_end)); 526 527 y_r = rgb_resulted[0].red; 528 y_g = rgb_resulted[0].green; 529 y_b = rgb_resulted[0].blue; 530 531 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 532 533 arr_points[0].y = y1_min; 534 arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 535 arr_points[0].x); 536 537 y_r = rgb_resulted[hw_points - 1].red; 538 y_g = rgb_resulted[hw_points - 1].green; 539 y_b = rgb_resulted[hw_points - 1].blue; 540 541 /* see comment above, m_arrPoints[1].y should be the Y value for the 542 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 543 */ 544 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 545 546 arr_points[1].y = y3_max; 547 548 arr_points[1].slope = dc_fixpt_zero; 549 550 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 551 /* for PQ, we want to have a straight line from last HW X point, 552 * and the slope to be such that we hit 1.0 at 10000 nits. 553 */ 554 const struct fixed31_32 end_value = dc_fixpt_from_int(125); 555 556 arr_points[1].slope = dc_fixpt_div( 557 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 558 dc_fixpt_sub(end_value, arr_points[1].x)); 559 } 560 561 regamma_params->hw_points_num = hw_points; 562 563 k = 0; 564 for (i = 1; i < 16; i++) { 565 if (seg_distr[k] != -1) { 566 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 567 regamma_params->arr_curve_points[i].offset = 568 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 569 } 570 k++; 571 } 572 573 if (seg_distr[k] != -1) 574 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 575 576 rgb = rgb_resulted; 577 rgb_plus_1 = rgb_resulted + 1; 578 579 i = 1; 580 581 while (i != hw_points + 1) { 582 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 583 rgb_plus_1->red = rgb->red; 584 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 585 rgb_plus_1->green = rgb->green; 586 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 587 rgb_plus_1->blue = rgb->blue; 588 589 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 590 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 591 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 592 593 ++rgb_plus_1; 594 ++rgb; 595 ++i; 596 } 597 598 convert_to_custom_float(rgb_resulted, arr_points, hw_points); 599 600 return true; 601 } 602 603 static bool 604 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 605 const struct dc_stream_state *stream) 606 { 607 struct transform *xfm = pipe_ctx->plane_res.xfm; 608 609 xfm->funcs->opp_power_on_regamma_lut(xfm, true); 610 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 611 612 if (stream->out_transfer_func && 613 stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 614 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 615 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 616 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 617 &xfm->regamma_params)) { 618 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 619 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 620 } else { 621 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 622 } 623 624 xfm->funcs->opp_power_on_regamma_lut(xfm, false); 625 626 return true; 627 } 628 629 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 630 { 631 bool is_hdmi_tmds; 632 bool is_dp; 633 634 ASSERT(pipe_ctx->stream); 635 636 if (pipe_ctx->stream_res.stream_enc == NULL) 637 return; /* this is not root pipe */ 638 639 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 640 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 641 642 if (!is_hdmi_tmds && !is_dp) 643 return; 644 645 if (is_hdmi_tmds) 646 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 647 pipe_ctx->stream_res.stream_enc, 648 &pipe_ctx->stream_res.encoder_info_frame); 649 else 650 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 651 pipe_ctx->stream_res.stream_enc, 652 &pipe_ctx->stream_res.encoder_info_frame); 653 } 654 655 void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 656 { 657 enum dc_lane_count lane_count = 658 pipe_ctx->stream->link->cur_link_settings.lane_count; 659 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 660 struct dc_link *link = pipe_ctx->stream->link; 661 const struct dc *dc = link->dc; 662 663 uint32_t active_total_with_borders; 664 uint32_t early_control = 0; 665 struct timing_generator *tg = pipe_ctx->stream_res.tg; 666 667 /* For MST, there are multiply stream go to only one link. 668 * connect DIG back_end to front_end while enable_stream and 669 * disconnect them during disable_stream 670 * BY this, it is logic clean to separate stream and link */ 671 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 672 pipe_ctx->stream_res.stream_enc->id, true); 673 674 dc->hwss.update_info_frame(pipe_ctx); 675 676 /* enable early control to avoid corruption on DP monitor*/ 677 active_total_with_borders = 678 timing->h_addressable 679 + timing->h_border_left 680 + timing->h_border_right; 681 682 if (lane_count != 0) 683 early_control = active_total_with_borders % lane_count; 684 685 if (early_control == 0) 686 early_control = lane_count; 687 688 tg->funcs->set_early_control(tg, early_control); 689 690 /* enable audio only within mode set */ 691 if (pipe_ctx->stream_res.audio != NULL) { 692 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 693 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 694 } 695 696 697 698 699 } 700 701 static enum bp_result link_transmitter_control( 702 struct dc_bios *bios, 703 struct bp_transmitter_control *cntl) 704 { 705 enum bp_result result; 706 707 result = bios->funcs->transmitter_control(bios, cntl); 708 709 return result; 710 } 711 712 /* 713 * @brief 714 * eDP only. 715 */ 716 void dce110_edp_wait_for_hpd_ready( 717 struct dc_link *link, 718 bool power_up) 719 { 720 struct dc_context *ctx = link->ctx; 721 struct graphics_object_id connector = link->link_enc->connector; 722 struct gpio *hpd; 723 struct dc_sink *sink = link->local_sink; 724 bool edp_hpd_high = false; 725 uint32_t time_elapsed = 0; 726 uint32_t timeout = power_up ? 727 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 728 729 if (dal_graphics_object_id_get_connector_id(connector) 730 != CONNECTOR_ID_EDP) { 731 BREAK_TO_DEBUGGER(); 732 return; 733 } 734 735 if (!power_up) 736 /* 737 * From KV, we will not HPD low after turning off VCC - 738 * instead, we will check the SW timer in power_up(). 739 */ 740 return; 741 742 /* 743 * When we power on/off the eDP panel, 744 * we need to wait until SENSE bit is high/low. 745 */ 746 747 /* obtain HPD */ 748 /* TODO what to do with this? */ 749 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 750 751 if (!hpd) { 752 BREAK_TO_DEBUGGER(); 753 return; 754 } 755 756 if (sink != NULL) { 757 if (sink->edid_caps.panel_patch.extra_t3_ms > 0) { 758 int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms; 759 760 msleep(extra_t3_in_ms); 761 } 762 } 763 764 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 765 766 /* wait until timeout or panel detected */ 767 768 do { 769 uint32_t detected = 0; 770 771 dal_gpio_get_value(hpd, &detected); 772 773 if (!(detected ^ power_up)) { 774 edp_hpd_high = true; 775 break; 776 } 777 778 msleep(HPD_CHECK_INTERVAL); 779 780 time_elapsed += HPD_CHECK_INTERVAL; 781 } while (time_elapsed < timeout); 782 783 dal_gpio_close(hpd); 784 785 dal_gpio_destroy_irq(&hpd); 786 787 if (false == edp_hpd_high) { 788 DC_LOG_ERROR( 789 "%s: wait timed out!\n", __func__); 790 } 791 } 792 793 void dce110_edp_power_control( 794 struct dc_link *link, 795 bool power_up) 796 { 797 struct dc_context *ctx = link->ctx; 798 struct bp_transmitter_control cntl = { 0 }; 799 enum bp_result bp_result; 800 801 802 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 803 != CONNECTOR_ID_EDP) { 804 BREAK_TO_DEBUGGER(); 805 return; 806 } 807 808 if (!link->panel_cntl) 809 return; 810 811 if (power_up != 812 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 813 814 unsigned long long current_ts = dm_get_timestamp(ctx); 815 unsigned long long time_since_edp_poweroff_ms = 816 div64_u64(dm_get_elapse_time_in_ns( 817 ctx, 818 current_ts, 819 link->link_trace.time_stamp.edp_poweroff), 1000000); 820 unsigned long long time_since_edp_poweron_ms = 821 div64_u64(dm_get_elapse_time_in_ns( 822 ctx, 823 current_ts, 824 link->link_trace.time_stamp.edp_poweron), 1000000); 825 DC_LOG_HW_RESUME_S3( 826 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 827 __func__, 828 power_up, 829 current_ts, 830 link->link_trace.time_stamp.edp_poweroff, 831 link->link_trace.time_stamp.edp_poweron, 832 time_since_edp_poweroff_ms, 833 time_since_edp_poweron_ms); 834 835 /* Send VBIOS command to prompt eDP panel power */ 836 if (power_up) { 837 /* edp requires a min of 500ms from LCDVDD off to on */ 838 unsigned long long remaining_min_edp_poweroff_time_ms = 500; 839 840 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 841 if (link->local_sink != NULL) 842 remaining_min_edp_poweroff_time_ms += 843 link->local_sink->edid_caps.panel_patch.extra_t12_ms; 844 845 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 846 if (link->link_trace.time_stamp.edp_poweroff != 0) { 847 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 848 remaining_min_edp_poweroff_time_ms = 849 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 850 else 851 remaining_min_edp_poweroff_time_ms = 0; 852 } 853 854 if (remaining_min_edp_poweroff_time_ms) { 855 DC_LOG_HW_RESUME_S3( 856 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 857 __func__, remaining_min_edp_poweroff_time_ms); 858 msleep(remaining_min_edp_poweroff_time_ms); 859 DC_LOG_HW_RESUME_S3( 860 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 861 __func__, remaining_min_edp_poweroff_time_ms); 862 dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 863 __func__, remaining_min_edp_poweroff_time_ms); 864 } else { 865 DC_LOG_HW_RESUME_S3( 866 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 867 __func__, remaining_min_edp_poweroff_time_ms); 868 } 869 } 870 871 DC_LOG_HW_RESUME_S3( 872 "%s: BEGIN: Panel Power action: %s\n", 873 __func__, (power_up ? "On":"Off")); 874 875 cntl.action = power_up ? 876 TRANSMITTER_CONTROL_POWER_ON : 877 TRANSMITTER_CONTROL_POWER_OFF; 878 cntl.transmitter = link->link_enc->transmitter; 879 cntl.connector_obj_id = link->link_enc->connector; 880 cntl.coherent = false; 881 cntl.lanes_number = LANE_COUNT_FOUR; 882 cntl.hpd_sel = link->link_enc->hpd_source; 883 884 if (ctx->dc->ctx->dmub_srv && 885 ctx->dc->debug.dmub_command_table) { 886 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) 887 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 888 LVTMA_CONTROL_POWER_ON); 889 else 890 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 891 LVTMA_CONTROL_POWER_OFF); 892 } 893 894 bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 895 896 DC_LOG_HW_RESUME_S3( 897 "%s: END: Panel Power action: %s bp_result=%u\n", 898 __func__, (power_up ? "On":"Off"), 899 bp_result); 900 901 if (!power_up) 902 /*save driver power off time stamp*/ 903 link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 904 else 905 link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 906 907 DC_LOG_HW_RESUME_S3( 908 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 909 __func__, 910 link->link_trace.time_stamp.edp_poweroff, 911 link->link_trace.time_stamp.edp_poweron); 912 913 if (bp_result != BP_RESULT_OK) 914 DC_LOG_ERROR( 915 "%s: Panel Power bp_result: %d\n", 916 __func__, bp_result); 917 } else { 918 DC_LOG_HW_RESUME_S3( 919 "%s: Skipping Panel Power action: %s\n", 920 __func__, (power_up ? "On":"Off")); 921 } 922 } 923 924 void dce110_edp_wait_for_T12( 925 struct dc_link *link) 926 { 927 struct dc_context *ctx = link->ctx; 928 929 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 930 != CONNECTOR_ID_EDP) { 931 BREAK_TO_DEBUGGER(); 932 return; 933 } 934 935 if (!link->panel_cntl) 936 return; 937 938 if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 939 link->link_trace.time_stamp.edp_poweroff != 0) { 940 unsigned int t12_duration = 500; // Default T12 as per spec 941 unsigned long long current_ts = dm_get_timestamp(ctx); 942 unsigned long long time_since_edp_poweroff_ms = 943 div64_u64(dm_get_elapse_time_in_ns( 944 ctx, 945 current_ts, 946 link->link_trace.time_stamp.edp_poweroff), 1000000); 947 948 t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12 949 950 if (time_since_edp_poweroff_ms < t12_duration) 951 msleep(t12_duration - time_since_edp_poweroff_ms); 952 } 953 } 954 955 /*todo: cloned in stream enc, fix*/ 956 /* 957 * @brief 958 * eDP only. Control the backlight of the eDP panel 959 */ 960 void dce110_edp_backlight_control( 961 struct dc_link *link, 962 bool enable) 963 { 964 struct dc_context *ctx = link->ctx; 965 struct bp_transmitter_control cntl = { 0 }; 966 967 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 968 != CONNECTOR_ID_EDP) { 969 BREAK_TO_DEBUGGER(); 970 return; 971 } 972 973 if (link->panel_cntl) { 974 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 975 976 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 977 DC_LOG_HW_RESUME_S3( 978 "%s: panel already powered up/off. Do nothing.\n", 979 __func__); 980 return; 981 } 982 } 983 984 /* Send VBIOS command to control eDP panel backlight */ 985 986 DC_LOG_HW_RESUME_S3( 987 "%s: backlight action: %s\n", 988 __func__, (enable ? "On":"Off")); 989 990 cntl.action = enable ? 991 TRANSMITTER_CONTROL_BACKLIGHT_ON : 992 TRANSMITTER_CONTROL_BACKLIGHT_OFF; 993 994 /*cntl.engine_id = ctx->engine;*/ 995 cntl.transmitter = link->link_enc->transmitter; 996 cntl.connector_obj_id = link->link_enc->connector; 997 /*todo: unhardcode*/ 998 cntl.lanes_number = LANE_COUNT_FOUR; 999 cntl.hpd_sel = link->link_enc->hpd_source; 1000 cntl.signal = SIGNAL_TYPE_EDP; 1001 1002 /* For eDP, the following delays might need to be considered 1003 * after link training completed: 1004 * idle period - min. accounts for required BS-Idle pattern, 1005 * max. allows for source frame synchronization); 1006 * 50 msec max. delay from valid video data from source 1007 * to video on dislpay or backlight enable. 1008 * 1009 * Disable the delay for now. 1010 * Enable it in the future if necessary. 1011 */ 1012 /* dc_service_sleep_in_milliseconds(50); */ 1013 /*edp 1.2*/ 1014 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 1015 edp_receiver_ready_T7(link); 1016 1017 if (ctx->dc->ctx->dmub_srv && 1018 ctx->dc->debug.dmub_command_table) { 1019 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 1020 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1021 LVTMA_CONTROL_LCD_BLON); 1022 else 1023 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1024 LVTMA_CONTROL_LCD_BLOFF); 1025 } 1026 1027 link_transmitter_control(ctx->dc_bios, &cntl); 1028 1029 if (enable && link->dpcd_sink_ext_caps.bits.oled) 1030 msleep(OLED_POST_T7_DELAY); 1031 1032 if (link->dpcd_sink_ext_caps.bits.oled || 1033 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 1034 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 1035 dc_link_backlight_enable_aux(link, enable); 1036 1037 /*edp 1.2*/ 1038 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) 1039 edp_add_delay_for_T9(link); 1040 1041 if (!enable && link->dpcd_sink_ext_caps.bits.oled) 1042 msleep(OLED_PRE_T11_DELAY); 1043 } 1044 1045 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 1046 { 1047 /* notify audio driver for audio modes of monitor */ 1048 struct dc *dc; 1049 struct clk_mgr *clk_mgr; 1050 unsigned int i, num_audio = 1; 1051 1052 if (!pipe_ctx->stream) 1053 return; 1054 1055 dc = pipe_ctx->stream->ctx->dc; 1056 clk_mgr = dc->clk_mgr; 1057 1058 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 1059 return; 1060 1061 if (pipe_ctx->stream_res.audio) { 1062 for (i = 0; i < MAX_PIPES; i++) { 1063 /*current_state not updated yet*/ 1064 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 1065 num_audio++; 1066 } 1067 1068 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 1069 1070 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 1071 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1072 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1073 /* un-mute audio */ 1074 /* TODO: audio should be per stream rather than per link */ 1075 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 1076 pipe_ctx->stream_res.stream_enc, false); 1077 if (pipe_ctx->stream_res.audio) 1078 pipe_ctx->stream_res.audio->enabled = true; 1079 } 1080 } 1081 1082 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 1083 { 1084 struct dc *dc; 1085 struct clk_mgr *clk_mgr; 1086 1087 if (!pipe_ctx || !pipe_ctx->stream) 1088 return; 1089 1090 dc = pipe_ctx->stream->ctx->dc; 1091 clk_mgr = dc->clk_mgr; 1092 1093 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 1094 return; 1095 1096 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 1097 pipe_ctx->stream_res.stream_enc, true); 1098 if (pipe_ctx->stream_res.audio) { 1099 pipe_ctx->stream_res.audio->enabled = false; 1100 1101 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1102 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 1103 pipe_ctx->stream_res.stream_enc); 1104 else 1105 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 1106 pipe_ctx->stream_res.stream_enc); 1107 1108 if (clk_mgr->funcs->enable_pme_wa) 1109 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1110 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1111 1112 /* TODO: notify audio driver for if audio modes list changed 1113 * add audio mode list change flag */ 1114 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 1115 * stream->stream_engine_id); 1116 */ 1117 } 1118 } 1119 1120 void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 1121 { 1122 struct dc_stream_state *stream = pipe_ctx->stream; 1123 struct dc_link *link = stream->link; 1124 struct dc *dc = pipe_ctx->stream->ctx->dc; 1125 1126 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 1127 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 1128 pipe_ctx->stream_res.stream_enc); 1129 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1130 pipe_ctx->stream_res.stream_enc); 1131 } 1132 1133 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1134 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 1135 pipe_ctx->stream_res.stream_enc); 1136 1137 dc->hwss.disable_audio_stream(pipe_ctx); 1138 1139 link->link_enc->funcs->connect_dig_be_to_fe( 1140 link->link_enc, 1141 pipe_ctx->stream_res.stream_enc->id, 1142 false); 1143 1144 } 1145 1146 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 1147 struct dc_link_settings *link_settings) 1148 { 1149 struct encoder_unblank_param params = { { 0 } }; 1150 struct dc_stream_state *stream = pipe_ctx->stream; 1151 struct dc_link *link = stream->link; 1152 struct dce_hwseq *hws = link->dc->hwseq; 1153 1154 /* only 3 items below are used by unblank */ 1155 params.timing = pipe_ctx->stream->timing; 1156 params.link_settings.link_rate = link_settings->link_rate; 1157 1158 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1159 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 1160 1161 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1162 hws->funcs.edp_backlight_control(link, true); 1163 } 1164 } 1165 1166 void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 1167 { 1168 struct dc_stream_state *stream = pipe_ctx->stream; 1169 struct dc_link *link = stream->link; 1170 struct dce_hwseq *hws = link->dc->hwseq; 1171 1172 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1173 hws->funcs.edp_backlight_control(link, false); 1174 link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1175 } 1176 1177 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1178 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 1179 1180 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1181 /* 1182 * After output is idle pattern some sinks need time to recognize the stream 1183 * has changed or they enter protection state and hang. 1184 */ 1185 msleep(60); 1186 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) 1187 edp_receiver_ready_T9(link); 1188 } 1189 1190 } 1191 1192 1193 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 1194 { 1195 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 1196 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 1197 } 1198 1199 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 1200 { 1201 switch (crtc_id) { 1202 case CONTROLLER_ID_D0: 1203 return DTO_SOURCE_ID0; 1204 case CONTROLLER_ID_D1: 1205 return DTO_SOURCE_ID1; 1206 case CONTROLLER_ID_D2: 1207 return DTO_SOURCE_ID2; 1208 case CONTROLLER_ID_D3: 1209 return DTO_SOURCE_ID3; 1210 case CONTROLLER_ID_D4: 1211 return DTO_SOURCE_ID4; 1212 case CONTROLLER_ID_D5: 1213 return DTO_SOURCE_ID5; 1214 default: 1215 return DTO_SOURCE_UNKNOWN; 1216 } 1217 } 1218 1219 static void build_audio_output( 1220 struct dc_state *state, 1221 const struct pipe_ctx *pipe_ctx, 1222 struct audio_output *audio_output) 1223 { 1224 const struct dc_stream_state *stream = pipe_ctx->stream; 1225 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 1226 1227 audio_output->signal = pipe_ctx->stream->signal; 1228 1229 /* audio_crtc_info */ 1230 1231 audio_output->crtc_info.h_total = 1232 stream->timing.h_total; 1233 1234 /* 1235 * Audio packets are sent during actual CRTC blank physical signal, we 1236 * need to specify actual active signal portion 1237 */ 1238 audio_output->crtc_info.h_active = 1239 stream->timing.h_addressable 1240 + stream->timing.h_border_left 1241 + stream->timing.h_border_right; 1242 1243 audio_output->crtc_info.v_active = 1244 stream->timing.v_addressable 1245 + stream->timing.v_border_top 1246 + stream->timing.v_border_bottom; 1247 1248 audio_output->crtc_info.pixel_repetition = 1; 1249 1250 audio_output->crtc_info.interlaced = 1251 stream->timing.flags.INTERLACE; 1252 1253 audio_output->crtc_info.refresh_rate = 1254 (stream->timing.pix_clk_100hz*100)/ 1255 (stream->timing.h_total*stream->timing.v_total); 1256 1257 audio_output->crtc_info.color_depth = 1258 stream->timing.display_color_depth; 1259 1260 audio_output->crtc_info.requested_pixel_clock_100Hz = 1261 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1262 1263 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1264 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1265 1266 /*for HDMI, audio ACR is with deep color ratio factor*/ 1267 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 1268 audio_output->crtc_info.requested_pixel_clock_100Hz == 1269 (stream->timing.pix_clk_100hz)) { 1270 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1271 audio_output->crtc_info.requested_pixel_clock_100Hz = 1272 audio_output->crtc_info.requested_pixel_clock_100Hz/2; 1273 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1274 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 1275 1276 } 1277 } 1278 1279 if (state->clk_mgr && 1280 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1281 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 1282 audio_output->pll_info.dp_dto_source_clock_in_khz = 1283 state->clk_mgr->funcs->get_dp_ref_clk_frequency( 1284 state->clk_mgr); 1285 } 1286 1287 audio_output->pll_info.feed_back_divider = 1288 pipe_ctx->pll_settings.feedback_divider; 1289 1290 audio_output->pll_info.dto_source = 1291 translate_to_dto_source( 1292 pipe_ctx->stream_res.tg->inst + 1); 1293 1294 /* TODO hard code to enable for now. Need get from stream */ 1295 audio_output->pll_info.ss_enabled = true; 1296 1297 audio_output->pll_info.ss_percentage = 1298 pipe_ctx->pll_settings.ss_percentage; 1299 } 1300 1301 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 1302 struct tg_color *color) 1303 { 1304 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; 1305 1306 switch (pipe_ctx->plane_res.scl_data.format) { 1307 case PIXEL_FORMAT_ARGB8888: 1308 /* set boarder color to red */ 1309 color->color_r_cr = color_value; 1310 break; 1311 1312 case PIXEL_FORMAT_ARGB2101010: 1313 /* set boarder color to blue */ 1314 color->color_b_cb = color_value; 1315 break; 1316 case PIXEL_FORMAT_420BPP8: 1317 /* set boarder color to green */ 1318 color->color_g_y = color_value; 1319 break; 1320 case PIXEL_FORMAT_420BPP10: 1321 /* set boarder color to yellow */ 1322 color->color_g_y = color_value; 1323 color->color_r_cr = color_value; 1324 break; 1325 case PIXEL_FORMAT_FP16: 1326 /* set boarder color to white */ 1327 color->color_r_cr = color_value; 1328 color->color_b_cb = color_value; 1329 color->color_g_y = color_value; 1330 break; 1331 default: 1332 break; 1333 } 1334 } 1335 1336 static void program_scaler(const struct dc *dc, 1337 const struct pipe_ctx *pipe_ctx) 1338 { 1339 struct tg_color color = {0}; 1340 1341 #if defined(CONFIG_DRM_AMD_DC_DCN) 1342 /* TOFPGA */ 1343 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1344 return; 1345 #endif 1346 1347 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 1348 get_surface_visual_confirm_color(pipe_ctx, &color); 1349 else 1350 color_space_to_black_color(dc, 1351 pipe_ctx->stream->output_color_space, 1352 &color); 1353 1354 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 1355 pipe_ctx->plane_res.xfm, 1356 pipe_ctx->plane_res.scl_data.lb_params.depth, 1357 &pipe_ctx->stream->bit_depth_params); 1358 1359 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 1360 /* 1361 * The way 420 is packed, 2 channels carry Y component, 1 channel 1362 * alternate between Cb and Cr, so both channels need the pixel 1363 * value for Y 1364 */ 1365 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1366 color.color_r_cr = color.color_g_y; 1367 1368 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 1369 pipe_ctx->stream_res.tg, 1370 &color); 1371 } 1372 1373 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 1374 &pipe_ctx->plane_res.scl_data); 1375 } 1376 1377 static enum dc_status dce110_enable_stream_timing( 1378 struct pipe_ctx *pipe_ctx, 1379 struct dc_state *context, 1380 struct dc *dc) 1381 { 1382 struct dc_stream_state *stream = pipe_ctx->stream; 1383 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 1384 pipe_ctx[pipe_ctx->pipe_idx]; 1385 struct tg_color black_color = {0}; 1386 1387 if (!pipe_ctx_old->stream) { 1388 1389 /* program blank color */ 1390 color_space_to_black_color(dc, 1391 stream->output_color_space, &black_color); 1392 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1393 pipe_ctx->stream_res.tg, 1394 &black_color); 1395 1396 /* 1397 * Must blank CRTC after disabling power gating and before any 1398 * programming, otherwise CRTC will be hung in bad state 1399 */ 1400 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 1401 1402 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 1403 pipe_ctx->clock_source, 1404 &pipe_ctx->stream_res.pix_clk_params, 1405 &pipe_ctx->pll_settings)) { 1406 BREAK_TO_DEBUGGER(); 1407 return DC_ERROR_UNEXPECTED; 1408 } 1409 1410 pipe_ctx->stream_res.tg->funcs->program_timing( 1411 pipe_ctx->stream_res.tg, 1412 &stream->timing, 1413 0, 1414 0, 1415 0, 1416 0, 1417 pipe_ctx->stream->signal, 1418 true); 1419 } 1420 1421 if (!pipe_ctx_old->stream) { 1422 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 1423 pipe_ctx->stream_res.tg)) { 1424 BREAK_TO_DEBUGGER(); 1425 return DC_ERROR_UNEXPECTED; 1426 } 1427 } 1428 1429 return DC_OK; 1430 } 1431 1432 static enum dc_status apply_single_controller_ctx_to_hw( 1433 struct pipe_ctx *pipe_ctx, 1434 struct dc_state *context, 1435 struct dc *dc) 1436 { 1437 struct dc_stream_state *stream = pipe_ctx->stream; 1438 struct drr_params params = {0}; 1439 unsigned int event_triggers = 0; 1440 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1441 struct dce_hwseq *hws = dc->hwseq; 1442 1443 if (hws->funcs.disable_stream_gating) { 1444 hws->funcs.disable_stream_gating(dc, pipe_ctx); 1445 } 1446 1447 if (pipe_ctx->stream_res.audio != NULL) { 1448 struct audio_output audio_output; 1449 1450 build_audio_output(context, pipe_ctx, &audio_output); 1451 1452 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1453 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 1454 pipe_ctx->stream_res.stream_enc, 1455 pipe_ctx->stream_res.audio->inst, 1456 &pipe_ctx->stream->audio_info); 1457 else 1458 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 1459 pipe_ctx->stream_res.stream_enc, 1460 pipe_ctx->stream_res.audio->inst, 1461 &pipe_ctx->stream->audio_info, 1462 &audio_output.crtc_info); 1463 1464 pipe_ctx->stream_res.audio->funcs->az_configure( 1465 pipe_ctx->stream_res.audio, 1466 pipe_ctx->stream->signal, 1467 &audio_output.crtc_info, 1468 &pipe_ctx->stream->audio_info); 1469 } 1470 1471 /* */ 1472 /* Do not touch stream timing on seamless boot optimization. */ 1473 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1474 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1475 1476 if (hws->funcs.setup_vupdate_interrupt) 1477 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1478 1479 params.vertical_total_min = stream->adjust.v_total_min; 1480 params.vertical_total_max = stream->adjust.v_total_max; 1481 if (pipe_ctx->stream_res.tg->funcs->set_drr) 1482 pipe_ctx->stream_res.tg->funcs->set_drr( 1483 pipe_ctx->stream_res.tg, ¶ms); 1484 1485 // DRR should set trigger event to monitor surface update event 1486 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 1487 event_triggers = 0x80; 1488 /* Event triggers and num frames initialized for DRR, but can be 1489 * later updated for PSR use. Note DRR trigger events are generated 1490 * regardless of whether num frames met. 1491 */ 1492 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 1493 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 1494 pipe_ctx->stream_res.tg, event_triggers, 2); 1495 1496 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1497 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1498 pipe_ctx->stream_res.stream_enc, 1499 pipe_ctx->stream_res.tg->inst); 1500 1501 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1502 pipe_ctx->stream_res.opp, 1503 COLOR_SPACE_YCBCR601, 1504 stream->timing.display_color_depth, 1505 stream->signal); 1506 1507 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1508 pipe_ctx->stream_res.opp, 1509 &stream->bit_depth_params, 1510 &stream->clamping); 1511 while (odm_pipe) { 1512 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 1513 odm_pipe->stream_res.opp, 1514 COLOR_SPACE_YCBCR601, 1515 stream->timing.display_color_depth, 1516 stream->signal); 1517 1518 odm_pipe->stream_res.opp->funcs->opp_program_fmt( 1519 odm_pipe->stream_res.opp, 1520 &stream->bit_depth_params, 1521 &stream->clamping); 1522 odm_pipe = odm_pipe->next_odm_pipe; 1523 } 1524 1525 if (!stream->dpms_off) 1526 core_link_enable_stream(context, pipe_ctx); 1527 1528 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 1529 1530 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 1531 1532 return DC_OK; 1533 } 1534 1535 /******************************************************************************/ 1536 1537 static void power_down_encoders(struct dc *dc) 1538 { 1539 int i; 1540 1541 /* do not know BIOS back-front mapping, simply blank all. It will not 1542 * hurt for non-DP 1543 */ 1544 for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1545 dc->res_pool->stream_enc[i]->funcs->dp_blank( 1546 dc->res_pool->stream_enc[i]); 1547 } 1548 1549 for (i = 0; i < dc->link_count; i++) { 1550 enum signal_type signal = dc->links[i]->connector_signal; 1551 1552 if ((signal == SIGNAL_TYPE_EDP) || 1553 (signal == SIGNAL_TYPE_DISPLAY_PORT)) 1554 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) 1555 dp_receiver_power_ctrl(dc->links[i], false); 1556 1557 if (signal != SIGNAL_TYPE_EDP) 1558 signal = SIGNAL_TYPE_NONE; 1559 1560 dc->links[i]->link_enc->funcs->disable_output( 1561 dc->links[i]->link_enc, signal); 1562 1563 dc->links[i]->link_status.link_active = false; 1564 memset(&dc->links[i]->cur_link_settings, 0, 1565 sizeof(dc->links[i]->cur_link_settings)); 1566 } 1567 } 1568 1569 static void power_down_controllers(struct dc *dc) 1570 { 1571 int i; 1572 1573 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1574 dc->res_pool->timing_generators[i]->funcs->disable_crtc( 1575 dc->res_pool->timing_generators[i]); 1576 } 1577 } 1578 1579 static void power_down_clock_sources(struct dc *dc) 1580 { 1581 int i; 1582 1583 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 1584 dc->res_pool->dp_clock_source) == false) 1585 dm_error("Failed to power down pll! (dp clk src)\n"); 1586 1587 for (i = 0; i < dc->res_pool->clk_src_count; i++) { 1588 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 1589 dc->res_pool->clock_sources[i]) == false) 1590 dm_error("Failed to power down pll! (clk src index=%d)\n", i); 1591 } 1592 } 1593 1594 static void power_down_all_hw_blocks(struct dc *dc) 1595 { 1596 power_down_encoders(dc); 1597 1598 power_down_controllers(dc); 1599 1600 power_down_clock_sources(dc); 1601 1602 if (dc->fbc_compressor) 1603 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 1604 } 1605 1606 static void disable_vga_and_power_gate_all_controllers( 1607 struct dc *dc) 1608 { 1609 int i; 1610 struct timing_generator *tg; 1611 struct dc_context *ctx = dc->ctx; 1612 1613 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1614 tg = dc->res_pool->timing_generators[i]; 1615 1616 if (tg->funcs->disable_vga) 1617 tg->funcs->disable_vga(tg); 1618 } 1619 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1620 /* Enable CLOCK gating for each pipe BEFORE controller 1621 * powergating. */ 1622 enable_display_pipe_clock_gating(ctx, 1623 true); 1624 1625 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 1626 dc->hwss.disable_plane(dc, 1627 &dc->current_state->res_ctx.pipe_ctx[i]); 1628 } 1629 } 1630 1631 1632 static struct dc_stream_state *get_edp_stream(struct dc_state *context) 1633 { 1634 int i; 1635 1636 for (i = 0; i < context->stream_count; i++) { 1637 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) 1638 return context->streams[i]; 1639 } 1640 return NULL; 1641 } 1642 1643 static struct dc_link *get_edp_link_with_sink( 1644 struct dc *dc, 1645 struct dc_state *context) 1646 { 1647 int i; 1648 struct dc_link *link = NULL; 1649 1650 /* check if there is an eDP panel not in use */ 1651 for (i = 0; i < dc->link_count; i++) { 1652 if (dc->links[i]->local_sink && 1653 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1654 link = dc->links[i]; 1655 break; 1656 } 1657 } 1658 1659 return link; 1660 } 1661 1662 /* 1663 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 1664 * 1. Power down all DC HW blocks 1665 * 2. Disable VGA engine on all controllers 1666 * 3. Enable power gating for controller 1667 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 1668 */ 1669 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 1670 { 1671 int i; 1672 struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context); 1673 struct dc_link *edp_link = get_edp_link(dc); 1674 struct dc_stream_state *edp_stream = NULL; 1675 bool can_apply_edp_fast_boot = false; 1676 bool can_apply_seamless_boot = false; 1677 bool keep_edp_vdd_on = false; 1678 struct dce_hwseq *hws = dc->hwseq; 1679 1680 if (hws->funcs.init_pipes) 1681 hws->funcs.init_pipes(dc, context); 1682 1683 edp_stream = get_edp_stream(context); 1684 1685 // Check fastboot support, disable on DCE8 because of blank screens 1686 if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 && 1687 dc->ctx->dce_version != DCE_VERSION_8_1 && 1688 dc->ctx->dce_version != DCE_VERSION_8_3) { 1689 1690 // enable fastboot if backend is enabled on eDP 1691 if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) { 1692 /* Set optimization flag on eDP stream*/ 1693 if (edp_stream && edp_link->link_status.link_active) { 1694 edp_stream->apply_edp_fast_boot_optimization = true; 1695 can_apply_edp_fast_boot = true; 1696 } 1697 } 1698 1699 // We are trying to enable eDP, don't power down VDD 1700 if (edp_stream) 1701 keep_edp_vdd_on = true; 1702 } 1703 1704 // Check seamless boot support 1705 for (i = 0; i < context->stream_count; i++) { 1706 if (context->streams[i]->apply_seamless_boot_optimization) { 1707 can_apply_seamless_boot = true; 1708 break; 1709 } 1710 } 1711 1712 /* eDP should not have stream in resume from S4 and so even with VBios post 1713 * it should get turned off 1714 */ 1715 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 1716 if (edp_link_with_sink && !keep_edp_vdd_on) { 1717 /*turn off backlight before DP_blank and encoder powered down*/ 1718 hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1719 } 1720 /*resume from S3, no vbios posting, no need to power down again*/ 1721 power_down_all_hw_blocks(dc); 1722 disable_vga_and_power_gate_all_controllers(dc); 1723 if (edp_link_with_sink && !keep_edp_vdd_on) 1724 dc->hwss.edp_power_control(edp_link_with_sink, false); 1725 } 1726 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 1727 } 1728 1729 static uint32_t compute_pstate_blackout_duration( 1730 struct bw_fixed blackout_duration, 1731 const struct dc_stream_state *stream) 1732 { 1733 uint32_t total_dest_line_time_ns; 1734 uint32_t pstate_blackout_duration_ns; 1735 1736 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 1737 1738 total_dest_line_time_ns = 1000000UL * 1739 (stream->timing.h_total * 10) / 1740 stream->timing.pix_clk_100hz + 1741 pstate_blackout_duration_ns; 1742 1743 return total_dest_line_time_ns; 1744 } 1745 1746 static void dce110_set_displaymarks( 1747 const struct dc *dc, 1748 struct dc_state *context) 1749 { 1750 uint8_t i, num_pipes; 1751 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1752 1753 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 1754 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1755 uint32_t total_dest_line_time_ns; 1756 1757 if (pipe_ctx->stream == NULL) 1758 continue; 1759 1760 total_dest_line_time_ns = compute_pstate_blackout_duration( 1761 dc->bw_vbios->blackout_duration, pipe_ctx->stream); 1762 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 1763 pipe_ctx->plane_res.mi, 1764 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1765 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1766 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1767 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1768 total_dest_line_time_ns); 1769 if (i == underlay_idx) { 1770 num_pipes++; 1771 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1772 pipe_ctx->plane_res.mi, 1773 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1774 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1775 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1776 total_dest_line_time_ns); 1777 } 1778 num_pipes++; 1779 } 1780 } 1781 1782 void dce110_set_safe_displaymarks( 1783 struct resource_context *res_ctx, 1784 const struct resource_pool *pool) 1785 { 1786 int i; 1787 int underlay_idx = pool->underlay_pipe_index; 1788 struct dce_watermarks max_marks = { 1789 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 1790 struct dce_watermarks nbp_marks = { 1791 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 1792 struct dce_watermarks min_marks = { 0, 0, 0, 0}; 1793 1794 for (i = 0; i < MAX_PIPES; i++) { 1795 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 1796 continue; 1797 1798 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 1799 res_ctx->pipe_ctx[i].plane_res.mi, 1800 nbp_marks, 1801 max_marks, 1802 min_marks, 1803 max_marks, 1804 MAX_WATERMARK); 1805 1806 if (i == underlay_idx) 1807 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1808 res_ctx->pipe_ctx[i].plane_res.mi, 1809 nbp_marks, 1810 max_marks, 1811 max_marks, 1812 MAX_WATERMARK); 1813 1814 } 1815 } 1816 1817 /******************************************************************************* 1818 * Public functions 1819 ******************************************************************************/ 1820 1821 static void set_drr(struct pipe_ctx **pipe_ctx, 1822 int num_pipes, unsigned int vmin, unsigned int vmax, 1823 unsigned int vmid, unsigned int vmid_frame_number) 1824 { 1825 int i = 0; 1826 struct drr_params params = {0}; 1827 // DRR should set trigger event to monitor surface update event 1828 unsigned int event_triggers = 0x80; 1829 // Note DRR trigger events are generated regardless of whether num frames met. 1830 unsigned int num_frames = 2; 1831 1832 params.vertical_total_max = vmax; 1833 params.vertical_total_min = vmin; 1834 1835 /* TODO: If multiple pipes are to be supported, you need 1836 * some GSL stuff. Static screen triggers may be programmed differently 1837 * as well. 1838 */ 1839 for (i = 0; i < num_pipes; i++) { 1840 pipe_ctx[i]->stream_res.tg->funcs->set_drr( 1841 pipe_ctx[i]->stream_res.tg, ¶ms); 1842 1843 if (vmax != 0 && vmin != 0) 1844 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 1845 pipe_ctx[i]->stream_res.tg, 1846 event_triggers, num_frames); 1847 } 1848 } 1849 1850 static void get_position(struct pipe_ctx **pipe_ctx, 1851 int num_pipes, 1852 struct crtc_position *position) 1853 { 1854 int i = 0; 1855 1856 /* TODO: handle pipes > 1 1857 */ 1858 for (i = 0; i < num_pipes; i++) 1859 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 1860 } 1861 1862 static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 1863 int num_pipes, const struct dc_static_screen_params *params) 1864 { 1865 unsigned int i; 1866 unsigned int triggers = 0; 1867 1868 if (params->triggers.overlay_update) 1869 triggers |= 0x100; 1870 if (params->triggers.surface_update) 1871 triggers |= 0x80; 1872 if (params->triggers.cursor_update) 1873 triggers |= 0x2; 1874 if (params->triggers.force_trigger) 1875 triggers |= 0x1; 1876 1877 if (num_pipes) { 1878 struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1879 1880 if (dc->fbc_compressor) 1881 triggers |= 0x84; 1882 } 1883 1884 for (i = 0; i < num_pipes; i++) 1885 pipe_ctx[i]->stream_res.tg->funcs-> 1886 set_static_screen_control(pipe_ctx[i]->stream_res.tg, 1887 triggers, params->num_frames); 1888 } 1889 1890 /* 1891 * Check if FBC can be enabled 1892 */ 1893 static bool should_enable_fbc(struct dc *dc, 1894 struct dc_state *context, 1895 uint32_t *pipe_idx) 1896 { 1897 uint32_t i; 1898 struct pipe_ctx *pipe_ctx = NULL; 1899 struct resource_context *res_ctx = &context->res_ctx; 1900 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1901 1902 1903 ASSERT(dc->fbc_compressor); 1904 1905 /* FBC memory should be allocated */ 1906 if (!dc->ctx->fbc_gpu_addr) 1907 return false; 1908 1909 /* Only supports single display */ 1910 if (context->stream_count != 1) 1911 return false; 1912 1913 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1914 if (res_ctx->pipe_ctx[i].stream) { 1915 1916 pipe_ctx = &res_ctx->pipe_ctx[i]; 1917 1918 if (!pipe_ctx) 1919 continue; 1920 1921 /* fbc not applicable on underlay pipe */ 1922 if (pipe_ctx->pipe_idx != underlay_idx) { 1923 *pipe_idx = i; 1924 break; 1925 } 1926 } 1927 } 1928 1929 if (i == dc->res_pool->pipe_count) 1930 return false; 1931 1932 if (!pipe_ctx->stream->link) 1933 return false; 1934 1935 /* Only supports eDP */ 1936 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 1937 return false; 1938 1939 /* PSR should not be enabled */ 1940 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 1941 return false; 1942 1943 /* Nothing to compress */ 1944 if (!pipe_ctx->plane_state) 1945 return false; 1946 1947 /* Only for non-linear tiling */ 1948 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 1949 return false; 1950 1951 return true; 1952 } 1953 1954 /* 1955 * Enable FBC 1956 */ 1957 static void enable_fbc( 1958 struct dc *dc, 1959 struct dc_state *context) 1960 { 1961 uint32_t pipe_idx = 0; 1962 1963 if (should_enable_fbc(dc, context, &pipe_idx)) { 1964 /* Program GRPH COMPRESSED ADDRESS and PITCH */ 1965 struct compr_addr_and_pitch_params params = {0, 0, 0}; 1966 struct compressor *compr = dc->fbc_compressor; 1967 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 1968 1969 params.source_view_width = pipe_ctx->stream->timing.h_addressable; 1970 params.source_view_height = pipe_ctx->stream->timing.v_addressable; 1971 params.inst = pipe_ctx->stream_res.tg->inst; 1972 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 1973 1974 compr->funcs->surface_address_and_pitch(compr, ¶ms); 1975 compr->funcs->set_fbc_invalidation_triggers(compr, 1); 1976 1977 compr->funcs->enable_fbc(compr, ¶ms); 1978 } 1979 } 1980 1981 static void dce110_reset_hw_ctx_wrap( 1982 struct dc *dc, 1983 struct dc_state *context) 1984 { 1985 int i; 1986 1987 /* Reset old context */ 1988 /* look up the targets that have been removed since last commit */ 1989 for (i = 0; i < MAX_PIPES; i++) { 1990 struct pipe_ctx *pipe_ctx_old = 1991 &dc->current_state->res_ctx.pipe_ctx[i]; 1992 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1993 1994 /* Note: We need to disable output if clock sources change, 1995 * since bios does optimization and doesn't apply if changing 1996 * PHY when not already disabled. 1997 */ 1998 1999 /* Skip underlay pipe since it will be handled in commit surface*/ 2000 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 2001 continue; 2002 2003 if (!pipe_ctx->stream || 2004 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2005 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2006 2007 /* Disable if new stream is null. O/w, if stream is 2008 * disabled already, no need to disable again. 2009 */ 2010 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 2011 core_link_disable_stream(pipe_ctx_old); 2012 2013 /* free acquired resources*/ 2014 if (pipe_ctx_old->stream_res.audio) { 2015 /*disable az_endpoint*/ 2016 pipe_ctx_old->stream_res.audio->funcs-> 2017 az_disable(pipe_ctx_old->stream_res.audio); 2018 2019 /*free audio*/ 2020 if (dc->caps.dynamic_audio == true) { 2021 /*we have to dynamic arbitrate the audio endpoints*/ 2022 /*we free the resource, need reset is_audio_acquired*/ 2023 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2024 pipe_ctx_old->stream_res.audio, false); 2025 pipe_ctx_old->stream_res.audio = NULL; 2026 } 2027 } 2028 } 2029 2030 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 2031 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 2032 dm_error("DC: failed to blank crtc!\n"); 2033 BREAK_TO_DEBUGGER(); 2034 } 2035 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 2036 pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2037 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 2038 2039 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2040 dc->res_pool, 2041 old_clk)) 2042 old_clk->funcs->cs_power_down(old_clk); 2043 2044 dc->hwss.disable_plane(dc, pipe_ctx_old); 2045 2046 pipe_ctx_old->stream = NULL; 2047 } 2048 } 2049 } 2050 2051 static void dce110_setup_audio_dto( 2052 struct dc *dc, 2053 struct dc_state *context) 2054 { 2055 int i; 2056 2057 /* program audio wall clock. use HDMI as clock source if HDMI 2058 * audio active. Otherwise, use DP as clock source 2059 * first, loop to find any HDMI audio, if not, loop find DP audio 2060 */ 2061 /* Setup audio rate clock source */ 2062 /* Issue: 2063 * Audio lag happened on DP monitor when unplug a HDMI monitor 2064 * 2065 * Cause: 2066 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 2067 * is set to either dto0 or dto1, audio should work fine. 2068 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 2069 * set to dto0 will cause audio lag. 2070 * 2071 * Solution: 2072 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 2073 * find first available pipe with audio, setup audio wall DTO per topology 2074 * instead of per pipe. 2075 */ 2076 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2077 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2078 2079 if (pipe_ctx->stream == NULL) 2080 continue; 2081 2082 if (pipe_ctx->top_pipe) 2083 continue; 2084 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 2085 continue; 2086 if (pipe_ctx->stream_res.audio != NULL) { 2087 struct audio_output audio_output; 2088 2089 build_audio_output(context, pipe_ctx, &audio_output); 2090 2091 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2092 pipe_ctx->stream_res.audio, 2093 pipe_ctx->stream->signal, 2094 &audio_output.crtc_info, 2095 &audio_output.pll_info); 2096 break; 2097 } 2098 } 2099 2100 /* no HDMI audio is found, try DP audio */ 2101 if (i == dc->res_pool->pipe_count) { 2102 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2103 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2104 2105 if (pipe_ctx->stream == NULL) 2106 continue; 2107 2108 if (pipe_ctx->top_pipe) 2109 continue; 2110 2111 if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 2112 continue; 2113 2114 if (pipe_ctx->stream_res.audio != NULL) { 2115 struct audio_output audio_output; 2116 2117 build_audio_output(context, pipe_ctx, &audio_output); 2118 2119 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2120 pipe_ctx->stream_res.audio, 2121 pipe_ctx->stream->signal, 2122 &audio_output.crtc_info, 2123 &audio_output.pll_info); 2124 break; 2125 } 2126 } 2127 } 2128 } 2129 2130 enum dc_status dce110_apply_ctx_to_hw( 2131 struct dc *dc, 2132 struct dc_state *context) 2133 { 2134 struct dce_hwseq *hws = dc->hwseq; 2135 struct dc_bios *dcb = dc->ctx->dc_bios; 2136 enum dc_status status; 2137 int i; 2138 2139 /* Reset old context */ 2140 /* look up the targets that have been removed since last commit */ 2141 hws->funcs.reset_hw_ctx_wrap(dc, context); 2142 2143 /* Skip applying if no targets */ 2144 if (context->stream_count <= 0) 2145 return DC_OK; 2146 2147 /* Apply new context */ 2148 dcb->funcs->set_scratch_critical_state(dcb, true); 2149 2150 /* below is for real asic only */ 2151 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2152 struct pipe_ctx *pipe_ctx_old = 2153 &dc->current_state->res_ctx.pipe_ctx[i]; 2154 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2155 2156 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 2157 continue; 2158 2159 if (pipe_ctx->stream == pipe_ctx_old->stream) { 2160 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 2161 dce_crtc_switch_to_clk_src(dc->hwseq, 2162 pipe_ctx->clock_source, i); 2163 continue; 2164 } 2165 2166 hws->funcs.enable_display_power_gating( 2167 dc, i, dc->ctx->dc_bios, 2168 PIPE_GATING_CONTROL_DISABLE); 2169 } 2170 2171 if (dc->fbc_compressor) 2172 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2173 2174 dce110_setup_audio_dto(dc, context); 2175 2176 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2177 struct pipe_ctx *pipe_ctx_old = 2178 &dc->current_state->res_ctx.pipe_ctx[i]; 2179 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2180 2181 if (pipe_ctx->stream == NULL) 2182 continue; 2183 2184 if (pipe_ctx->stream == pipe_ctx_old->stream && 2185 pipe_ctx->stream->link->link_state_valid) { 2186 continue; 2187 } 2188 2189 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2190 continue; 2191 2192 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2193 continue; 2194 2195 status = apply_single_controller_ctx_to_hw( 2196 pipe_ctx, 2197 context, 2198 dc); 2199 2200 if (DC_OK != status) 2201 return status; 2202 } 2203 2204 if (dc->fbc_compressor) 2205 enable_fbc(dc, dc->current_state); 2206 2207 dcb->funcs->set_scratch_critical_state(dcb, false); 2208 2209 return DC_OK; 2210 } 2211 2212 /******************************************************************************* 2213 * Front End programming 2214 ******************************************************************************/ 2215 static void set_default_colors(struct pipe_ctx *pipe_ctx) 2216 { 2217 struct default_adjustment default_adjust = { 0 }; 2218 2219 default_adjust.force_hw_default = false; 2220 default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 2221 default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 2222 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 2223 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 2224 2225 /* display color depth */ 2226 default_adjust.color_depth = 2227 pipe_ctx->stream->timing.display_color_depth; 2228 2229 /* Lb color depth */ 2230 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 2231 2232 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 2233 pipe_ctx->plane_res.xfm, &default_adjust); 2234 } 2235 2236 2237 /******************************************************************************* 2238 * In order to turn on/off specific surface we will program 2239 * Blender + CRTC 2240 * 2241 * In case that we have two surfaces and they have a different visibility 2242 * we can't turn off the CRTC since it will turn off the entire display 2243 * 2244 * |----------------------------------------------- | 2245 * |bottom pipe|curr pipe | | | 2246 * |Surface |Surface | Blender | CRCT | 2247 * |visibility |visibility | Configuration| | 2248 * |------------------------------------------------| 2249 * | off | off | CURRENT_PIPE | blank | 2250 * | off | on | CURRENT_PIPE | unblank | 2251 * | on | off | OTHER_PIPE | unblank | 2252 * | on | on | BLENDING | unblank | 2253 * -------------------------------------------------| 2254 * 2255 ******************************************************************************/ 2256 static void program_surface_visibility(const struct dc *dc, 2257 struct pipe_ctx *pipe_ctx) 2258 { 2259 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2260 bool blank_target = false; 2261 2262 if (pipe_ctx->bottom_pipe) { 2263 2264 /* For now we are supporting only two pipes */ 2265 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2266 2267 if (pipe_ctx->bottom_pipe->plane_state->visible) { 2268 if (pipe_ctx->plane_state->visible) 2269 blender_mode = BLND_MODE_BLENDING; 2270 else 2271 blender_mode = BLND_MODE_OTHER_PIPE; 2272 2273 } else if (!pipe_ctx->plane_state->visible) 2274 blank_target = true; 2275 2276 } else if (!pipe_ctx->plane_state->visible) 2277 blank_target = true; 2278 2279 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 2280 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2281 2282 } 2283 2284 static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 2285 { 2286 int i = 0; 2287 struct xfm_grph_csc_adjustment adjust; 2288 memset(&adjust, 0, sizeof(adjust)); 2289 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2290 2291 2292 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2293 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2294 2295 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2296 adjust.temperature_matrix[i] = 2297 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2298 } 2299 2300 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2301 } 2302 static void update_plane_addr(const struct dc *dc, 2303 struct pipe_ctx *pipe_ctx) 2304 { 2305 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2306 2307 if (plane_state == NULL) 2308 return; 2309 2310 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 2311 pipe_ctx->plane_res.mi, 2312 &plane_state->address, 2313 plane_state->flip_immediate); 2314 2315 plane_state->status.requested_address = plane_state->address; 2316 } 2317 2318 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 2319 { 2320 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2321 2322 if (plane_state == NULL) 2323 return; 2324 2325 plane_state->status.is_flip_pending = 2326 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 2327 pipe_ctx->plane_res.mi); 2328 2329 if (plane_state->status.is_flip_pending && !plane_state->visible) 2330 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 2331 2332 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 2333 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2334 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 2335 plane_state->status.is_right_eye =\ 2336 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 2337 } 2338 } 2339 2340 void dce110_power_down(struct dc *dc) 2341 { 2342 power_down_all_hw_blocks(dc); 2343 disable_vga_and_power_gate_all_controllers(dc); 2344 } 2345 2346 static bool wait_for_reset_trigger_to_occur( 2347 struct dc_context *dc_ctx, 2348 struct timing_generator *tg) 2349 { 2350 bool rc = false; 2351 2352 /* To avoid endless loop we wait at most 2353 * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 2354 const uint32_t frames_to_wait_on_triggered_reset = 10; 2355 uint32_t i; 2356 2357 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 2358 2359 if (!tg->funcs->is_counter_moving(tg)) { 2360 DC_ERROR("TG counter is not moving!\n"); 2361 break; 2362 } 2363 2364 if (tg->funcs->did_triggered_reset_occur(tg)) { 2365 rc = true; 2366 /* usually occurs at i=1 */ 2367 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 2368 i); 2369 break; 2370 } 2371 2372 /* Wait for one frame. */ 2373 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 2374 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 2375 } 2376 2377 if (false == rc) 2378 DC_ERROR("GSL: Timeout on reset trigger!\n"); 2379 2380 return rc; 2381 } 2382 2383 /* Enable timing synchronization for a group of Timing Generators. */ 2384 static void dce110_enable_timing_synchronization( 2385 struct dc *dc, 2386 int group_index, 2387 int group_size, 2388 struct pipe_ctx *grouped_pipes[]) 2389 { 2390 struct dc_context *dc_ctx = dc->ctx; 2391 struct dcp_gsl_params gsl_params = { 0 }; 2392 int i; 2393 2394 DC_SYNC_INFO("GSL: Setting-up...\n"); 2395 2396 /* Designate a single TG in the group as a master. 2397 * Since HW doesn't care which one, we always assign 2398 * the 1st one in the group. */ 2399 gsl_params.gsl_group = 0; 2400 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 2401 2402 for (i = 0; i < group_size; i++) 2403 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2404 grouped_pipes[i]->stream_res.tg, &gsl_params); 2405 2406 /* Reset slave controllers on master VSync */ 2407 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2408 2409 for (i = 1 /* skip the master */; i < group_size; i++) 2410 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2411 grouped_pipes[i]->stream_res.tg, 2412 gsl_params.gsl_group); 2413 2414 for (i = 1 /* skip the master */; i < group_size; i++) { 2415 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2416 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2417 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2418 grouped_pipes[i]->stream_res.tg); 2419 } 2420 2421 /* GSL Vblank synchronization is a one time sync mechanism, assumption 2422 * is that the sync'ed displays will not drift out of sync over time*/ 2423 DC_SYNC_INFO("GSL: Restoring register states.\n"); 2424 for (i = 0; i < group_size; i++) 2425 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2426 2427 DC_SYNC_INFO("GSL: Set-up complete.\n"); 2428 } 2429 2430 static void dce110_enable_per_frame_crtc_position_reset( 2431 struct dc *dc, 2432 int group_size, 2433 struct pipe_ctx *grouped_pipes[]) 2434 { 2435 struct dc_context *dc_ctx = dc->ctx; 2436 struct dcp_gsl_params gsl_params = { 0 }; 2437 int i; 2438 2439 gsl_params.gsl_group = 0; 2440 gsl_params.gsl_master = 0; 2441 2442 for (i = 0; i < group_size; i++) 2443 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2444 grouped_pipes[i]->stream_res.tg, &gsl_params); 2445 2446 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2447 2448 for (i = 1; i < group_size; i++) 2449 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2450 grouped_pipes[i]->stream_res.tg, 2451 gsl_params.gsl_master, 2452 &grouped_pipes[i]->stream->triggered_crtc_reset); 2453 2454 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2455 for (i = 1; i < group_size; i++) 2456 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2457 2458 for (i = 0; i < group_size; i++) 2459 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2460 2461 } 2462 2463 static void init_pipes(struct dc *dc, struct dc_state *context) 2464 { 2465 // Do nothing 2466 } 2467 2468 static void init_hw(struct dc *dc) 2469 { 2470 int i; 2471 struct dc_bios *bp; 2472 struct transform *xfm; 2473 struct abm *abm; 2474 struct dmcu *dmcu; 2475 struct dce_hwseq *hws = dc->hwseq; 2476 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 2477 2478 bp = dc->ctx->dc_bios; 2479 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2480 xfm = dc->res_pool->transforms[i]; 2481 xfm->funcs->transform_reset(xfm); 2482 2483 hws->funcs.enable_display_power_gating( 2484 dc, i, bp, 2485 PIPE_GATING_CONTROL_INIT); 2486 hws->funcs.enable_display_power_gating( 2487 dc, i, bp, 2488 PIPE_GATING_CONTROL_DISABLE); 2489 hws->funcs.enable_display_pipe_clock_gating( 2490 dc->ctx, 2491 true); 2492 } 2493 2494 dce_clock_gating_power_up(dc->hwseq, false); 2495 /***************************************/ 2496 2497 for (i = 0; i < dc->link_count; i++) { 2498 /****************************************/ 2499 /* Power up AND update implementation according to the 2500 * required signal (which may be different from the 2501 * default signal on connector). */ 2502 struct dc_link *link = dc->links[i]; 2503 2504 link->link_enc->funcs->hw_init(link->link_enc); 2505 } 2506 2507 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2508 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2509 2510 tg->funcs->disable_vga(tg); 2511 2512 /* Blank controller using driver code instead of 2513 * command table. */ 2514 tg->funcs->set_blank(tg, true); 2515 hwss_wait_for_blank_complete(tg); 2516 } 2517 2518 for (i = 0; i < dc->res_pool->audio_count; i++) { 2519 struct audio *audio = dc->res_pool->audios[i]; 2520 audio->funcs->hw_init(audio); 2521 } 2522 2523 for (i = 0; i < dc->link_count; i++) { 2524 struct dc_link *link = dc->links[i]; 2525 2526 if (link->panel_cntl) 2527 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 2528 } 2529 2530 abm = dc->res_pool->abm; 2531 if (abm != NULL) 2532 abm->funcs->abm_init(abm, backlight); 2533 2534 dmcu = dc->res_pool->dmcu; 2535 if (dmcu != NULL && abm != NULL) 2536 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 2537 2538 if (dc->fbc_compressor) 2539 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2540 2541 } 2542 2543 2544 void dce110_prepare_bandwidth( 2545 struct dc *dc, 2546 struct dc_state *context) 2547 { 2548 struct clk_mgr *dccg = dc->clk_mgr; 2549 2550 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2551 2552 dccg->funcs->update_clocks( 2553 dccg, 2554 context, 2555 false); 2556 } 2557 2558 void dce110_optimize_bandwidth( 2559 struct dc *dc, 2560 struct dc_state *context) 2561 { 2562 struct clk_mgr *dccg = dc->clk_mgr; 2563 2564 dce110_set_displaymarks(dc, context); 2565 2566 dccg->funcs->update_clocks( 2567 dccg, 2568 context, 2569 true); 2570 } 2571 2572 static void dce110_program_front_end_for_pipe( 2573 struct dc *dc, struct pipe_ctx *pipe_ctx) 2574 { 2575 struct mem_input *mi = pipe_ctx->plane_res.mi; 2576 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2577 struct xfm_grph_csc_adjustment adjust; 2578 struct out_csc_color_matrix tbl_entry; 2579 unsigned int i; 2580 struct dce_hwseq *hws = dc->hwseq; 2581 2582 DC_LOGGER_INIT(); 2583 memset(&tbl_entry, 0, sizeof(tbl_entry)); 2584 2585 memset(&adjust, 0, sizeof(adjust)); 2586 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2587 2588 dce_enable_fe_clock(dc->hwseq, mi->inst, true); 2589 2590 set_default_colors(pipe_ctx); 2591 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 2592 == true) { 2593 tbl_entry.color_space = 2594 pipe_ctx->stream->output_color_space; 2595 2596 for (i = 0; i < 12; i++) 2597 tbl_entry.regval[i] = 2598 pipe_ctx->stream->csc_color_matrix.matrix[i]; 2599 2600 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 2601 (pipe_ctx->plane_res.xfm, &tbl_entry); 2602 } 2603 2604 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2605 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2606 2607 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2608 adjust.temperature_matrix[i] = 2609 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2610 } 2611 2612 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2613 2614 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2615 2616 program_scaler(dc, pipe_ctx); 2617 2618 mi->funcs->mem_input_program_surface_config( 2619 mi, 2620 plane_state->format, 2621 &plane_state->tiling_info, 2622 &plane_state->plane_size, 2623 plane_state->rotation, 2624 NULL, 2625 false); 2626 if (mi->funcs->set_blank) 2627 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 2628 2629 if (dc->config.gpu_vm_support) 2630 mi->funcs->mem_input_program_pte_vm( 2631 pipe_ctx->plane_res.mi, 2632 plane_state->format, 2633 &plane_state->tiling_info, 2634 plane_state->rotation); 2635 2636 /* Moved programming gamma from dc to hwss */ 2637 if (pipe_ctx->plane_state->update_flags.bits.full_update || 2638 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2639 pipe_ctx->plane_state->update_flags.bits.gamma_change) 2640 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2641 2642 if (pipe_ctx->plane_state->update_flags.bits.full_update) 2643 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2644 2645 DC_LOG_SURFACE( 2646 "Pipe:%d %p: addr hi:0x%x, " 2647 "addr low:0x%x, " 2648 "src: %d, %d, %d," 2649 " %d; dst: %d, %d, %d, %d;" 2650 "clip: %d, %d, %d, %d\n", 2651 pipe_ctx->pipe_idx, 2652 (void *) pipe_ctx->plane_state, 2653 pipe_ctx->plane_state->address.grph.addr.high_part, 2654 pipe_ctx->plane_state->address.grph.addr.low_part, 2655 pipe_ctx->plane_state->src_rect.x, 2656 pipe_ctx->plane_state->src_rect.y, 2657 pipe_ctx->plane_state->src_rect.width, 2658 pipe_ctx->plane_state->src_rect.height, 2659 pipe_ctx->plane_state->dst_rect.x, 2660 pipe_ctx->plane_state->dst_rect.y, 2661 pipe_ctx->plane_state->dst_rect.width, 2662 pipe_ctx->plane_state->dst_rect.height, 2663 pipe_ctx->plane_state->clip_rect.x, 2664 pipe_ctx->plane_state->clip_rect.y, 2665 pipe_ctx->plane_state->clip_rect.width, 2666 pipe_ctx->plane_state->clip_rect.height); 2667 2668 DC_LOG_SURFACE( 2669 "Pipe %d: width, height, x, y\n" 2670 "viewport:%d, %d, %d, %d\n" 2671 "recout: %d, %d, %d, %d\n", 2672 pipe_ctx->pipe_idx, 2673 pipe_ctx->plane_res.scl_data.viewport.width, 2674 pipe_ctx->plane_res.scl_data.viewport.height, 2675 pipe_ctx->plane_res.scl_data.viewport.x, 2676 pipe_ctx->plane_res.scl_data.viewport.y, 2677 pipe_ctx->plane_res.scl_data.recout.width, 2678 pipe_ctx->plane_res.scl_data.recout.height, 2679 pipe_ctx->plane_res.scl_data.recout.x, 2680 pipe_ctx->plane_res.scl_data.recout.y); 2681 } 2682 2683 static void dce110_apply_ctx_for_surface( 2684 struct dc *dc, 2685 const struct dc_stream_state *stream, 2686 int num_planes, 2687 struct dc_state *context) 2688 { 2689 int i; 2690 2691 if (num_planes == 0) 2692 return; 2693 2694 if (dc->fbc_compressor) 2695 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2696 2697 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2698 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2699 2700 if (pipe_ctx->stream != stream) 2701 continue; 2702 2703 /* Need to allocate mem before program front end for Fiji */ 2704 pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 2705 pipe_ctx->plane_res.mi, 2706 pipe_ctx->stream->timing.h_total, 2707 pipe_ctx->stream->timing.v_total, 2708 pipe_ctx->stream->timing.pix_clk_100hz / 10, 2709 context->stream_count); 2710 2711 dce110_program_front_end_for_pipe(dc, pipe_ctx); 2712 2713 dc->hwss.update_plane_addr(dc, pipe_ctx); 2714 2715 program_surface_visibility(dc, pipe_ctx); 2716 2717 } 2718 2719 if (dc->fbc_compressor) 2720 enable_fbc(dc, context); 2721 } 2722 2723 static void dce110_post_unlock_program_front_end( 2724 struct dc *dc, 2725 struct dc_state *context) 2726 { 2727 } 2728 2729 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 2730 { 2731 struct dce_hwseq *hws = dc->hwseq; 2732 int fe_idx = pipe_ctx->plane_res.mi ? 2733 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2734 2735 /* Do not power down fe when stream is active on dce*/ 2736 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 2737 return; 2738 2739 hws->funcs.enable_display_power_gating( 2740 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2741 2742 dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2743 dc->res_pool->transforms[fe_idx]); 2744 } 2745 2746 static void dce110_wait_for_mpcc_disconnect( 2747 struct dc *dc, 2748 struct resource_pool *res_pool, 2749 struct pipe_ctx *pipe_ctx) 2750 { 2751 /* do nothing*/ 2752 } 2753 2754 static void program_output_csc(struct dc *dc, 2755 struct pipe_ctx *pipe_ctx, 2756 enum dc_color_space colorspace, 2757 uint16_t *matrix, 2758 int opp_id) 2759 { 2760 int i; 2761 struct out_csc_color_matrix tbl_entry; 2762 2763 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 2764 enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 2765 2766 for (i = 0; i < 12; i++) 2767 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 2768 2769 tbl_entry.color_space = color_space; 2770 2771 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 2772 pipe_ctx->plane_res.xfm, &tbl_entry); 2773 } 2774 } 2775 2776 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 2777 { 2778 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 2779 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2780 struct mem_input *mi = pipe_ctx->plane_res.mi; 2781 struct dc_cursor_mi_param param = { 2782 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 2783 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 2784 .viewport = pipe_ctx->plane_res.scl_data.viewport, 2785 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 2786 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 2787 .rotation = pipe_ctx->plane_state->rotation, 2788 .mirror = pipe_ctx->plane_state->horizontal_mirror 2789 }; 2790 2791 /** 2792 * If the cursor's source viewport is clipped then we need to 2793 * translate the cursor to appear in the correct position on 2794 * the screen. 2795 * 2796 * This translation isn't affected by scaling so it needs to be 2797 * done *after* we adjust the position for the scale factor. 2798 * 2799 * This is only done by opt-in for now since there are still 2800 * some usecases like tiled display that might enable the 2801 * cursor on both streams while expecting dc to clip it. 2802 */ 2803 if (pos_cpy.translate_by_source) { 2804 pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 2805 pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2806 } 2807 2808 if (pipe_ctx->plane_state->address.type 2809 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2810 pos_cpy.enable = false; 2811 2812 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 2813 pos_cpy.enable = false; 2814 2815 if (ipp->funcs->ipp_cursor_set_position) 2816 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2817 if (mi->funcs->set_cursor_position) 2818 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 2819 } 2820 2821 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 2822 { 2823 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 2824 2825 if (pipe_ctx->plane_res.ipp && 2826 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 2827 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 2828 pipe_ctx->plane_res.ipp, attributes); 2829 2830 if (pipe_ctx->plane_res.mi && 2831 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 2832 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 2833 pipe_ctx->plane_res.mi, attributes); 2834 2835 if (pipe_ctx->plane_res.xfm && 2836 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 2837 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 2838 pipe_ctx->plane_res.xfm, attributes); 2839 } 2840 2841 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 2842 uint32_t backlight_pwm_u16_16, 2843 uint32_t frame_ramp) 2844 { 2845 struct dc_link *link = pipe_ctx->stream->link; 2846 struct dc *dc = link->ctx->dc; 2847 struct abm *abm = pipe_ctx->stream_res.abm; 2848 struct panel_cntl *panel_cntl = link->panel_cntl; 2849 struct dmcu *dmcu = dc->res_pool->dmcu; 2850 bool fw_set_brightness = true; 2851 /* DMCU -1 for all controller id values, 2852 * therefore +1 here 2853 */ 2854 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 2855 2856 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 2857 return false; 2858 2859 if (dmcu) 2860 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 2861 2862 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 2863 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 2864 else 2865 abm->funcs->set_backlight_level_pwm( 2866 abm, 2867 backlight_pwm_u16_16, 2868 frame_ramp, 2869 controller_id, 2870 link->panel_cntl->inst); 2871 2872 return true; 2873 } 2874 2875 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 2876 { 2877 struct abm *abm = pipe_ctx->stream_res.abm; 2878 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 2879 2880 if (abm) 2881 abm->funcs->set_abm_immediate_disable(abm, 2882 pipe_ctx->stream->link->panel_cntl->inst); 2883 2884 if (panel_cntl) 2885 panel_cntl->funcs->store_backlight_level(panel_cntl); 2886 } 2887 2888 void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 2889 { 2890 struct abm *abm = pipe_ctx->stream_res.abm; 2891 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 2892 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 2893 2894 if (abm && panel_cntl) 2895 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 2896 } 2897 2898 static const struct hw_sequencer_funcs dce110_funcs = { 2899 .program_gamut_remap = program_gamut_remap, 2900 .program_output_csc = program_output_csc, 2901 .init_hw = init_hw, 2902 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 2903 .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 2904 .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 2905 .update_plane_addr = update_plane_addr, 2906 .update_pending_status = dce110_update_pending_status, 2907 .enable_accelerated_mode = dce110_enable_accelerated_mode, 2908 .enable_timing_synchronization = dce110_enable_timing_synchronization, 2909 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 2910 .update_info_frame = dce110_update_info_frame, 2911 .enable_stream = dce110_enable_stream, 2912 .disable_stream = dce110_disable_stream, 2913 .unblank_stream = dce110_unblank_stream, 2914 .blank_stream = dce110_blank_stream, 2915 .enable_audio_stream = dce110_enable_audio_stream, 2916 .disable_audio_stream = dce110_disable_audio_stream, 2917 .disable_plane = dce110_power_down_fe, 2918 .pipe_control_lock = dce_pipe_control_lock, 2919 .interdependent_update_lock = NULL, 2920 .cursor_lock = dce_pipe_control_lock, 2921 .prepare_bandwidth = dce110_prepare_bandwidth, 2922 .optimize_bandwidth = dce110_optimize_bandwidth, 2923 .set_drr = set_drr, 2924 .get_position = get_position, 2925 .set_static_screen_control = set_static_screen_control, 2926 .setup_stereo = NULL, 2927 .set_avmute = dce110_set_avmute, 2928 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 2929 .edp_backlight_control = dce110_edp_backlight_control, 2930 .edp_power_control = dce110_edp_power_control, 2931 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 2932 .set_cursor_position = dce110_set_cursor_position, 2933 .set_cursor_attribute = dce110_set_cursor_attribute, 2934 .set_backlight_level = dce110_set_backlight_level, 2935 .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 2936 .set_pipe = dce110_set_pipe, 2937 }; 2938 2939 static const struct hwseq_private_funcs dce110_private_funcs = { 2940 .init_pipes = init_pipes, 2941 .update_plane_addr = update_plane_addr, 2942 .set_input_transfer_func = dce110_set_input_transfer_func, 2943 .set_output_transfer_func = dce110_set_output_transfer_func, 2944 .power_down = dce110_power_down, 2945 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 2946 .enable_display_power_gating = dce110_enable_display_power_gating, 2947 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 2948 .enable_stream_timing = dce110_enable_stream_timing, 2949 .disable_stream_gating = NULL, 2950 .enable_stream_gating = NULL, 2951 .edp_backlight_control = dce110_edp_backlight_control, 2952 }; 2953 2954 void dce110_hw_sequencer_construct(struct dc *dc) 2955 { 2956 dc->hwss = dce110_funcs; 2957 dc->hwseq->funcs = dce110_private_funcs; 2958 } 2959 2960