14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 25c366be54SSam Ravnborg 26c366be54SSam Ravnborg #include <linux/delay.h> 27c366be54SSam Ravnborg 284562236bSHarry Wentland #include "dm_services.h" 294562236bSHarry Wentland #include "dc.h" 304562236bSHarry Wentland #include "dc_bios_types.h" 314562236bSHarry Wentland #include "core_types.h" 324562236bSHarry Wentland #include "core_status.h" 334562236bSHarry Wentland #include "resource.h" 344562236bSHarry Wentland #include "dm_helpers.h" 354562236bSHarry Wentland #include "dce110_timing_generator.h" 3698489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 3787401969SAndrew Jiang #include "gpio_service_interface.h" 384562236bSHarry Wentland 391663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 401663ae1cSBhawanpreet Lakha 414562236bSHarry Wentland #include "bios/bios_parser_helper.h" 424562236bSHarry Wentland #include "timing_generator.h" 434562236bSHarry Wentland #include "mem_input.h" 444562236bSHarry Wentland #include "opp.h" 454562236bSHarry Wentland #include "ipp.h" 464562236bSHarry Wentland #include "transform.h" 474562236bSHarry Wentland #include "stream_encoder.h" 484562236bSHarry Wentland #include "link_encoder.h" 4987401969SAndrew Jiang #include "link_hwss.h" 50f9fc6f39SMichael Strauss #include "dc_link_dp.h" 518fe44c08SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 5264b1d0e8SNicholas Kazlauskas #include "dccg.h" 5364b1d0e8SNicholas Kazlauskas #endif 544562236bSHarry Wentland #include "clock_source.h" 55dc88b4a6SEric Yang #include "clk_mgr.h" 565e7773a2SAnthony Koo #include "abm.h" 574562236bSHarry Wentland #include "audio.h" 5808b16886SZeyu Fan #include "reg_helper.h" 59d4caa72eSAnthony Koo #include "panel_cntl.h" 604562236bSHarry Wentland 614562236bSHarry Wentland /* include DCE11 register header files */ 624562236bSHarry Wentland #include "dce/dce_11_0_d.h" 634562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 64e266fdf6SVitaly Prosyak #include "custom_float.h" 654562236bSHarry Wentland 664cac1e6dSYongqiang Sun #include "atomfirmware.h" 674cac1e6dSYongqiang Sun 68a76eb7d3SLee Jones #include "dcn10/dcn10_hw_sequencer.h" 696e4a14ccSLee Jones 7078c77382SAnthony Koo #define GAMMA_HW_POINTS_NUM 256 7178c77382SAnthony Koo 7287401969SAndrew Jiang /* 7387401969SAndrew Jiang * All values are in milliseconds; 7487401969SAndrew Jiang * For eDP, after power-up/power/down, 7587401969SAndrew Jiang * 300/500 msec max. delay from LCDVCC to black video generation 7687401969SAndrew Jiang */ 7787401969SAndrew Jiang #define PANEL_POWER_UP_TIMEOUT 300 7887401969SAndrew Jiang #define PANEL_POWER_DOWN_TIMEOUT 500 7987401969SAndrew Jiang #define HPD_CHECK_INTERVAL 10 8096577cf8SHersen Wu #define OLED_POST_T7_DELAY 100 8196577cf8SHersen Wu #define OLED_PRE_T11_DELAY 150 8287401969SAndrew Jiang 835eefbc40SYue Hin Lau #define CTX \ 845eefbc40SYue Hin Lau hws->ctx 855d4b05ddSBhawanpreet Lakha 865d4b05ddSBhawanpreet Lakha #define DC_LOGGER_INIT() 875d4b05ddSBhawanpreet Lakha 885eefbc40SYue Hin Lau #define REG(reg)\ 895eefbc40SYue Hin Lau hws->regs->reg 905eefbc40SYue Hin Lau 915eefbc40SYue Hin Lau #undef FN 925eefbc40SYue Hin Lau #define FN(reg_name, field_name) \ 935eefbc40SYue Hin Lau hws->shifts->field_name, hws->masks->field_name 945eefbc40SYue Hin Lau 954562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 964562236bSHarry Wentland uint32_t crtc; 974562236bSHarry Wentland }; 984562236bSHarry Wentland 994562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 1004562236bSHarry Wentland { 1014562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1024562236bSHarry Wentland }, 1034562236bSHarry Wentland { 1044562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1054562236bSHarry Wentland }, 1064562236bSHarry Wentland { 1074562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1084562236bSHarry Wentland }, 1094562236bSHarry Wentland { 1104562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1114562236bSHarry Wentland } 1124562236bSHarry Wentland }; 1134562236bSHarry Wentland 1144562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 1154562236bSHarry Wentland (reg + reg_offsets[id].blnd) 1164562236bSHarry Wentland 1174562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 1184562236bSHarry Wentland (reg + reg_offsets[id].crtc) 1194562236bSHarry Wentland 1204562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 1214562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 1224562236bSHarry Wentland 1234562236bSHarry Wentland /******************************************************************************* 1244562236bSHarry Wentland * Private definitions 1254562236bSHarry Wentland ******************************************************************************/ 1264562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 1274562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 1284562236bSHarry Wentland { 1294562236bSHarry Wentland uint32_t addr; 1304562236bSHarry Wentland uint32_t value = 0; 1314562236bSHarry Wentland uint32_t chunk_int = 0; 1324562236bSHarry Wentland uint32_t chunk_mul = 0; 1334562236bSHarry Wentland 1344562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 1354562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1364562236bSHarry Wentland 1374562236bSHarry Wentland set_reg_field_value( 1384562236bSHarry Wentland value, 1394562236bSHarry Wentland 0, 1404562236bSHarry Wentland DVMM_PTE_CONTROL, 1414562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1424562236bSHarry Wentland 1434562236bSHarry Wentland set_reg_field_value( 1444562236bSHarry Wentland value, 1454562236bSHarry Wentland 1, 1464562236bSHarry Wentland DVMM_PTE_CONTROL, 1474562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1484562236bSHarry Wentland 1494562236bSHarry Wentland set_reg_field_value( 1504562236bSHarry Wentland value, 1514562236bSHarry Wentland 1, 1524562236bSHarry Wentland DVMM_PTE_CONTROL, 1534562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1544562236bSHarry Wentland 1554562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1564562236bSHarry Wentland 1574562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1584562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1594562236bSHarry Wentland 1604562236bSHarry Wentland chunk_int = get_reg_field_value( 1614562236bSHarry Wentland value, 1624562236bSHarry Wentland DVMM_PTE_REQ, 1634562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1644562236bSHarry Wentland 1654562236bSHarry Wentland chunk_mul = get_reg_field_value( 1664562236bSHarry Wentland value, 1674562236bSHarry Wentland DVMM_PTE_REQ, 1684562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1694562236bSHarry Wentland 1704562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1714562236bSHarry Wentland 1724562236bSHarry Wentland set_reg_field_value( 1734562236bSHarry Wentland value, 1744562236bSHarry Wentland 255, 1754562236bSHarry Wentland DVMM_PTE_REQ, 1764562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1774562236bSHarry Wentland 1784562236bSHarry Wentland set_reg_field_value( 1794562236bSHarry Wentland value, 1804562236bSHarry Wentland 4, 1814562236bSHarry Wentland DVMM_PTE_REQ, 1824562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1834562236bSHarry Wentland 1844562236bSHarry Wentland set_reg_field_value( 1854562236bSHarry Wentland value, 1864562236bSHarry Wentland 4, 1874562236bSHarry Wentland DVMM_PTE_REQ, 1884562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1894562236bSHarry Wentland 1904562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1914562236bSHarry Wentland } 1924562236bSHarry Wentland } 1934562236bSHarry Wentland /**************************************************************************/ 1944562236bSHarry Wentland 1954562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1964562236bSHarry Wentland struct dc_context *ctx, 1974562236bSHarry Wentland bool clock_gating) 1984562236bSHarry Wentland { 1994562236bSHarry Wentland /*TODO*/ 2004562236bSHarry Wentland } 2014562236bSHarry Wentland 2024562236bSHarry Wentland static bool dce110_enable_display_power_gating( 203fb3466a4SBhawanpreet Lakha struct dc *dc, 2044562236bSHarry Wentland uint8_t controller_id, 2054562236bSHarry Wentland struct dc_bios *dcb, 2064562236bSHarry Wentland enum pipe_gating_control power_gating) 2074562236bSHarry Wentland { 2084562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 2094562236bSHarry Wentland enum bp_pipe_control_action cntl; 2104562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 2114562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 2124562236bSHarry Wentland 2134562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 2144562236bSHarry Wentland return true; 2154562236bSHarry Wentland 2164562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 2174562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 2184562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 2194562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 2204562236bSHarry Wentland else 2214562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 2224562236bSHarry Wentland 2234562236bSHarry Wentland if (controller_id == underlay_idx) 2244562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 2254562236bSHarry Wentland 2264562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 2274562236bSHarry Wentland 2284562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 2294562236bSHarry Wentland dcb, controller_id + 1, cntl); 2304562236bSHarry Wentland 2314562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 2324562236bSHarry Wentland * by default when command table is called 2334562236bSHarry Wentland * 2344562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 2354562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2364562236bSHarry Wentland * than 3. 2374562236bSHarry Wentland */ 2384562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2394562236bSHarry Wentland dm_write_reg(ctx, 2404562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2414562236bSHarry Wentland 0); 2424562236bSHarry Wentland } 2434562236bSHarry Wentland 2444562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2454562236bSHarry Wentland dce110_init_pte(ctx); 2464562236bSHarry Wentland 2474562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2484562236bSHarry Wentland return true; 2494562236bSHarry Wentland else 2504562236bSHarry Wentland return false; 2514562236bSHarry Wentland } 2524562236bSHarry Wentland 2534562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2543be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2554562236bSHarry Wentland { 2564562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2574562236bSHarry Wentland 2583be5262eSHarry Wentland switch (plane_state->format) { 2591352c779SNicholas Kazlauskas case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2601352c779SNicholas Kazlauskas prescale_params->scale = 0x2082; 2611352c779SNicholas Kazlauskas break; 2624562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2638693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2644562236bSHarry Wentland prescale_params->scale = 0x2020; 2654562236bSHarry Wentland break; 2664562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2674562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2684562236bSHarry Wentland prescale_params->scale = 0x2008; 2694562236bSHarry Wentland break; 2704562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 271050cd3d6SMario Kleiner case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 2724562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2734562236bSHarry Wentland prescale_params->scale = 0x2000; 2744562236bSHarry Wentland break; 2754562236bSHarry Wentland default: 2764562236bSHarry Wentland ASSERT(false); 277d7194cf6SAric Cyr break; 2784562236bSHarry Wentland } 2794562236bSHarry Wentland } 2804562236bSHarry Wentland 281a6114e85SHarry Wentland static bool 28278c77382SAnthony Koo dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 2833be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2844562236bSHarry Wentland { 28586a66c4eSHarry Wentland struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2867b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 28790e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 28890e508baSAnthony Koo bool result = true; 28990e508baSAnthony Koo 29090e508baSAnthony Koo if (ipp == NULL) 29190e508baSAnthony Koo return false; 29290e508baSAnthony Koo 2933be5262eSHarry Wentland if (plane_state->in_transfer_func) 2943be5262eSHarry Wentland tf = plane_state->in_transfer_func; 29590e508baSAnthony Koo 2963be5262eSHarry Wentland build_prescale_params(&prescale_params, plane_state); 29790e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 29890e508baSAnthony Koo 29984ffa801SLeo (Sunpeng) Li if (plane_state->gamma_correction && 30084ffa801SLeo (Sunpeng) Li !plane_state->gamma_correction->is_identity && 30184ffa801SLeo (Sunpeng) Li dce_use_lut(plane_state->format)) 3023be5262eSHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 303d7194cf6SAric Cyr 30490e508baSAnthony Koo if (tf == NULL) { 30590e508baSAnthony Koo /* Default case if no input transfer function specified */ 306a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 3077b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 3087b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 30990e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 310a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 31190e508baSAnthony Koo break; 31290e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 313a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 31490e508baSAnthony Koo break; 31590e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 316a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 31790e508baSAnthony Koo break; 31890e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 31990e508baSAnthony Koo default: 32090e508baSAnthony Koo result = false; 321d7194cf6SAric Cyr break; 32290e508baSAnthony Koo } 3237b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 32470063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 32590e508baSAnthony Koo } else { 32690e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 32790e508baSAnthony Koo result = false; 32890e508baSAnthony Koo } 32990e508baSAnthony Koo 33090e508baSAnthony Koo return result; 33190e508baSAnthony Koo } 33290e508baSAnthony Koo 333bd1be8e8SHarry Wentland static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 334fcd2f4bfSAmy Zhang struct curve_points *arr_points, 335fcd2f4bfSAmy Zhang uint32_t hw_points_num) 336fcd2f4bfSAmy Zhang { 337fcd2f4bfSAmy Zhang struct custom_float_format fmt; 338fcd2f4bfSAmy Zhang 339fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 340fcd2f4bfSAmy Zhang 341fcd2f4bfSAmy Zhang uint32_t i = 0; 342fcd2f4bfSAmy Zhang 343fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 344fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 345fcd2f4bfSAmy Zhang fmt.sign = true; 346fcd2f4bfSAmy Zhang 347bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 348fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 349fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 350fcd2f4bfSAmy Zhang return false; 351fcd2f4bfSAmy Zhang } 352fcd2f4bfSAmy Zhang 353bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 354fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 355fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 356fcd2f4bfSAmy Zhang return false; 357fcd2f4bfSAmy Zhang } 358fcd2f4bfSAmy Zhang 359bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 360fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 361fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 362fcd2f4bfSAmy Zhang return false; 363fcd2f4bfSAmy Zhang } 364fcd2f4bfSAmy Zhang 365fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 366fcd2f4bfSAmy Zhang fmt.sign = false; 367fcd2f4bfSAmy Zhang 368bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 369fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 370fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 371fcd2f4bfSAmy Zhang return false; 372fcd2f4bfSAmy Zhang } 373fcd2f4bfSAmy Zhang 374bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 375fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 376fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 377fcd2f4bfSAmy Zhang return false; 378fcd2f4bfSAmy Zhang } 379fcd2f4bfSAmy Zhang 3804d06ccd0SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 3814d06ccd0SHarry Wentland &arr_points[1].custom_float_slope)) { 382fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 383fcd2f4bfSAmy Zhang return false; 384fcd2f4bfSAmy Zhang } 385fcd2f4bfSAmy Zhang 386fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 387fcd2f4bfSAmy Zhang fmt.sign = true; 388fcd2f4bfSAmy Zhang 389fcd2f4bfSAmy Zhang while (i != hw_points_num) { 390bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->red, &fmt, 391fcd2f4bfSAmy Zhang &rgb->red_reg)) { 392fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 393fcd2f4bfSAmy Zhang return false; 394fcd2f4bfSAmy Zhang } 395fcd2f4bfSAmy Zhang 396bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->green, &fmt, 397fcd2f4bfSAmy Zhang &rgb->green_reg)) { 398fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 399fcd2f4bfSAmy Zhang return false; 400fcd2f4bfSAmy Zhang } 401fcd2f4bfSAmy Zhang 402bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->blue, &fmt, 403fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 404fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 405fcd2f4bfSAmy Zhang return false; 406fcd2f4bfSAmy Zhang } 407fcd2f4bfSAmy Zhang 408bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 409fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 410fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 411fcd2f4bfSAmy Zhang return false; 412fcd2f4bfSAmy Zhang } 413fcd2f4bfSAmy Zhang 414bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 415fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 416fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 417fcd2f4bfSAmy Zhang return false; 418fcd2f4bfSAmy Zhang } 419fcd2f4bfSAmy Zhang 420bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 421fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 422fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 423fcd2f4bfSAmy Zhang return false; 424fcd2f4bfSAmy Zhang } 425fcd2f4bfSAmy Zhang 426fcd2f4bfSAmy Zhang ++rgb; 427fcd2f4bfSAmy Zhang ++i; 428fcd2f4bfSAmy Zhang } 429fcd2f4bfSAmy Zhang 430fcd2f4bfSAmy Zhang return true; 431fcd2f4bfSAmy Zhang } 432fcd2f4bfSAmy Zhang 43308616da5SLeo (Sunpeng) Li #define MAX_LOW_POINT 25 4348f8372c7SKrunoslav Kovac #define NUMBER_REGIONS 16 4358f8372c7SKrunoslav Kovac #define NUMBER_SW_SEGMENTS 16 4368f8372c7SKrunoslav Kovac 437b310b081SHarry Wentland static bool 438b310b081SHarry Wentland dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 439b310b081SHarry Wentland struct pwl_params *regamma_params) 440fcd2f4bfSAmy Zhang { 44123ae4f8eSAmy Zhang struct curve_points *arr_points; 44223ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 44323ae4f8eSAmy Zhang struct pwl_result_data *rgb; 44423ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 445fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 446fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 447fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 448fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 449fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 450fcd2f4bfSAmy Zhang 4518f8372c7SKrunoslav Kovac int32_t region_start, region_end; 4528f8372c7SKrunoslav Kovac uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 45323ae4f8eSAmy Zhang 454b310b081SHarry Wentland if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 45523ae4f8eSAmy Zhang return false; 45623ae4f8eSAmy Zhang 45723ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 45823ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 45923ae4f8eSAmy Zhang hw_points = 0; 460fcd2f4bfSAmy Zhang 461fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 462fcd2f4bfSAmy Zhang 463fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 464534db198SAmy Zhang /* 16 segments 465fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 466fcd2f4bfSAmy Zhang */ 46708616da5SLeo (Sunpeng) Li region_start = -11; 46808616da5SLeo (Sunpeng) Li region_end = region_start + NUMBER_REGIONS; 469fcd2f4bfSAmy Zhang 4708f8372c7SKrunoslav Kovac for (i = 0; i < NUMBER_REGIONS; i++) 4718f8372c7SKrunoslav Kovac seg_distr[i] = 4; 472534db198SAmy Zhang 473fcd2f4bfSAmy Zhang } else { 474534db198SAmy Zhang /* 10 segments 475fc6de1c5SLeo (Sunpeng) Li * segment is from 2^-10 to 2^1 476fc6de1c5SLeo (Sunpeng) Li * We include an extra segment for range [2^0, 2^1). This is to 477fc6de1c5SLeo (Sunpeng) Li * ensure that colors with normalized values of 1 don't miss the 478fc6de1c5SLeo (Sunpeng) Li * LUT. 479fcd2f4bfSAmy Zhang */ 4808f8372c7SKrunoslav Kovac region_start = -10; 481fc6de1c5SLeo (Sunpeng) Li region_end = 1; 482534db198SAmy Zhang 4838f8372c7SKrunoslav Kovac seg_distr[0] = 4; 484534db198SAmy Zhang seg_distr[1] = 4; 485534db198SAmy Zhang seg_distr[2] = 4; 486534db198SAmy Zhang seg_distr[3] = 4; 487534db198SAmy Zhang seg_distr[4] = 4; 488534db198SAmy Zhang seg_distr[5] = 4; 489534db198SAmy Zhang seg_distr[6] = 4; 490534db198SAmy Zhang seg_distr[7] = 4; 4918f8372c7SKrunoslav Kovac seg_distr[8] = 4; 4928f8372c7SKrunoslav Kovac seg_distr[9] = 4; 493fc6de1c5SLeo (Sunpeng) Li seg_distr[10] = 0; 494534db198SAmy Zhang seg_distr[11] = -1; 495534db198SAmy Zhang seg_distr[12] = -1; 496534db198SAmy Zhang seg_distr[13] = -1; 497534db198SAmy Zhang seg_distr[14] = -1; 498534db198SAmy Zhang seg_distr[15] = -1; 499fcd2f4bfSAmy Zhang } 500fcd2f4bfSAmy Zhang 501534db198SAmy Zhang for (k = 0; k < 16; k++) { 502534db198SAmy Zhang if (seg_distr[k] != -1) 503534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 504534db198SAmy Zhang } 505534db198SAmy Zhang 506fcd2f4bfSAmy Zhang j = 0; 5078f8372c7SKrunoslav Kovac for (k = 0; k < (region_end - region_start); k++) { 508ec47734aSLeo (Sunpeng) Li increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 5098f8372c7SKrunoslav Kovac start_index = (region_start + k + MAX_LOW_POINT) * 5108f8372c7SKrunoslav Kovac NUMBER_SW_SEGMENTS; 5118f8372c7SKrunoslav Kovac for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 5128f8372c7SKrunoslav Kovac i += increment) { 513534db198SAmy Zhang if (j == hw_points - 1) 514fcd2f4bfSAmy Zhang break; 515fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 516fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 517fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 518fcd2f4bfSAmy Zhang j++; 519fcd2f4bfSAmy Zhang } 520534db198SAmy Zhang } 521534db198SAmy Zhang 522534db198SAmy Zhang /* last point */ 5238f8372c7SKrunoslav Kovac start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 524b310b081SHarry Wentland rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 525b310b081SHarry Wentland rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 526b310b081SHarry Wentland rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 527fcd2f4bfSAmy Zhang 528eb0e5154SDmytro Laktyushkin arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 529eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_start)); 530eb0e5154SDmytro Laktyushkin arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 531eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_end)); 532fcd2f4bfSAmy Zhang 533fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 534fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 535fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 536fcd2f4bfSAmy Zhang 537eb0e5154SDmytro Laktyushkin y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 538fcd2f4bfSAmy Zhang 539fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 540eb0e5154SDmytro Laktyushkin arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 541fcd2f4bfSAmy Zhang arr_points[0].x); 542fcd2f4bfSAmy Zhang 543fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 544fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 545fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 546fcd2f4bfSAmy Zhang 547fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 548fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 549fcd2f4bfSAmy Zhang */ 550eb0e5154SDmytro Laktyushkin y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 551fcd2f4bfSAmy Zhang 552fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 553fcd2f4bfSAmy Zhang 554eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_zero; 555fcd2f4bfSAmy Zhang 556fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 557fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 558fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 559fcd2f4bfSAmy Zhang */ 560eb0e5154SDmytro Laktyushkin const struct fixed31_32 end_value = dc_fixpt_from_int(125); 561fcd2f4bfSAmy Zhang 562eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_div( 563eb0e5154SDmytro Laktyushkin dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 564eb0e5154SDmytro Laktyushkin dc_fixpt_sub(end_value, arr_points[1].x)); 565fcd2f4bfSAmy Zhang } 566fcd2f4bfSAmy Zhang 567fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 568fcd2f4bfSAmy Zhang 56969133b89SAric Cyr k = 0; 57069133b89SAric Cyr for (i = 1; i < 16; i++) { 571534db198SAmy Zhang if (seg_distr[k] != -1) { 572b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 573534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 574b310b081SHarry Wentland regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 575fcd2f4bfSAmy Zhang } 57669133b89SAric Cyr k++; 577534db198SAmy Zhang } 578534db198SAmy Zhang 579534db198SAmy Zhang if (seg_distr[k] != -1) 580b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 581fcd2f4bfSAmy Zhang 58223ae4f8eSAmy Zhang rgb = rgb_resulted; 58323ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 584fcd2f4bfSAmy Zhang 585fcd2f4bfSAmy Zhang i = 1; 586fcd2f4bfSAmy Zhang 587fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 588eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 589fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 590eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 591fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 592eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 593fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 594fcd2f4bfSAmy Zhang 595eb0e5154SDmytro Laktyushkin rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 596eb0e5154SDmytro Laktyushkin rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 597eb0e5154SDmytro Laktyushkin rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 598fcd2f4bfSAmy Zhang 599fcd2f4bfSAmy Zhang ++rgb_plus_1; 600fcd2f4bfSAmy Zhang ++rgb; 601fcd2f4bfSAmy Zhang ++i; 602fcd2f4bfSAmy Zhang } 603fcd2f4bfSAmy Zhang 604fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 605fcd2f4bfSAmy Zhang 606fcd2f4bfSAmy Zhang return true; 607fcd2f4bfSAmy Zhang } 608fcd2f4bfSAmy Zhang 609a6114e85SHarry Wentland static bool 61078c77382SAnthony Koo dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 6110971c40eSHarry Wentland const struct dc_stream_state *stream) 61290e508baSAnthony Koo { 61386a66c4eSHarry Wentland struct transform *xfm = pipe_ctx->plane_res.xfm; 6144562236bSHarry Wentland 6157a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, true); 6167a09f5beSYue Hin Lau xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 6174562236bSHarry Wentland 6184fa086b9SLeo (Sunpeng) Li if (stream->out_transfer_func && 619efd52204SHarry Wentland stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 620efd52204SHarry Wentland stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 6217a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 622efd52204SHarry Wentland } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 623efd52204SHarry Wentland &xfm->regamma_params)) { 6247a09f5beSYue Hin Lau xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 6257a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 6264562236bSHarry Wentland } else { 6277a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 6284562236bSHarry Wentland } 6294562236bSHarry Wentland 6307a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, false); 6314562236bSHarry Wentland 632cc0cb445SLeon Elazar return true; 6334562236bSHarry Wentland } 6344562236bSHarry Wentland 6354562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6364562236bSHarry Wentland { 63702553f57SEric Bernstein bool is_hdmi_tmds; 6386f0db2dcSKrunoslav Kovac bool is_dp; 6396f0db2dcSKrunoslav Kovac 64086e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 64186e2e1beSHersen Wu 6428e9c4c8cSHarry Wentland if (pipe_ctx->stream_res.stream_enc == NULL) 64386e2e1beSHersen Wu return; /* this is not root pipe */ 64486e2e1beSHersen Wu 64502553f57SEric Bernstein is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 6466f0db2dcSKrunoslav Kovac is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 6476f0db2dcSKrunoslav Kovac 64802553f57SEric Bernstein if (!is_hdmi_tmds && !is_dp) 6496f0db2dcSKrunoslav Kovac return; 6506f0db2dcSKrunoslav Kovac 65102553f57SEric Bernstein if (is_hdmi_tmds) 6528e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 6538e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 65496c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6556f0db2dcSKrunoslav Kovac else 6568e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 6578e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 65896c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6594562236bSHarry Wentland } 6604562236bSHarry Wentland 6614562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6624562236bSHarry Wentland { 6634562236bSHarry Wentland enum dc_lane_count lane_count = 664ceb3dbb4SJun Lei pipe_ctx->stream->link->cur_link_settings.lane_count; 6654fa086b9SLeo (Sunpeng) Li struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 666ceb3dbb4SJun Lei struct dc_link *link = pipe_ctx->stream->link; 667f42ea55bSAnthony Koo const struct dc *dc = link->dc; 668f215a57dSEric Yang 6694562236bSHarry Wentland uint32_t active_total_with_borders; 6704562236bSHarry Wentland uint32_t early_control = 0; 6716b670fa9SHarry Wentland struct timing_generator *tg = pipe_ctx->stream_res.tg; 6724562236bSHarry Wentland 673f215a57dSEric Yang /* For MST, there are multiply stream go to only one link. 674f215a57dSEric Yang * connect DIG back_end to front_end while enable_stream and 675f215a57dSEric Yang * disconnect them during disable_stream 676f215a57dSEric Yang * BY this, it is logic clean to separate stream and link */ 677f215a57dSEric Yang link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 678f215a57dSEric Yang pipe_ctx->stream_res.stream_enc->id, true); 679f215a57dSEric Yang 680f42ea55bSAnthony Koo dc->hwss.update_info_frame(pipe_ctx); 681f215a57dSEric Yang 6824562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 6834562236bSHarry Wentland active_total_with_borders = 6844562236bSHarry Wentland timing->h_addressable 6854562236bSHarry Wentland + timing->h_border_left 6864562236bSHarry Wentland + timing->h_border_right; 6874562236bSHarry Wentland 6884562236bSHarry Wentland if (lane_count != 0) 6894562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 6904562236bSHarry Wentland 6914562236bSHarry Wentland if (early_control == 0) 6924562236bSHarry Wentland early_control = lane_count; 6934562236bSHarry Wentland 6944562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 6954562236bSHarry Wentland 6964562236bSHarry Wentland /* enable audio only within mode set */ 697afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 6984562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6998e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 7004562236bSHarry Wentland } 7014562236bSHarry Wentland 702f215a57dSEric Yang 703f215a57dSEric Yang 7044562236bSHarry Wentland 7054562236bSHarry Wentland } 7064562236bSHarry Wentland 7075eefbc40SYue Hin Lau static enum bp_result link_transmitter_control( 70887401969SAndrew Jiang struct dc_bios *bios, 7095eefbc40SYue Hin Lau struct bp_transmitter_control *cntl) 7105eefbc40SYue Hin Lau { 7115eefbc40SYue Hin Lau enum bp_result result; 7125eefbc40SYue Hin Lau 71387401969SAndrew Jiang result = bios->funcs->transmitter_control(bios, cntl); 7145eefbc40SYue Hin Lau 7155eefbc40SYue Hin Lau return result; 7165eefbc40SYue Hin Lau } 7175eefbc40SYue Hin Lau 71887401969SAndrew Jiang /* 71987401969SAndrew Jiang * @brief 72087401969SAndrew Jiang * eDP only. 72187401969SAndrew Jiang */ 7228a31820bSMartin Leung void dce110_edp_wait_for_hpd_ready( 723069d418fSAndrew Jiang struct dc_link *link, 72487401969SAndrew Jiang bool power_up) 72587401969SAndrew Jiang { 726069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 727069d418fSAndrew Jiang struct graphics_object_id connector = link->link_enc->connector; 72887401969SAndrew Jiang struct gpio *hpd; 7296798d042SLewis Huang struct dc_sink *sink = link->local_sink; 73087401969SAndrew Jiang bool edp_hpd_high = false; 73187401969SAndrew Jiang uint32_t time_elapsed = 0; 73287401969SAndrew Jiang uint32_t timeout = power_up ? 73387401969SAndrew Jiang PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 73487401969SAndrew Jiang 73587401969SAndrew Jiang if (dal_graphics_object_id_get_connector_id(connector) 73687401969SAndrew Jiang != CONNECTOR_ID_EDP) { 73787401969SAndrew Jiang BREAK_TO_DEBUGGER(); 73887401969SAndrew Jiang return; 73987401969SAndrew Jiang } 74087401969SAndrew Jiang 74187401969SAndrew Jiang if (!power_up) 74287401969SAndrew Jiang /* 74387401969SAndrew Jiang * From KV, we will not HPD low after turning off VCC - 74487401969SAndrew Jiang * instead, we will check the SW timer in power_up(). 74587401969SAndrew Jiang */ 74687401969SAndrew Jiang return; 74787401969SAndrew Jiang 74887401969SAndrew Jiang /* 74987401969SAndrew Jiang * When we power on/off the eDP panel, 75087401969SAndrew Jiang * we need to wait until SENSE bit is high/low. 75187401969SAndrew Jiang */ 75287401969SAndrew Jiang 75387401969SAndrew Jiang /* obtain HPD */ 75487401969SAndrew Jiang /* TODO what to do with this? */ 75587401969SAndrew Jiang hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 75687401969SAndrew Jiang 75787401969SAndrew Jiang if (!hpd) { 75887401969SAndrew Jiang BREAK_TO_DEBUGGER(); 75987401969SAndrew Jiang return; 76087401969SAndrew Jiang } 76187401969SAndrew Jiang 7626798d042SLewis Huang if (sink != NULL) { 7636798d042SLewis Huang if (sink->edid_caps.panel_patch.extra_t3_ms > 0) { 7646798d042SLewis Huang int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms; 7656798d042SLewis Huang 7666798d042SLewis Huang msleep(extra_t3_in_ms); 7676798d042SLewis Huang } 7686798d042SLewis Huang } 7696798d042SLewis Huang 77087401969SAndrew Jiang dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 77187401969SAndrew Jiang 77287401969SAndrew Jiang /* wait until timeout or panel detected */ 77387401969SAndrew Jiang 77487401969SAndrew Jiang do { 77587401969SAndrew Jiang uint32_t detected = 0; 77687401969SAndrew Jiang 77787401969SAndrew Jiang dal_gpio_get_value(hpd, &detected); 77887401969SAndrew Jiang 77987401969SAndrew Jiang if (!(detected ^ power_up)) { 78087401969SAndrew Jiang edp_hpd_high = true; 78187401969SAndrew Jiang break; 78287401969SAndrew Jiang } 78387401969SAndrew Jiang 78487401969SAndrew Jiang msleep(HPD_CHECK_INTERVAL); 78587401969SAndrew Jiang 78687401969SAndrew Jiang time_elapsed += HPD_CHECK_INTERVAL; 78787401969SAndrew Jiang } while (time_elapsed < timeout); 78887401969SAndrew Jiang 78987401969SAndrew Jiang dal_gpio_close(hpd); 79087401969SAndrew Jiang 79187401969SAndrew Jiang dal_gpio_destroy_irq(&hpd); 79287401969SAndrew Jiang 79387401969SAndrew Jiang if (false == edp_hpd_high) { 7941296423bSBhawanpreet Lakha DC_LOG_ERROR( 79587401969SAndrew Jiang "%s: wait timed out!\n", __func__); 79687401969SAndrew Jiang } 79787401969SAndrew Jiang } 79887401969SAndrew Jiang 7998a31820bSMartin Leung void dce110_edp_power_control( 800069d418fSAndrew Jiang struct dc_link *link, 80187401969SAndrew Jiang bool power_up) 80287401969SAndrew Jiang { 803069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 80487401969SAndrew Jiang struct bp_transmitter_control cntl = { 0 }; 80587401969SAndrew Jiang enum bp_result bp_result; 80606ddcee4SJake Wang uint8_t panel_instance; 80787401969SAndrew Jiang 80887401969SAndrew Jiang 809069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 81087401969SAndrew Jiang != CONNECTOR_ID_EDP) { 81187401969SAndrew Jiang BREAK_TO_DEBUGGER(); 81287401969SAndrew Jiang return; 81387401969SAndrew Jiang } 81487401969SAndrew Jiang 815ffadb9d6SAnthony Koo if (!link->panel_cntl) 816904fb6e0SAnthony Koo return; 817d4caa72eSAnthony Koo if (power_up != 818d4caa72eSAnthony Koo link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 819172c9b77SAshley Thomas 82078d5d04dSCharlene Liu unsigned long long current_ts = dm_get_timestamp(ctx); 821172c9b77SAshley Thomas unsigned long long time_since_edp_poweroff_ms = 82293ed1814SHugo Hu div64_u64(dm_get_elapse_time_in_ns( 82378d5d04dSCharlene Liu ctx, 82478d5d04dSCharlene Liu current_ts, 82593ed1814SHugo Hu link->link_trace.time_stamp.edp_poweroff), 1000000); 826172c9b77SAshley Thomas unsigned long long time_since_edp_poweron_ms = 827172c9b77SAshley Thomas div64_u64(dm_get_elapse_time_in_ns( 828172c9b77SAshley Thomas ctx, 829172c9b77SAshley Thomas current_ts, 830172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron), 1000000); 831172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 832172c9b77SAshley Thomas "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 833172c9b77SAshley Thomas __func__, 834172c9b77SAshley Thomas power_up, 835172c9b77SAshley Thomas current_ts, 836172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 837172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron, 838172c9b77SAshley Thomas time_since_edp_poweroff_ms, 839172c9b77SAshley Thomas time_since_edp_poweron_ms); 84078d5d04dSCharlene Liu 841172c9b77SAshley Thomas /* Send VBIOS command to prompt eDP panel power */ 842172c9b77SAshley Thomas if (power_up) { 843172c9b77SAshley Thomas /* edp requires a min of 500ms from LCDVDD off to on */ 844172c9b77SAshley Thomas unsigned long long remaining_min_edp_poweroff_time_ms = 500; 845ff587987SHugo Hu 846172c9b77SAshley Thomas /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 8476c4fff06SYue Hin Lau if (link->local_sink != NULL) 848172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms += 849172c9b77SAshley Thomas link->local_sink->edid_caps.panel_patch.extra_t12_ms; 85078d5d04dSCharlene Liu 851172c9b77SAshley Thomas /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 852172c9b77SAshley Thomas if (link->link_trace.time_stamp.edp_poweroff != 0) { 853172c9b77SAshley Thomas if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 854172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 855172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 856172c9b77SAshley Thomas else 857172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 0; 85878d5d04dSCharlene Liu } 85978d5d04dSCharlene Liu 860172c9b77SAshley Thomas if (remaining_min_edp_poweroff_time_ms) { 861172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 862172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 863172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 864172c9b77SAshley Thomas msleep(remaining_min_edp_poweroff_time_ms); 865172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 866172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 867172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 868172c9b77SAshley Thomas dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 869172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 870172c9b77SAshley Thomas } else { 871172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 872172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 873172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 874172c9b77SAshley Thomas } 87578d5d04dSCharlene Liu } 87687401969SAndrew Jiang 8771296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 878172c9b77SAshley Thomas "%s: BEGIN: Panel Power action: %s\n", 87987401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 88087401969SAndrew Jiang 88187401969SAndrew Jiang cntl.action = power_up ? 88287401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_ON : 88387401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_OFF; 884069d418fSAndrew Jiang cntl.transmitter = link->link_enc->transmitter; 885069d418fSAndrew Jiang cntl.connector_obj_id = link->link_enc->connector; 88687401969SAndrew Jiang cntl.coherent = false; 88787401969SAndrew Jiang cntl.lanes_number = LANE_COUNT_FOUR; 888069d418fSAndrew Jiang cntl.hpd_sel = link->link_enc->hpd_source; 88906ddcee4SJake Wang panel_instance = link->panel_cntl->inst; 8908a0e210cSChris Park 8918a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 8928a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 8938a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) 8948a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 89506ddcee4SJake Wang LVTMA_CONTROL_POWER_ON, 89606ddcee4SJake Wang panel_instance); 8978a0e210cSChris Park else 8988a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 89906ddcee4SJake Wang LVTMA_CONTROL_POWER_OFF, 90006ddcee4SJake Wang panel_instance); 9018a0e210cSChris Park } 9028a0e210cSChris Park 90387401969SAndrew Jiang bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 90487401969SAndrew Jiang 905172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 906172c9b77SAshley Thomas "%s: END: Panel Power action: %s bp_result=%u\n", 907172c9b77SAshley Thomas __func__, (power_up ? "On":"Off"), 908172c9b77SAshley Thomas bp_result); 909172c9b77SAshley Thomas 91078d5d04dSCharlene Liu if (!power_up) 91178d5d04dSCharlene Liu /*save driver power off time stamp*/ 91278d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 91378d5d04dSCharlene Liu else 91478d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 91578d5d04dSCharlene Liu 916172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 917172c9b77SAshley Thomas "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 918172c9b77SAshley Thomas __func__, 919172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 920172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron); 921172c9b77SAshley Thomas 92287401969SAndrew Jiang if (bp_result != BP_RESULT_OK) 9231296423bSBhawanpreet Lakha DC_LOG_ERROR( 92487401969SAndrew Jiang "%s: Panel Power bp_result: %d\n", 92587401969SAndrew Jiang __func__, bp_result); 92687401969SAndrew Jiang } else { 9271296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 92887401969SAndrew Jiang "%s: Skipping Panel Power action: %s\n", 92987401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 93087401969SAndrew Jiang } 93187401969SAndrew Jiang } 9325eefbc40SYue Hin Lau 933cf3a2627SJun Lei void dce110_edp_wait_for_T12( 934cf3a2627SJun Lei struct dc_link *link) 935cf3a2627SJun Lei { 936cf3a2627SJun Lei struct dc_context *ctx = link->ctx; 937cf3a2627SJun Lei 938cf3a2627SJun Lei if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 939cf3a2627SJun Lei != CONNECTOR_ID_EDP) { 940cf3a2627SJun Lei BREAK_TO_DEBUGGER(); 941cf3a2627SJun Lei return; 942cf3a2627SJun Lei } 943cf3a2627SJun Lei 944cf3a2627SJun Lei if (!link->panel_cntl) 945cf3a2627SJun Lei return; 946cf3a2627SJun Lei 947cf3a2627SJun Lei if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 948cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff != 0) { 949cf3a2627SJun Lei unsigned int t12_duration = 500; // Default T12 as per spec 950cf3a2627SJun Lei unsigned long long current_ts = dm_get_timestamp(ctx); 951cf3a2627SJun Lei unsigned long long time_since_edp_poweroff_ms = 952cf3a2627SJun Lei div64_u64(dm_get_elapse_time_in_ns( 953cf3a2627SJun Lei ctx, 954cf3a2627SJun Lei current_ts, 955cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff), 1000000); 956cf3a2627SJun Lei 957cf3a2627SJun Lei t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12 958cf3a2627SJun Lei 959cf3a2627SJun Lei if (time_since_edp_poweroff_ms < t12_duration) 960cf3a2627SJun Lei msleep(t12_duration - time_since_edp_poweroff_ms); 961cf3a2627SJun Lei } 962cf3a2627SJun Lei } 963cf3a2627SJun Lei 9645eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 9655eefbc40SYue Hin Lau /* 9665eefbc40SYue Hin Lau * @brief 9675eefbc40SYue Hin Lau * eDP only. Control the backlight of the eDP panel 9685eefbc40SYue Hin Lau */ 9698a31820bSMartin Leung void dce110_edp_backlight_control( 9705eefbc40SYue Hin Lau struct dc_link *link, 9715eefbc40SYue Hin Lau bool enable) 9725eefbc40SYue Hin Lau { 973069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 9745eefbc40SYue Hin Lau struct bp_transmitter_control cntl = { 0 }; 97506ddcee4SJake Wang uint8_t panel_instance; 9765eefbc40SYue Hin Lau 977069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 9785eefbc40SYue Hin Lau != CONNECTOR_ID_EDP) { 9795eefbc40SYue Hin Lau BREAK_TO_DEBUGGER(); 9805eefbc40SYue Hin Lau return; 9815eefbc40SYue Hin Lau } 9825eefbc40SYue Hin Lau 983014427adSSherry if (link->panel_cntl) { 984014427adSSherry bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 985014427adSSherry 986014427adSSherry if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 9871296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 988014427adSSherry "%s: panel already powered up/off. Do nothing.\n", 9895eefbc40SYue Hin Lau __func__); 9905eefbc40SYue Hin Lau return; 9915eefbc40SYue Hin Lau } 992014427adSSherry } 9935eefbc40SYue Hin Lau 9945eefbc40SYue Hin Lau /* Send VBIOS command to control eDP panel backlight */ 9955eefbc40SYue Hin Lau 9961296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 9975eefbc40SYue Hin Lau "%s: backlight action: %s\n", 9985eefbc40SYue Hin Lau __func__, (enable ? "On":"Off")); 9995eefbc40SYue Hin Lau 10005eefbc40SYue Hin Lau cntl.action = enable ? 10015eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_ON : 10025eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_OFF; 100387401969SAndrew Jiang 10045eefbc40SYue Hin Lau /*cntl.engine_id = ctx->engine;*/ 10055eefbc40SYue Hin Lau cntl.transmitter = link->link_enc->transmitter; 10065eefbc40SYue Hin Lau cntl.connector_obj_id = link->link_enc->connector; 10075eefbc40SYue Hin Lau /*todo: unhardcode*/ 10085eefbc40SYue Hin Lau cntl.lanes_number = LANE_COUNT_FOUR; 10095eefbc40SYue Hin Lau cntl.hpd_sel = link->link_enc->hpd_source; 1010cf1835f0SCharlene Liu cntl.signal = SIGNAL_TYPE_EDP; 10115eefbc40SYue Hin Lau 10125eefbc40SYue Hin Lau /* For eDP, the following delays might need to be considered 10135eefbc40SYue Hin Lau * after link training completed: 10145eefbc40SYue Hin Lau * idle period - min. accounts for required BS-Idle pattern, 10155eefbc40SYue Hin Lau * max. allows for source frame synchronization); 10165eefbc40SYue Hin Lau * 50 msec max. delay from valid video data from source 10175eefbc40SYue Hin Lau * to video on dislpay or backlight enable. 10185eefbc40SYue Hin Lau * 10195eefbc40SYue Hin Lau * Disable the delay for now. 10205eefbc40SYue Hin Lau * Enable it in the future if necessary. 10215eefbc40SYue Hin Lau */ 10225eefbc40SYue Hin Lau /* dc_service_sleep_in_milliseconds(50); */ 10235180d4a4SCharlene Liu /*edp 1.2*/ 102406ddcee4SJake Wang panel_instance = link->panel_cntl->inst; 1025a5148245SZhan Liu 1026a5148245SZhan Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { 1027a5148245SZhan Liu if (!link->dc->config.edp_no_power_sequencing) 1028a5148245SZhan Liu /* 1029a5148245SZhan Liu * Sometimes, DP receiver chip power-controlled externally by an 1030a5148245SZhan Liu * Embedded Controller could be treated and used as eDP, 1031a5148245SZhan Liu * if it drives mobile display. In this case, 1032a5148245SZhan Liu * we shouldn't be doing power-sequencing, hence we can skip 1033a5148245SZhan Liu * waiting for T7-ready. 1034a5148245SZhan Liu */ 10355180d4a4SCharlene Liu edp_receiver_ready_T7(link); 1036a5148245SZhan Liu else 1037a5148245SZhan Liu DC_LOG_DC("edp_receiver_ready_T7 skipped\n"); 1038a5148245SZhan Liu } 10398a0e210cSChris Park 10408a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 10418a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 10428a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 10438a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 104406ddcee4SJake Wang LVTMA_CONTROL_LCD_BLON, 104506ddcee4SJake Wang panel_instance); 10468a0e210cSChris Park else 10478a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 104806ddcee4SJake Wang LVTMA_CONTROL_LCD_BLOFF, 104906ddcee4SJake Wang panel_instance); 10508a0e210cSChris Park } 10518a0e210cSChris Park 1052069d418fSAndrew Jiang link_transmitter_control(ctx->dc_bios, &cntl); 105396577cf8SHersen Wu 105496577cf8SHersen Wu if (enable && link->dpcd_sink_ext_caps.bits.oled) 105596577cf8SHersen Wu msleep(OLED_POST_T7_DELAY); 105696577cf8SHersen Wu 105796577cf8SHersen Wu if (link->dpcd_sink_ext_caps.bits.oled || 105896577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 105996577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 106096577cf8SHersen Wu dc_link_backlight_enable_aux(link, enable); 106196577cf8SHersen Wu 106269b9723aSCharlene Liu /*edp 1.2*/ 1063a5148245SZhan Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) { 1064a5148245SZhan Liu if (!link->dc->config.edp_no_power_sequencing) 1065a5148245SZhan Liu /* 1066a5148245SZhan Liu * Sometimes, DP receiver chip power-controlled externally by an 1067a5148245SZhan Liu * Embedded Controller could be treated and used as eDP, 1068a5148245SZhan Liu * if it drives mobile display. In this case, 1069a5148245SZhan Liu * we shouldn't be doing power-sequencing, hence we can skip 1070a5148245SZhan Liu * waiting for T9-ready. 1071a5148245SZhan Liu */ 10723a372bedSHugo Hu edp_add_delay_for_T9(link); 1073a5148245SZhan Liu else 1074a5148245SZhan Liu DC_LOG_DC("edp_receiver_ready_T9 skipped\n"); 1075a5148245SZhan Liu } 107696577cf8SHersen Wu 107796577cf8SHersen Wu if (!enable && link->dpcd_sink_ext_caps.bits.oled) 107896577cf8SHersen Wu msleep(OLED_PRE_T11_DELAY); 10795eefbc40SYue Hin Lau } 10805eefbc40SYue Hin Lau 10811a05873fSAnthony Koo void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 10824562236bSHarry Wentland { 10831a05873fSAnthony Koo /* notify audio driver for audio modes of monitor */ 10842b77dcc5SAnthony Koo struct dc *dc; 10851d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 10861a05873fSAnthony Koo unsigned int i, num_audio = 1; 10871a05873fSAnthony Koo 10881d0610bcSAlvin Lee if (!pipe_ctx->stream) 10891d0610bcSAlvin Lee return; 10901d0610bcSAlvin Lee 10912b77dcc5SAnthony Koo dc = pipe_ctx->stream->ctx->dc; 10922b77dcc5SAnthony Koo clk_mgr = dc->clk_mgr; 10931d0610bcSAlvin Lee 10940a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 10950a32df9cSEryk Brol return; 10960a32df9cSEryk Brol 10971a05873fSAnthony Koo if (pipe_ctx->stream_res.audio) { 10981a05873fSAnthony Koo for (i = 0; i < MAX_PIPES; i++) { 10991a05873fSAnthony Koo /*current_state not updated yet*/ 11002b77dcc5SAnthony Koo if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 11011a05873fSAnthony Koo num_audio++; 11021a05873fSAnthony Koo } 11031a05873fSAnthony Koo 11041a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 11051a05873fSAnthony Koo 1106170a2398SSu Sung Chung if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 11071a05873fSAnthony Koo /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1108170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 11091a05873fSAnthony Koo /* un-mute audio */ 11101a05873fSAnthony Koo /* TODO: audio should be per stream rather than per link */ 1111*f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1112*f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1113*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( 1114*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc, false); 1115*f01ee019SFangzhi Zuo else 11161a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 11171a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, false); 1118*f01ee019SFangzhi Zuo #else 1119*f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 1120*f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc, false); 1121*f01ee019SFangzhi Zuo #endif 11220a32df9cSEryk Brol if (pipe_ctx->stream_res.audio) 11230a32df9cSEryk Brol pipe_ctx->stream_res.audio->enabled = true; 11241a05873fSAnthony Koo } 11251a05873fSAnthony Koo } 11261a05873fSAnthony Koo 112757430404SSu Sung Chung void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 11281a05873fSAnthony Koo { 11291d0610bcSAlvin Lee struct dc *dc; 11301d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 11311d0610bcSAlvin Lee 11321d0610bcSAlvin Lee if (!pipe_ctx || !pipe_ctx->stream) 11331d0610bcSAlvin Lee return; 11341d0610bcSAlvin Lee 11351d0610bcSAlvin Lee dc = pipe_ctx->stream->ctx->dc; 11361d0610bcSAlvin Lee clk_mgr = dc->clk_mgr; 11374562236bSHarry Wentland 11380a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 11390a32df9cSEryk Brol return; 11400a32df9cSEryk Brol 1141*f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1142*f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1143*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( 1144*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc, true); 1145*f01ee019SFangzhi Zuo else 11462b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 11472b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc, true); 1148*f01ee019SFangzhi Zuo #else 1149*f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 1150*f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc, true); 1151*f01ee019SFangzhi Zuo #endif 1152afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio) { 11533f52aa9fSNicholas Kazlauskas pipe_ctx->stream_res.audio->enabled = false; 11543f52aa9fSNicholas Kazlauskas 11554562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1156*f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1157*f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1158*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable( 1159*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1160*f01ee019SFangzhi Zuo else 11618e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 11628e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 1163*f01ee019SFangzhi Zuo #else 1164*f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 1165*f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc); 1166*f01ee019SFangzhi Zuo #endif 11674562236bSHarry Wentland else 11688e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 11698e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 117057430404SSu Sung Chung 1171170a2398SSu Sung Chung if (clk_mgr->funcs->enable_pme_wa) 1172070fe724SCharlene Liu /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1173170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 11744562236bSHarry Wentland 11754562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 11764562236bSHarry Wentland * add audio mode list change flag */ 11774562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 11784562236bSHarry Wentland * stream->stream_engine_id); 11794562236bSHarry Wentland */ 11804562236bSHarry Wentland } 11811a05873fSAnthony Koo } 11824562236bSHarry Wentland 118357430404SSu Sung Chung void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 11841a05873fSAnthony Koo { 11851a05873fSAnthony Koo struct dc_stream_state *stream = pipe_ctx->stream; 1186ceb3dbb4SJun Lei struct dc_link *link = stream->link; 11871a05873fSAnthony Koo struct dc *dc = pipe_ctx->stream->ctx->dc; 11881a05873fSAnthony Koo 1189ac42fd63SWenjing Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 11901a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 11911a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 1192ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1193ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc); 1194ac42fd63SWenjing Liu } 11951a05873fSAnthony Koo 1196*f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1197*f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) { 1198*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets( 1199*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1200*f01ee019SFangzhi Zuo } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1201*f01ee019SFangzhi Zuo #else 12021a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1203*f01ee019SFangzhi Zuo #endif 12041a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 12051a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 12061a05873fSAnthony Koo 120757430404SSu Sung Chung dc->hwss.disable_audio_stream(pipe_ctx); 1208904623eeSYongqiang Sun 1209*f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1210*f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) { 1211*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->disable( 1212*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1213*f01ee019SFangzhi Zuo setup_dp_hpo_stream(pipe_ctx, false); 1214*f01ee019SFangzhi Zuo /* TODO - DP2.0 HW: unmap stream from link encoder here */ 1215*f01ee019SFangzhi Zuo } else { 12164562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 12174562236bSHarry Wentland link->link_enc, 12188e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->id, 12194562236bSHarry Wentland false); 1220*f01ee019SFangzhi Zuo } 1221*f01ee019SFangzhi Zuo #else 1222*f01ee019SFangzhi Zuo link->link_enc->funcs->connect_dig_be_to_fe( 1223*f01ee019SFangzhi Zuo link->link_enc, 1224*f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->id, 1225*f01ee019SFangzhi Zuo false); 1226*f01ee019SFangzhi Zuo #endif 12274562236bSHarry Wentland 12284562236bSHarry Wentland } 12294562236bSHarry Wentland 12304562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 12314562236bSHarry Wentland struct dc_link_settings *link_settings) 12324562236bSHarry Wentland { 12334562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 123441b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1235ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1236f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 12374562236bSHarry Wentland 12384562236bSHarry Wentland /* only 3 items below are used by unblank */ 12397fe538a4SCharlene Liu params.timing = pipe_ctx->stream->timing; 12404562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 124141b49742SCharlene Liu 124241b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 12438e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 124441b49742SCharlene Liu 124514d6f644SYongqiang Sun if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1246f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, true); 124714d6f644SYongqiang Sun } 124841b49742SCharlene Liu } 12492c850b7bSDmytro Laktyushkin 125041b49742SCharlene Liu void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 125141b49742SCharlene Liu { 125241b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1253ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1254f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 125541b49742SCharlene Liu 1256ab892598SRoman Li if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1257f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, false); 12583ba01817SYongqiang Sun link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1259ab892598SRoman Li } 126041b49742SCharlene Liu 1261*f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1262*f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) { 1263*f01ee019SFangzhi Zuo /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1264*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank( 1265*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1266*f01ee019SFangzhi Zuo } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1267*f01ee019SFangzhi Zuo #else 1268eec3303dSAric Cyr if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1269*f01ee019SFangzhi Zuo #endif 127041b49742SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 1271eec3303dSAric Cyr 12723a372bedSHugo Hu if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1273eec3303dSAric Cyr /* 1274eec3303dSAric Cyr * After output is idle pattern some sinks need time to recognize the stream 1275eec3303dSAric Cyr * has changed or they enter protection state and hang. 1276eec3303dSAric Cyr */ 1277eec3303dSAric Cyr msleep(60); 12783a372bedSHugo Hu } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) 12793a372bedSHugo Hu edp_receiver_ready_T9(link); 1280eec3303dSAric Cyr } 1281eec3303dSAric Cyr 12824562236bSHarry Wentland } 12834562236bSHarry Wentland 128415e17335SCharlene Liu 128515e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 128615e17335SCharlene Liu { 12878e9c4c8cSHarry Wentland if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 12888e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 128915e17335SCharlene Liu } 129015e17335SCharlene Liu 12914562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 12924562236bSHarry Wentland { 12934562236bSHarry Wentland switch (crtc_id) { 12944562236bSHarry Wentland case CONTROLLER_ID_D0: 12954562236bSHarry Wentland return DTO_SOURCE_ID0; 12964562236bSHarry Wentland case CONTROLLER_ID_D1: 12974562236bSHarry Wentland return DTO_SOURCE_ID1; 12984562236bSHarry Wentland case CONTROLLER_ID_D2: 12994562236bSHarry Wentland return DTO_SOURCE_ID2; 13004562236bSHarry Wentland case CONTROLLER_ID_D3: 13014562236bSHarry Wentland return DTO_SOURCE_ID3; 13024562236bSHarry Wentland case CONTROLLER_ID_D4: 13034562236bSHarry Wentland return DTO_SOURCE_ID4; 13044562236bSHarry Wentland case CONTROLLER_ID_D5: 13054562236bSHarry Wentland return DTO_SOURCE_ID5; 13064562236bSHarry Wentland default: 13074562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 13084562236bSHarry Wentland } 13094562236bSHarry Wentland } 13104562236bSHarry Wentland 13114562236bSHarry Wentland static void build_audio_output( 1312ab8db3e1SAndrey Grodzovsky struct dc_state *state, 13134562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 13144562236bSHarry Wentland struct audio_output *audio_output) 13154562236bSHarry Wentland { 13160971c40eSHarry Wentland const struct dc_stream_state *stream = pipe_ctx->stream; 13178e9c4c8cSHarry Wentland audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 13184562236bSHarry Wentland 13194562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 13204562236bSHarry Wentland 13214562236bSHarry Wentland /* audio_crtc_info */ 13224562236bSHarry Wentland 13234562236bSHarry Wentland audio_output->crtc_info.h_total = 13244fa086b9SLeo (Sunpeng) Li stream->timing.h_total; 13254562236bSHarry Wentland 13264562236bSHarry Wentland /* 13274562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 13284562236bSHarry Wentland * need to specify actual active signal portion 13294562236bSHarry Wentland */ 13304562236bSHarry Wentland audio_output->crtc_info.h_active = 13314fa086b9SLeo (Sunpeng) Li stream->timing.h_addressable 13324fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_left 13334fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_right; 13344562236bSHarry Wentland 13354562236bSHarry Wentland audio_output->crtc_info.v_active = 13364fa086b9SLeo (Sunpeng) Li stream->timing.v_addressable 13374fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_top 13384fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_bottom; 13394562236bSHarry Wentland 13404562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 13414562236bSHarry Wentland 13424562236bSHarry Wentland audio_output->crtc_info.interlaced = 13434fa086b9SLeo (Sunpeng) Li stream->timing.flags.INTERLACE; 13444562236bSHarry Wentland 13454562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 134640fd9090SNevenko Stupar (stream->timing.pix_clk_100hz*100)/ 13474fa086b9SLeo (Sunpeng) Li (stream->timing.h_total*stream->timing.v_total); 13484562236bSHarry Wentland 13494562236bSHarry Wentland audio_output->crtc_info.color_depth = 13504fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth; 13514562236bSHarry Wentland 135240fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 135340fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 13544562236bSHarry Wentland 135540fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 135640fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 13574562236bSHarry Wentland 135887b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 13592166d9fbSCharlene Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 136040fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz == 136140fd9090SNevenko Stupar (stream->timing.pix_clk_100hz)) { 136210688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 136340fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 136440fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz/2; 136540fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 136640fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 136787b58768SCharlene Liu 136887b58768SCharlene Liu } 136987b58768SCharlene Liu } 137087b58768SCharlene Liu 1371ed476602SAhzo if (state->clk_mgr && 1372ed476602SAhzo (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1373ed476602SAhzo pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 13744562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 13750de34efcSDmytro Laktyushkin state->clk_mgr->funcs->get_dp_ref_clk_frequency( 13760de34efcSDmytro Laktyushkin state->clk_mgr); 13774562236bSHarry Wentland } 13784562236bSHarry Wentland 13794562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 13804562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 13814562236bSHarry Wentland 13824562236bSHarry Wentland audio_output->pll_info.dto_source = 13834562236bSHarry Wentland translate_to_dto_source( 1384e07f541fSYongqiang Sun pipe_ctx->stream_res.tg->inst + 1); 13854562236bSHarry Wentland 13864562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 13874562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 13884562236bSHarry Wentland 13894562236bSHarry Wentland audio_output->pll_info.ss_percentage = 13904562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 13914562236bSHarry Wentland } 13924562236bSHarry Wentland 1393fb3466a4SBhawanpreet Lakha static void program_scaler(const struct dc *dc, 13944562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 13954562236bSHarry Wentland { 13964562236bSHarry Wentland struct tg_color color = {0}; 13974562236bSHarry Wentland 1398b86a1aa3SBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC_DCN) 1399ff5ef992SAlex Deucher /* TOFPGA */ 140086a66c4eSHarry Wentland if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1401ff5ef992SAlex Deucher return; 1402ff5ef992SAlex Deucher #endif 1403ff5ef992SAlex Deucher 1404bf53769dSGloria Li if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 14054562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 14064562236bSHarry Wentland else 14074562236bSHarry Wentland color_space_to_black_color(dc, 14084fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space, 14094562236bSHarry Wentland &color); 14104562236bSHarry Wentland 141186a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 141286a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, 14136702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.depth, 14144562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 14154562236bSHarry Wentland 141612750d16SEric Yang if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 141712750d16SEric Yang /* 141812750d16SEric Yang * The way 420 is packed, 2 channels carry Y component, 1 channel 141912750d16SEric Yang * alternate between Cb and Cr, so both channels need the pixel 142012750d16SEric Yang * value for Y 142112750d16SEric Yang */ 142212750d16SEric Yang if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 142312750d16SEric Yang color.color_r_cr = color.color_g_y; 142412750d16SEric Yang 14256b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 14266b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14274562236bSHarry Wentland &color); 142812750d16SEric Yang } 14294562236bSHarry Wentland 143086a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 14316702a9acSHarry Wentland &pipe_ctx->plane_res.scl_data); 14324562236bSHarry Wentland } 14334562236bSHarry Wentland 14343158223eSEric Bernstein static enum dc_status dce110_enable_stream_timing( 14354562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1436608ac7bbSJerry Zuo struct dc_state *context, 1437fb3466a4SBhawanpreet Lakha struct dc *dc) 14384562236bSHarry Wentland { 14390971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1440608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 14414562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 14424562236bSHarry Wentland struct tg_color black_color = {0}; 14434562236bSHarry Wentland 14444562236bSHarry Wentland if (!pipe_ctx_old->stream) { 14454562236bSHarry Wentland 14464562236bSHarry Wentland /* program blank color */ 14474562236bSHarry Wentland color_space_to_black_color(dc, 14484fa086b9SLeo (Sunpeng) Li stream->output_color_space, &black_color); 14496b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank_color( 14506b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14514562236bSHarry Wentland &black_color); 14524b5e7d62SHersen Wu 14534562236bSHarry Wentland /* 14544562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 14554562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 14564562236bSHarry Wentland */ 14576b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 14584562236bSHarry Wentland 14594562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 14604562236bSHarry Wentland pipe_ctx->clock_source, 146110688217SHarry Wentland &pipe_ctx->stream_res.pix_clk_params, 14624562236bSHarry Wentland &pipe_ctx->pll_settings)) { 14634562236bSHarry Wentland BREAK_TO_DEBUGGER(); 14644562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 14654562236bSHarry Wentland } 14664562236bSHarry Wentland 14676b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->program_timing( 14686b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14694fa086b9SLeo (Sunpeng) Li &stream->timing, 1470e7e10c46SDmytro Laktyushkin 0, 1471e7e10c46SDmytro Laktyushkin 0, 1472e7e10c46SDmytro Laktyushkin 0, 1473e7e10c46SDmytro Laktyushkin 0, 1474e7e10c46SDmytro Laktyushkin pipe_ctx->stream->signal, 14754562236bSHarry Wentland true); 14764562236bSHarry Wentland } 14774562236bSHarry Wentland 14784562236bSHarry Wentland if (!pipe_ctx_old->stream) { 14796b670fa9SHarry Wentland if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 14806b670fa9SHarry Wentland pipe_ctx->stream_res.tg)) { 14814562236bSHarry Wentland BREAK_TO_DEBUGGER(); 14824562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 14834562236bSHarry Wentland } 14844562236bSHarry Wentland } 14854562236bSHarry Wentland 14864562236bSHarry Wentland return DC_OK; 14874562236bSHarry Wentland } 14884562236bSHarry Wentland 14894562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 14904562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1491608ac7bbSJerry Zuo struct dc_state *context, 1492fb3466a4SBhawanpreet Lakha struct dc *dc) 14934562236bSHarry Wentland { 14940971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 14959c0fb8d4SAnthony Koo struct drr_params params = {0}; 14969c0fb8d4SAnthony Koo unsigned int event_triggers = 0; 1497b1f6d01cSDmytro Laktyushkin struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1498f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 14994562236bSHarry Wentland 1500f42ea55bSAnthony Koo if (hws->funcs.disable_stream_gating) { 1501f42ea55bSAnthony Koo hws->funcs.disable_stream_gating(dc, pipe_ctx); 1502240d09d0SGary Kattan } 1503240d09d0SGary Kattan 15041a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 15051a05873fSAnthony Koo struct audio_output audio_output; 15061a05873fSAnthony Koo 15071a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 15081a05873fSAnthony Koo 15091a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1510*f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1511*f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1512*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( 1513*f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc, 1514*f01ee019SFangzhi Zuo pipe_ctx->stream_res.audio->inst, 1515*f01ee019SFangzhi Zuo &pipe_ctx->stream->audio_info); 1516*f01ee019SFangzhi Zuo else 15171a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 15181a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 15191a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 15201a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 1521*f01ee019SFangzhi Zuo #else 1522*f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 1523*f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc, 1524*f01ee019SFangzhi Zuo pipe_ctx->stream_res.audio->inst, 1525*f01ee019SFangzhi Zuo &pipe_ctx->stream->audio_info); 1526*f01ee019SFangzhi Zuo #endif 15271a05873fSAnthony Koo else 15281a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 15291a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 15301a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 15311a05873fSAnthony Koo &pipe_ctx->stream->audio_info, 15321a05873fSAnthony Koo &audio_output.crtc_info); 15331a05873fSAnthony Koo 15341a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_configure( 15351a05873fSAnthony Koo pipe_ctx->stream_res.audio, 15361a05873fSAnthony Koo pipe_ctx->stream->signal, 15371a05873fSAnthony Koo &audio_output.crtc_info, 15381a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 15391a05873fSAnthony Koo } 15401a05873fSAnthony Koo 1541*f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1542*f01ee019SFangzhi Zuo /* DCN3.1 FPGA Workaround 1543*f01ee019SFangzhi Zuo * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1544*f01ee019SFangzhi Zuo * To do so, move calling function enable_stream_timing to only be done AFTER calling 1545*f01ee019SFangzhi Zuo * function core_link_enable_stream 1546*f01ee019SFangzhi Zuo */ 1547*f01ee019SFangzhi Zuo if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx))) 1548*f01ee019SFangzhi Zuo #endif 15494562236bSHarry Wentland /* */ 1550d2d7885fSAnthony Koo /* Do not touch stream timing on seamless boot optimization. */ 1551d2d7885fSAnthony Koo if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1552f42ea55bSAnthony Koo hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 15534562236bSHarry Wentland 1554f42ea55bSAnthony Koo if (hws->funcs.setup_vupdate_interrupt) 1555f42ea55bSAnthony Koo hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1556a122b62dSAnthony Koo 15579c0fb8d4SAnthony Koo params.vertical_total_min = stream->adjust.v_total_min; 15589c0fb8d4SAnthony Koo params.vertical_total_max = stream->adjust.v_total_max; 15599c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_drr) 15609c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_drr( 15619c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg, ¶ms); 15629c0fb8d4SAnthony Koo 15639c0fb8d4SAnthony Koo // DRR should set trigger event to monitor surface update event 15649c0fb8d4SAnthony Koo if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 15659c0fb8d4SAnthony Koo event_triggers = 0x80; 15665b5abe95SAnthony Koo /* Event triggers and num frames initialized for DRR, but can be 15675b5abe95SAnthony Koo * later updated for PSR use. Note DRR trigger events are generated 15685b5abe95SAnthony Koo * regardless of whether num frames met. 15695b5abe95SAnthony Koo */ 15709c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 15719c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 15725b5abe95SAnthony Koo pipe_ctx->stream_res.tg, event_triggers, 2); 15739c0fb8d4SAnthony Koo 1574248cbed6SEric Bernstein if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1575d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1576d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc, 1577d2c460e7Shersen wu pipe_ctx->stream_res.tg->inst); 1578aa9c4abeSNikola Cornij 1579f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1580f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp, 1581f0c4d997SCorbin McElhanney COLOR_SPACE_YCBCR601, 1582f0c4d997SCorbin McElhanney stream->timing.display_color_depth, 1583661a8cd9SDmytro Laktyushkin stream->signal); 15844562236bSHarry Wentland 1585a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1586a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 1587181a888fSCharlene Liu &stream->bit_depth_params, 1588181a888fSCharlene Liu &stream->clamping); 1589b1f6d01cSDmytro Laktyushkin while (odm_pipe) { 15907ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 15917ed4e635SHarry Wentland odm_pipe->stream_res.opp, 15927ed4e635SHarry Wentland COLOR_SPACE_YCBCR601, 15937ed4e635SHarry Wentland stream->timing.display_color_depth, 15947ed4e635SHarry Wentland stream->signal); 15957ed4e635SHarry Wentland 15967ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_program_fmt( 15977ed4e635SHarry Wentland odm_pipe->stream_res.opp, 15987ed4e635SHarry Wentland &stream->bit_depth_params, 15997ed4e635SHarry Wentland &stream->clamping); 1600b1f6d01cSDmytro Laktyushkin odm_pipe = odm_pipe->next_odm_pipe; 16017ed4e635SHarry Wentland } 1602603767f9STony Cheng 16031e7e86c4SSamson Tam if (!stream->dpms_off) 1604ab8db3e1SAndrey Grodzovsky core_link_enable_stream(context, pipe_ctx); 16054562236bSHarry Wentland 1606*f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1607*f01ee019SFangzhi Zuo /* DCN3.1 FPGA Workaround 1608*f01ee019SFangzhi Zuo * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1609*f01ee019SFangzhi Zuo * To do so, move calling function enable_stream_timing to only be done AFTER calling 1610*f01ee019SFangzhi Zuo * function core_link_enable_stream 1611*f01ee019SFangzhi Zuo */ 1612*f01ee019SFangzhi Zuo if (hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)) { 1613*f01ee019SFangzhi Zuo if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1614*f01ee019SFangzhi Zuo hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1615*f01ee019SFangzhi Zuo } 1616*f01ee019SFangzhi Zuo #endif 1617*f01ee019SFangzhi Zuo 16186702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 16194562236bSHarry Wentland 1620d1ebfdd8SWyatt Wood pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 162194267b3dSSylvia Tsai 16224562236bSHarry Wentland return DC_OK; 16234562236bSHarry Wentland } 16244562236bSHarry Wentland 16254562236bSHarry Wentland /******************************************************************************/ 16264562236bSHarry Wentland 1627fb3466a4SBhawanpreet Lakha static void power_down_encoders(struct dc *dc) 16284562236bSHarry Wentland { 16294562236bSHarry Wentland int i; 1630b9b171ffSHersen Wu 1631b9b171ffSHersen Wu /* do not know BIOS back-front mapping, simply blank all. It will not 1632b9b171ffSHersen Wu * hurt for non-DP 1633b9b171ffSHersen Wu */ 1634b9b171ffSHersen Wu for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1635b9b171ffSHersen Wu dc->res_pool->stream_enc[i]->funcs->dp_blank( 1636b9b171ffSHersen Wu dc->res_pool->stream_enc[i]); 1637b9b171ffSHersen Wu } 1638b9b171ffSHersen Wu 16394562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 1640d4c2a96fSLewis Huang enum signal_type signal = dc->links[i]->connector_signal; 1641a0c38ebaSCharlene Liu 1642d4c2a96fSLewis Huang if ((signal == SIGNAL_TYPE_EDP) || 1643d4c2a96fSLewis Huang (signal == SIGNAL_TYPE_DISPLAY_PORT)) 1644a0c38ebaSCharlene Liu if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) 1645a0c38ebaSCharlene Liu dp_receiver_power_ctrl(dc->links[i], false); 1646a0c38ebaSCharlene Liu 16474338ffa8SSung Lee if (signal != SIGNAL_TYPE_EDP) 16484338ffa8SSung Lee signal = SIGNAL_TYPE_NONE; 16494338ffa8SSung Lee 16504562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 1651069d418fSAndrew Jiang dc->links[i]->link_enc, signal); 1652b56e90eaSPaul Hsieh 1653b56e90eaSPaul Hsieh dc->links[i]->link_status.link_active = false; 165407920450SJoshua Aberback memset(&dc->links[i]->cur_link_settings, 0, 165507920450SJoshua Aberback sizeof(dc->links[i]->cur_link_settings)); 16564562236bSHarry Wentland } 16574562236bSHarry Wentland } 16584562236bSHarry Wentland 1659fb3466a4SBhawanpreet Lakha static void power_down_controllers(struct dc *dc) 16604562236bSHarry Wentland { 16614562236bSHarry Wentland int i; 16624562236bSHarry Wentland 16637f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 16644562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 16654562236bSHarry Wentland dc->res_pool->timing_generators[i]); 16664562236bSHarry Wentland } 16674562236bSHarry Wentland } 16684562236bSHarry Wentland 1669fb3466a4SBhawanpreet Lakha static void power_down_clock_sources(struct dc *dc) 16704562236bSHarry Wentland { 16714562236bSHarry Wentland int i; 16724562236bSHarry Wentland 16734562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 16744562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 16754562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 16764562236bSHarry Wentland 16774562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 16784562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 16794562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 16804562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 16814562236bSHarry Wentland } 16824562236bSHarry Wentland } 16834562236bSHarry Wentland 1684fb3466a4SBhawanpreet Lakha static void power_down_all_hw_blocks(struct dc *dc) 16854562236bSHarry Wentland { 16864562236bSHarry Wentland power_down_encoders(dc); 16874562236bSHarry Wentland 16884562236bSHarry Wentland power_down_controllers(dc); 16894562236bSHarry Wentland 16904562236bSHarry Wentland power_down_clock_sources(dc); 16911663ae1cSBhawanpreet Lakha 16922f3bfb27SRoman Li if (dc->fbc_compressor) 16931663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 16944562236bSHarry Wentland } 16954562236bSHarry Wentland 16964562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 1697fb3466a4SBhawanpreet Lakha struct dc *dc) 16984562236bSHarry Wentland { 16994562236bSHarry Wentland int i; 17004562236bSHarry Wentland struct timing_generator *tg; 17014562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 17024562236bSHarry Wentland 17037f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 17044562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 17054562236bSHarry Wentland 17060a87425aSTony Cheng if (tg->funcs->disable_vga) 17074562236bSHarry Wentland tg->funcs->disable_vga(tg); 17087f93c1deSCharlene Liu } 17097f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->pipe_count; i++) { 17104562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 17114562236bSHarry Wentland * powergating. */ 17124562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 17134562236bSHarry Wentland true); 17144562236bSHarry Wentland 1715e6c258cbSYongqiang Sun dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 17167f914a62SYongqiang Sun dc->hwss.disable_plane(dc, 1717e6c258cbSYongqiang Sun &dc->current_state->res_ctx.pipe_ctx[i]); 17184562236bSHarry Wentland } 17194562236bSHarry Wentland } 17204562236bSHarry Wentland 17213de5aa81SSivapiriyanKumarasamy 172245a1261bSJake Wang static void get_edp_streams(struct dc_state *context, 172345a1261bSJake Wang struct dc_stream_state **edp_streams, 172445a1261bSJake Wang int *edp_stream_num) 17253de5aa81SSivapiriyanKumarasamy { 17263de5aa81SSivapiriyanKumarasamy int i; 17273de5aa81SSivapiriyanKumarasamy 172845a1261bSJake Wang *edp_stream_num = 0; 17293de5aa81SSivapiriyanKumarasamy for (i = 0; i < context->stream_count; i++) { 173045a1261bSJake Wang if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 173145a1261bSJake Wang edp_streams[*edp_stream_num] = context->streams[i]; 173245a1261bSJake Wang if (++(*edp_stream_num) == MAX_NUM_EDP) 173345a1261bSJake Wang return; 17343de5aa81SSivapiriyanKumarasamy } 173545a1261bSJake Wang } 17363de5aa81SSivapiriyanKumarasamy } 17373de5aa81SSivapiriyanKumarasamy 173845a1261bSJake Wang static void get_edp_links_with_sink( 173925292028SYongqiang Sun struct dc *dc, 174045a1261bSJake Wang struct dc_link **edp_links_with_sink, 174145a1261bSJake Wang int *edp_with_sink_num) 174225292028SYongqiang Sun { 174325292028SYongqiang Sun int i; 174425292028SYongqiang Sun 174525292028SYongqiang Sun /* check if there is an eDP panel not in use */ 174645a1261bSJake Wang *edp_with_sink_num = 0; 174725292028SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 174825292028SYongqiang Sun if (dc->links[i]->local_sink && 174925292028SYongqiang Sun dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 175045a1261bSJake Wang edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; 175145a1261bSJake Wang if (++(*edp_with_sink_num) == MAX_NUM_EDP) 175245a1261bSJake Wang return; 175325292028SYongqiang Sun } 175425292028SYongqiang Sun } 175525292028SYongqiang Sun } 175625292028SYongqiang Sun 17571c17952eSLee Jones /* 17584562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 17594562236bSHarry Wentland * 1. Power down all DC HW blocks 17604562236bSHarry Wentland * 2. Disable VGA engine on all controllers 17614562236bSHarry Wentland * 3. Enable power gating for controller 17624562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 17634562236bSHarry Wentland */ 176425292028SYongqiang Sun void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 17654562236bSHarry Wentland { 176645a1261bSJake Wang struct dc_link *edp_links_with_sink[MAX_NUM_EDP]; 176745a1261bSJake Wang struct dc_link *edp_links[MAX_NUM_EDP]; 176845a1261bSJake Wang struct dc_stream_state *edp_streams[MAX_NUM_EDP]; 176945a1261bSJake Wang struct dc_link *edp_link_with_sink = NULL; 177045a1261bSJake Wang struct dc_link *edp_link = NULL; 17713de5aa81SSivapiriyanKumarasamy struct dc_stream_state *edp_stream = NULL; 177245a1261bSJake Wang struct dce_hwseq *hws = dc->hwseq; 177345a1261bSJake Wang int edp_with_sink_num; 177445a1261bSJake Wang int edp_num; 177545a1261bSJake Wang int edp_stream_num; 177645a1261bSJake Wang int i; 1777be4b289fSSivapiriyanKumarasamy bool can_apply_edp_fast_boot = false; 1778ce72741bSAnthony Koo bool can_apply_seamless_boot = false; 17793de5aa81SSivapiriyanKumarasamy bool keep_edp_vdd_on = false; 17800eda55caSMichael Strauss DC_LOGGER_INIT(); 17810eda55caSMichael Strauss 178245a1261bSJake Wang 178345a1261bSJake Wang get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); 178445a1261bSJake Wang get_edp_links(dc, edp_links, &edp_num); 1785ce72741bSAnthony Koo 1786f42ea55bSAnthony Koo if (hws->funcs.init_pipes) 1787f42ea55bSAnthony Koo hws->funcs.init_pipes(dc, context); 1788be4b289fSSivapiriyanKumarasamy 178945a1261bSJake Wang get_edp_streams(context, edp_streams, &edp_stream_num); 17903de5aa81SSivapiriyanKumarasamy 1791be4b289fSSivapiriyanKumarasamy // Check fastboot support, disable on DCE8 because of blank screens 179245a1261bSJake Wang if (edp_num && dc->ctx->dce_version != DCE_VERSION_8_0 && 1793be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_1 && 1794be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_3) { 179545a1261bSJake Wang for (i = 0; i < edp_num; i++) { 179645a1261bSJake Wang edp_link = edp_links[i]; 1797be4b289fSSivapiriyanKumarasamy // enable fastboot if backend is enabled on eDP 1798be4b289fSSivapiriyanKumarasamy if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) { 17993de5aa81SSivapiriyanKumarasamy /* Set optimization flag on eDP stream*/ 180045a1261bSJake Wang if (edp_stream_num && edp_link->link_status.link_active) { 180145a1261bSJake Wang edp_stream = edp_streams[0]; 1802f9fc6f39SMichael Strauss can_apply_edp_fast_boot = !is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing); 1803f9fc6f39SMichael Strauss edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot; 18040eda55caSMichael Strauss if (can_apply_edp_fast_boot) 18050eda55caSMichael Strauss DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n"); 1806f9fc6f39SMichael Strauss 180745a1261bSJake Wang break; 1808be4b289fSSivapiriyanKumarasamy } 1809be4b289fSSivapiriyanKumarasamy } 181045a1261bSJake Wang } 18113de5aa81SSivapiriyanKumarasamy // We are trying to enable eDP, don't power down VDD 181245a1261bSJake Wang if (edp_stream_num) 18133de5aa81SSivapiriyanKumarasamy keep_edp_vdd_on = true; 1814be4b289fSSivapiriyanKumarasamy } 1815be4b289fSSivapiriyanKumarasamy 1816be4b289fSSivapiriyanKumarasamy // Check seamless boot support 1817ce72741bSAnthony Koo for (i = 0; i < context->stream_count; i++) { 1818ce72741bSAnthony Koo if (context->streams[i]->apply_seamless_boot_optimization) { 1819ce72741bSAnthony Koo can_apply_seamless_boot = true; 1820ce72741bSAnthony Koo break; 1821ce72741bSAnthony Koo } 1822ce72741bSAnthony Koo } 18234cac1e6dSYongqiang Sun 1824be4b289fSSivapiriyanKumarasamy /* eDP should not have stream in resume from S4 and so even with VBios post 1825be4b289fSSivapiriyanKumarasamy * it should get turned off 18262c37e49aSYongqiang Sun */ 182745a1261bSJake Wang if (edp_with_sink_num) 182845a1261bSJake Wang edp_link_with_sink = edp_links_with_sink[0]; 182945a1261bSJake Wang 1830be4b289fSSivapiriyanKumarasamy if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 18313de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) { 18324cac1e6dSYongqiang Sun /*turn off backlight before DP_blank and encoder powered down*/ 1833f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1834c5fc7f59SCharlene Liu } 1835c5fc7f59SCharlene Liu /*resume from S3, no vbios posting, no need to power down again*/ 183625292028SYongqiang Sun power_down_all_hw_blocks(dc); 18374562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 18383de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) 1839be4b289fSSivapiriyanKumarasamy dc->hwss.edp_power_control(edp_link_with_sink, false); 1840c5fc7f59SCharlene Liu } 18411c5ea40cSYao Wang1 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); 18424562236bSHarry Wentland } 18434562236bSHarry Wentland 18444562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 18454562236bSHarry Wentland struct bw_fixed blackout_duration, 18460971c40eSHarry Wentland const struct dc_stream_state *stream) 18474562236bSHarry Wentland { 18484562236bSHarry Wentland uint32_t total_dest_line_time_ns; 18494562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 18504562236bSHarry Wentland 18514562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 18524562236bSHarry Wentland 18534562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 1854380604e2SKen Chalmers (stream->timing.h_total * 10) / 1855380604e2SKen Chalmers stream->timing.pix_clk_100hz + 18564562236bSHarry Wentland pstate_blackout_duration_ns; 18574562236bSHarry Wentland 18584562236bSHarry Wentland return total_dest_line_time_ns; 18594562236bSHarry Wentland } 18604562236bSHarry Wentland 1861f774b339SEric Yang static void dce110_set_displaymarks( 1862fb3466a4SBhawanpreet Lakha const struct dc *dc, 1863608ac7bbSJerry Zuo struct dc_state *context) 18644562236bSHarry Wentland { 18654562236bSHarry Wentland uint8_t i, num_pipes; 18664562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 18674562236bSHarry Wentland 18684562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 18694562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 18704562236bSHarry Wentland uint32_t total_dest_line_time_ns; 18714562236bSHarry Wentland 18724562236bSHarry Wentland if (pipe_ctx->stream == NULL) 18734562236bSHarry Wentland continue; 18744562236bSHarry Wentland 18754562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 187677a4ea53SBhawanpreet Lakha dc->bw_vbios->blackout_duration, pipe_ctx->stream); 187786a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 187886a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1879813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1880813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1881813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1882813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 18834562236bSHarry Wentland total_dest_line_time_ns); 18844562236bSHarry Wentland if (i == underlay_idx) { 18854562236bSHarry Wentland num_pipes++; 188686a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 188786a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1888813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1889813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1890813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 18914562236bSHarry Wentland total_dest_line_time_ns); 18924562236bSHarry Wentland } 18934562236bSHarry Wentland num_pipes++; 18944562236bSHarry Wentland } 18954562236bSHarry Wentland } 18964562236bSHarry Wentland 1897fab55d61SDmytro Laktyushkin void dce110_set_safe_displaymarks( 1898a2b8659dSTony Cheng struct resource_context *res_ctx, 1899a2b8659dSTony Cheng const struct resource_pool *pool) 19004562236bSHarry Wentland { 19014562236bSHarry Wentland int i; 1902a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 19039037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 19044562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 19059037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 19064562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 19073722c794SMikita Lipski struct dce_watermarks min_marks = { 0, 0, 0, 0}; 19084562236bSHarry Wentland 19094562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 19108feabd03SYue Hin Lau if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 19114562236bSHarry Wentland continue; 19124562236bSHarry Wentland 191386a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 191486a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 19154562236bSHarry Wentland nbp_marks, 19164562236bSHarry Wentland max_marks, 19173722c794SMikita Lipski min_marks, 19184562236bSHarry Wentland max_marks, 19194562236bSHarry Wentland MAX_WATERMARK); 19208feabd03SYue Hin Lau 19214562236bSHarry Wentland if (i == underlay_idx) 192286a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 192386a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 19244562236bSHarry Wentland nbp_marks, 19254562236bSHarry Wentland max_marks, 19264562236bSHarry Wentland max_marks, 19274562236bSHarry Wentland MAX_WATERMARK); 19288feabd03SYue Hin Lau 19294562236bSHarry Wentland } 19304562236bSHarry Wentland } 19314562236bSHarry Wentland 19324562236bSHarry Wentland /******************************************************************************* 19334562236bSHarry Wentland * Public functions 19344562236bSHarry Wentland ******************************************************************************/ 19354562236bSHarry Wentland 19364562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 193749c70eceSAlvin Lee int num_pipes, struct dc_crtc_timing_adjust adjust) 19384562236bSHarry Wentland { 19394562236bSHarry Wentland int i = 0; 19404562236bSHarry Wentland struct drr_params params = {0}; 194198e6436dSAnthony Koo // DRR should set trigger event to monitor surface update event 194298e6436dSAnthony Koo unsigned int event_triggers = 0x80; 19435b5abe95SAnthony Koo // Note DRR trigger events are generated regardless of whether num frames met. 19445b5abe95SAnthony Koo unsigned int num_frames = 2; 19454562236bSHarry Wentland 194649c70eceSAlvin Lee params.vertical_total_max = adjust.v_total_max; 194749c70eceSAlvin Lee params.vertical_total_min = adjust.v_total_min; 19484562236bSHarry Wentland 19494562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 195098e6436dSAnthony Koo * some GSL stuff. Static screen triggers may be programmed differently 195198e6436dSAnthony Koo * as well. 19524562236bSHarry Wentland */ 19534562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 195498e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_drr( 195598e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, ¶ms); 195698e6436dSAnthony Koo 195749c70eceSAlvin Lee if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 195898e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 195998e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, 19605b5abe95SAnthony Koo event_triggers, num_frames); 19614562236bSHarry Wentland } 19624562236bSHarry Wentland } 19634562236bSHarry Wentland 196472ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 196572ada5f7SEric Cook int num_pipes, 196672ada5f7SEric Cook struct crtc_position *position) 196772ada5f7SEric Cook { 196872ada5f7SEric Cook int i = 0; 196972ada5f7SEric Cook 197072ada5f7SEric Cook /* TODO: handle pipes > 1 197172ada5f7SEric Cook */ 197272ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 19736b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 197472ada5f7SEric Cook } 197572ada5f7SEric Cook 19764562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 19775b5abe95SAnthony Koo int num_pipes, const struct dc_static_screen_params *params) 19784562236bSHarry Wentland { 19794562236bSHarry Wentland unsigned int i; 19805b5abe95SAnthony Koo unsigned int triggers = 0; 198194267b3dSSylvia Tsai 19825b5abe95SAnthony Koo if (params->triggers.overlay_update) 19835b5abe95SAnthony Koo triggers |= 0x100; 19845b5abe95SAnthony Koo if (params->triggers.surface_update) 19855b5abe95SAnthony Koo triggers |= 0x80; 19865b5abe95SAnthony Koo if (params->triggers.cursor_update) 19875b5abe95SAnthony Koo triggers |= 0x2; 19885b5abe95SAnthony Koo if (params->triggers.force_trigger) 19895b5abe95SAnthony Koo triggers |= 0x1; 19904562236bSHarry Wentland 1991593f79a2SAlex Deucher if (num_pipes) { 1992593f79a2SAlex Deucher struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1993593f79a2SAlex Deucher 1994593f79a2SAlex Deucher if (dc->fbc_compressor) 19955b5abe95SAnthony Koo triggers |= 0x84; 1996593f79a2SAlex Deucher } 1997c3aa1d67SBhawanpreet Lakha 19984562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 19996b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs-> 20005b5abe95SAnthony Koo set_static_screen_control(pipe_ctx[i]->stream_res.tg, 20015b5abe95SAnthony Koo triggers, params->num_frames); 20024562236bSHarry Wentland } 20034562236bSHarry Wentland 2004f6baff4dSHarry Wentland /* 2005690b5e39SRoman Li * Check if FBC can be enabled 2006690b5e39SRoman Li */ 20079c6569deSHarry Wentland static bool should_enable_fbc(struct dc *dc, 20083bc4aaa9SRoman Li struct dc_state *context, 20093bc4aaa9SRoman Li uint32_t *pipe_idx) 2010690b5e39SRoman Li { 20113bc4aaa9SRoman Li uint32_t i; 20123bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = NULL; 20133bc4aaa9SRoman Li struct resource_context *res_ctx = &context->res_ctx; 201465d38262Shersen wu unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 20153bc4aaa9SRoman Li 2016690b5e39SRoman Li 2017690b5e39SRoman Li ASSERT(dc->fbc_compressor); 2018690b5e39SRoman Li 2019690b5e39SRoman Li /* FBC memory should be allocated */ 2020690b5e39SRoman Li if (!dc->ctx->fbc_gpu_addr) 20219c6569deSHarry Wentland return false; 2022690b5e39SRoman Li 2023690b5e39SRoman Li /* Only supports single display */ 2024690b5e39SRoman Li if (context->stream_count != 1) 20259c6569deSHarry Wentland return false; 2026690b5e39SRoman Li 20273bc4aaa9SRoman Li for (i = 0; i < dc->res_pool->pipe_count; i++) { 20283bc4aaa9SRoman Li if (res_ctx->pipe_ctx[i].stream) { 202965d38262Shersen wu 20303bc4aaa9SRoman Li pipe_ctx = &res_ctx->pipe_ctx[i]; 203165d38262Shersen wu 203265d38262Shersen wu if (!pipe_ctx) 203365d38262Shersen wu continue; 203465d38262Shersen wu 203565d38262Shersen wu /* fbc not applicable on underlay pipe */ 203665d38262Shersen wu if (pipe_ctx->pipe_idx != underlay_idx) { 20373bc4aaa9SRoman Li *pipe_idx = i; 20383bc4aaa9SRoman Li break; 20393bc4aaa9SRoman Li } 20403bc4aaa9SRoman Li } 204165d38262Shersen wu } 20423bc4aaa9SRoman Li 204365d38262Shersen wu if (i == dc->res_pool->pipe_count) 204465d38262Shersen wu return false; 204565d38262Shersen wu 2046ceb3dbb4SJun Lei if (!pipe_ctx->stream->link) 204765d38262Shersen wu return false; 20487a840773SRoman Li 2049690b5e39SRoman Li /* Only supports eDP */ 2050ceb3dbb4SJun Lei if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 20519c6569deSHarry Wentland return false; 2052690b5e39SRoman Li 2053690b5e39SRoman Li /* PSR should not be enabled */ 2054d1ebfdd8SWyatt Wood if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 20559c6569deSHarry Wentland return false; 2056690b5e39SRoman Li 205793984bbcSShirish S /* Nothing to compress */ 205893984bbcSShirish S if (!pipe_ctx->plane_state) 20599c6569deSHarry Wentland return false; 206093984bbcSShirish S 206105230fa9SRoman Li /* Only for non-linear tiling */ 206205230fa9SRoman Li if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 20639c6569deSHarry Wentland return false; 206405230fa9SRoman Li 20659c6569deSHarry Wentland return true; 2066690b5e39SRoman Li } 2067690b5e39SRoman Li 2068690b5e39SRoman Li /* 2069690b5e39SRoman Li * Enable FBC 2070690b5e39SRoman Li */ 207165d38262Shersen wu static void enable_fbc( 207265d38262Shersen wu struct dc *dc, 2073608ac7bbSJerry Zuo struct dc_state *context) 2074690b5e39SRoman Li { 20753bc4aaa9SRoman Li uint32_t pipe_idx = 0; 20763bc4aaa9SRoman Li 20773bc4aaa9SRoman Li if (should_enable_fbc(dc, context, &pipe_idx)) { 2078690b5e39SRoman Li /* Program GRPH COMPRESSED ADDRESS and PITCH */ 2079690b5e39SRoman Li struct compr_addr_and_pitch_params params = {0, 0, 0}; 2080690b5e39SRoman Li struct compressor *compr = dc->fbc_compressor; 20813bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 20823bc4aaa9SRoman Li 20839c6569deSHarry Wentland params.source_view_width = pipe_ctx->stream->timing.h_addressable; 20849c6569deSHarry Wentland params.source_view_height = pipe_ctx->stream->timing.v_addressable; 208565d38262Shersen wu params.inst = pipe_ctx->stream_res.tg->inst; 2086690b5e39SRoman Li compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 2087690b5e39SRoman Li 2088690b5e39SRoman Li compr->funcs->surface_address_and_pitch(compr, ¶ms); 2089690b5e39SRoman Li compr->funcs->set_fbc_invalidation_triggers(compr, 1); 2090690b5e39SRoman Li 2091690b5e39SRoman Li compr->funcs->enable_fbc(compr, ¶ms); 2092690b5e39SRoman Li } 2093690b5e39SRoman Li } 2094690b5e39SRoman Li 209554e8695eSDmytro Laktyushkin static void dce110_reset_hw_ctx_wrap( 2096fb3466a4SBhawanpreet Lakha struct dc *dc, 2097608ac7bbSJerry Zuo struct dc_state *context) 20984562236bSHarry Wentland { 20994562236bSHarry Wentland int i; 21004562236bSHarry Wentland 21014562236bSHarry Wentland /* Reset old context */ 21024562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 2103a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 21044562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2105608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 21064562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 21074562236bSHarry Wentland 21084562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 21094562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 21104562236bSHarry Wentland * PHY when not already disabled. 21114562236bSHarry Wentland */ 21124562236bSHarry Wentland 21134562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 21144562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 21154562236bSHarry Wentland continue; 21164562236bSHarry Wentland 21174562236bSHarry Wentland if (!pipe_ctx->stream || 211854e8695eSDmytro Laktyushkin pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 211921e67d4dSHarry Wentland struct clock_source *old_clk = pipe_ctx_old->clock_source; 212021e67d4dSHarry Wentland 2121827f11e9SLeo (Sunpeng) Li /* Disable if new stream is null. O/w, if stream is 2122827f11e9SLeo (Sunpeng) Li * disabled already, no need to disable again. 2123827f11e9SLeo (Sunpeng) Li */ 212457430404SSu Sung Chung if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 212557430404SSu Sung Chung core_link_disable_stream(pipe_ctx_old); 212657430404SSu Sung Chung 212757430404SSu Sung Chung /* free acquired resources*/ 212857430404SSu Sung Chung if (pipe_ctx_old->stream_res.audio) { 212957430404SSu Sung Chung /*disable az_endpoint*/ 213057430404SSu Sung Chung pipe_ctx_old->stream_res.audio->funcs-> 213157430404SSu Sung Chung az_disable(pipe_ctx_old->stream_res.audio); 213257430404SSu Sung Chung 213357430404SSu Sung Chung /*free audio*/ 213457430404SSu Sung Chung if (dc->caps.dynamic_audio == true) { 213557430404SSu Sung Chung /*we have to dynamic arbitrate the audio endpoints*/ 213657430404SSu Sung Chung /*we free the resource, need reset is_audio_acquired*/ 213757430404SSu Sung Chung update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 213857430404SSu Sung Chung pipe_ctx_old->stream_res.audio, false); 213957430404SSu Sung Chung pipe_ctx_old->stream_res.audio = NULL; 214057430404SSu Sung Chung } 214157430404SSu Sung Chung } 214257430404SSu Sung Chung } 2143d050f8edSHersen Wu 21446b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 21456b670fa9SHarry Wentland if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 214654e8695eSDmytro Laktyushkin dm_error("DC: failed to blank crtc!\n"); 214754e8695eSDmytro Laktyushkin BREAK_TO_DEBUGGER(); 214854e8695eSDmytro Laktyushkin } 21496b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 215086a66c4eSHarry Wentland pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2151608ac7bbSJerry Zuo pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 215254e8695eSDmytro Laktyushkin 2153ad8960a6SMikita Lipski if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2154ad8960a6SMikita Lipski dc->res_pool, 2155ad8960a6SMikita Lipski old_clk)) 215621e67d4dSHarry Wentland old_clk->funcs->cs_power_down(old_clk); 215721e67d4dSHarry Wentland 21587f914a62SYongqiang Sun dc->hwss.disable_plane(dc, pipe_ctx_old); 215954e8695eSDmytro Laktyushkin 216054e8695eSDmytro Laktyushkin pipe_ctx_old->stream = NULL; 216154e8695eSDmytro Laktyushkin } 21624562236bSHarry Wentland } 21634562236bSHarry Wentland } 21644562236bSHarry Wentland 21651a05873fSAnthony Koo static void dce110_setup_audio_dto( 21661a05873fSAnthony Koo struct dc *dc, 21671a05873fSAnthony Koo struct dc_state *context) 21681a05873fSAnthony Koo { 21691a05873fSAnthony Koo int i; 21701a05873fSAnthony Koo 21711a05873fSAnthony Koo /* program audio wall clock. use HDMI as clock source if HDMI 21721a05873fSAnthony Koo * audio active. Otherwise, use DP as clock source 21731a05873fSAnthony Koo * first, loop to find any HDMI audio, if not, loop find DP audio 21741a05873fSAnthony Koo */ 21751a05873fSAnthony Koo /* Setup audio rate clock source */ 21761a05873fSAnthony Koo /* Issue: 21771a05873fSAnthony Koo * Audio lag happened on DP monitor when unplug a HDMI monitor 21781a05873fSAnthony Koo * 21791a05873fSAnthony Koo * Cause: 21801a05873fSAnthony Koo * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 21811a05873fSAnthony Koo * is set to either dto0 or dto1, audio should work fine. 21821a05873fSAnthony Koo * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 21831a05873fSAnthony Koo * set to dto0 will cause audio lag. 21841a05873fSAnthony Koo * 21851a05873fSAnthony Koo * Solution: 21861a05873fSAnthony Koo * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 21871a05873fSAnthony Koo * find first available pipe with audio, setup audio wall DTO per topology 21881a05873fSAnthony Koo * instead of per pipe. 21891a05873fSAnthony Koo */ 21901a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 21911a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 21921a05873fSAnthony Koo 21931a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 21941a05873fSAnthony Koo continue; 21951a05873fSAnthony Koo 21961a05873fSAnthony Koo if (pipe_ctx->top_pipe) 21971a05873fSAnthony Koo continue; 21981a05873fSAnthony Koo if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 21991a05873fSAnthony Koo continue; 22001a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 22011a05873fSAnthony Koo struct audio_output audio_output; 22021a05873fSAnthony Koo 22031a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 22041a05873fSAnthony Koo 22058fe44c08SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 220664b1d0e8SNicholas Kazlauskas /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */ 220764b1d0e8SNicholas Kazlauskas if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 220864b1d0e8SNicholas Kazlauskas /* disable audio DTBCLK DTO */ 220964b1d0e8SNicholas Kazlauskas dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 221064b1d0e8SNicholas Kazlauskas dc->res_pool->dccg, 0); 221164b1d0e8SNicholas Kazlauskas 22121a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 22131a05873fSAnthony Koo pipe_ctx->stream_res.audio, 22141a05873fSAnthony Koo pipe_ctx->stream->signal, 22151a05873fSAnthony Koo &audio_output.crtc_info, 22161a05873fSAnthony Koo &audio_output.pll_info); 221764b1d0e8SNicholas Kazlauskas } else 221864b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 221964b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, 222064b1d0e8SNicholas Kazlauskas pipe_ctx->stream->signal, 222164b1d0e8SNicholas Kazlauskas &audio_output.crtc_info, 222264b1d0e8SNicholas Kazlauskas &audio_output.pll_info); 222364b1d0e8SNicholas Kazlauskas #else 222464b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 222564b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, 222664b1d0e8SNicholas Kazlauskas pipe_ctx->stream->signal, 222764b1d0e8SNicholas Kazlauskas &audio_output.crtc_info, 222864b1d0e8SNicholas Kazlauskas &audio_output.pll_info); 222964b1d0e8SNicholas Kazlauskas #endif 22301a05873fSAnthony Koo break; 22311a05873fSAnthony Koo } 22321a05873fSAnthony Koo } 22331a05873fSAnthony Koo 22341a05873fSAnthony Koo /* no HDMI audio is found, try DP audio */ 22351a05873fSAnthony Koo if (i == dc->res_pool->pipe_count) { 22361a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 22371a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 22381a05873fSAnthony Koo 22391a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 22401a05873fSAnthony Koo continue; 22411a05873fSAnthony Koo 22421a05873fSAnthony Koo if (pipe_ctx->top_pipe) 22431a05873fSAnthony Koo continue; 22441a05873fSAnthony Koo 22451a05873fSAnthony Koo if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 22461a05873fSAnthony Koo continue; 22471a05873fSAnthony Koo 22481a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 22491a05873fSAnthony Koo struct audio_output audio_output; 22501a05873fSAnthony Koo 22511a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 22521a05873fSAnthony Koo 22531a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 22541a05873fSAnthony Koo pipe_ctx->stream_res.audio, 22551a05873fSAnthony Koo pipe_ctx->stream->signal, 22561a05873fSAnthony Koo &audio_output.crtc_info, 22571a05873fSAnthony Koo &audio_output.pll_info); 22581a05873fSAnthony Koo break; 22591a05873fSAnthony Koo } 22601a05873fSAnthony Koo } 22611a05873fSAnthony Koo } 22621a05873fSAnthony Koo } 2263cf437593SDmytro Laktyushkin 22644562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 2265fb3466a4SBhawanpreet Lakha struct dc *dc, 2266608ac7bbSJerry Zuo struct dc_state *context) 22674562236bSHarry Wentland { 2268f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 22694562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 22704562236bSHarry Wentland enum dc_status status; 22714562236bSHarry Wentland int i; 22724562236bSHarry Wentland 22734562236bSHarry Wentland /* Reset old context */ 22744562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 2275f42ea55bSAnthony Koo hws->funcs.reset_hw_ctx_wrap(dc, context); 22764562236bSHarry Wentland 22774562236bSHarry Wentland /* Skip applying if no targets */ 2278ab2541b6SAric Cyr if (context->stream_count <= 0) 22794562236bSHarry Wentland return DC_OK; 22804562236bSHarry Wentland 22814562236bSHarry Wentland /* Apply new context */ 22824562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 22834562236bSHarry Wentland 22844562236bSHarry Wentland /* below is for real asic only */ 2285a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 22864562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2287608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 22884562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 22894562236bSHarry Wentland 22904562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 22914562236bSHarry Wentland continue; 22924562236bSHarry Wentland 22934562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 22944562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 22954562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 22964562236bSHarry Wentland pipe_ctx->clock_source, i); 22974562236bSHarry Wentland continue; 22984562236bSHarry Wentland } 22994562236bSHarry Wentland 2300f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 23014562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 23024562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 23034562236bSHarry Wentland } 23044562236bSHarry Wentland 23052f3bfb27SRoman Li if (dc->fbc_compressor) 23061663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 23075099114bSAlex Deucher 23081a05873fSAnthony Koo dce110_setup_audio_dto(dc, context); 2309ab8812a3SHersen Wu 2310a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2311ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 2312608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 2313ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2314ab8812a3SHersen Wu 2315ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2316ab8812a3SHersen Wu continue; 2317ab8812a3SHersen Wu 2318eed928dcSCharlene Liu if (pipe_ctx->stream == pipe_ctx_old->stream && 2319eed928dcSCharlene Liu pipe_ctx->stream->link->link_state_valid) { 2320ab8812a3SHersen Wu continue; 2321eed928dcSCharlene Liu } 2322ab8812a3SHersen Wu 23235b92d9d4SHarry Wentland if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2324313bf4ffSYongqiang Sun continue; 2325313bf4ffSYongqiang Sun 2326b1f6d01cSDmytro Laktyushkin if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2327ab8812a3SHersen Wu continue; 2328ab8812a3SHersen Wu 23294562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 23304562236bSHarry Wentland pipe_ctx, 23314562236bSHarry Wentland context, 23324562236bSHarry Wentland dc); 23334562236bSHarry Wentland 23344562236bSHarry Wentland if (DC_OK != status) 23354562236bSHarry Wentland return status; 23364562236bSHarry Wentland } 23374562236bSHarry Wentland 2338690b5e39SRoman Li if (dc->fbc_compressor) 233965d38262Shersen wu enable_fbc(dc, dc->current_state); 234065d38262Shersen wu 234165d38262Shersen wu dcb->funcs->set_scratch_critical_state(dcb, false); 2342690b5e39SRoman Li 23434562236bSHarry Wentland return DC_OK; 23444562236bSHarry Wentland } 23454562236bSHarry Wentland 23464562236bSHarry Wentland /******************************************************************************* 23474562236bSHarry Wentland * Front End programming 23484562236bSHarry Wentland ******************************************************************************/ 23494562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 23504562236bSHarry Wentland { 23514562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 23524562236bSHarry Wentland 23534562236bSHarry Wentland default_adjust.force_hw_default = false; 235434996173SHarry Wentland default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 235534996173SHarry Wentland default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 23564562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 23576702a9acSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 23584562236bSHarry Wentland 23594562236bSHarry Wentland /* display color depth */ 23604562236bSHarry Wentland default_adjust.color_depth = 23614fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.display_color_depth; 23624562236bSHarry Wentland 23634562236bSHarry Wentland /* Lb color depth */ 23646702a9acSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 23654562236bSHarry Wentland 236686a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 236786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, &default_adjust); 23684562236bSHarry Wentland } 23694562236bSHarry Wentland 2370b06b7680SLeon Elazar 2371b06b7680SLeon Elazar /******************************************************************************* 2372b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 2373b06b7680SLeon Elazar * Blender + CRTC 2374b06b7680SLeon Elazar * 2375b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 2376b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 2377b06b7680SLeon Elazar * 2378b06b7680SLeon Elazar * |----------------------------------------------- | 2379b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 2380b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 2381b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 2382b06b7680SLeon Elazar * |------------------------------------------------| 2383b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 2384b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 2385b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 2386b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 2387b06b7680SLeon Elazar * -------------------------------------------------| 2388b06b7680SLeon Elazar * 2389b06b7680SLeon Elazar ******************************************************************************/ 2390fb3466a4SBhawanpreet Lakha static void program_surface_visibility(const struct dc *dc, 23914562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 23924562236bSHarry Wentland { 23934562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2394b06b7680SLeon Elazar bool blank_target = false; 23954562236bSHarry Wentland 23964562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 2397b06b7680SLeon Elazar 2398b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 2399b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2400b06b7680SLeon Elazar 24013be5262eSHarry Wentland if (pipe_ctx->bottom_pipe->plane_state->visible) { 24023be5262eSHarry Wentland if (pipe_ctx->plane_state->visible) 24034562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 24044562236bSHarry Wentland else 24054562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 2406b06b7680SLeon Elazar 24073be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2408b06b7680SLeon Elazar blank_target = true; 2409b06b7680SLeon Elazar 24103be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2411b06b7680SLeon Elazar blank_target = true; 2412b06b7680SLeon Elazar 2413e07f541fSYongqiang Sun dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 24146b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2415b06b7680SLeon Elazar 24164562236bSHarry Wentland } 24174562236bSHarry Wentland 24181bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 24191bf56e62SZeyu Fan { 2420146a9f63SKrunoslav Kovac int i = 0; 24211bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 24221bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 24231bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 24241bf56e62SZeyu Fan 24251bf56e62SZeyu Fan 24264fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 24271bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2428146a9f63SKrunoslav Kovac 2429146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2430146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2431146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 24321bf56e62SZeyu Fan } 24331bf56e62SZeyu Fan 243486a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 24351bf56e62SZeyu Fan } 2436fb3466a4SBhawanpreet Lakha static void update_plane_addr(const struct dc *dc, 24374562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 24384562236bSHarry Wentland { 24393be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 24404562236bSHarry Wentland 24413be5262eSHarry Wentland if (plane_state == NULL) 24424562236bSHarry Wentland return; 24434562236bSHarry Wentland 244486a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 244586a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 24463be5262eSHarry Wentland &plane_state->address, 24473be5262eSHarry Wentland plane_state->flip_immediate); 24484562236bSHarry Wentland 24493be5262eSHarry Wentland plane_state->status.requested_address = plane_state->address; 24504562236bSHarry Wentland } 24514562236bSHarry Wentland 2452f774b339SEric Yang static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 24534562236bSHarry Wentland { 24543be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 24554562236bSHarry Wentland 24563be5262eSHarry Wentland if (plane_state == NULL) 24574562236bSHarry Wentland return; 24584562236bSHarry Wentland 24593be5262eSHarry Wentland plane_state->status.is_flip_pending = 246086a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 246186a66c4eSHarry Wentland pipe_ctx->plane_res.mi); 24624562236bSHarry Wentland 24633be5262eSHarry Wentland if (plane_state->status.is_flip_pending && !plane_state->visible) 246486a66c4eSHarry Wentland pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 24654562236bSHarry Wentland 246686a66c4eSHarry Wentland plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 246786a66c4eSHarry Wentland if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 24686b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 24693be5262eSHarry Wentland plane_state->status.is_right_eye =\ 24706b670fa9SHarry Wentland !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 24717f5c22d1SVitaly Prosyak } 24724562236bSHarry Wentland } 24734562236bSHarry Wentland 2474fb3466a4SBhawanpreet Lakha void dce110_power_down(struct dc *dc) 24754562236bSHarry Wentland { 24764562236bSHarry Wentland power_down_all_hw_blocks(dc); 24774562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 24784562236bSHarry Wentland } 24794562236bSHarry Wentland 24804562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 24814562236bSHarry Wentland struct dc_context *dc_ctx, 24824562236bSHarry Wentland struct timing_generator *tg) 24834562236bSHarry Wentland { 24844562236bSHarry Wentland bool rc = false; 24854562236bSHarry Wentland 24864562236bSHarry Wentland /* To avoid endless loop we wait at most 24874562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 24884562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 24894562236bSHarry Wentland uint32_t i; 24904562236bSHarry Wentland 24914562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 24924562236bSHarry Wentland 24934562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 24944562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 24954562236bSHarry Wentland break; 24964562236bSHarry Wentland } 24974562236bSHarry Wentland 24984562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 24994562236bSHarry Wentland rc = true; 25004562236bSHarry Wentland /* usually occurs at i=1 */ 25014562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 25024562236bSHarry Wentland i); 25034562236bSHarry Wentland break; 25044562236bSHarry Wentland } 25054562236bSHarry Wentland 25064562236bSHarry Wentland /* Wait for one frame. */ 25074562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 25084562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 25094562236bSHarry Wentland } 25104562236bSHarry Wentland 25114562236bSHarry Wentland if (false == rc) 25124562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 25134562236bSHarry Wentland 25144562236bSHarry Wentland return rc; 25154562236bSHarry Wentland } 25164562236bSHarry Wentland 25174562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 25184562236bSHarry Wentland static void dce110_enable_timing_synchronization( 2519fb3466a4SBhawanpreet Lakha struct dc *dc, 25204562236bSHarry Wentland int group_index, 25214562236bSHarry Wentland int group_size, 25224562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 25234562236bSHarry Wentland { 25244562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 25254562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 25264562236bSHarry Wentland int i; 25274562236bSHarry Wentland 25284562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 25294562236bSHarry Wentland 25304562236bSHarry Wentland /* Designate a single TG in the group as a master. 25314562236bSHarry Wentland * Since HW doesn't care which one, we always assign 25324562236bSHarry Wentland * the 1st one in the group. */ 25334562236bSHarry Wentland gsl_params.gsl_group = 0; 25346b670fa9SHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 25354562236bSHarry Wentland 25364562236bSHarry Wentland for (i = 0; i < group_size; i++) 25376b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 25386b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg, &gsl_params); 25394562236bSHarry Wentland 25404562236bSHarry Wentland /* Reset slave controllers on master VSync */ 25414562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 25424562236bSHarry Wentland 25434562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 25446b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2545fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2546fa2123dbSMikita Lipski gsl_params.gsl_group); 25474562236bSHarry Wentland 25484562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 25494562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 25506b670fa9SHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2551fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2552fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg); 25534562236bSHarry Wentland } 25544562236bSHarry Wentland 25554562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 25564562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 25574562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 25584562236bSHarry Wentland for (i = 0; i < group_size; i++) 25596b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 25604562236bSHarry Wentland 25614562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 25624562236bSHarry Wentland } 25634562236bSHarry Wentland 2564fa2123dbSMikita Lipski static void dce110_enable_per_frame_crtc_position_reset( 2565fa2123dbSMikita Lipski struct dc *dc, 2566fa2123dbSMikita Lipski int group_size, 2567fa2123dbSMikita Lipski struct pipe_ctx *grouped_pipes[]) 2568fa2123dbSMikita Lipski { 2569fa2123dbSMikita Lipski struct dc_context *dc_ctx = dc->ctx; 2570fa2123dbSMikita Lipski struct dcp_gsl_params gsl_params = { 0 }; 2571fa2123dbSMikita Lipski int i; 2572fa2123dbSMikita Lipski 2573fa2123dbSMikita Lipski gsl_params.gsl_group = 0; 257437cd85ceSDavid Francis gsl_params.gsl_master = 0; 2575fa2123dbSMikita Lipski 2576fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2577fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2578fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, &gsl_params); 2579fa2123dbSMikita Lipski 2580fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2581fa2123dbSMikita Lipski 2582fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2583fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2584fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2585fa2123dbSMikita Lipski gsl_params.gsl_master, 2586fa2123dbSMikita Lipski &grouped_pipes[i]->stream->triggered_crtc_reset); 2587fa2123dbSMikita Lipski 2588fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2589fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2590fa2123dbSMikita Lipski wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2591fa2123dbSMikita Lipski 2592fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2593fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2594fa2123dbSMikita Lipski 2595fa2123dbSMikita Lipski } 2596fa2123dbSMikita Lipski 2597fb55546eSAnthony Koo static void init_pipes(struct dc *dc, struct dc_state *context) 2598fb55546eSAnthony Koo { 2599fb55546eSAnthony Koo // Do nothing 2600fb55546eSAnthony Koo } 2601fb55546eSAnthony Koo 2602fb3466a4SBhawanpreet Lakha static void init_hw(struct dc *dc) 26034562236bSHarry Wentland { 26044562236bSHarry Wentland int i; 26054562236bSHarry Wentland struct dc_bios *bp; 26064562236bSHarry Wentland struct transform *xfm; 26075e7773a2SAnthony Koo struct abm *abm; 260870d9e8cbSPaul Hsieh struct dmcu *dmcu; 2609f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 26103ba01817SYongqiang Sun uint32_t backlight = MAX_BACKLIGHT_LEVEL; 26114562236bSHarry Wentland 26124562236bSHarry Wentland bp = dc->ctx->dc_bios; 26134562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 26144562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 26154562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 26164562236bSHarry Wentland 2617f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 26184562236bSHarry Wentland dc, i, bp, 26194562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 2620f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 26214562236bSHarry Wentland dc, i, bp, 26224562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 2623f42ea55bSAnthony Koo hws->funcs.enable_display_pipe_clock_gating( 26244562236bSHarry Wentland dc->ctx, 26254562236bSHarry Wentland true); 26264562236bSHarry Wentland } 26274562236bSHarry Wentland 2628e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 26294562236bSHarry Wentland /***************************************/ 26304562236bSHarry Wentland 26314562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 26324562236bSHarry Wentland /****************************************/ 26334562236bSHarry Wentland /* Power up AND update implementation according to the 26344562236bSHarry Wentland * required signal (which may be different from the 26354562236bSHarry Wentland * default signal on connector). */ 2636d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 2637069d418fSAndrew Jiang 26384562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 26394562236bSHarry Wentland } 26404562236bSHarry Wentland 26414562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 26424562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 26434562236bSHarry Wentland 26444562236bSHarry Wentland tg->funcs->disable_vga(tg); 26454562236bSHarry Wentland 26464562236bSHarry Wentland /* Blank controller using driver code instead of 26474562236bSHarry Wentland * command table. */ 26484562236bSHarry Wentland tg->funcs->set_blank(tg, true); 26494b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 26504562236bSHarry Wentland } 26514562236bSHarry Wentland 26524562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 26534562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 26544562236bSHarry Wentland audio->funcs->hw_init(audio); 26554562236bSHarry Wentland } 26565e7773a2SAnthony Koo 26573ba01817SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 26583ba01817SYongqiang Sun struct dc_link *link = dc->links[i]; 26593ba01817SYongqiang Sun 26603ba01817SYongqiang Sun if (link->panel_cntl) 26613ba01817SYongqiang Sun backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 26624562236bSHarry Wentland } 26635099114bSAlex Deucher 26643ba01817SYongqiang Sun abm = dc->res_pool->abm; 26653ba01817SYongqiang Sun if (abm != NULL) 26663ba01817SYongqiang Sun abm->funcs->abm_init(abm, backlight); 26673ba01817SYongqiang Sun 266870d9e8cbSPaul Hsieh dmcu = dc->res_pool->dmcu; 266970d9e8cbSPaul Hsieh if (dmcu != NULL && abm != NULL) 267070d9e8cbSPaul Hsieh abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 267170d9e8cbSPaul Hsieh 26722f3bfb27SRoman Li if (dc->fbc_compressor) 26731663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2674690b5e39SRoman Li 26756728b30cSAnthony Koo } 26764562236bSHarry Wentland 26779566b675SDmytro Laktyushkin 26789566b675SDmytro Laktyushkin void dce110_prepare_bandwidth( 2679fb3466a4SBhawanpreet Lakha struct dc *dc, 26809566b675SDmytro Laktyushkin struct dc_state *context) 2681cf437593SDmytro Laktyushkin { 2682dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 2683fab55d61SDmytro Laktyushkin 2684fab55d61SDmytro Laktyushkin dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2685cf437593SDmytro Laktyushkin 26865a83c932SNicholas Kazlauskas dccg->funcs->update_clocks( 26875a83c932SNicholas Kazlauskas dccg, 268824f7dd7eSDmytro Laktyushkin context, 26899566b675SDmytro Laktyushkin false); 26909566b675SDmytro Laktyushkin } 26919566b675SDmytro Laktyushkin 26929566b675SDmytro Laktyushkin void dce110_optimize_bandwidth( 26939566b675SDmytro Laktyushkin struct dc *dc, 26949566b675SDmytro Laktyushkin struct dc_state *context) 26959566b675SDmytro Laktyushkin { 2696dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 26979566b675SDmytro Laktyushkin 26989566b675SDmytro Laktyushkin dce110_set_displaymarks(dc, context); 26999566b675SDmytro Laktyushkin 27009566b675SDmytro Laktyushkin dccg->funcs->update_clocks( 27019566b675SDmytro Laktyushkin dccg, 27029566b675SDmytro Laktyushkin context, 27039566b675SDmytro Laktyushkin true); 27044562236bSHarry Wentland } 27054562236bSHarry Wentland 27064562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 2707fb3466a4SBhawanpreet Lakha struct dc *dc, struct pipe_ctx *pipe_ctx) 27084562236bSHarry Wentland { 270986a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 27103be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 27114562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 27124562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 27134562236bSHarry Wentland unsigned int i; 2714f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2715f42ea55bSAnthony Koo 27165d4b05ddSBhawanpreet Lakha DC_LOGGER_INIT(); 27174562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 27184562236bSHarry Wentland 27194562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 27204562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 27214562236bSHarry Wentland 2722e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 27234562236bSHarry Wentland 27244562236bSHarry Wentland set_default_colors(pipe_ctx); 27254fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 27264562236bSHarry Wentland == true) { 27274562236bSHarry Wentland tbl_entry.color_space = 27284fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 27294562236bSHarry Wentland 27304562236bSHarry Wentland for (i = 0; i < 12; i++) 27314562236bSHarry Wentland tbl_entry.regval[i] = 27324fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 27334562236bSHarry Wentland 273486a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 273586a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 27364562236bSHarry Wentland } 27374562236bSHarry Wentland 27384fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 27394562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2740146a9f63SKrunoslav Kovac 2741146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2742146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2743146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 27444562236bSHarry Wentland } 27454562236bSHarry Wentland 274686a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 27474562236bSHarry Wentland 27486702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2749c1473558SAndrey Grodzovsky 27504562236bSHarry Wentland program_scaler(dc, pipe_ctx); 27514562236bSHarry Wentland 27524562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 27534562236bSHarry Wentland mi, 27543be5262eSHarry Wentland plane_state->format, 27553be5262eSHarry Wentland &plane_state->tiling_info, 27563be5262eSHarry Wentland &plane_state->plane_size, 27573be5262eSHarry Wentland plane_state->rotation, 2758624d7c47SYongqiang Sun NULL, 27594b28b76bSDmytro Laktyushkin false); 27604b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 27613be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 27624562236bSHarry Wentland 2763fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 27644562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 276586a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 27663be5262eSHarry Wentland plane_state->format, 27673be5262eSHarry Wentland &plane_state->tiling_info, 27683be5262eSHarry Wentland plane_state->rotation); 27694562236bSHarry Wentland 2770067c878aSYongqiang Sun /* Moved programming gamma from dc to hwss */ 2771405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update || 2772405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2773405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.gamma_change) 2774f42ea55bSAnthony Koo hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2775405c50a0SAndrew Jiang 2776405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update) 2777f42ea55bSAnthony Koo hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2778067c878aSYongqiang Sun 27791296423bSBhawanpreet Lakha DC_LOG_SURFACE( 27803032deb5SBhawanpreet Lakha "Pipe:%d %p: addr hi:0x%x, " 27814562236bSHarry Wentland "addr low:0x%x, " 27824562236bSHarry Wentland "src: %d, %d, %d," 27834562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 27844562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 27854562236bSHarry Wentland pipe_ctx->pipe_idx, 27863032deb5SBhawanpreet Lakha (void *) pipe_ctx->plane_state, 27873be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.high_part, 27883be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.low_part, 27893be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.x, 27903be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.y, 27913be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.width, 27923be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.height, 27933be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.x, 27943be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.y, 27953be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.width, 27963be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.height, 27973be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.x, 27983be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.y, 27993be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.width, 28003be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.height); 28014562236bSHarry Wentland 28021296423bSBhawanpreet Lakha DC_LOG_SURFACE( 28034562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 28044562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 28054562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 28064562236bSHarry Wentland pipe_ctx->pipe_idx, 28076702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.width, 28086702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.height, 28096702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.x, 28106702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.y, 28116702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.width, 28126702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.height, 28136702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.x, 28146702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.y); 28154562236bSHarry Wentland } 28164562236bSHarry Wentland 28174562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 2818fb3466a4SBhawanpreet Lakha struct dc *dc, 28193e9ad616SEric Yang const struct dc_stream_state *stream, 28203e9ad616SEric Yang int num_planes, 2821608ac7bbSJerry Zuo struct dc_state *context) 28224562236bSHarry Wentland { 28232194e3aeSRoman Li int i; 28244562236bSHarry Wentland 28253e9ad616SEric Yang if (num_planes == 0) 28264562236bSHarry Wentland return; 28274562236bSHarry Wentland 282865d38262Shersen wu if (dc->fbc_compressor) 282965d38262Shersen wu dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 283065d38262Shersen wu 28313e9ad616SEric Yang for (i = 0; i < dc->res_pool->pipe_count; i++) { 28323dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 28334562236bSHarry Wentland 2834a2607aefSHarry Wentland if (pipe_ctx->stream != stream) 28354562236bSHarry Wentland continue; 28364562236bSHarry Wentland 28373b21b6d2SJerry Zuo /* Need to allocate mem before program front end for Fiji */ 28383b21b6d2SJerry Zuo pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 28393b21b6d2SJerry Zuo pipe_ctx->plane_res.mi, 28403b21b6d2SJerry Zuo pipe_ctx->stream->timing.h_total, 28413b21b6d2SJerry Zuo pipe_ctx->stream->timing.v_total, 2842380604e2SKen Chalmers pipe_ctx->stream->timing.pix_clk_100hz / 10, 28433b21b6d2SJerry Zuo context->stream_count); 28443b21b6d2SJerry Zuo 28454562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 28464f804817SYongqiang Sun 28474f804817SYongqiang Sun dc->hwss.update_plane_addr(dc, pipe_ctx); 28484f804817SYongqiang Sun 2849b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 28504562236bSHarry Wentland 28514562236bSHarry Wentland } 28523dc780ecSYongqiang Sun 285365d38262Shersen wu if (dc->fbc_compressor) 285412a8bd88SShirish S enable_fbc(dc, context); 28554562236bSHarry Wentland } 28564562236bSHarry Wentland 2857bbf5f6c3SAnthony Koo static void dce110_post_unlock_program_front_end( 2858bbf5f6c3SAnthony Koo struct dc *dc, 2859bbf5f6c3SAnthony Koo struct dc_state *context) 2860bbf5f6c3SAnthony Koo { 2861bbf5f6c3SAnthony Koo } 2862009114f6SAnthony Koo 2863e6c258cbSYongqiang Sun static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 28644562236bSHarry Wentland { 2865f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2866bc373a89SRoman Li int fe_idx = pipe_ctx->plane_res.mi ? 2867bc373a89SRoman Li pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2868e6c258cbSYongqiang Sun 28697950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2870608ac7bbSJerry Zuo if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 28714562236bSHarry Wentland return; 28724562236bSHarry Wentland 2873f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 2874cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2875cfe4645eSDmytro Laktyushkin 2876cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2877cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 28784562236bSHarry Wentland } 28794562236bSHarry Wentland 28806be425f3SEric Yang static void dce110_wait_for_mpcc_disconnect( 2881fb3466a4SBhawanpreet Lakha struct dc *dc, 28826be425f3SEric Yang struct resource_pool *res_pool, 28836be425f3SEric Yang struct pipe_ctx *pipe_ctx) 2884b6762f0cSEric Yang { 2885b6762f0cSEric Yang /* do nothing*/ 2886b6762f0cSEric Yang } 2887b6762f0cSEric Yang 28884bd0dc68SJoshua Aberback static void program_output_csc(struct dc *dc, 28894bd0dc68SJoshua Aberback struct pipe_ctx *pipe_ctx, 28904bd0dc68SJoshua Aberback enum dc_color_space colorspace, 28914bd0dc68SJoshua Aberback uint16_t *matrix, 28924bd0dc68SJoshua Aberback int opp_id) 28934bd0dc68SJoshua Aberback { 28944bd0dc68SJoshua Aberback int i; 28954bd0dc68SJoshua Aberback struct out_csc_color_matrix tbl_entry; 28964bd0dc68SJoshua Aberback 28974bd0dc68SJoshua Aberback if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 28984bd0dc68SJoshua Aberback enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 28994bd0dc68SJoshua Aberback 29004bd0dc68SJoshua Aberback for (i = 0; i < 12; i++) 29014bd0dc68SJoshua Aberback tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 29024bd0dc68SJoshua Aberback 29034bd0dc68SJoshua Aberback tbl_entry.color_space = color_space; 29044bd0dc68SJoshua Aberback 29054bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 29064bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm, &tbl_entry); 29074bd0dc68SJoshua Aberback } 29084bd0dc68SJoshua Aberback } 29094bd0dc68SJoshua Aberback 2910faf0389fSJason Yan static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 291133fd17d9SEric Yang { 291233fd17d9SEric Yang struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 291333fd17d9SEric Yang struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 291433fd17d9SEric Yang struct mem_input *mi = pipe_ctx->plane_res.mi; 291533fd17d9SEric Yang struct dc_cursor_mi_param param = { 2916380604e2SKen Chalmers .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 291733d7598dSJun Lei .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 291839a9f4d8SDmytro Laktyushkin .viewport = pipe_ctx->plane_res.scl_data.viewport, 291939a9f4d8SDmytro Laktyushkin .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 292039a9f4d8SDmytro Laktyushkin .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 292108ed681cSDmytro Laktyushkin .rotation = pipe_ctx->plane_state->rotation, 292208ed681cSDmytro Laktyushkin .mirror = pipe_ctx->plane_state->horizontal_mirror 292333fd17d9SEric Yang }; 292433fd17d9SEric Yang 292503a4059bSNicholas Kazlauskas /** 292603a4059bSNicholas Kazlauskas * If the cursor's source viewport is clipped then we need to 292703a4059bSNicholas Kazlauskas * translate the cursor to appear in the correct position on 292803a4059bSNicholas Kazlauskas * the screen. 292903a4059bSNicholas Kazlauskas * 293003a4059bSNicholas Kazlauskas * This translation isn't affected by scaling so it needs to be 293103a4059bSNicholas Kazlauskas * done *after* we adjust the position for the scale factor. 2932033baeeeSNicholas Kazlauskas * 2933033baeeeSNicholas Kazlauskas * This is only done by opt-in for now since there are still 2934033baeeeSNicholas Kazlauskas * some usecases like tiled display that might enable the 2935033baeeeSNicholas Kazlauskas * cursor on both streams while expecting dc to clip it. 293603a4059bSNicholas Kazlauskas */ 2937033baeeeSNicholas Kazlauskas if (pos_cpy.translate_by_source) { 293803a4059bSNicholas Kazlauskas pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 293903a4059bSNicholas Kazlauskas pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2940033baeeeSNicholas Kazlauskas } 294103a4059bSNicholas Kazlauskas 294233fd17d9SEric Yang if (pipe_ctx->plane_state->address.type 294333fd17d9SEric Yang == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 294433fd17d9SEric Yang pos_cpy.enable = false; 294533fd17d9SEric Yang 294633fd17d9SEric Yang if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 294733fd17d9SEric Yang pos_cpy.enable = false; 294833fd17d9SEric Yang 2949dc75dd70SRoman Li if (ipp->funcs->ipp_cursor_set_position) 295033fd17d9SEric Yang ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2951dc75dd70SRoman Li if (mi->funcs->set_cursor_position) 295233fd17d9SEric Yang mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 295333fd17d9SEric Yang } 295433fd17d9SEric Yang 2955faf0389fSJason Yan static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 295633fd17d9SEric Yang { 295733fd17d9SEric Yang struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 295833fd17d9SEric Yang 2959d1aaad05SHarry Wentland if (pipe_ctx->plane_res.ipp && 2960d1aaad05SHarry Wentland pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 296133fd17d9SEric Yang pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 296233fd17d9SEric Yang pipe_ctx->plane_res.ipp, attributes); 296333fd17d9SEric Yang 2964d1aaad05SHarry Wentland if (pipe_ctx->plane_res.mi && 2965d1aaad05SHarry Wentland pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 296633fd17d9SEric Yang pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 296733fd17d9SEric Yang pipe_ctx->plane_res.mi, attributes); 296833fd17d9SEric Yang 2969d1aaad05SHarry Wentland if (pipe_ctx->plane_res.xfm && 2970d1aaad05SHarry Wentland pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 297133fd17d9SEric Yang pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 297233fd17d9SEric Yang pipe_ctx->plane_res.xfm, attributes); 297333fd17d9SEric Yang } 297433fd17d9SEric Yang 29754b0e95d1SYongqiang Sun bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 29764b0e95d1SYongqiang Sun uint32_t backlight_pwm_u16_16, 29774b0e95d1SYongqiang Sun uint32_t frame_ramp) 29784b0e95d1SYongqiang Sun { 29794b0e95d1SYongqiang Sun struct dc_link *link = pipe_ctx->stream->link; 29804b0e95d1SYongqiang Sun struct dc *dc = link->ctx->dc; 29814b0e95d1SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 29823ba01817SYongqiang Sun struct panel_cntl *panel_cntl = link->panel_cntl; 29834b0e95d1SYongqiang Sun struct dmcu *dmcu = dc->res_pool->dmcu; 29844b0e95d1SYongqiang Sun bool fw_set_brightness = true; 29854b0e95d1SYongqiang Sun /* DMCU -1 for all controller id values, 29864b0e95d1SYongqiang Sun * therefore +1 here 29874b0e95d1SYongqiang Sun */ 29884b0e95d1SYongqiang Sun uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 29894b0e95d1SYongqiang Sun 29903ba01817SYongqiang Sun if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 29914b0e95d1SYongqiang Sun return false; 29924b0e95d1SYongqiang Sun 29934b0e95d1SYongqiang Sun if (dmcu) 29944b0e95d1SYongqiang Sun fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 29954b0e95d1SYongqiang Sun 29963ba01817SYongqiang Sun if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 29973ba01817SYongqiang Sun panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 29983ba01817SYongqiang Sun else 29994b0e95d1SYongqiang Sun abm->funcs->set_backlight_level_pwm( 30004b0e95d1SYongqiang Sun abm, 30014b0e95d1SYongqiang Sun backlight_pwm_u16_16, 30024b0e95d1SYongqiang Sun frame_ramp, 30034b0e95d1SYongqiang Sun controller_id, 30043ba01817SYongqiang Sun link->panel_cntl->inst); 30054b0e95d1SYongqiang Sun 30064b0e95d1SYongqiang Sun return true; 30074b0e95d1SYongqiang Sun } 30084b0e95d1SYongqiang Sun 30093ba01817SYongqiang Sun void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 30103ba01817SYongqiang Sun { 30113ba01817SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 30123ba01817SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 30133ba01817SYongqiang Sun 30143ba01817SYongqiang Sun if (abm) 30153ba01817SYongqiang Sun abm->funcs->set_abm_immediate_disable(abm, 30163ba01817SYongqiang Sun pipe_ctx->stream->link->panel_cntl->inst); 30173ba01817SYongqiang Sun 30183ba01817SYongqiang Sun if (panel_cntl) 30193ba01817SYongqiang Sun panel_cntl->funcs->store_backlight_level(panel_cntl); 30203ba01817SYongqiang Sun } 30213ba01817SYongqiang Sun 3022474ac4a8SYongqiang Sun void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 3023474ac4a8SYongqiang Sun { 3024474ac4a8SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 3025474ac4a8SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 3026474ac4a8SYongqiang Sun uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 3027474ac4a8SYongqiang Sun 3028474ac4a8SYongqiang Sun if (abm && panel_cntl) 3029474ac4a8SYongqiang Sun abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 3030474ac4a8SYongqiang Sun } 3031474ac4a8SYongqiang Sun 30324562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 30331bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 30344bd0dc68SJoshua Aberback .program_output_csc = program_output_csc, 30354562236bSHarry Wentland .init_hw = init_hw, 30364562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 30374562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 3038bbf5f6c3SAnthony Koo .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 30394562236bSHarry Wentland .update_plane_addr = update_plane_addr, 30404562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 30414562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 30424562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 3043fa2123dbSMikita Lipski .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 30444562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 30454562236bSHarry Wentland .enable_stream = dce110_enable_stream, 30464562236bSHarry Wentland .disable_stream = dce110_disable_stream, 30474562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 304841b49742SCharlene Liu .blank_stream = dce110_blank_stream, 30491a05873fSAnthony Koo .enable_audio_stream = dce110_enable_audio_stream, 30501a05873fSAnthony Koo .disable_audio_stream = dce110_disable_audio_stream, 30517f914a62SYongqiang Sun .disable_plane = dce110_power_down_fe, 30524562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 3053009114f6SAnthony Koo .interdependent_update_lock = NULL, 30541e461c37SAric Cyr .cursor_lock = dce_pipe_control_lock, 30559566b675SDmytro Laktyushkin .prepare_bandwidth = dce110_prepare_bandwidth, 30569566b675SDmytro Laktyushkin .optimize_bandwidth = dce110_optimize_bandwidth, 30574562236bSHarry Wentland .set_drr = set_drr, 305872ada5f7SEric Cook .get_position = get_position, 30594562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 306015e17335SCharlene Liu .setup_stereo = NULL, 306115e17335SCharlene Liu .set_avmute = dce110_set_avmute, 306241f97c07SHersen Wu .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 3063099303e9SPeikang Zhang .edp_backlight_control = dce110_edp_backlight_control, 30648a31820bSMartin Leung .edp_power_control = dce110_edp_power_control, 30658a31820bSMartin Leung .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 306633fd17d9SEric Yang .set_cursor_position = dce110_set_cursor_position, 30674b0e95d1SYongqiang Sun .set_cursor_attribute = dce110_set_cursor_attribute, 30684b0e95d1SYongqiang Sun .set_backlight_level = dce110_set_backlight_level, 30693ba01817SYongqiang Sun .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 3070474ac4a8SYongqiang Sun .set_pipe = dce110_set_pipe, 30714562236bSHarry Wentland }; 30724562236bSHarry Wentland 3073f42ea55bSAnthony Koo static const struct hwseq_private_funcs dce110_private_funcs = { 3074f42ea55bSAnthony Koo .init_pipes = init_pipes, 3075f42ea55bSAnthony Koo .update_plane_addr = update_plane_addr, 3076f42ea55bSAnthony Koo .set_input_transfer_func = dce110_set_input_transfer_func, 3077f42ea55bSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 3078f42ea55bSAnthony Koo .power_down = dce110_power_down, 3079f42ea55bSAnthony Koo .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 3080f42ea55bSAnthony Koo .enable_display_power_gating = dce110_enable_display_power_gating, 3081f42ea55bSAnthony Koo .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 3082f42ea55bSAnthony Koo .enable_stream_timing = dce110_enable_stream_timing, 3083f42ea55bSAnthony Koo .disable_stream_gating = NULL, 3084f42ea55bSAnthony Koo .enable_stream_gating = NULL, 3085f42ea55bSAnthony Koo .edp_backlight_control = dce110_edp_backlight_control, 3086f42ea55bSAnthony Koo }; 3087f42ea55bSAnthony Koo 3088c13b408bSDave Airlie void dce110_hw_sequencer_construct(struct dc *dc) 30894562236bSHarry Wentland { 30904562236bSHarry Wentland dc->hwss = dce110_funcs; 3091f42ea55bSAnthony Koo dc->hwseq->funcs = dce110_private_funcs; 30924562236bSHarry Wentland } 30934562236bSHarry Wentland 3094