14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 25c366be54SSam Ravnborg 26c366be54SSam Ravnborg #include <linux/delay.h> 27c366be54SSam Ravnborg 284562236bSHarry Wentland #include "dm_services.h" 294562236bSHarry Wentland #include "dc.h" 304562236bSHarry Wentland #include "dc_bios_types.h" 314562236bSHarry Wentland #include "core_types.h" 324562236bSHarry Wentland #include "core_status.h" 334562236bSHarry Wentland #include "resource.h" 344562236bSHarry Wentland #include "dm_helpers.h" 354562236bSHarry Wentland #include "dce110_hw_sequencer.h" 364562236bSHarry Wentland #include "dce110_timing_generator.h" 3798489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 3887401969SAndrew Jiang #include "gpio_service_interface.h" 394562236bSHarry Wentland 401663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 411663ae1cSBhawanpreet Lakha 424562236bSHarry Wentland #include "bios/bios_parser_helper.h" 434562236bSHarry Wentland #include "timing_generator.h" 444562236bSHarry Wentland #include "mem_input.h" 454562236bSHarry Wentland #include "opp.h" 464562236bSHarry Wentland #include "ipp.h" 474562236bSHarry Wentland #include "transform.h" 484562236bSHarry Wentland #include "stream_encoder.h" 494562236bSHarry Wentland #include "link_encoder.h" 5087401969SAndrew Jiang #include "link_hwss.h" 514562236bSHarry Wentland #include "clock_source.h" 52dc88b4a6SEric Yang #include "clk_mgr.h" 535e7773a2SAnthony Koo #include "abm.h" 544562236bSHarry Wentland #include "audio.h" 5508b16886SZeyu Fan #include "reg_helper.h" 56d4caa72eSAnthony Koo #include "panel_cntl.h" 574562236bSHarry Wentland 584562236bSHarry Wentland /* include DCE11 register header files */ 594562236bSHarry Wentland #include "dce/dce_11_0_d.h" 604562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 61e266fdf6SVitaly Prosyak #include "custom_float.h" 624562236bSHarry Wentland 634cac1e6dSYongqiang Sun #include "atomfirmware.h" 644cac1e6dSYongqiang Sun 6578c77382SAnthony Koo #define GAMMA_HW_POINTS_NUM 256 6678c77382SAnthony Koo 6787401969SAndrew Jiang /* 6887401969SAndrew Jiang * All values are in milliseconds; 6987401969SAndrew Jiang * For eDP, after power-up/power/down, 7087401969SAndrew Jiang * 300/500 msec max. delay from LCDVCC to black video generation 7187401969SAndrew Jiang */ 7287401969SAndrew Jiang #define PANEL_POWER_UP_TIMEOUT 300 7387401969SAndrew Jiang #define PANEL_POWER_DOWN_TIMEOUT 500 7487401969SAndrew Jiang #define HPD_CHECK_INTERVAL 10 7596577cf8SHersen Wu #define OLED_POST_T7_DELAY 100 7696577cf8SHersen Wu #define OLED_PRE_T11_DELAY 150 7787401969SAndrew Jiang 785eefbc40SYue Hin Lau #define CTX \ 795eefbc40SYue Hin Lau hws->ctx 805d4b05ddSBhawanpreet Lakha 815d4b05ddSBhawanpreet Lakha #define DC_LOGGER_INIT() 825d4b05ddSBhawanpreet Lakha 835eefbc40SYue Hin Lau #define REG(reg)\ 845eefbc40SYue Hin Lau hws->regs->reg 855eefbc40SYue Hin Lau 865eefbc40SYue Hin Lau #undef FN 875eefbc40SYue Hin Lau #define FN(reg_name, field_name) \ 885eefbc40SYue Hin Lau hws->shifts->field_name, hws->masks->field_name 895eefbc40SYue Hin Lau 904562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 914562236bSHarry Wentland uint32_t crtc; 924562236bSHarry Wentland }; 934562236bSHarry Wentland 944562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 954562236bSHarry Wentland { 964562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 974562236bSHarry Wentland }, 984562236bSHarry Wentland { 994562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1004562236bSHarry Wentland }, 1014562236bSHarry Wentland { 1024562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1034562236bSHarry Wentland }, 1044562236bSHarry Wentland { 1054562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1064562236bSHarry Wentland } 1074562236bSHarry Wentland }; 1084562236bSHarry Wentland 1094562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 1104562236bSHarry Wentland (reg + reg_offsets[id].blnd) 1114562236bSHarry Wentland 1124562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 1134562236bSHarry Wentland (reg + reg_offsets[id].crtc) 1144562236bSHarry Wentland 1154562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 1164562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 1174562236bSHarry Wentland 1184562236bSHarry Wentland /******************************************************************************* 1194562236bSHarry Wentland * Private definitions 1204562236bSHarry Wentland ******************************************************************************/ 1214562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 1224562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 1234562236bSHarry Wentland { 1244562236bSHarry Wentland uint32_t addr; 1254562236bSHarry Wentland uint32_t value = 0; 1264562236bSHarry Wentland uint32_t chunk_int = 0; 1274562236bSHarry Wentland uint32_t chunk_mul = 0; 1284562236bSHarry Wentland 1294562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 1304562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1314562236bSHarry Wentland 1324562236bSHarry Wentland set_reg_field_value( 1334562236bSHarry Wentland value, 1344562236bSHarry Wentland 0, 1354562236bSHarry Wentland DVMM_PTE_CONTROL, 1364562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1374562236bSHarry Wentland 1384562236bSHarry Wentland set_reg_field_value( 1394562236bSHarry Wentland value, 1404562236bSHarry Wentland 1, 1414562236bSHarry Wentland DVMM_PTE_CONTROL, 1424562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1434562236bSHarry Wentland 1444562236bSHarry Wentland set_reg_field_value( 1454562236bSHarry Wentland value, 1464562236bSHarry Wentland 1, 1474562236bSHarry Wentland DVMM_PTE_CONTROL, 1484562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1494562236bSHarry Wentland 1504562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1514562236bSHarry Wentland 1524562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1534562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1544562236bSHarry Wentland 1554562236bSHarry Wentland chunk_int = get_reg_field_value( 1564562236bSHarry Wentland value, 1574562236bSHarry Wentland DVMM_PTE_REQ, 1584562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1594562236bSHarry Wentland 1604562236bSHarry Wentland chunk_mul = get_reg_field_value( 1614562236bSHarry Wentland value, 1624562236bSHarry Wentland DVMM_PTE_REQ, 1634562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1644562236bSHarry Wentland 1654562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1664562236bSHarry Wentland 1674562236bSHarry Wentland set_reg_field_value( 1684562236bSHarry Wentland value, 1694562236bSHarry Wentland 255, 1704562236bSHarry Wentland DVMM_PTE_REQ, 1714562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1724562236bSHarry Wentland 1734562236bSHarry Wentland set_reg_field_value( 1744562236bSHarry Wentland value, 1754562236bSHarry Wentland 4, 1764562236bSHarry Wentland DVMM_PTE_REQ, 1774562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1784562236bSHarry Wentland 1794562236bSHarry Wentland set_reg_field_value( 1804562236bSHarry Wentland value, 1814562236bSHarry Wentland 4, 1824562236bSHarry Wentland DVMM_PTE_REQ, 1834562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1844562236bSHarry Wentland 1854562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1864562236bSHarry Wentland } 1874562236bSHarry Wentland } 1884562236bSHarry Wentland /**************************************************************************/ 1894562236bSHarry Wentland 1904562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1914562236bSHarry Wentland struct dc_context *ctx, 1924562236bSHarry Wentland bool clock_gating) 1934562236bSHarry Wentland { 1944562236bSHarry Wentland /*TODO*/ 1954562236bSHarry Wentland } 1964562236bSHarry Wentland 1974562236bSHarry Wentland static bool dce110_enable_display_power_gating( 198fb3466a4SBhawanpreet Lakha struct dc *dc, 1994562236bSHarry Wentland uint8_t controller_id, 2004562236bSHarry Wentland struct dc_bios *dcb, 2014562236bSHarry Wentland enum pipe_gating_control power_gating) 2024562236bSHarry Wentland { 2034562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 2044562236bSHarry Wentland enum bp_pipe_control_action cntl; 2054562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 2064562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 2074562236bSHarry Wentland 2084562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 2094562236bSHarry Wentland return true; 2104562236bSHarry Wentland 2114562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 2124562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 2134562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 2144562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 2154562236bSHarry Wentland else 2164562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 2174562236bSHarry Wentland 2184562236bSHarry Wentland if (controller_id == underlay_idx) 2194562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 2204562236bSHarry Wentland 2214562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 2224562236bSHarry Wentland 2234562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 2244562236bSHarry Wentland dcb, controller_id + 1, cntl); 2254562236bSHarry Wentland 2264562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 2274562236bSHarry Wentland * by default when command table is called 2284562236bSHarry Wentland * 2294562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 2304562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2314562236bSHarry Wentland * than 3. 2324562236bSHarry Wentland */ 2334562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2344562236bSHarry Wentland dm_write_reg(ctx, 2354562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2364562236bSHarry Wentland 0); 2374562236bSHarry Wentland } 2384562236bSHarry Wentland 2394562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2404562236bSHarry Wentland dce110_init_pte(ctx); 2414562236bSHarry Wentland 2424562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2434562236bSHarry Wentland return true; 2444562236bSHarry Wentland else 2454562236bSHarry Wentland return false; 2464562236bSHarry Wentland } 2474562236bSHarry Wentland 2484562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2493be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2504562236bSHarry Wentland { 2514562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2524562236bSHarry Wentland 2533be5262eSHarry Wentland switch (plane_state->format) { 2541352c779SNicholas Kazlauskas case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2551352c779SNicholas Kazlauskas prescale_params->scale = 0x2082; 2561352c779SNicholas Kazlauskas break; 2574562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2588693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2594562236bSHarry Wentland prescale_params->scale = 0x2020; 2604562236bSHarry Wentland break; 2614562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2624562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2634562236bSHarry Wentland prescale_params->scale = 0x2008; 2644562236bSHarry Wentland break; 2654562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2664562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2674562236bSHarry Wentland prescale_params->scale = 0x2000; 2684562236bSHarry Wentland break; 2694562236bSHarry Wentland default: 2704562236bSHarry Wentland ASSERT(false); 271d7194cf6SAric Cyr break; 2724562236bSHarry Wentland } 2734562236bSHarry Wentland } 2744562236bSHarry Wentland 275a6114e85SHarry Wentland static bool 27678c77382SAnthony Koo dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 2773be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2784562236bSHarry Wentland { 27986a66c4eSHarry Wentland struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2807b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 28190e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 28290e508baSAnthony Koo bool result = true; 28390e508baSAnthony Koo 28490e508baSAnthony Koo if (ipp == NULL) 28590e508baSAnthony Koo return false; 28690e508baSAnthony Koo 2873be5262eSHarry Wentland if (plane_state->in_transfer_func) 2883be5262eSHarry Wentland tf = plane_state->in_transfer_func; 28990e508baSAnthony Koo 2903be5262eSHarry Wentland build_prescale_params(&prescale_params, plane_state); 29190e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 29290e508baSAnthony Koo 29384ffa801SLeo (Sunpeng) Li if (plane_state->gamma_correction && 29484ffa801SLeo (Sunpeng) Li !plane_state->gamma_correction->is_identity && 29584ffa801SLeo (Sunpeng) Li dce_use_lut(plane_state->format)) 2963be5262eSHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 297d7194cf6SAric Cyr 29890e508baSAnthony Koo if (tf == NULL) { 29990e508baSAnthony Koo /* Default case if no input transfer function specified */ 300a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 3017b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 3027b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 30390e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 304a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 30590e508baSAnthony Koo break; 30690e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 307a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 30890e508baSAnthony Koo break; 30990e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 310a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 31190e508baSAnthony Koo break; 31290e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 31390e508baSAnthony Koo default: 31490e508baSAnthony Koo result = false; 315d7194cf6SAric Cyr break; 31690e508baSAnthony Koo } 3177b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 31870063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 31990e508baSAnthony Koo } else { 32090e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 32190e508baSAnthony Koo result = false; 32290e508baSAnthony Koo } 32390e508baSAnthony Koo 32490e508baSAnthony Koo return result; 32590e508baSAnthony Koo } 32690e508baSAnthony Koo 327bd1be8e8SHarry Wentland static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 328fcd2f4bfSAmy Zhang struct curve_points *arr_points, 329fcd2f4bfSAmy Zhang uint32_t hw_points_num) 330fcd2f4bfSAmy Zhang { 331fcd2f4bfSAmy Zhang struct custom_float_format fmt; 332fcd2f4bfSAmy Zhang 333fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 334fcd2f4bfSAmy Zhang 335fcd2f4bfSAmy Zhang uint32_t i = 0; 336fcd2f4bfSAmy Zhang 337fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 338fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 339fcd2f4bfSAmy Zhang fmt.sign = true; 340fcd2f4bfSAmy Zhang 341bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 342fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 343fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 344fcd2f4bfSAmy Zhang return false; 345fcd2f4bfSAmy Zhang } 346fcd2f4bfSAmy Zhang 347bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 348fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 349fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 350fcd2f4bfSAmy Zhang return false; 351fcd2f4bfSAmy Zhang } 352fcd2f4bfSAmy Zhang 353bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 354fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 355fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 356fcd2f4bfSAmy Zhang return false; 357fcd2f4bfSAmy Zhang } 358fcd2f4bfSAmy Zhang 359fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 360fcd2f4bfSAmy Zhang fmt.sign = false; 361fcd2f4bfSAmy Zhang 362bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 363fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 364fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 365fcd2f4bfSAmy Zhang return false; 366fcd2f4bfSAmy Zhang } 367fcd2f4bfSAmy Zhang 368bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 369fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 370fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 371fcd2f4bfSAmy Zhang return false; 372fcd2f4bfSAmy Zhang } 373fcd2f4bfSAmy Zhang 3744d06ccd0SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 3754d06ccd0SHarry Wentland &arr_points[1].custom_float_slope)) { 376fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 377fcd2f4bfSAmy Zhang return false; 378fcd2f4bfSAmy Zhang } 379fcd2f4bfSAmy Zhang 380fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 381fcd2f4bfSAmy Zhang fmt.sign = true; 382fcd2f4bfSAmy Zhang 383fcd2f4bfSAmy Zhang while (i != hw_points_num) { 384bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->red, &fmt, 385fcd2f4bfSAmy Zhang &rgb->red_reg)) { 386fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 387fcd2f4bfSAmy Zhang return false; 388fcd2f4bfSAmy Zhang } 389fcd2f4bfSAmy Zhang 390bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->green, &fmt, 391fcd2f4bfSAmy Zhang &rgb->green_reg)) { 392fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 393fcd2f4bfSAmy Zhang return false; 394fcd2f4bfSAmy Zhang } 395fcd2f4bfSAmy Zhang 396bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->blue, &fmt, 397fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 398fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 399fcd2f4bfSAmy Zhang return false; 400fcd2f4bfSAmy Zhang } 401fcd2f4bfSAmy Zhang 402bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 403fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 404fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 405fcd2f4bfSAmy Zhang return false; 406fcd2f4bfSAmy Zhang } 407fcd2f4bfSAmy Zhang 408bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 409fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 410fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 411fcd2f4bfSAmy Zhang return false; 412fcd2f4bfSAmy Zhang } 413fcd2f4bfSAmy Zhang 414bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 415fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 416fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 417fcd2f4bfSAmy Zhang return false; 418fcd2f4bfSAmy Zhang } 419fcd2f4bfSAmy Zhang 420fcd2f4bfSAmy Zhang ++rgb; 421fcd2f4bfSAmy Zhang ++i; 422fcd2f4bfSAmy Zhang } 423fcd2f4bfSAmy Zhang 424fcd2f4bfSAmy Zhang return true; 425fcd2f4bfSAmy Zhang } 426fcd2f4bfSAmy Zhang 42708616da5SLeo (Sunpeng) Li #define MAX_LOW_POINT 25 4288f8372c7SKrunoslav Kovac #define NUMBER_REGIONS 16 4298f8372c7SKrunoslav Kovac #define NUMBER_SW_SEGMENTS 16 4308f8372c7SKrunoslav Kovac 431b310b081SHarry Wentland static bool 432b310b081SHarry Wentland dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 433b310b081SHarry Wentland struct pwl_params *regamma_params) 434fcd2f4bfSAmy Zhang { 43523ae4f8eSAmy Zhang struct curve_points *arr_points; 43623ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 43723ae4f8eSAmy Zhang struct pwl_result_data *rgb; 43823ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 439fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 440fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 441fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 442fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 443fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 444fcd2f4bfSAmy Zhang 4458f8372c7SKrunoslav Kovac int32_t region_start, region_end; 4468f8372c7SKrunoslav Kovac uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 44723ae4f8eSAmy Zhang 448b310b081SHarry Wentland if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 44923ae4f8eSAmy Zhang return false; 45023ae4f8eSAmy Zhang 45123ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 45223ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 45323ae4f8eSAmy Zhang hw_points = 0; 454fcd2f4bfSAmy Zhang 455fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 456fcd2f4bfSAmy Zhang 457fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 458534db198SAmy Zhang /* 16 segments 459fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 460fcd2f4bfSAmy Zhang */ 46108616da5SLeo (Sunpeng) Li region_start = -11; 46208616da5SLeo (Sunpeng) Li region_end = region_start + NUMBER_REGIONS; 463fcd2f4bfSAmy Zhang 4648f8372c7SKrunoslav Kovac for (i = 0; i < NUMBER_REGIONS; i++) 4658f8372c7SKrunoslav Kovac seg_distr[i] = 4; 466534db198SAmy Zhang 467fcd2f4bfSAmy Zhang } else { 468534db198SAmy Zhang /* 10 segments 469fc6de1c5SLeo (Sunpeng) Li * segment is from 2^-10 to 2^1 470fc6de1c5SLeo (Sunpeng) Li * We include an extra segment for range [2^0, 2^1). This is to 471fc6de1c5SLeo (Sunpeng) Li * ensure that colors with normalized values of 1 don't miss the 472fc6de1c5SLeo (Sunpeng) Li * LUT. 473fcd2f4bfSAmy Zhang */ 4748f8372c7SKrunoslav Kovac region_start = -10; 475fc6de1c5SLeo (Sunpeng) Li region_end = 1; 476534db198SAmy Zhang 4778f8372c7SKrunoslav Kovac seg_distr[0] = 4; 478534db198SAmy Zhang seg_distr[1] = 4; 479534db198SAmy Zhang seg_distr[2] = 4; 480534db198SAmy Zhang seg_distr[3] = 4; 481534db198SAmy Zhang seg_distr[4] = 4; 482534db198SAmy Zhang seg_distr[5] = 4; 483534db198SAmy Zhang seg_distr[6] = 4; 484534db198SAmy Zhang seg_distr[7] = 4; 4858f8372c7SKrunoslav Kovac seg_distr[8] = 4; 4868f8372c7SKrunoslav Kovac seg_distr[9] = 4; 487fc6de1c5SLeo (Sunpeng) Li seg_distr[10] = 0; 488534db198SAmy Zhang seg_distr[11] = -1; 489534db198SAmy Zhang seg_distr[12] = -1; 490534db198SAmy Zhang seg_distr[13] = -1; 491534db198SAmy Zhang seg_distr[14] = -1; 492534db198SAmy Zhang seg_distr[15] = -1; 493fcd2f4bfSAmy Zhang } 494fcd2f4bfSAmy Zhang 495534db198SAmy Zhang for (k = 0; k < 16; k++) { 496534db198SAmy Zhang if (seg_distr[k] != -1) 497534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 498534db198SAmy Zhang } 499534db198SAmy Zhang 500fcd2f4bfSAmy Zhang j = 0; 5018f8372c7SKrunoslav Kovac for (k = 0; k < (region_end - region_start); k++) { 502ec47734aSLeo (Sunpeng) Li increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 5038f8372c7SKrunoslav Kovac start_index = (region_start + k + MAX_LOW_POINT) * 5048f8372c7SKrunoslav Kovac NUMBER_SW_SEGMENTS; 5058f8372c7SKrunoslav Kovac for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 5068f8372c7SKrunoslav Kovac i += increment) { 507534db198SAmy Zhang if (j == hw_points - 1) 508fcd2f4bfSAmy Zhang break; 509fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 510fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 511fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 512fcd2f4bfSAmy Zhang j++; 513fcd2f4bfSAmy Zhang } 514534db198SAmy Zhang } 515534db198SAmy Zhang 516534db198SAmy Zhang /* last point */ 5178f8372c7SKrunoslav Kovac start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 518b310b081SHarry Wentland rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 519b310b081SHarry Wentland rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 520b310b081SHarry Wentland rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 521fcd2f4bfSAmy Zhang 522eb0e5154SDmytro Laktyushkin arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 523eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_start)); 524eb0e5154SDmytro Laktyushkin arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 525eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_end)); 526fcd2f4bfSAmy Zhang 527fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 528fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 529fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 530fcd2f4bfSAmy Zhang 531eb0e5154SDmytro Laktyushkin y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 532fcd2f4bfSAmy Zhang 533fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 534eb0e5154SDmytro Laktyushkin arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 535fcd2f4bfSAmy Zhang arr_points[0].x); 536fcd2f4bfSAmy Zhang 537fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 538fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 539fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 540fcd2f4bfSAmy Zhang 541fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 542fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 543fcd2f4bfSAmy Zhang */ 544eb0e5154SDmytro Laktyushkin y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 545fcd2f4bfSAmy Zhang 546fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 547fcd2f4bfSAmy Zhang 548eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_zero; 549fcd2f4bfSAmy Zhang 550fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 551fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 552fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 553fcd2f4bfSAmy Zhang */ 554eb0e5154SDmytro Laktyushkin const struct fixed31_32 end_value = dc_fixpt_from_int(125); 555fcd2f4bfSAmy Zhang 556eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_div( 557eb0e5154SDmytro Laktyushkin dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 558eb0e5154SDmytro Laktyushkin dc_fixpt_sub(end_value, arr_points[1].x)); 559fcd2f4bfSAmy Zhang } 560fcd2f4bfSAmy Zhang 561fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 562fcd2f4bfSAmy Zhang 56369133b89SAric Cyr k = 0; 56469133b89SAric Cyr for (i = 1; i < 16; i++) { 565534db198SAmy Zhang if (seg_distr[k] != -1) { 566b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 567534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 568b310b081SHarry Wentland regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 569fcd2f4bfSAmy Zhang } 57069133b89SAric Cyr k++; 571534db198SAmy Zhang } 572534db198SAmy Zhang 573534db198SAmy Zhang if (seg_distr[k] != -1) 574b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 575fcd2f4bfSAmy Zhang 57623ae4f8eSAmy Zhang rgb = rgb_resulted; 57723ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 578fcd2f4bfSAmy Zhang 579fcd2f4bfSAmy Zhang i = 1; 580fcd2f4bfSAmy Zhang 581fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 582eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 583fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 584eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 585fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 586eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 587fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 588fcd2f4bfSAmy Zhang 589eb0e5154SDmytro Laktyushkin rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 590eb0e5154SDmytro Laktyushkin rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 591eb0e5154SDmytro Laktyushkin rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 592fcd2f4bfSAmy Zhang 593fcd2f4bfSAmy Zhang ++rgb_plus_1; 594fcd2f4bfSAmy Zhang ++rgb; 595fcd2f4bfSAmy Zhang ++i; 596fcd2f4bfSAmy Zhang } 597fcd2f4bfSAmy Zhang 598fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 599fcd2f4bfSAmy Zhang 600fcd2f4bfSAmy Zhang return true; 601fcd2f4bfSAmy Zhang } 602fcd2f4bfSAmy Zhang 603a6114e85SHarry Wentland static bool 60478c77382SAnthony Koo dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 6050971c40eSHarry Wentland const struct dc_stream_state *stream) 60690e508baSAnthony Koo { 60786a66c4eSHarry Wentland struct transform *xfm = pipe_ctx->plane_res.xfm; 6084562236bSHarry Wentland 6097a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, true); 6107a09f5beSYue Hin Lau xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 6114562236bSHarry Wentland 6124fa086b9SLeo (Sunpeng) Li if (stream->out_transfer_func && 613efd52204SHarry Wentland stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 614efd52204SHarry Wentland stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 6157a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 616efd52204SHarry Wentland } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 617efd52204SHarry Wentland &xfm->regamma_params)) { 6187a09f5beSYue Hin Lau xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 6197a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 6204562236bSHarry Wentland } else { 6217a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 6224562236bSHarry Wentland } 6234562236bSHarry Wentland 6247a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, false); 6254562236bSHarry Wentland 626cc0cb445SLeon Elazar return true; 6274562236bSHarry Wentland } 6284562236bSHarry Wentland 6294562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6304562236bSHarry Wentland { 63102553f57SEric Bernstein bool is_hdmi_tmds; 6326f0db2dcSKrunoslav Kovac bool is_dp; 6336f0db2dcSKrunoslav Kovac 63486e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 63586e2e1beSHersen Wu 6368e9c4c8cSHarry Wentland if (pipe_ctx->stream_res.stream_enc == NULL) 63786e2e1beSHersen Wu return; /* this is not root pipe */ 63886e2e1beSHersen Wu 63902553f57SEric Bernstein is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 6406f0db2dcSKrunoslav Kovac is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 6416f0db2dcSKrunoslav Kovac 64202553f57SEric Bernstein if (!is_hdmi_tmds && !is_dp) 6436f0db2dcSKrunoslav Kovac return; 6446f0db2dcSKrunoslav Kovac 64502553f57SEric Bernstein if (is_hdmi_tmds) 6468e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 6478e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 64896c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6496f0db2dcSKrunoslav Kovac else 6508e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 6518e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 65296c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6534562236bSHarry Wentland } 6544562236bSHarry Wentland 6554562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6564562236bSHarry Wentland { 6574562236bSHarry Wentland enum dc_lane_count lane_count = 658ceb3dbb4SJun Lei pipe_ctx->stream->link->cur_link_settings.lane_count; 6594fa086b9SLeo (Sunpeng) Li struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 660ceb3dbb4SJun Lei struct dc_link *link = pipe_ctx->stream->link; 661f42ea55bSAnthony Koo const struct dc *dc = link->dc; 662f215a57dSEric Yang 6634562236bSHarry Wentland uint32_t active_total_with_borders; 6644562236bSHarry Wentland uint32_t early_control = 0; 6656b670fa9SHarry Wentland struct timing_generator *tg = pipe_ctx->stream_res.tg; 6664562236bSHarry Wentland 667f215a57dSEric Yang /* For MST, there are multiply stream go to only one link. 668f215a57dSEric Yang * connect DIG back_end to front_end while enable_stream and 669f215a57dSEric Yang * disconnect them during disable_stream 670f215a57dSEric Yang * BY this, it is logic clean to separate stream and link */ 671f215a57dSEric Yang link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 672f215a57dSEric Yang pipe_ctx->stream_res.stream_enc->id, true); 673f215a57dSEric Yang 674f42ea55bSAnthony Koo dc->hwss.update_info_frame(pipe_ctx); 675f215a57dSEric Yang 6764562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 6774562236bSHarry Wentland active_total_with_borders = 6784562236bSHarry Wentland timing->h_addressable 6794562236bSHarry Wentland + timing->h_border_left 6804562236bSHarry Wentland + timing->h_border_right; 6814562236bSHarry Wentland 6824562236bSHarry Wentland if (lane_count != 0) 6834562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 6844562236bSHarry Wentland 6854562236bSHarry Wentland if (early_control == 0) 6864562236bSHarry Wentland early_control = lane_count; 6874562236bSHarry Wentland 6884562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 6894562236bSHarry Wentland 6904562236bSHarry Wentland /* enable audio only within mode set */ 691afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 6924562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6938e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 6944562236bSHarry Wentland } 6954562236bSHarry Wentland 696f215a57dSEric Yang 697f215a57dSEric Yang 6984562236bSHarry Wentland 6994562236bSHarry Wentland } 7004562236bSHarry Wentland 7015eefbc40SYue Hin Lau static enum bp_result link_transmitter_control( 70287401969SAndrew Jiang struct dc_bios *bios, 7035eefbc40SYue Hin Lau struct bp_transmitter_control *cntl) 7045eefbc40SYue Hin Lau { 7055eefbc40SYue Hin Lau enum bp_result result; 7065eefbc40SYue Hin Lau 70787401969SAndrew Jiang result = bios->funcs->transmitter_control(bios, cntl); 7085eefbc40SYue Hin Lau 7095eefbc40SYue Hin Lau return result; 7105eefbc40SYue Hin Lau } 7115eefbc40SYue Hin Lau 71287401969SAndrew Jiang /* 71387401969SAndrew Jiang * @brief 71487401969SAndrew Jiang * eDP only. 71587401969SAndrew Jiang */ 7168a31820bSMartin Leung void dce110_edp_wait_for_hpd_ready( 717069d418fSAndrew Jiang struct dc_link *link, 71887401969SAndrew Jiang bool power_up) 71987401969SAndrew Jiang { 720069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 721069d418fSAndrew Jiang struct graphics_object_id connector = link->link_enc->connector; 72287401969SAndrew Jiang struct gpio *hpd; 7236798d042SLewis Huang struct dc_sink *sink = link->local_sink; 72487401969SAndrew Jiang bool edp_hpd_high = false; 72587401969SAndrew Jiang uint32_t time_elapsed = 0; 72687401969SAndrew Jiang uint32_t timeout = power_up ? 72787401969SAndrew Jiang PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 72887401969SAndrew Jiang 72987401969SAndrew Jiang if (dal_graphics_object_id_get_connector_id(connector) 73087401969SAndrew Jiang != CONNECTOR_ID_EDP) { 73187401969SAndrew Jiang BREAK_TO_DEBUGGER(); 73287401969SAndrew Jiang return; 73387401969SAndrew Jiang } 73487401969SAndrew Jiang 73587401969SAndrew Jiang if (!power_up) 73687401969SAndrew Jiang /* 73787401969SAndrew Jiang * From KV, we will not HPD low after turning off VCC - 73887401969SAndrew Jiang * instead, we will check the SW timer in power_up(). 73987401969SAndrew Jiang */ 74087401969SAndrew Jiang return; 74187401969SAndrew Jiang 74287401969SAndrew Jiang /* 74387401969SAndrew Jiang * When we power on/off the eDP panel, 74487401969SAndrew Jiang * we need to wait until SENSE bit is high/low. 74587401969SAndrew Jiang */ 74687401969SAndrew Jiang 74787401969SAndrew Jiang /* obtain HPD */ 74887401969SAndrew Jiang /* TODO what to do with this? */ 74987401969SAndrew Jiang hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 75087401969SAndrew Jiang 75187401969SAndrew Jiang if (!hpd) { 75287401969SAndrew Jiang BREAK_TO_DEBUGGER(); 75387401969SAndrew Jiang return; 75487401969SAndrew Jiang } 75587401969SAndrew Jiang 7566798d042SLewis Huang if (sink != NULL) { 7576798d042SLewis Huang if (sink->edid_caps.panel_patch.extra_t3_ms > 0) { 7586798d042SLewis Huang int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms; 7596798d042SLewis Huang 7606798d042SLewis Huang msleep(extra_t3_in_ms); 7616798d042SLewis Huang } 7626798d042SLewis Huang } 7636798d042SLewis Huang 76487401969SAndrew Jiang dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 76587401969SAndrew Jiang 76687401969SAndrew Jiang /* wait until timeout or panel detected */ 76787401969SAndrew Jiang 76887401969SAndrew Jiang do { 76987401969SAndrew Jiang uint32_t detected = 0; 77087401969SAndrew Jiang 77187401969SAndrew Jiang dal_gpio_get_value(hpd, &detected); 77287401969SAndrew Jiang 77387401969SAndrew Jiang if (!(detected ^ power_up)) { 77487401969SAndrew Jiang edp_hpd_high = true; 77587401969SAndrew Jiang break; 77687401969SAndrew Jiang } 77787401969SAndrew Jiang 77887401969SAndrew Jiang msleep(HPD_CHECK_INTERVAL); 77987401969SAndrew Jiang 78087401969SAndrew Jiang time_elapsed += HPD_CHECK_INTERVAL; 78187401969SAndrew Jiang } while (time_elapsed < timeout); 78287401969SAndrew Jiang 78387401969SAndrew Jiang dal_gpio_close(hpd); 78487401969SAndrew Jiang 78587401969SAndrew Jiang dal_gpio_destroy_irq(&hpd); 78687401969SAndrew Jiang 78787401969SAndrew Jiang if (false == edp_hpd_high) { 7881296423bSBhawanpreet Lakha DC_LOG_ERROR( 78987401969SAndrew Jiang "%s: wait timed out!\n", __func__); 79087401969SAndrew Jiang } 79187401969SAndrew Jiang } 79287401969SAndrew Jiang 7938a31820bSMartin Leung void dce110_edp_power_control( 794069d418fSAndrew Jiang struct dc_link *link, 79587401969SAndrew Jiang bool power_up) 79687401969SAndrew Jiang { 797069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 79887401969SAndrew Jiang struct bp_transmitter_control cntl = { 0 }; 79987401969SAndrew Jiang enum bp_result bp_result; 80087401969SAndrew Jiang 80187401969SAndrew Jiang 802069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 80387401969SAndrew Jiang != CONNECTOR_ID_EDP) { 80487401969SAndrew Jiang BREAK_TO_DEBUGGER(); 80587401969SAndrew Jiang return; 80687401969SAndrew Jiang } 80787401969SAndrew Jiang 808ffadb9d6SAnthony Koo if (!link->panel_cntl) 809904fb6e0SAnthony Koo return; 810904fb6e0SAnthony Koo 811d4caa72eSAnthony Koo if (power_up != 812d4caa72eSAnthony Koo link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 813172c9b77SAshley Thomas 81478d5d04dSCharlene Liu unsigned long long current_ts = dm_get_timestamp(ctx); 815172c9b77SAshley Thomas unsigned long long time_since_edp_poweroff_ms = 81693ed1814SHugo Hu div64_u64(dm_get_elapse_time_in_ns( 81778d5d04dSCharlene Liu ctx, 81878d5d04dSCharlene Liu current_ts, 81993ed1814SHugo Hu link->link_trace.time_stamp.edp_poweroff), 1000000); 820172c9b77SAshley Thomas unsigned long long time_since_edp_poweron_ms = 821172c9b77SAshley Thomas div64_u64(dm_get_elapse_time_in_ns( 822172c9b77SAshley Thomas ctx, 823172c9b77SAshley Thomas current_ts, 824172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron), 1000000); 825172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 826172c9b77SAshley Thomas "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 827172c9b77SAshley Thomas __func__, 828172c9b77SAshley Thomas power_up, 829172c9b77SAshley Thomas current_ts, 830172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 831172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron, 832172c9b77SAshley Thomas time_since_edp_poweroff_ms, 833172c9b77SAshley Thomas time_since_edp_poweron_ms); 83478d5d04dSCharlene Liu 835172c9b77SAshley Thomas /* Send VBIOS command to prompt eDP panel power */ 836172c9b77SAshley Thomas if (power_up) { 837172c9b77SAshley Thomas /* edp requires a min of 500ms from LCDVDD off to on */ 838172c9b77SAshley Thomas unsigned long long remaining_min_edp_poweroff_time_ms = 500; 839ff587987SHugo Hu 840172c9b77SAshley Thomas /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 8416c4fff06SYue Hin Lau if (link->local_sink != NULL) 842172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms += 843172c9b77SAshley Thomas link->local_sink->edid_caps.panel_patch.extra_t12_ms; 84478d5d04dSCharlene Liu 845172c9b77SAshley Thomas /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 846172c9b77SAshley Thomas if (link->link_trace.time_stamp.edp_poweroff != 0) { 847172c9b77SAshley Thomas if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 848172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 849172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 850172c9b77SAshley Thomas else 851172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 0; 85278d5d04dSCharlene Liu } 85378d5d04dSCharlene Liu 854172c9b77SAshley Thomas if (remaining_min_edp_poweroff_time_ms) { 855172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 856172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 857172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 858172c9b77SAshley Thomas msleep(remaining_min_edp_poweroff_time_ms); 859172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 860172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 861172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 862172c9b77SAshley Thomas dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 863172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 864172c9b77SAshley Thomas } else { 865172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 866172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 867172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 868172c9b77SAshley Thomas } 86978d5d04dSCharlene Liu } 87087401969SAndrew Jiang 8711296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 872172c9b77SAshley Thomas "%s: BEGIN: Panel Power action: %s\n", 87387401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 87487401969SAndrew Jiang 87587401969SAndrew Jiang cntl.action = power_up ? 87687401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_ON : 87787401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_OFF; 878069d418fSAndrew Jiang cntl.transmitter = link->link_enc->transmitter; 879069d418fSAndrew Jiang cntl.connector_obj_id = link->link_enc->connector; 88087401969SAndrew Jiang cntl.coherent = false; 88187401969SAndrew Jiang cntl.lanes_number = LANE_COUNT_FOUR; 882069d418fSAndrew Jiang cntl.hpd_sel = link->link_enc->hpd_source; 8838a0e210cSChris Park 8848a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 8858a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 8868a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) 8878a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 8888a0e210cSChris Park LVTMA_CONTROL_POWER_ON); 8898a0e210cSChris Park else 8908a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 8918a0e210cSChris Park LVTMA_CONTROL_POWER_OFF); 8928a0e210cSChris Park } 8938a0e210cSChris Park 89487401969SAndrew Jiang bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 89587401969SAndrew Jiang 896172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 897172c9b77SAshley Thomas "%s: END: Panel Power action: %s bp_result=%u\n", 898172c9b77SAshley Thomas __func__, (power_up ? "On":"Off"), 899172c9b77SAshley Thomas bp_result); 900172c9b77SAshley Thomas 90178d5d04dSCharlene Liu if (!power_up) 90278d5d04dSCharlene Liu /*save driver power off time stamp*/ 90378d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 90478d5d04dSCharlene Liu else 90578d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 90678d5d04dSCharlene Liu 907172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 908172c9b77SAshley Thomas "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 909172c9b77SAshley Thomas __func__, 910172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 911172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron); 912172c9b77SAshley Thomas 91387401969SAndrew Jiang if (bp_result != BP_RESULT_OK) 9141296423bSBhawanpreet Lakha DC_LOG_ERROR( 91587401969SAndrew Jiang "%s: Panel Power bp_result: %d\n", 91687401969SAndrew Jiang __func__, bp_result); 91787401969SAndrew Jiang } else { 9181296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 91987401969SAndrew Jiang "%s: Skipping Panel Power action: %s\n", 92087401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 92187401969SAndrew Jiang } 92287401969SAndrew Jiang } 9235eefbc40SYue Hin Lau 924*cf3a2627SJun Lei void dce110_edp_wait_for_T12( 925*cf3a2627SJun Lei struct dc_link *link) 926*cf3a2627SJun Lei { 927*cf3a2627SJun Lei struct dc_context *ctx = link->ctx; 928*cf3a2627SJun Lei 929*cf3a2627SJun Lei if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 930*cf3a2627SJun Lei != CONNECTOR_ID_EDP) { 931*cf3a2627SJun Lei BREAK_TO_DEBUGGER(); 932*cf3a2627SJun Lei return; 933*cf3a2627SJun Lei } 934*cf3a2627SJun Lei 935*cf3a2627SJun Lei if (!link->panel_cntl) 936*cf3a2627SJun Lei return; 937*cf3a2627SJun Lei 938*cf3a2627SJun Lei if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 939*cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff != 0) { 940*cf3a2627SJun Lei unsigned int t12_duration = 500; // Default T12 as per spec 941*cf3a2627SJun Lei unsigned long long current_ts = dm_get_timestamp(ctx); 942*cf3a2627SJun Lei unsigned long long time_since_edp_poweroff_ms = 943*cf3a2627SJun Lei div64_u64(dm_get_elapse_time_in_ns( 944*cf3a2627SJun Lei ctx, 945*cf3a2627SJun Lei current_ts, 946*cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff), 1000000); 947*cf3a2627SJun Lei 948*cf3a2627SJun Lei t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12 949*cf3a2627SJun Lei 950*cf3a2627SJun Lei if (time_since_edp_poweroff_ms < t12_duration) 951*cf3a2627SJun Lei msleep(t12_duration - time_since_edp_poweroff_ms); 952*cf3a2627SJun Lei } 953*cf3a2627SJun Lei } 954*cf3a2627SJun Lei 9555eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 9565eefbc40SYue Hin Lau /* 9575eefbc40SYue Hin Lau * @brief 9585eefbc40SYue Hin Lau * eDP only. Control the backlight of the eDP panel 9595eefbc40SYue Hin Lau */ 9608a31820bSMartin Leung void dce110_edp_backlight_control( 9615eefbc40SYue Hin Lau struct dc_link *link, 9625eefbc40SYue Hin Lau bool enable) 9635eefbc40SYue Hin Lau { 964069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 9655eefbc40SYue Hin Lau struct bp_transmitter_control cntl = { 0 }; 9665eefbc40SYue Hin Lau 967069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 9685eefbc40SYue Hin Lau != CONNECTOR_ID_EDP) { 9695eefbc40SYue Hin Lau BREAK_TO_DEBUGGER(); 9705eefbc40SYue Hin Lau return; 9715eefbc40SYue Hin Lau } 9725eefbc40SYue Hin Lau 973014427adSSherry if (link->panel_cntl) { 974014427adSSherry bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 975014427adSSherry 976014427adSSherry if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 9771296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 978014427adSSherry "%s: panel already powered up/off. Do nothing.\n", 9795eefbc40SYue Hin Lau __func__); 9805eefbc40SYue Hin Lau return; 9815eefbc40SYue Hin Lau } 982014427adSSherry } 9835eefbc40SYue Hin Lau 9845eefbc40SYue Hin Lau /* Send VBIOS command to control eDP panel backlight */ 9855eefbc40SYue Hin Lau 9861296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 9875eefbc40SYue Hin Lau "%s: backlight action: %s\n", 9885eefbc40SYue Hin Lau __func__, (enable ? "On":"Off")); 9895eefbc40SYue Hin Lau 9905eefbc40SYue Hin Lau cntl.action = enable ? 9915eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_ON : 9925eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_OFF; 99387401969SAndrew Jiang 9945eefbc40SYue Hin Lau /*cntl.engine_id = ctx->engine;*/ 9955eefbc40SYue Hin Lau cntl.transmitter = link->link_enc->transmitter; 9965eefbc40SYue Hin Lau cntl.connector_obj_id = link->link_enc->connector; 9975eefbc40SYue Hin Lau /*todo: unhardcode*/ 9985eefbc40SYue Hin Lau cntl.lanes_number = LANE_COUNT_FOUR; 9995eefbc40SYue Hin Lau cntl.hpd_sel = link->link_enc->hpd_source; 1000cf1835f0SCharlene Liu cntl.signal = SIGNAL_TYPE_EDP; 10015eefbc40SYue Hin Lau 10025eefbc40SYue Hin Lau /* For eDP, the following delays might need to be considered 10035eefbc40SYue Hin Lau * after link training completed: 10045eefbc40SYue Hin Lau * idle period - min. accounts for required BS-Idle pattern, 10055eefbc40SYue Hin Lau * max. allows for source frame synchronization); 10065eefbc40SYue Hin Lau * 50 msec max. delay from valid video data from source 10075eefbc40SYue Hin Lau * to video on dislpay or backlight enable. 10085eefbc40SYue Hin Lau * 10095eefbc40SYue Hin Lau * Disable the delay for now. 10105eefbc40SYue Hin Lau * Enable it in the future if necessary. 10115eefbc40SYue Hin Lau */ 10125eefbc40SYue Hin Lau /* dc_service_sleep_in_milliseconds(50); */ 10135180d4a4SCharlene Liu /*edp 1.2*/ 10145180d4a4SCharlene Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 10155180d4a4SCharlene Liu edp_receiver_ready_T7(link); 10168a0e210cSChris Park 10178a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 10188a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 10198a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 10208a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 10218a0e210cSChris Park LVTMA_CONTROL_LCD_BLON); 10228a0e210cSChris Park else 10238a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 10248a0e210cSChris Park LVTMA_CONTROL_LCD_BLOFF); 10258a0e210cSChris Park } 10268a0e210cSChris Park 1027069d418fSAndrew Jiang link_transmitter_control(ctx->dc_bios, &cntl); 102896577cf8SHersen Wu 102996577cf8SHersen Wu if (enable && link->dpcd_sink_ext_caps.bits.oled) 103096577cf8SHersen Wu msleep(OLED_POST_T7_DELAY); 103196577cf8SHersen Wu 103296577cf8SHersen Wu if (link->dpcd_sink_ext_caps.bits.oled || 103396577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 103496577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 103596577cf8SHersen Wu dc_link_backlight_enable_aux(link, enable); 103696577cf8SHersen Wu 103769b9723aSCharlene Liu /*edp 1.2*/ 10385180d4a4SCharlene Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) 10393a372bedSHugo Hu edp_add_delay_for_T9(link); 104096577cf8SHersen Wu 104196577cf8SHersen Wu if (!enable && link->dpcd_sink_ext_caps.bits.oled) 104296577cf8SHersen Wu msleep(OLED_PRE_T11_DELAY); 10435eefbc40SYue Hin Lau } 10445eefbc40SYue Hin Lau 10451a05873fSAnthony Koo void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 10464562236bSHarry Wentland { 10471a05873fSAnthony Koo /* notify audio driver for audio modes of monitor */ 10482b77dcc5SAnthony Koo struct dc *dc; 10491d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 10501a05873fSAnthony Koo unsigned int i, num_audio = 1; 10511a05873fSAnthony Koo 10521d0610bcSAlvin Lee if (!pipe_ctx->stream) 10531d0610bcSAlvin Lee return; 10541d0610bcSAlvin Lee 10552b77dcc5SAnthony Koo dc = pipe_ctx->stream->ctx->dc; 10562b77dcc5SAnthony Koo clk_mgr = dc->clk_mgr; 10571d0610bcSAlvin Lee 10580a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 10590a32df9cSEryk Brol return; 10600a32df9cSEryk Brol 10611a05873fSAnthony Koo if (pipe_ctx->stream_res.audio) { 10621a05873fSAnthony Koo for (i = 0; i < MAX_PIPES; i++) { 10631a05873fSAnthony Koo /*current_state not updated yet*/ 10642b77dcc5SAnthony Koo if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 10651a05873fSAnthony Koo num_audio++; 10661a05873fSAnthony Koo } 10671a05873fSAnthony Koo 10681a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 10691a05873fSAnthony Koo 1070170a2398SSu Sung Chung if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 10711a05873fSAnthony Koo /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1072170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 10731a05873fSAnthony Koo /* un-mute audio */ 10741a05873fSAnthony Koo /* TODO: audio should be per stream rather than per link */ 10751a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 10761a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, false); 10770a32df9cSEryk Brol if (pipe_ctx->stream_res.audio) 10780a32df9cSEryk Brol pipe_ctx->stream_res.audio->enabled = true; 10791a05873fSAnthony Koo } 10801a05873fSAnthony Koo } 10811a05873fSAnthony Koo 108257430404SSu Sung Chung void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 10831a05873fSAnthony Koo { 10841d0610bcSAlvin Lee struct dc *dc; 10851d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 10861d0610bcSAlvin Lee 10871d0610bcSAlvin Lee if (!pipe_ctx || !pipe_ctx->stream) 10881d0610bcSAlvin Lee return; 10891d0610bcSAlvin Lee 10901d0610bcSAlvin Lee dc = pipe_ctx->stream->ctx->dc; 10911d0610bcSAlvin Lee clk_mgr = dc->clk_mgr; 10924562236bSHarry Wentland 10930a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 10940a32df9cSEryk Brol return; 10950a32df9cSEryk Brol 10962b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 10972b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc, true); 1098afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio) { 10993f52aa9fSNicholas Kazlauskas pipe_ctx->stream_res.audio->enabled = false; 11003f52aa9fSNicholas Kazlauskas 11014562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11028e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 11038e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 11044562236bSHarry Wentland else 11058e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 11068e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 110757430404SSu Sung Chung 1108170a2398SSu Sung Chung if (clk_mgr->funcs->enable_pme_wa) 1109070fe724SCharlene Liu /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1110170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 11114562236bSHarry Wentland 11124562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 11134562236bSHarry Wentland * add audio mode list change flag */ 11144562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 11154562236bSHarry Wentland * stream->stream_engine_id); 11164562236bSHarry Wentland */ 11174562236bSHarry Wentland } 11181a05873fSAnthony Koo } 11194562236bSHarry Wentland 112057430404SSu Sung Chung void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 11211a05873fSAnthony Koo { 11221a05873fSAnthony Koo struct dc_stream_state *stream = pipe_ctx->stream; 1123ceb3dbb4SJun Lei struct dc_link *link = stream->link; 11241a05873fSAnthony Koo struct dc *dc = pipe_ctx->stream->ctx->dc; 11251a05873fSAnthony Koo 1126ac42fd63SWenjing Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 11271a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 11281a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 1129ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1130ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc); 1131ac42fd63SWenjing Liu } 11321a05873fSAnthony Koo 11331a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11341a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 11351a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 11361a05873fSAnthony Koo 113757430404SSu Sung Chung dc->hwss.disable_audio_stream(pipe_ctx); 1138904623eeSYongqiang Sun 11394562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 11404562236bSHarry Wentland link->link_enc, 11418e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->id, 11424562236bSHarry Wentland false); 11434562236bSHarry Wentland 11444562236bSHarry Wentland } 11454562236bSHarry Wentland 11464562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 11474562236bSHarry Wentland struct dc_link_settings *link_settings) 11484562236bSHarry Wentland { 11494562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 115041b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1151ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1152f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 11534562236bSHarry Wentland 11544562236bSHarry Wentland /* only 3 items below are used by unblank */ 11557fe538a4SCharlene Liu params.timing = pipe_ctx->stream->timing; 11564562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 115741b49742SCharlene Liu 115841b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11598e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 116041b49742SCharlene Liu 116114d6f644SYongqiang Sun if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1162f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, true); 116314d6f644SYongqiang Sun } 116441b49742SCharlene Liu } 11652c850b7bSDmytro Laktyushkin 116641b49742SCharlene Liu void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 116741b49742SCharlene Liu { 116841b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1169ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1170f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 117141b49742SCharlene Liu 1172ab892598SRoman Li if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1173f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, false); 11743ba01817SYongqiang Sun link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1175ab892598SRoman Li } 117641b49742SCharlene Liu 1177eec3303dSAric Cyr if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 117841b49742SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 1179eec3303dSAric Cyr 11803a372bedSHugo Hu if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1181eec3303dSAric Cyr /* 1182eec3303dSAric Cyr * After output is idle pattern some sinks need time to recognize the stream 1183eec3303dSAric Cyr * has changed or they enter protection state and hang. 1184eec3303dSAric Cyr */ 1185eec3303dSAric Cyr msleep(60); 11863a372bedSHugo Hu } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) 11873a372bedSHugo Hu edp_receiver_ready_T9(link); 1188eec3303dSAric Cyr } 1189eec3303dSAric Cyr 11904562236bSHarry Wentland } 11914562236bSHarry Wentland 119215e17335SCharlene Liu 119315e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 119415e17335SCharlene Liu { 11958e9c4c8cSHarry Wentland if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 11968e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 119715e17335SCharlene Liu } 119815e17335SCharlene Liu 11994562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 12004562236bSHarry Wentland { 12014562236bSHarry Wentland switch (crtc_id) { 12024562236bSHarry Wentland case CONTROLLER_ID_D0: 12034562236bSHarry Wentland return DTO_SOURCE_ID0; 12044562236bSHarry Wentland case CONTROLLER_ID_D1: 12054562236bSHarry Wentland return DTO_SOURCE_ID1; 12064562236bSHarry Wentland case CONTROLLER_ID_D2: 12074562236bSHarry Wentland return DTO_SOURCE_ID2; 12084562236bSHarry Wentland case CONTROLLER_ID_D3: 12094562236bSHarry Wentland return DTO_SOURCE_ID3; 12104562236bSHarry Wentland case CONTROLLER_ID_D4: 12114562236bSHarry Wentland return DTO_SOURCE_ID4; 12124562236bSHarry Wentland case CONTROLLER_ID_D5: 12134562236bSHarry Wentland return DTO_SOURCE_ID5; 12144562236bSHarry Wentland default: 12154562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 12164562236bSHarry Wentland } 12174562236bSHarry Wentland } 12184562236bSHarry Wentland 12194562236bSHarry Wentland static void build_audio_output( 1220ab8db3e1SAndrey Grodzovsky struct dc_state *state, 12214562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 12224562236bSHarry Wentland struct audio_output *audio_output) 12234562236bSHarry Wentland { 12240971c40eSHarry Wentland const struct dc_stream_state *stream = pipe_ctx->stream; 12258e9c4c8cSHarry Wentland audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 12264562236bSHarry Wentland 12274562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 12284562236bSHarry Wentland 12294562236bSHarry Wentland /* audio_crtc_info */ 12304562236bSHarry Wentland 12314562236bSHarry Wentland audio_output->crtc_info.h_total = 12324fa086b9SLeo (Sunpeng) Li stream->timing.h_total; 12334562236bSHarry Wentland 12344562236bSHarry Wentland /* 12354562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 12364562236bSHarry Wentland * need to specify actual active signal portion 12374562236bSHarry Wentland */ 12384562236bSHarry Wentland audio_output->crtc_info.h_active = 12394fa086b9SLeo (Sunpeng) Li stream->timing.h_addressable 12404fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_left 12414fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_right; 12424562236bSHarry Wentland 12434562236bSHarry Wentland audio_output->crtc_info.v_active = 12444fa086b9SLeo (Sunpeng) Li stream->timing.v_addressable 12454fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_top 12464fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_bottom; 12474562236bSHarry Wentland 12484562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 12494562236bSHarry Wentland 12504562236bSHarry Wentland audio_output->crtc_info.interlaced = 12514fa086b9SLeo (Sunpeng) Li stream->timing.flags.INTERLACE; 12524562236bSHarry Wentland 12534562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 125440fd9090SNevenko Stupar (stream->timing.pix_clk_100hz*100)/ 12554fa086b9SLeo (Sunpeng) Li (stream->timing.h_total*stream->timing.v_total); 12564562236bSHarry Wentland 12574562236bSHarry Wentland audio_output->crtc_info.color_depth = 12584fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth; 12594562236bSHarry Wentland 126040fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 126140fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 12624562236bSHarry Wentland 126340fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 126440fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 12654562236bSHarry Wentland 126687b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 12672166d9fbSCharlene Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 126840fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz == 126940fd9090SNevenko Stupar (stream->timing.pix_clk_100hz)) { 127010688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 127140fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 127240fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz/2; 127340fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 127440fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 127587b58768SCharlene Liu 127687b58768SCharlene Liu } 127787b58768SCharlene Liu } 127887b58768SCharlene Liu 1279ed476602SAhzo if (state->clk_mgr && 1280ed476602SAhzo (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1281ed476602SAhzo pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 12824562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 12830de34efcSDmytro Laktyushkin state->clk_mgr->funcs->get_dp_ref_clk_frequency( 12840de34efcSDmytro Laktyushkin state->clk_mgr); 12854562236bSHarry Wentland } 12864562236bSHarry Wentland 12874562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 12884562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 12894562236bSHarry Wentland 12904562236bSHarry Wentland audio_output->pll_info.dto_source = 12914562236bSHarry Wentland translate_to_dto_source( 1292e07f541fSYongqiang Sun pipe_ctx->stream_res.tg->inst + 1); 12934562236bSHarry Wentland 12944562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 12954562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 12964562236bSHarry Wentland 12974562236bSHarry Wentland audio_output->pll_info.ss_percentage = 12984562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 12994562236bSHarry Wentland } 13004562236bSHarry Wentland 13014562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 13024562236bSHarry Wentland struct tg_color *color) 13034562236bSHarry Wentland { 13042a54bd6eSJerry (Fangzhi) Zuo uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; 13054562236bSHarry Wentland 13066702a9acSHarry Wentland switch (pipe_ctx->plane_res.scl_data.format) { 13074562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 13084562236bSHarry Wentland /* set boarder color to red */ 13094562236bSHarry Wentland color->color_r_cr = color_value; 13104562236bSHarry Wentland break; 13114562236bSHarry Wentland 13124562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 13134562236bSHarry Wentland /* set boarder color to blue */ 13144562236bSHarry Wentland color->color_b_cb = color_value; 13154562236bSHarry Wentland break; 131687449a90SAnthony Koo case PIXEL_FORMAT_420BPP8: 13174562236bSHarry Wentland /* set boarder color to green */ 13184562236bSHarry Wentland color->color_g_y = color_value; 13194562236bSHarry Wentland break; 132087449a90SAnthony Koo case PIXEL_FORMAT_420BPP10: 132187449a90SAnthony Koo /* set boarder color to yellow */ 132287449a90SAnthony Koo color->color_g_y = color_value; 132387449a90SAnthony Koo color->color_r_cr = color_value; 132487449a90SAnthony Koo break; 13254562236bSHarry Wentland case PIXEL_FORMAT_FP16: 13264562236bSHarry Wentland /* set boarder color to white */ 13274562236bSHarry Wentland color->color_r_cr = color_value; 13284562236bSHarry Wentland color->color_b_cb = color_value; 13294562236bSHarry Wentland color->color_g_y = color_value; 13304562236bSHarry Wentland break; 13314562236bSHarry Wentland default: 13324562236bSHarry Wentland break; 13334562236bSHarry Wentland } 13344562236bSHarry Wentland } 13354562236bSHarry Wentland 1336fb3466a4SBhawanpreet Lakha static void program_scaler(const struct dc *dc, 13374562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 13384562236bSHarry Wentland { 13394562236bSHarry Wentland struct tg_color color = {0}; 13404562236bSHarry Wentland 1341b86a1aa3SBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC_DCN) 1342ff5ef992SAlex Deucher /* TOFPGA */ 134386a66c4eSHarry Wentland if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1344ff5ef992SAlex Deucher return; 1345ff5ef992SAlex Deucher #endif 1346ff5ef992SAlex Deucher 1347bf53769dSGloria Li if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 13484562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 13494562236bSHarry Wentland else 13504562236bSHarry Wentland color_space_to_black_color(dc, 13514fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space, 13524562236bSHarry Wentland &color); 13534562236bSHarry Wentland 135486a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 135586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, 13566702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.depth, 13574562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 13584562236bSHarry Wentland 135912750d16SEric Yang if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 136012750d16SEric Yang /* 136112750d16SEric Yang * The way 420 is packed, 2 channels carry Y component, 1 channel 136212750d16SEric Yang * alternate between Cb and Cr, so both channels need the pixel 136312750d16SEric Yang * value for Y 136412750d16SEric Yang */ 136512750d16SEric Yang if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 136612750d16SEric Yang color.color_r_cr = color.color_g_y; 136712750d16SEric Yang 13686b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 13696b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 13704562236bSHarry Wentland &color); 137112750d16SEric Yang } 13724562236bSHarry Wentland 137386a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 13746702a9acSHarry Wentland &pipe_ctx->plane_res.scl_data); 13754562236bSHarry Wentland } 13764562236bSHarry Wentland 13773158223eSEric Bernstein static enum dc_status dce110_enable_stream_timing( 13784562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1379608ac7bbSJerry Zuo struct dc_state *context, 1380fb3466a4SBhawanpreet Lakha struct dc *dc) 13814562236bSHarry Wentland { 13820971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1383608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 13844562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 13854562236bSHarry Wentland struct tg_color black_color = {0}; 13864562236bSHarry Wentland 13874562236bSHarry Wentland if (!pipe_ctx_old->stream) { 13884562236bSHarry Wentland 13894562236bSHarry Wentland /* program blank color */ 13904562236bSHarry Wentland color_space_to_black_color(dc, 13914fa086b9SLeo (Sunpeng) Li stream->output_color_space, &black_color); 13926b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank_color( 13936b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 13944562236bSHarry Wentland &black_color); 13954b5e7d62SHersen Wu 13964562236bSHarry Wentland /* 13974562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 13984562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 13994562236bSHarry Wentland */ 14006b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 14014562236bSHarry Wentland 14024562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 14034562236bSHarry Wentland pipe_ctx->clock_source, 140410688217SHarry Wentland &pipe_ctx->stream_res.pix_clk_params, 14054562236bSHarry Wentland &pipe_ctx->pll_settings)) { 14064562236bSHarry Wentland BREAK_TO_DEBUGGER(); 14074562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 14084562236bSHarry Wentland } 14094562236bSHarry Wentland 14106b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->program_timing( 14116b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14124fa086b9SLeo (Sunpeng) Li &stream->timing, 1413e7e10c46SDmytro Laktyushkin 0, 1414e7e10c46SDmytro Laktyushkin 0, 1415e7e10c46SDmytro Laktyushkin 0, 1416e7e10c46SDmytro Laktyushkin 0, 1417e7e10c46SDmytro Laktyushkin pipe_ctx->stream->signal, 14184562236bSHarry Wentland true); 14194562236bSHarry Wentland } 14204562236bSHarry Wentland 14214562236bSHarry Wentland if (!pipe_ctx_old->stream) { 14226b670fa9SHarry Wentland if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 14236b670fa9SHarry Wentland pipe_ctx->stream_res.tg)) { 14244562236bSHarry Wentland BREAK_TO_DEBUGGER(); 14254562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 14264562236bSHarry Wentland } 14274562236bSHarry Wentland } 14284562236bSHarry Wentland 14294562236bSHarry Wentland return DC_OK; 14304562236bSHarry Wentland } 14314562236bSHarry Wentland 14324562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 14334562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1434608ac7bbSJerry Zuo struct dc_state *context, 1435fb3466a4SBhawanpreet Lakha struct dc *dc) 14364562236bSHarry Wentland { 14370971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 14389c0fb8d4SAnthony Koo struct drr_params params = {0}; 14399c0fb8d4SAnthony Koo unsigned int event_triggers = 0; 1440b1f6d01cSDmytro Laktyushkin struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1441f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 14424562236bSHarry Wentland 1443f42ea55bSAnthony Koo if (hws->funcs.disable_stream_gating) { 1444f42ea55bSAnthony Koo hws->funcs.disable_stream_gating(dc, pipe_ctx); 1445240d09d0SGary Kattan } 1446240d09d0SGary Kattan 14471a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 14481a05873fSAnthony Koo struct audio_output audio_output; 14491a05873fSAnthony Koo 14501a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 14511a05873fSAnthony Koo 14521a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 14531a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 14541a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 14551a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 14561a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 14571a05873fSAnthony Koo else 14581a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 14591a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 14601a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 14611a05873fSAnthony Koo &pipe_ctx->stream->audio_info, 14621a05873fSAnthony Koo &audio_output.crtc_info); 14631a05873fSAnthony Koo 14641a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_configure( 14651a05873fSAnthony Koo pipe_ctx->stream_res.audio, 14661a05873fSAnthony Koo pipe_ctx->stream->signal, 14671a05873fSAnthony Koo &audio_output.crtc_info, 14681a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 14691a05873fSAnthony Koo } 14701a05873fSAnthony Koo 14714562236bSHarry Wentland /* */ 1472d2d7885fSAnthony Koo /* Do not touch stream timing on seamless boot optimization. */ 1473d2d7885fSAnthony Koo if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1474f42ea55bSAnthony Koo hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 14754562236bSHarry Wentland 1476f42ea55bSAnthony Koo if (hws->funcs.setup_vupdate_interrupt) 1477f42ea55bSAnthony Koo hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1478a122b62dSAnthony Koo 14799c0fb8d4SAnthony Koo params.vertical_total_min = stream->adjust.v_total_min; 14809c0fb8d4SAnthony Koo params.vertical_total_max = stream->adjust.v_total_max; 14819c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_drr) 14829c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_drr( 14839c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg, ¶ms); 14849c0fb8d4SAnthony Koo 14859c0fb8d4SAnthony Koo // DRR should set trigger event to monitor surface update event 14869c0fb8d4SAnthony Koo if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 14879c0fb8d4SAnthony Koo event_triggers = 0x80; 14885b5abe95SAnthony Koo /* Event triggers and num frames initialized for DRR, but can be 14895b5abe95SAnthony Koo * later updated for PSR use. Note DRR trigger events are generated 14905b5abe95SAnthony Koo * regardless of whether num frames met. 14915b5abe95SAnthony Koo */ 14929c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 14939c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 14945b5abe95SAnthony Koo pipe_ctx->stream_res.tg, event_triggers, 2); 14959c0fb8d4SAnthony Koo 1496248cbed6SEric Bernstein if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1497d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1498d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc, 1499d2c460e7Shersen wu pipe_ctx->stream_res.tg->inst); 1500aa9c4abeSNikola Cornij 1501f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1502f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp, 1503f0c4d997SCorbin McElhanney COLOR_SPACE_YCBCR601, 1504f0c4d997SCorbin McElhanney stream->timing.display_color_depth, 1505661a8cd9SDmytro Laktyushkin stream->signal); 15064562236bSHarry Wentland 1507a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1508a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 1509181a888fSCharlene Liu &stream->bit_depth_params, 1510181a888fSCharlene Liu &stream->clamping); 1511b1f6d01cSDmytro Laktyushkin while (odm_pipe) { 15127ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 15137ed4e635SHarry Wentland odm_pipe->stream_res.opp, 15147ed4e635SHarry Wentland COLOR_SPACE_YCBCR601, 15157ed4e635SHarry Wentland stream->timing.display_color_depth, 15167ed4e635SHarry Wentland stream->signal); 15177ed4e635SHarry Wentland 15187ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_program_fmt( 15197ed4e635SHarry Wentland odm_pipe->stream_res.opp, 15207ed4e635SHarry Wentland &stream->bit_depth_params, 15217ed4e635SHarry Wentland &stream->clamping); 1522b1f6d01cSDmytro Laktyushkin odm_pipe = odm_pipe->next_odm_pipe; 15237ed4e635SHarry Wentland } 1524603767f9STony Cheng 15251e7e86c4SSamson Tam if (!stream->dpms_off) 1526ab8db3e1SAndrey Grodzovsky core_link_enable_stream(context, pipe_ctx); 15274562236bSHarry Wentland 15286702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 15294562236bSHarry Wentland 1530d1ebfdd8SWyatt Wood pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 153194267b3dSSylvia Tsai 15324562236bSHarry Wentland return DC_OK; 15334562236bSHarry Wentland } 15344562236bSHarry Wentland 15354562236bSHarry Wentland /******************************************************************************/ 15364562236bSHarry Wentland 1537fb3466a4SBhawanpreet Lakha static void power_down_encoders(struct dc *dc) 15384562236bSHarry Wentland { 15394562236bSHarry Wentland int i; 1540b9b171ffSHersen Wu 1541b9b171ffSHersen Wu /* do not know BIOS back-front mapping, simply blank all. It will not 1542b9b171ffSHersen Wu * hurt for non-DP 1543b9b171ffSHersen Wu */ 1544b9b171ffSHersen Wu for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1545b9b171ffSHersen Wu dc->res_pool->stream_enc[i]->funcs->dp_blank( 1546b9b171ffSHersen Wu dc->res_pool->stream_enc[i]); 1547b9b171ffSHersen Wu } 1548b9b171ffSHersen Wu 15494562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 1550d4c2a96fSLewis Huang enum signal_type signal = dc->links[i]->connector_signal; 1551a0c38ebaSCharlene Liu 1552d4c2a96fSLewis Huang if ((signal == SIGNAL_TYPE_EDP) || 1553d4c2a96fSLewis Huang (signal == SIGNAL_TYPE_DISPLAY_PORT)) 1554a0c38ebaSCharlene Liu if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) 1555a0c38ebaSCharlene Liu dp_receiver_power_ctrl(dc->links[i], false); 1556a0c38ebaSCharlene Liu 15574338ffa8SSung Lee if (signal != SIGNAL_TYPE_EDP) 15584338ffa8SSung Lee signal = SIGNAL_TYPE_NONE; 15594338ffa8SSung Lee 15604562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 1561069d418fSAndrew Jiang dc->links[i]->link_enc, signal); 1562b56e90eaSPaul Hsieh 1563b56e90eaSPaul Hsieh dc->links[i]->link_status.link_active = false; 156407920450SJoshua Aberback memset(&dc->links[i]->cur_link_settings, 0, 156507920450SJoshua Aberback sizeof(dc->links[i]->cur_link_settings)); 15664562236bSHarry Wentland } 15674562236bSHarry Wentland } 15684562236bSHarry Wentland 1569fb3466a4SBhawanpreet Lakha static void power_down_controllers(struct dc *dc) 15704562236bSHarry Wentland { 15714562236bSHarry Wentland int i; 15724562236bSHarry Wentland 15737f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 15744562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 15754562236bSHarry Wentland dc->res_pool->timing_generators[i]); 15764562236bSHarry Wentland } 15774562236bSHarry Wentland } 15784562236bSHarry Wentland 1579fb3466a4SBhawanpreet Lakha static void power_down_clock_sources(struct dc *dc) 15804562236bSHarry Wentland { 15814562236bSHarry Wentland int i; 15824562236bSHarry Wentland 15834562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 15844562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 15854562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 15864562236bSHarry Wentland 15874562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 15884562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 15894562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 15904562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 15914562236bSHarry Wentland } 15924562236bSHarry Wentland } 15934562236bSHarry Wentland 1594fb3466a4SBhawanpreet Lakha static void power_down_all_hw_blocks(struct dc *dc) 15954562236bSHarry Wentland { 15964562236bSHarry Wentland power_down_encoders(dc); 15974562236bSHarry Wentland 15984562236bSHarry Wentland power_down_controllers(dc); 15994562236bSHarry Wentland 16004562236bSHarry Wentland power_down_clock_sources(dc); 16011663ae1cSBhawanpreet Lakha 16022f3bfb27SRoman Li if (dc->fbc_compressor) 16031663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 16044562236bSHarry Wentland } 16054562236bSHarry Wentland 16064562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 1607fb3466a4SBhawanpreet Lakha struct dc *dc) 16084562236bSHarry Wentland { 16094562236bSHarry Wentland int i; 16104562236bSHarry Wentland struct timing_generator *tg; 16114562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 16124562236bSHarry Wentland 16137f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 16144562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 16154562236bSHarry Wentland 16160a87425aSTony Cheng if (tg->funcs->disable_vga) 16174562236bSHarry Wentland tg->funcs->disable_vga(tg); 16187f93c1deSCharlene Liu } 16197f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->pipe_count; i++) { 16204562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 16214562236bSHarry Wentland * powergating. */ 16224562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 16234562236bSHarry Wentland true); 16244562236bSHarry Wentland 1625e6c258cbSYongqiang Sun dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 16267f914a62SYongqiang Sun dc->hwss.disable_plane(dc, 1627e6c258cbSYongqiang Sun &dc->current_state->res_ctx.pipe_ctx[i]); 16284562236bSHarry Wentland } 16294562236bSHarry Wentland } 16304562236bSHarry Wentland 16313de5aa81SSivapiriyanKumarasamy 16323de5aa81SSivapiriyanKumarasamy static struct dc_stream_state *get_edp_stream(struct dc_state *context) 16333de5aa81SSivapiriyanKumarasamy { 16343de5aa81SSivapiriyanKumarasamy int i; 16353de5aa81SSivapiriyanKumarasamy 16363de5aa81SSivapiriyanKumarasamy for (i = 0; i < context->stream_count; i++) { 16373de5aa81SSivapiriyanKumarasamy if (context->streams[i]->signal == SIGNAL_TYPE_EDP) 16383de5aa81SSivapiriyanKumarasamy return context->streams[i]; 16393de5aa81SSivapiriyanKumarasamy } 16403de5aa81SSivapiriyanKumarasamy return NULL; 16413de5aa81SSivapiriyanKumarasamy } 16423de5aa81SSivapiriyanKumarasamy 1643be4b289fSSivapiriyanKumarasamy static struct dc_link *get_edp_link_with_sink( 164425292028SYongqiang Sun struct dc *dc, 164525292028SYongqiang Sun struct dc_state *context) 164625292028SYongqiang Sun { 164725292028SYongqiang Sun int i; 164825292028SYongqiang Sun struct dc_link *link = NULL; 164925292028SYongqiang Sun 165025292028SYongqiang Sun /* check if there is an eDP panel not in use */ 165125292028SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 165225292028SYongqiang Sun if (dc->links[i]->local_sink && 165325292028SYongqiang Sun dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 165425292028SYongqiang Sun link = dc->links[i]; 165525292028SYongqiang Sun break; 165625292028SYongqiang Sun } 165725292028SYongqiang Sun } 165825292028SYongqiang Sun 165925292028SYongqiang Sun return link; 166025292028SYongqiang Sun } 166125292028SYongqiang Sun 16624562236bSHarry Wentland /** 16634562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 16644562236bSHarry Wentland * 1. Power down all DC HW blocks 16654562236bSHarry Wentland * 2. Disable VGA engine on all controllers 16664562236bSHarry Wentland * 3. Enable power gating for controller 16674562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 16684562236bSHarry Wentland */ 166925292028SYongqiang Sun void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 16704562236bSHarry Wentland { 1671d82f9942SAnthony Koo int i; 1672be4b289fSSivapiriyanKumarasamy struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context); 1673be4b289fSSivapiriyanKumarasamy struct dc_link *edp_link = get_edp_link(dc); 16743de5aa81SSivapiriyanKumarasamy struct dc_stream_state *edp_stream = NULL; 1675be4b289fSSivapiriyanKumarasamy bool can_apply_edp_fast_boot = false; 1676ce72741bSAnthony Koo bool can_apply_seamless_boot = false; 16773de5aa81SSivapiriyanKumarasamy bool keep_edp_vdd_on = false; 1678f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 1679ce72741bSAnthony Koo 1680f42ea55bSAnthony Koo if (hws->funcs.init_pipes) 1681f42ea55bSAnthony Koo hws->funcs.init_pipes(dc, context); 1682be4b289fSSivapiriyanKumarasamy 16833de5aa81SSivapiriyanKumarasamy edp_stream = get_edp_stream(context); 16843de5aa81SSivapiriyanKumarasamy 1685be4b289fSSivapiriyanKumarasamy // Check fastboot support, disable on DCE8 because of blank screens 1686be4b289fSSivapiriyanKumarasamy if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 && 1687be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_1 && 1688be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_3) { 1689be4b289fSSivapiriyanKumarasamy 1690be4b289fSSivapiriyanKumarasamy // enable fastboot if backend is enabled on eDP 1691be4b289fSSivapiriyanKumarasamy if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) { 16923de5aa81SSivapiriyanKumarasamy /* Set optimization flag on eDP stream*/ 1693ba578afdSChiawen Huang if (edp_stream && edp_link->link_status.link_active) { 16943de5aa81SSivapiriyanKumarasamy edp_stream->apply_edp_fast_boot_optimization = true; 1695be4b289fSSivapiriyanKumarasamy can_apply_edp_fast_boot = true; 1696be4b289fSSivapiriyanKumarasamy } 1697be4b289fSSivapiriyanKumarasamy } 16983de5aa81SSivapiriyanKumarasamy 16993de5aa81SSivapiriyanKumarasamy // We are trying to enable eDP, don't power down VDD 17003de5aa81SSivapiriyanKumarasamy if (edp_stream) 17013de5aa81SSivapiriyanKumarasamy keep_edp_vdd_on = true; 1702be4b289fSSivapiriyanKumarasamy } 1703be4b289fSSivapiriyanKumarasamy 1704be4b289fSSivapiriyanKumarasamy // Check seamless boot support 1705ce72741bSAnthony Koo for (i = 0; i < context->stream_count; i++) { 1706ce72741bSAnthony Koo if (context->streams[i]->apply_seamless_boot_optimization) { 1707ce72741bSAnthony Koo can_apply_seamless_boot = true; 1708ce72741bSAnthony Koo break; 1709ce72741bSAnthony Koo } 1710ce72741bSAnthony Koo } 17114cac1e6dSYongqiang Sun 1712be4b289fSSivapiriyanKumarasamy /* eDP should not have stream in resume from S4 and so even with VBios post 1713be4b289fSSivapiriyanKumarasamy * it should get turned off 17142c37e49aSYongqiang Sun */ 1715be4b289fSSivapiriyanKumarasamy if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 17163de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) { 17174cac1e6dSYongqiang Sun /*turn off backlight before DP_blank and encoder powered down*/ 1718f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1719c5fc7f59SCharlene Liu } 1720c5fc7f59SCharlene Liu /*resume from S3, no vbios posting, no need to power down again*/ 172125292028SYongqiang Sun power_down_all_hw_blocks(dc); 17224562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 17233de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) 1724be4b289fSSivapiriyanKumarasamy dc->hwss.edp_power_control(edp_link_with_sink, false); 1725c5fc7f59SCharlene Liu } 17264562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 17274562236bSHarry Wentland } 17284562236bSHarry Wentland 17294562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 17304562236bSHarry Wentland struct bw_fixed blackout_duration, 17310971c40eSHarry Wentland const struct dc_stream_state *stream) 17324562236bSHarry Wentland { 17334562236bSHarry Wentland uint32_t total_dest_line_time_ns; 17344562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 17354562236bSHarry Wentland 17364562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 17374562236bSHarry Wentland 17384562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 1739380604e2SKen Chalmers (stream->timing.h_total * 10) / 1740380604e2SKen Chalmers stream->timing.pix_clk_100hz + 17414562236bSHarry Wentland pstate_blackout_duration_ns; 17424562236bSHarry Wentland 17434562236bSHarry Wentland return total_dest_line_time_ns; 17444562236bSHarry Wentland } 17454562236bSHarry Wentland 1746f774b339SEric Yang static void dce110_set_displaymarks( 1747fb3466a4SBhawanpreet Lakha const struct dc *dc, 1748608ac7bbSJerry Zuo struct dc_state *context) 17494562236bSHarry Wentland { 17504562236bSHarry Wentland uint8_t i, num_pipes; 17514562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 17524562236bSHarry Wentland 17534562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 17544562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 17554562236bSHarry Wentland uint32_t total_dest_line_time_ns; 17564562236bSHarry Wentland 17574562236bSHarry Wentland if (pipe_ctx->stream == NULL) 17584562236bSHarry Wentland continue; 17594562236bSHarry Wentland 17604562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 176177a4ea53SBhawanpreet Lakha dc->bw_vbios->blackout_duration, pipe_ctx->stream); 176286a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 176386a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1764813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1765813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1766813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1767813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 17684562236bSHarry Wentland total_dest_line_time_ns); 17694562236bSHarry Wentland if (i == underlay_idx) { 17704562236bSHarry Wentland num_pipes++; 177186a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 177286a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1773813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1774813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1775813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 17764562236bSHarry Wentland total_dest_line_time_ns); 17774562236bSHarry Wentland } 17784562236bSHarry Wentland num_pipes++; 17794562236bSHarry Wentland } 17804562236bSHarry Wentland } 17814562236bSHarry Wentland 1782fab55d61SDmytro Laktyushkin void dce110_set_safe_displaymarks( 1783a2b8659dSTony Cheng struct resource_context *res_ctx, 1784a2b8659dSTony Cheng const struct resource_pool *pool) 17854562236bSHarry Wentland { 17864562236bSHarry Wentland int i; 1787a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 17889037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 17894562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 17909037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 17914562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 17923722c794SMikita Lipski struct dce_watermarks min_marks = { 0, 0, 0, 0}; 17934562236bSHarry Wentland 17944562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 17958feabd03SYue Hin Lau if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 17964562236bSHarry Wentland continue; 17974562236bSHarry Wentland 179886a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 179986a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 18004562236bSHarry Wentland nbp_marks, 18014562236bSHarry Wentland max_marks, 18023722c794SMikita Lipski min_marks, 18034562236bSHarry Wentland max_marks, 18044562236bSHarry Wentland MAX_WATERMARK); 18058feabd03SYue Hin Lau 18064562236bSHarry Wentland if (i == underlay_idx) 180786a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 180886a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 18094562236bSHarry Wentland nbp_marks, 18104562236bSHarry Wentland max_marks, 18114562236bSHarry Wentland max_marks, 18124562236bSHarry Wentland MAX_WATERMARK); 18138feabd03SYue Hin Lau 18144562236bSHarry Wentland } 18154562236bSHarry Wentland } 18164562236bSHarry Wentland 18174562236bSHarry Wentland /******************************************************************************* 18184562236bSHarry Wentland * Public functions 18194562236bSHarry Wentland ******************************************************************************/ 18204562236bSHarry Wentland 18214562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 1822470e2ca5SBayan Zabihiyan int num_pipes, unsigned int vmin, unsigned int vmax, 1823470e2ca5SBayan Zabihiyan unsigned int vmid, unsigned int vmid_frame_number) 18244562236bSHarry Wentland { 18254562236bSHarry Wentland int i = 0; 18264562236bSHarry Wentland struct drr_params params = {0}; 182798e6436dSAnthony Koo // DRR should set trigger event to monitor surface update event 182898e6436dSAnthony Koo unsigned int event_triggers = 0x80; 18295b5abe95SAnthony Koo // Note DRR trigger events are generated regardless of whether num frames met. 18305b5abe95SAnthony Koo unsigned int num_frames = 2; 18314562236bSHarry Wentland 18324562236bSHarry Wentland params.vertical_total_max = vmax; 18334562236bSHarry Wentland params.vertical_total_min = vmin; 18344562236bSHarry Wentland 18354562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 183698e6436dSAnthony Koo * some GSL stuff. Static screen triggers may be programmed differently 183798e6436dSAnthony Koo * as well. 18384562236bSHarry Wentland */ 18394562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 184098e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_drr( 184198e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, ¶ms); 184298e6436dSAnthony Koo 184398e6436dSAnthony Koo if (vmax != 0 && vmin != 0) 184498e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 184598e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, 18465b5abe95SAnthony Koo event_triggers, num_frames); 18474562236bSHarry Wentland } 18484562236bSHarry Wentland } 18494562236bSHarry Wentland 185072ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 185172ada5f7SEric Cook int num_pipes, 185272ada5f7SEric Cook struct crtc_position *position) 185372ada5f7SEric Cook { 185472ada5f7SEric Cook int i = 0; 185572ada5f7SEric Cook 185672ada5f7SEric Cook /* TODO: handle pipes > 1 185772ada5f7SEric Cook */ 185872ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 18596b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 186072ada5f7SEric Cook } 186172ada5f7SEric Cook 18624562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 18635b5abe95SAnthony Koo int num_pipes, const struct dc_static_screen_params *params) 18644562236bSHarry Wentland { 18654562236bSHarry Wentland unsigned int i; 18665b5abe95SAnthony Koo unsigned int triggers = 0; 186794267b3dSSylvia Tsai 18685b5abe95SAnthony Koo if (params->triggers.overlay_update) 18695b5abe95SAnthony Koo triggers |= 0x100; 18705b5abe95SAnthony Koo if (params->triggers.surface_update) 18715b5abe95SAnthony Koo triggers |= 0x80; 18725b5abe95SAnthony Koo if (params->triggers.cursor_update) 18735b5abe95SAnthony Koo triggers |= 0x2; 18745b5abe95SAnthony Koo if (params->triggers.force_trigger) 18755b5abe95SAnthony Koo triggers |= 0x1; 18764562236bSHarry Wentland 1877593f79a2SAlex Deucher if (num_pipes) { 1878593f79a2SAlex Deucher struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1879593f79a2SAlex Deucher 1880593f79a2SAlex Deucher if (dc->fbc_compressor) 18815b5abe95SAnthony Koo triggers |= 0x84; 1882593f79a2SAlex Deucher } 1883c3aa1d67SBhawanpreet Lakha 18844562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 18856b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs-> 18865b5abe95SAnthony Koo set_static_screen_control(pipe_ctx[i]->stream_res.tg, 18875b5abe95SAnthony Koo triggers, params->num_frames); 18884562236bSHarry Wentland } 18894562236bSHarry Wentland 1890f6baff4dSHarry Wentland /* 1891690b5e39SRoman Li * Check if FBC can be enabled 1892690b5e39SRoman Li */ 18939c6569deSHarry Wentland static bool should_enable_fbc(struct dc *dc, 18943bc4aaa9SRoman Li struct dc_state *context, 18953bc4aaa9SRoman Li uint32_t *pipe_idx) 1896690b5e39SRoman Li { 18973bc4aaa9SRoman Li uint32_t i; 18983bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = NULL; 18993bc4aaa9SRoman Li struct resource_context *res_ctx = &context->res_ctx; 190065d38262Shersen wu unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 19013bc4aaa9SRoman Li 1902690b5e39SRoman Li 1903690b5e39SRoman Li ASSERT(dc->fbc_compressor); 1904690b5e39SRoman Li 1905690b5e39SRoman Li /* FBC memory should be allocated */ 1906690b5e39SRoman Li if (!dc->ctx->fbc_gpu_addr) 19079c6569deSHarry Wentland return false; 1908690b5e39SRoman Li 1909690b5e39SRoman Li /* Only supports single display */ 1910690b5e39SRoman Li if (context->stream_count != 1) 19119c6569deSHarry Wentland return false; 1912690b5e39SRoman Li 19133bc4aaa9SRoman Li for (i = 0; i < dc->res_pool->pipe_count; i++) { 19143bc4aaa9SRoman Li if (res_ctx->pipe_ctx[i].stream) { 191565d38262Shersen wu 19163bc4aaa9SRoman Li pipe_ctx = &res_ctx->pipe_ctx[i]; 191765d38262Shersen wu 191865d38262Shersen wu if (!pipe_ctx) 191965d38262Shersen wu continue; 192065d38262Shersen wu 192165d38262Shersen wu /* fbc not applicable on underlay pipe */ 192265d38262Shersen wu if (pipe_ctx->pipe_idx != underlay_idx) { 19233bc4aaa9SRoman Li *pipe_idx = i; 19243bc4aaa9SRoman Li break; 19253bc4aaa9SRoman Li } 19263bc4aaa9SRoman Li } 192765d38262Shersen wu } 19283bc4aaa9SRoman Li 192965d38262Shersen wu if (i == dc->res_pool->pipe_count) 193065d38262Shersen wu return false; 193165d38262Shersen wu 1932ceb3dbb4SJun Lei if (!pipe_ctx->stream->link) 193365d38262Shersen wu return false; 19347a840773SRoman Li 1935690b5e39SRoman Li /* Only supports eDP */ 1936ceb3dbb4SJun Lei if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 19379c6569deSHarry Wentland return false; 1938690b5e39SRoman Li 1939690b5e39SRoman Li /* PSR should not be enabled */ 1940d1ebfdd8SWyatt Wood if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 19419c6569deSHarry Wentland return false; 1942690b5e39SRoman Li 194393984bbcSShirish S /* Nothing to compress */ 194493984bbcSShirish S if (!pipe_ctx->plane_state) 19459c6569deSHarry Wentland return false; 194693984bbcSShirish S 194705230fa9SRoman Li /* Only for non-linear tiling */ 194805230fa9SRoman Li if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 19499c6569deSHarry Wentland return false; 195005230fa9SRoman Li 19519c6569deSHarry Wentland return true; 1952690b5e39SRoman Li } 1953690b5e39SRoman Li 1954690b5e39SRoman Li /* 1955690b5e39SRoman Li * Enable FBC 1956690b5e39SRoman Li */ 195765d38262Shersen wu static void enable_fbc( 195865d38262Shersen wu struct dc *dc, 1959608ac7bbSJerry Zuo struct dc_state *context) 1960690b5e39SRoman Li { 19613bc4aaa9SRoman Li uint32_t pipe_idx = 0; 19623bc4aaa9SRoman Li 19633bc4aaa9SRoman Li if (should_enable_fbc(dc, context, &pipe_idx)) { 1964690b5e39SRoman Li /* Program GRPH COMPRESSED ADDRESS and PITCH */ 1965690b5e39SRoman Li struct compr_addr_and_pitch_params params = {0, 0, 0}; 1966690b5e39SRoman Li struct compressor *compr = dc->fbc_compressor; 19673bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 19683bc4aaa9SRoman Li 19699c6569deSHarry Wentland params.source_view_width = pipe_ctx->stream->timing.h_addressable; 19709c6569deSHarry Wentland params.source_view_height = pipe_ctx->stream->timing.v_addressable; 197165d38262Shersen wu params.inst = pipe_ctx->stream_res.tg->inst; 1972690b5e39SRoman Li compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 1973690b5e39SRoman Li 1974690b5e39SRoman Li compr->funcs->surface_address_and_pitch(compr, ¶ms); 1975690b5e39SRoman Li compr->funcs->set_fbc_invalidation_triggers(compr, 1); 1976690b5e39SRoman Li 1977690b5e39SRoman Li compr->funcs->enable_fbc(compr, ¶ms); 1978690b5e39SRoman Li } 1979690b5e39SRoman Li } 1980690b5e39SRoman Li 198154e8695eSDmytro Laktyushkin static void dce110_reset_hw_ctx_wrap( 1982fb3466a4SBhawanpreet Lakha struct dc *dc, 1983608ac7bbSJerry Zuo struct dc_state *context) 19844562236bSHarry Wentland { 19854562236bSHarry Wentland int i; 19864562236bSHarry Wentland 19874562236bSHarry Wentland /* Reset old context */ 19884562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 1989a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 19904562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 1991608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 19924562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 19934562236bSHarry Wentland 19944562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 19954562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 19964562236bSHarry Wentland * PHY when not already disabled. 19974562236bSHarry Wentland */ 19984562236bSHarry Wentland 19994562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 20004562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 20014562236bSHarry Wentland continue; 20024562236bSHarry Wentland 20034562236bSHarry Wentland if (!pipe_ctx->stream || 200454e8695eSDmytro Laktyushkin pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 200521e67d4dSHarry Wentland struct clock_source *old_clk = pipe_ctx_old->clock_source; 200621e67d4dSHarry Wentland 2007827f11e9SLeo (Sunpeng) Li /* Disable if new stream is null. O/w, if stream is 2008827f11e9SLeo (Sunpeng) Li * disabled already, no need to disable again. 2009827f11e9SLeo (Sunpeng) Li */ 201057430404SSu Sung Chung if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 201157430404SSu Sung Chung core_link_disable_stream(pipe_ctx_old); 201257430404SSu Sung Chung 201357430404SSu Sung Chung /* free acquired resources*/ 201457430404SSu Sung Chung if (pipe_ctx_old->stream_res.audio) { 201557430404SSu Sung Chung /*disable az_endpoint*/ 201657430404SSu Sung Chung pipe_ctx_old->stream_res.audio->funcs-> 201757430404SSu Sung Chung az_disable(pipe_ctx_old->stream_res.audio); 201857430404SSu Sung Chung 201957430404SSu Sung Chung /*free audio*/ 202057430404SSu Sung Chung if (dc->caps.dynamic_audio == true) { 202157430404SSu Sung Chung /*we have to dynamic arbitrate the audio endpoints*/ 202257430404SSu Sung Chung /*we free the resource, need reset is_audio_acquired*/ 202357430404SSu Sung Chung update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 202457430404SSu Sung Chung pipe_ctx_old->stream_res.audio, false); 202557430404SSu Sung Chung pipe_ctx_old->stream_res.audio = NULL; 202657430404SSu Sung Chung } 202757430404SSu Sung Chung } 202857430404SSu Sung Chung } 2029d050f8edSHersen Wu 20306b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 20316b670fa9SHarry Wentland if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 203254e8695eSDmytro Laktyushkin dm_error("DC: failed to blank crtc!\n"); 203354e8695eSDmytro Laktyushkin BREAK_TO_DEBUGGER(); 203454e8695eSDmytro Laktyushkin } 20356b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 203686a66c4eSHarry Wentland pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2037608ac7bbSJerry Zuo pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 203854e8695eSDmytro Laktyushkin 2039ad8960a6SMikita Lipski if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2040ad8960a6SMikita Lipski dc->res_pool, 2041ad8960a6SMikita Lipski old_clk)) 204221e67d4dSHarry Wentland old_clk->funcs->cs_power_down(old_clk); 204321e67d4dSHarry Wentland 20447f914a62SYongqiang Sun dc->hwss.disable_plane(dc, pipe_ctx_old); 204554e8695eSDmytro Laktyushkin 204654e8695eSDmytro Laktyushkin pipe_ctx_old->stream = NULL; 204754e8695eSDmytro Laktyushkin } 20484562236bSHarry Wentland } 20494562236bSHarry Wentland } 20504562236bSHarry Wentland 20511a05873fSAnthony Koo static void dce110_setup_audio_dto( 20521a05873fSAnthony Koo struct dc *dc, 20531a05873fSAnthony Koo struct dc_state *context) 20541a05873fSAnthony Koo { 20551a05873fSAnthony Koo int i; 20561a05873fSAnthony Koo 20571a05873fSAnthony Koo /* program audio wall clock. use HDMI as clock source if HDMI 20581a05873fSAnthony Koo * audio active. Otherwise, use DP as clock source 20591a05873fSAnthony Koo * first, loop to find any HDMI audio, if not, loop find DP audio 20601a05873fSAnthony Koo */ 20611a05873fSAnthony Koo /* Setup audio rate clock source */ 20621a05873fSAnthony Koo /* Issue: 20631a05873fSAnthony Koo * Audio lag happened on DP monitor when unplug a HDMI monitor 20641a05873fSAnthony Koo * 20651a05873fSAnthony Koo * Cause: 20661a05873fSAnthony Koo * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 20671a05873fSAnthony Koo * is set to either dto0 or dto1, audio should work fine. 20681a05873fSAnthony Koo * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 20691a05873fSAnthony Koo * set to dto0 will cause audio lag. 20701a05873fSAnthony Koo * 20711a05873fSAnthony Koo * Solution: 20721a05873fSAnthony Koo * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 20731a05873fSAnthony Koo * find first available pipe with audio, setup audio wall DTO per topology 20741a05873fSAnthony Koo * instead of per pipe. 20751a05873fSAnthony Koo */ 20761a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 20771a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 20781a05873fSAnthony Koo 20791a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 20801a05873fSAnthony Koo continue; 20811a05873fSAnthony Koo 20821a05873fSAnthony Koo if (pipe_ctx->top_pipe) 20831a05873fSAnthony Koo continue; 20841a05873fSAnthony Koo if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 20851a05873fSAnthony Koo continue; 20861a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 20871a05873fSAnthony Koo struct audio_output audio_output; 20881a05873fSAnthony Koo 20891a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 20901a05873fSAnthony Koo 20911a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 20921a05873fSAnthony Koo pipe_ctx->stream_res.audio, 20931a05873fSAnthony Koo pipe_ctx->stream->signal, 20941a05873fSAnthony Koo &audio_output.crtc_info, 20951a05873fSAnthony Koo &audio_output.pll_info); 20961a05873fSAnthony Koo break; 20971a05873fSAnthony Koo } 20981a05873fSAnthony Koo } 20991a05873fSAnthony Koo 21001a05873fSAnthony Koo /* no HDMI audio is found, try DP audio */ 21011a05873fSAnthony Koo if (i == dc->res_pool->pipe_count) { 21021a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 21031a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 21041a05873fSAnthony Koo 21051a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 21061a05873fSAnthony Koo continue; 21071a05873fSAnthony Koo 21081a05873fSAnthony Koo if (pipe_ctx->top_pipe) 21091a05873fSAnthony Koo continue; 21101a05873fSAnthony Koo 21111a05873fSAnthony Koo if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 21121a05873fSAnthony Koo continue; 21131a05873fSAnthony Koo 21141a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 21151a05873fSAnthony Koo struct audio_output audio_output; 21161a05873fSAnthony Koo 21171a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 21181a05873fSAnthony Koo 21191a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 21201a05873fSAnthony Koo pipe_ctx->stream_res.audio, 21211a05873fSAnthony Koo pipe_ctx->stream->signal, 21221a05873fSAnthony Koo &audio_output.crtc_info, 21231a05873fSAnthony Koo &audio_output.pll_info); 21241a05873fSAnthony Koo break; 21251a05873fSAnthony Koo } 21261a05873fSAnthony Koo } 21271a05873fSAnthony Koo } 21281a05873fSAnthony Koo } 2129cf437593SDmytro Laktyushkin 21304562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 2131fb3466a4SBhawanpreet Lakha struct dc *dc, 2132608ac7bbSJerry Zuo struct dc_state *context) 21334562236bSHarry Wentland { 2134f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 21354562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 21364562236bSHarry Wentland enum dc_status status; 21374562236bSHarry Wentland int i; 21384562236bSHarry Wentland 21394562236bSHarry Wentland /* Reset old context */ 21404562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 2141f42ea55bSAnthony Koo hws->funcs.reset_hw_ctx_wrap(dc, context); 21424562236bSHarry Wentland 21434562236bSHarry Wentland /* Skip applying if no targets */ 2144ab2541b6SAric Cyr if (context->stream_count <= 0) 21454562236bSHarry Wentland return DC_OK; 21464562236bSHarry Wentland 21474562236bSHarry Wentland /* Apply new context */ 21484562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 21494562236bSHarry Wentland 21504562236bSHarry Wentland /* below is for real asic only */ 2151a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 21524562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2153608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 21544562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 21554562236bSHarry Wentland 21564562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 21574562236bSHarry Wentland continue; 21584562236bSHarry Wentland 21594562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 21604562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 21614562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 21624562236bSHarry Wentland pipe_ctx->clock_source, i); 21634562236bSHarry Wentland continue; 21644562236bSHarry Wentland } 21654562236bSHarry Wentland 2166f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 21674562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 21684562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 21694562236bSHarry Wentland } 21704562236bSHarry Wentland 21712f3bfb27SRoman Li if (dc->fbc_compressor) 21721663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 21735099114bSAlex Deucher 21741a05873fSAnthony Koo dce110_setup_audio_dto(dc, context); 2175ab8812a3SHersen Wu 2176a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2177ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 2178608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 2179ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2180ab8812a3SHersen Wu 2181ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2182ab8812a3SHersen Wu continue; 2183ab8812a3SHersen Wu 2184eed928dcSCharlene Liu if (pipe_ctx->stream == pipe_ctx_old->stream && 2185eed928dcSCharlene Liu pipe_ctx->stream->link->link_state_valid) { 2186ab8812a3SHersen Wu continue; 2187eed928dcSCharlene Liu } 2188ab8812a3SHersen Wu 21895b92d9d4SHarry Wentland if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2190313bf4ffSYongqiang Sun continue; 2191313bf4ffSYongqiang Sun 2192b1f6d01cSDmytro Laktyushkin if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2193ab8812a3SHersen Wu continue; 2194ab8812a3SHersen Wu 21954562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 21964562236bSHarry Wentland pipe_ctx, 21974562236bSHarry Wentland context, 21984562236bSHarry Wentland dc); 21994562236bSHarry Wentland 22004562236bSHarry Wentland if (DC_OK != status) 22014562236bSHarry Wentland return status; 22024562236bSHarry Wentland } 22034562236bSHarry Wentland 2204690b5e39SRoman Li if (dc->fbc_compressor) 220565d38262Shersen wu enable_fbc(dc, dc->current_state); 220665d38262Shersen wu 220765d38262Shersen wu dcb->funcs->set_scratch_critical_state(dcb, false); 2208690b5e39SRoman Li 22094562236bSHarry Wentland return DC_OK; 22104562236bSHarry Wentland } 22114562236bSHarry Wentland 22124562236bSHarry Wentland /******************************************************************************* 22134562236bSHarry Wentland * Front End programming 22144562236bSHarry Wentland ******************************************************************************/ 22154562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 22164562236bSHarry Wentland { 22174562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 22184562236bSHarry Wentland 22194562236bSHarry Wentland default_adjust.force_hw_default = false; 222034996173SHarry Wentland default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 222134996173SHarry Wentland default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 22224562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 22236702a9acSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 22244562236bSHarry Wentland 22254562236bSHarry Wentland /* display color depth */ 22264562236bSHarry Wentland default_adjust.color_depth = 22274fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.display_color_depth; 22284562236bSHarry Wentland 22294562236bSHarry Wentland /* Lb color depth */ 22306702a9acSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 22314562236bSHarry Wentland 223286a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 223386a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, &default_adjust); 22344562236bSHarry Wentland } 22354562236bSHarry Wentland 2236b06b7680SLeon Elazar 2237b06b7680SLeon Elazar /******************************************************************************* 2238b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 2239b06b7680SLeon Elazar * Blender + CRTC 2240b06b7680SLeon Elazar * 2241b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 2242b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 2243b06b7680SLeon Elazar * 2244b06b7680SLeon Elazar * |----------------------------------------------- | 2245b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 2246b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 2247b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 2248b06b7680SLeon Elazar * |------------------------------------------------| 2249b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 2250b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 2251b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 2252b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 2253b06b7680SLeon Elazar * -------------------------------------------------| 2254b06b7680SLeon Elazar * 2255b06b7680SLeon Elazar ******************************************************************************/ 2256fb3466a4SBhawanpreet Lakha static void program_surface_visibility(const struct dc *dc, 22574562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 22584562236bSHarry Wentland { 22594562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2260b06b7680SLeon Elazar bool blank_target = false; 22614562236bSHarry Wentland 22624562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 2263b06b7680SLeon Elazar 2264b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 2265b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2266b06b7680SLeon Elazar 22673be5262eSHarry Wentland if (pipe_ctx->bottom_pipe->plane_state->visible) { 22683be5262eSHarry Wentland if (pipe_ctx->plane_state->visible) 22694562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 22704562236bSHarry Wentland else 22714562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 2272b06b7680SLeon Elazar 22733be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2274b06b7680SLeon Elazar blank_target = true; 2275b06b7680SLeon Elazar 22763be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2277b06b7680SLeon Elazar blank_target = true; 2278b06b7680SLeon Elazar 2279e07f541fSYongqiang Sun dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 22806b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2281b06b7680SLeon Elazar 22824562236bSHarry Wentland } 22834562236bSHarry Wentland 22841bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 22851bf56e62SZeyu Fan { 2286146a9f63SKrunoslav Kovac int i = 0; 22871bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 22881bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 22891bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 22901bf56e62SZeyu Fan 22911bf56e62SZeyu Fan 22924fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 22931bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2294146a9f63SKrunoslav Kovac 2295146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2296146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2297146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 22981bf56e62SZeyu Fan } 22991bf56e62SZeyu Fan 230086a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 23011bf56e62SZeyu Fan } 2302fb3466a4SBhawanpreet Lakha static void update_plane_addr(const struct dc *dc, 23034562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 23044562236bSHarry Wentland { 23053be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 23064562236bSHarry Wentland 23073be5262eSHarry Wentland if (plane_state == NULL) 23084562236bSHarry Wentland return; 23094562236bSHarry Wentland 231086a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 231186a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 23123be5262eSHarry Wentland &plane_state->address, 23133be5262eSHarry Wentland plane_state->flip_immediate); 23144562236bSHarry Wentland 23153be5262eSHarry Wentland plane_state->status.requested_address = plane_state->address; 23164562236bSHarry Wentland } 23174562236bSHarry Wentland 2318f774b339SEric Yang static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 23194562236bSHarry Wentland { 23203be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 23214562236bSHarry Wentland 23223be5262eSHarry Wentland if (plane_state == NULL) 23234562236bSHarry Wentland return; 23244562236bSHarry Wentland 23253be5262eSHarry Wentland plane_state->status.is_flip_pending = 232686a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 232786a66c4eSHarry Wentland pipe_ctx->plane_res.mi); 23284562236bSHarry Wentland 23293be5262eSHarry Wentland if (plane_state->status.is_flip_pending && !plane_state->visible) 233086a66c4eSHarry Wentland pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 23314562236bSHarry Wentland 233286a66c4eSHarry Wentland plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 233386a66c4eSHarry Wentland if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 23346b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 23353be5262eSHarry Wentland plane_state->status.is_right_eye =\ 23366b670fa9SHarry Wentland !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 23377f5c22d1SVitaly Prosyak } 23384562236bSHarry Wentland } 23394562236bSHarry Wentland 2340fb3466a4SBhawanpreet Lakha void dce110_power_down(struct dc *dc) 23414562236bSHarry Wentland { 23424562236bSHarry Wentland power_down_all_hw_blocks(dc); 23434562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 23444562236bSHarry Wentland } 23454562236bSHarry Wentland 23464562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 23474562236bSHarry Wentland struct dc_context *dc_ctx, 23484562236bSHarry Wentland struct timing_generator *tg) 23494562236bSHarry Wentland { 23504562236bSHarry Wentland bool rc = false; 23514562236bSHarry Wentland 23524562236bSHarry Wentland /* To avoid endless loop we wait at most 23534562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 23544562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 23554562236bSHarry Wentland uint32_t i; 23564562236bSHarry Wentland 23574562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 23584562236bSHarry Wentland 23594562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 23604562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 23614562236bSHarry Wentland break; 23624562236bSHarry Wentland } 23634562236bSHarry Wentland 23644562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 23654562236bSHarry Wentland rc = true; 23664562236bSHarry Wentland /* usually occurs at i=1 */ 23674562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 23684562236bSHarry Wentland i); 23694562236bSHarry Wentland break; 23704562236bSHarry Wentland } 23714562236bSHarry Wentland 23724562236bSHarry Wentland /* Wait for one frame. */ 23734562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 23744562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 23754562236bSHarry Wentland } 23764562236bSHarry Wentland 23774562236bSHarry Wentland if (false == rc) 23784562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 23794562236bSHarry Wentland 23804562236bSHarry Wentland return rc; 23814562236bSHarry Wentland } 23824562236bSHarry Wentland 23834562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 23844562236bSHarry Wentland static void dce110_enable_timing_synchronization( 2385fb3466a4SBhawanpreet Lakha struct dc *dc, 23864562236bSHarry Wentland int group_index, 23874562236bSHarry Wentland int group_size, 23884562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 23894562236bSHarry Wentland { 23904562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 23914562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 23924562236bSHarry Wentland int i; 23934562236bSHarry Wentland 23944562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 23954562236bSHarry Wentland 23964562236bSHarry Wentland /* Designate a single TG in the group as a master. 23974562236bSHarry Wentland * Since HW doesn't care which one, we always assign 23984562236bSHarry Wentland * the 1st one in the group. */ 23994562236bSHarry Wentland gsl_params.gsl_group = 0; 24006b670fa9SHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 24014562236bSHarry Wentland 24024562236bSHarry Wentland for (i = 0; i < group_size; i++) 24036b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 24046b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg, &gsl_params); 24054562236bSHarry Wentland 24064562236bSHarry Wentland /* Reset slave controllers on master VSync */ 24074562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 24084562236bSHarry Wentland 24094562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 24106b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2411fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2412fa2123dbSMikita Lipski gsl_params.gsl_group); 24134562236bSHarry Wentland 24144562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 24154562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 24166b670fa9SHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2417fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2418fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg); 24194562236bSHarry Wentland } 24204562236bSHarry Wentland 24214562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 24224562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 24234562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 24244562236bSHarry Wentland for (i = 0; i < group_size; i++) 24256b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 24264562236bSHarry Wentland 24274562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 24284562236bSHarry Wentland } 24294562236bSHarry Wentland 2430fa2123dbSMikita Lipski static void dce110_enable_per_frame_crtc_position_reset( 2431fa2123dbSMikita Lipski struct dc *dc, 2432fa2123dbSMikita Lipski int group_size, 2433fa2123dbSMikita Lipski struct pipe_ctx *grouped_pipes[]) 2434fa2123dbSMikita Lipski { 2435fa2123dbSMikita Lipski struct dc_context *dc_ctx = dc->ctx; 2436fa2123dbSMikita Lipski struct dcp_gsl_params gsl_params = { 0 }; 2437fa2123dbSMikita Lipski int i; 2438fa2123dbSMikita Lipski 2439fa2123dbSMikita Lipski gsl_params.gsl_group = 0; 244037cd85ceSDavid Francis gsl_params.gsl_master = 0; 2441fa2123dbSMikita Lipski 2442fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2443fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2444fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, &gsl_params); 2445fa2123dbSMikita Lipski 2446fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2447fa2123dbSMikita Lipski 2448fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2449fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2450fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2451fa2123dbSMikita Lipski gsl_params.gsl_master, 2452fa2123dbSMikita Lipski &grouped_pipes[i]->stream->triggered_crtc_reset); 2453fa2123dbSMikita Lipski 2454fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2455fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2456fa2123dbSMikita Lipski wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2457fa2123dbSMikita Lipski 2458fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2459fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2460fa2123dbSMikita Lipski 2461fa2123dbSMikita Lipski } 2462fa2123dbSMikita Lipski 2463fb55546eSAnthony Koo static void init_pipes(struct dc *dc, struct dc_state *context) 2464fb55546eSAnthony Koo { 2465fb55546eSAnthony Koo // Do nothing 2466fb55546eSAnthony Koo } 2467fb55546eSAnthony Koo 2468fb3466a4SBhawanpreet Lakha static void init_hw(struct dc *dc) 24694562236bSHarry Wentland { 24704562236bSHarry Wentland int i; 24714562236bSHarry Wentland struct dc_bios *bp; 24724562236bSHarry Wentland struct transform *xfm; 24735e7773a2SAnthony Koo struct abm *abm; 247470d9e8cbSPaul Hsieh struct dmcu *dmcu; 2475f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 24763ba01817SYongqiang Sun uint32_t backlight = MAX_BACKLIGHT_LEVEL; 24774562236bSHarry Wentland 24784562236bSHarry Wentland bp = dc->ctx->dc_bios; 24794562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 24804562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 24814562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 24824562236bSHarry Wentland 2483f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 24844562236bSHarry Wentland dc, i, bp, 24854562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 2486f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 24874562236bSHarry Wentland dc, i, bp, 24884562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 2489f42ea55bSAnthony Koo hws->funcs.enable_display_pipe_clock_gating( 24904562236bSHarry Wentland dc->ctx, 24914562236bSHarry Wentland true); 24924562236bSHarry Wentland } 24934562236bSHarry Wentland 2494e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 24954562236bSHarry Wentland /***************************************/ 24964562236bSHarry Wentland 24974562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 24984562236bSHarry Wentland /****************************************/ 24994562236bSHarry Wentland /* Power up AND update implementation according to the 25004562236bSHarry Wentland * required signal (which may be different from the 25014562236bSHarry Wentland * default signal on connector). */ 2502d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 2503069d418fSAndrew Jiang 25044562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 25054562236bSHarry Wentland } 25064562236bSHarry Wentland 25074562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 25084562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 25094562236bSHarry Wentland 25104562236bSHarry Wentland tg->funcs->disable_vga(tg); 25114562236bSHarry Wentland 25124562236bSHarry Wentland /* Blank controller using driver code instead of 25134562236bSHarry Wentland * command table. */ 25144562236bSHarry Wentland tg->funcs->set_blank(tg, true); 25154b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 25164562236bSHarry Wentland } 25174562236bSHarry Wentland 25184562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 25194562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 25204562236bSHarry Wentland audio->funcs->hw_init(audio); 25214562236bSHarry Wentland } 25225e7773a2SAnthony Koo 25233ba01817SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 25243ba01817SYongqiang Sun struct dc_link *link = dc->links[i]; 25253ba01817SYongqiang Sun 25263ba01817SYongqiang Sun if (link->panel_cntl) 25273ba01817SYongqiang Sun backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 25284562236bSHarry Wentland } 25295099114bSAlex Deucher 25303ba01817SYongqiang Sun abm = dc->res_pool->abm; 25313ba01817SYongqiang Sun if (abm != NULL) 25323ba01817SYongqiang Sun abm->funcs->abm_init(abm, backlight); 25333ba01817SYongqiang Sun 253470d9e8cbSPaul Hsieh dmcu = dc->res_pool->dmcu; 253570d9e8cbSPaul Hsieh if (dmcu != NULL && abm != NULL) 253670d9e8cbSPaul Hsieh abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 253770d9e8cbSPaul Hsieh 25382f3bfb27SRoman Li if (dc->fbc_compressor) 25391663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2540690b5e39SRoman Li 25416728b30cSAnthony Koo } 25424562236bSHarry Wentland 25439566b675SDmytro Laktyushkin 25449566b675SDmytro Laktyushkin void dce110_prepare_bandwidth( 2545fb3466a4SBhawanpreet Lakha struct dc *dc, 25469566b675SDmytro Laktyushkin struct dc_state *context) 2547cf437593SDmytro Laktyushkin { 2548dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 2549fab55d61SDmytro Laktyushkin 2550fab55d61SDmytro Laktyushkin dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2551cf437593SDmytro Laktyushkin 25525a83c932SNicholas Kazlauskas dccg->funcs->update_clocks( 25535a83c932SNicholas Kazlauskas dccg, 255424f7dd7eSDmytro Laktyushkin context, 25559566b675SDmytro Laktyushkin false); 25569566b675SDmytro Laktyushkin } 25579566b675SDmytro Laktyushkin 25589566b675SDmytro Laktyushkin void dce110_optimize_bandwidth( 25599566b675SDmytro Laktyushkin struct dc *dc, 25609566b675SDmytro Laktyushkin struct dc_state *context) 25619566b675SDmytro Laktyushkin { 2562dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 25639566b675SDmytro Laktyushkin 25649566b675SDmytro Laktyushkin dce110_set_displaymarks(dc, context); 25659566b675SDmytro Laktyushkin 25669566b675SDmytro Laktyushkin dccg->funcs->update_clocks( 25679566b675SDmytro Laktyushkin dccg, 25689566b675SDmytro Laktyushkin context, 25699566b675SDmytro Laktyushkin true); 25704562236bSHarry Wentland } 25714562236bSHarry Wentland 25724562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 2573fb3466a4SBhawanpreet Lakha struct dc *dc, struct pipe_ctx *pipe_ctx) 25744562236bSHarry Wentland { 257586a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 25763be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 25774562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 25784562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 25794562236bSHarry Wentland unsigned int i; 2580f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2581f42ea55bSAnthony Koo 25825d4b05ddSBhawanpreet Lakha DC_LOGGER_INIT(); 25834562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 25844562236bSHarry Wentland 25854562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 25864562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 25874562236bSHarry Wentland 2588e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 25894562236bSHarry Wentland 25904562236bSHarry Wentland set_default_colors(pipe_ctx); 25914fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 25924562236bSHarry Wentland == true) { 25934562236bSHarry Wentland tbl_entry.color_space = 25944fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 25954562236bSHarry Wentland 25964562236bSHarry Wentland for (i = 0; i < 12; i++) 25974562236bSHarry Wentland tbl_entry.regval[i] = 25984fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 25994562236bSHarry Wentland 260086a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 260186a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 26024562236bSHarry Wentland } 26034562236bSHarry Wentland 26044fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 26054562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2606146a9f63SKrunoslav Kovac 2607146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2608146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2609146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 26104562236bSHarry Wentland } 26114562236bSHarry Wentland 261286a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 26134562236bSHarry Wentland 26146702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2615c1473558SAndrey Grodzovsky 26164562236bSHarry Wentland program_scaler(dc, pipe_ctx); 26174562236bSHarry Wentland 26184562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 26194562236bSHarry Wentland mi, 26203be5262eSHarry Wentland plane_state->format, 26213be5262eSHarry Wentland &plane_state->tiling_info, 26223be5262eSHarry Wentland &plane_state->plane_size, 26233be5262eSHarry Wentland plane_state->rotation, 2624624d7c47SYongqiang Sun NULL, 26254b28b76bSDmytro Laktyushkin false); 26264b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 26273be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 26284562236bSHarry Wentland 2629fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 26304562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 263186a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 26323be5262eSHarry Wentland plane_state->format, 26333be5262eSHarry Wentland &plane_state->tiling_info, 26343be5262eSHarry Wentland plane_state->rotation); 26354562236bSHarry Wentland 2636067c878aSYongqiang Sun /* Moved programming gamma from dc to hwss */ 2637405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update || 2638405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2639405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.gamma_change) 2640f42ea55bSAnthony Koo hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2641405c50a0SAndrew Jiang 2642405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update) 2643f42ea55bSAnthony Koo hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2644067c878aSYongqiang Sun 26451296423bSBhawanpreet Lakha DC_LOG_SURFACE( 26463032deb5SBhawanpreet Lakha "Pipe:%d %p: addr hi:0x%x, " 26474562236bSHarry Wentland "addr low:0x%x, " 26484562236bSHarry Wentland "src: %d, %d, %d," 26494562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 26504562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 26514562236bSHarry Wentland pipe_ctx->pipe_idx, 26523032deb5SBhawanpreet Lakha (void *) pipe_ctx->plane_state, 26533be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.high_part, 26543be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.low_part, 26553be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.x, 26563be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.y, 26573be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.width, 26583be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.height, 26593be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.x, 26603be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.y, 26613be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.width, 26623be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.height, 26633be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.x, 26643be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.y, 26653be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.width, 26663be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.height); 26674562236bSHarry Wentland 26681296423bSBhawanpreet Lakha DC_LOG_SURFACE( 26694562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 26704562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 26714562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 26724562236bSHarry Wentland pipe_ctx->pipe_idx, 26736702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.width, 26746702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.height, 26756702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.x, 26766702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.y, 26776702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.width, 26786702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.height, 26796702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.x, 26806702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.y); 26814562236bSHarry Wentland } 26824562236bSHarry Wentland 26834562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 2684fb3466a4SBhawanpreet Lakha struct dc *dc, 26853e9ad616SEric Yang const struct dc_stream_state *stream, 26863e9ad616SEric Yang int num_planes, 2687608ac7bbSJerry Zuo struct dc_state *context) 26884562236bSHarry Wentland { 26892194e3aeSRoman Li int i; 26904562236bSHarry Wentland 26913e9ad616SEric Yang if (num_planes == 0) 26924562236bSHarry Wentland return; 26934562236bSHarry Wentland 269465d38262Shersen wu if (dc->fbc_compressor) 269565d38262Shersen wu dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 269665d38262Shersen wu 26973e9ad616SEric Yang for (i = 0; i < dc->res_pool->pipe_count; i++) { 26983dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 26994562236bSHarry Wentland 2700a2607aefSHarry Wentland if (pipe_ctx->stream != stream) 27014562236bSHarry Wentland continue; 27024562236bSHarry Wentland 27033b21b6d2SJerry Zuo /* Need to allocate mem before program front end for Fiji */ 27043b21b6d2SJerry Zuo pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 27053b21b6d2SJerry Zuo pipe_ctx->plane_res.mi, 27063b21b6d2SJerry Zuo pipe_ctx->stream->timing.h_total, 27073b21b6d2SJerry Zuo pipe_ctx->stream->timing.v_total, 2708380604e2SKen Chalmers pipe_ctx->stream->timing.pix_clk_100hz / 10, 27093b21b6d2SJerry Zuo context->stream_count); 27103b21b6d2SJerry Zuo 27114562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 27124f804817SYongqiang Sun 27134f804817SYongqiang Sun dc->hwss.update_plane_addr(dc, pipe_ctx); 27144f804817SYongqiang Sun 2715b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 27164562236bSHarry Wentland 27174562236bSHarry Wentland } 27183dc780ecSYongqiang Sun 271965d38262Shersen wu if (dc->fbc_compressor) 272012a8bd88SShirish S enable_fbc(dc, context); 27214562236bSHarry Wentland } 27224562236bSHarry Wentland 2723bbf5f6c3SAnthony Koo static void dce110_post_unlock_program_front_end( 2724bbf5f6c3SAnthony Koo struct dc *dc, 2725bbf5f6c3SAnthony Koo struct dc_state *context) 2726bbf5f6c3SAnthony Koo { 2727bbf5f6c3SAnthony Koo } 2728009114f6SAnthony Koo 2729e6c258cbSYongqiang Sun static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 27304562236bSHarry Wentland { 2731f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2732bc373a89SRoman Li int fe_idx = pipe_ctx->plane_res.mi ? 2733bc373a89SRoman Li pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2734e6c258cbSYongqiang Sun 27357950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2736608ac7bbSJerry Zuo if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 27374562236bSHarry Wentland return; 27384562236bSHarry Wentland 2739f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 2740cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2741cfe4645eSDmytro Laktyushkin 2742cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2743cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 27444562236bSHarry Wentland } 27454562236bSHarry Wentland 27466be425f3SEric Yang static void dce110_wait_for_mpcc_disconnect( 2747fb3466a4SBhawanpreet Lakha struct dc *dc, 27486be425f3SEric Yang struct resource_pool *res_pool, 27496be425f3SEric Yang struct pipe_ctx *pipe_ctx) 2750b6762f0cSEric Yang { 2751b6762f0cSEric Yang /* do nothing*/ 2752b6762f0cSEric Yang } 2753b6762f0cSEric Yang 27544bd0dc68SJoshua Aberback static void program_output_csc(struct dc *dc, 27554bd0dc68SJoshua Aberback struct pipe_ctx *pipe_ctx, 27564bd0dc68SJoshua Aberback enum dc_color_space colorspace, 27574bd0dc68SJoshua Aberback uint16_t *matrix, 27584bd0dc68SJoshua Aberback int opp_id) 27594bd0dc68SJoshua Aberback { 27604bd0dc68SJoshua Aberback int i; 27614bd0dc68SJoshua Aberback struct out_csc_color_matrix tbl_entry; 27624bd0dc68SJoshua Aberback 27634bd0dc68SJoshua Aberback if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 27644bd0dc68SJoshua Aberback enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 27654bd0dc68SJoshua Aberback 27664bd0dc68SJoshua Aberback for (i = 0; i < 12; i++) 27674bd0dc68SJoshua Aberback tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 27684bd0dc68SJoshua Aberback 27694bd0dc68SJoshua Aberback tbl_entry.color_space = color_space; 27704bd0dc68SJoshua Aberback 27714bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 27724bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm, &tbl_entry); 27734bd0dc68SJoshua Aberback } 27744bd0dc68SJoshua Aberback } 27754bd0dc68SJoshua Aberback 2776faf0389fSJason Yan static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 277733fd17d9SEric Yang { 277833fd17d9SEric Yang struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 277933fd17d9SEric Yang struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 278033fd17d9SEric Yang struct mem_input *mi = pipe_ctx->plane_res.mi; 278133fd17d9SEric Yang struct dc_cursor_mi_param param = { 2782380604e2SKen Chalmers .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 278333d7598dSJun Lei .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 278439a9f4d8SDmytro Laktyushkin .viewport = pipe_ctx->plane_res.scl_data.viewport, 278539a9f4d8SDmytro Laktyushkin .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 278639a9f4d8SDmytro Laktyushkin .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 278708ed681cSDmytro Laktyushkin .rotation = pipe_ctx->plane_state->rotation, 278808ed681cSDmytro Laktyushkin .mirror = pipe_ctx->plane_state->horizontal_mirror 278933fd17d9SEric Yang }; 279033fd17d9SEric Yang 279103a4059bSNicholas Kazlauskas /** 279203a4059bSNicholas Kazlauskas * If the cursor's source viewport is clipped then we need to 279303a4059bSNicholas Kazlauskas * translate the cursor to appear in the correct position on 279403a4059bSNicholas Kazlauskas * the screen. 279503a4059bSNicholas Kazlauskas * 279603a4059bSNicholas Kazlauskas * This translation isn't affected by scaling so it needs to be 279703a4059bSNicholas Kazlauskas * done *after* we adjust the position for the scale factor. 2798033baeeeSNicholas Kazlauskas * 2799033baeeeSNicholas Kazlauskas * This is only done by opt-in for now since there are still 2800033baeeeSNicholas Kazlauskas * some usecases like tiled display that might enable the 2801033baeeeSNicholas Kazlauskas * cursor on both streams while expecting dc to clip it. 280203a4059bSNicholas Kazlauskas */ 2803033baeeeSNicholas Kazlauskas if (pos_cpy.translate_by_source) { 280403a4059bSNicholas Kazlauskas pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 280503a4059bSNicholas Kazlauskas pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2806033baeeeSNicholas Kazlauskas } 280703a4059bSNicholas Kazlauskas 280833fd17d9SEric Yang if (pipe_ctx->plane_state->address.type 280933fd17d9SEric Yang == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 281033fd17d9SEric Yang pos_cpy.enable = false; 281133fd17d9SEric Yang 281233fd17d9SEric Yang if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 281333fd17d9SEric Yang pos_cpy.enable = false; 281433fd17d9SEric Yang 2815dc75dd70SRoman Li if (ipp->funcs->ipp_cursor_set_position) 281633fd17d9SEric Yang ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2817dc75dd70SRoman Li if (mi->funcs->set_cursor_position) 281833fd17d9SEric Yang mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 281933fd17d9SEric Yang } 282033fd17d9SEric Yang 2821faf0389fSJason Yan static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 282233fd17d9SEric Yang { 282333fd17d9SEric Yang struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 282433fd17d9SEric Yang 2825d1aaad05SHarry Wentland if (pipe_ctx->plane_res.ipp && 2826d1aaad05SHarry Wentland pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 282733fd17d9SEric Yang pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 282833fd17d9SEric Yang pipe_ctx->plane_res.ipp, attributes); 282933fd17d9SEric Yang 2830d1aaad05SHarry Wentland if (pipe_ctx->plane_res.mi && 2831d1aaad05SHarry Wentland pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 283233fd17d9SEric Yang pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 283333fd17d9SEric Yang pipe_ctx->plane_res.mi, attributes); 283433fd17d9SEric Yang 2835d1aaad05SHarry Wentland if (pipe_ctx->plane_res.xfm && 2836d1aaad05SHarry Wentland pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 283733fd17d9SEric Yang pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 283833fd17d9SEric Yang pipe_ctx->plane_res.xfm, attributes); 283933fd17d9SEric Yang } 284033fd17d9SEric Yang 28414b0e95d1SYongqiang Sun bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 28424b0e95d1SYongqiang Sun uint32_t backlight_pwm_u16_16, 28434b0e95d1SYongqiang Sun uint32_t frame_ramp) 28444b0e95d1SYongqiang Sun { 28454b0e95d1SYongqiang Sun struct dc_link *link = pipe_ctx->stream->link; 28464b0e95d1SYongqiang Sun struct dc *dc = link->ctx->dc; 28474b0e95d1SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 28483ba01817SYongqiang Sun struct panel_cntl *panel_cntl = link->panel_cntl; 28494b0e95d1SYongqiang Sun struct dmcu *dmcu = dc->res_pool->dmcu; 28504b0e95d1SYongqiang Sun bool fw_set_brightness = true; 28514b0e95d1SYongqiang Sun /* DMCU -1 for all controller id values, 28524b0e95d1SYongqiang Sun * therefore +1 here 28534b0e95d1SYongqiang Sun */ 28544b0e95d1SYongqiang Sun uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 28554b0e95d1SYongqiang Sun 28563ba01817SYongqiang Sun if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 28574b0e95d1SYongqiang Sun return false; 28584b0e95d1SYongqiang Sun 28594b0e95d1SYongqiang Sun if (dmcu) 28604b0e95d1SYongqiang Sun fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 28614b0e95d1SYongqiang Sun 28623ba01817SYongqiang Sun if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 28633ba01817SYongqiang Sun panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 28643ba01817SYongqiang Sun else 28654b0e95d1SYongqiang Sun abm->funcs->set_backlight_level_pwm( 28664b0e95d1SYongqiang Sun abm, 28674b0e95d1SYongqiang Sun backlight_pwm_u16_16, 28684b0e95d1SYongqiang Sun frame_ramp, 28694b0e95d1SYongqiang Sun controller_id, 28703ba01817SYongqiang Sun link->panel_cntl->inst); 28714b0e95d1SYongqiang Sun 28724b0e95d1SYongqiang Sun return true; 28734b0e95d1SYongqiang Sun } 28744b0e95d1SYongqiang Sun 28753ba01817SYongqiang Sun void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 28763ba01817SYongqiang Sun { 28773ba01817SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 28783ba01817SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 28793ba01817SYongqiang Sun 28803ba01817SYongqiang Sun if (abm) 28813ba01817SYongqiang Sun abm->funcs->set_abm_immediate_disable(abm, 28823ba01817SYongqiang Sun pipe_ctx->stream->link->panel_cntl->inst); 28833ba01817SYongqiang Sun 28843ba01817SYongqiang Sun if (panel_cntl) 28853ba01817SYongqiang Sun panel_cntl->funcs->store_backlight_level(panel_cntl); 28863ba01817SYongqiang Sun } 28873ba01817SYongqiang Sun 2888474ac4a8SYongqiang Sun void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 2889474ac4a8SYongqiang Sun { 2890474ac4a8SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 2891474ac4a8SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 2892474ac4a8SYongqiang Sun uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 2893474ac4a8SYongqiang Sun 2894474ac4a8SYongqiang Sun if (abm && panel_cntl) 2895474ac4a8SYongqiang Sun abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 2896474ac4a8SYongqiang Sun } 2897474ac4a8SYongqiang Sun 28984562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 28991bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 29004bd0dc68SJoshua Aberback .program_output_csc = program_output_csc, 29014562236bSHarry Wentland .init_hw = init_hw, 29024562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 29034562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 2904bbf5f6c3SAnthony Koo .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 29054562236bSHarry Wentland .update_plane_addr = update_plane_addr, 29064562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 29074562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 29084562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 2909fa2123dbSMikita Lipski .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 29104562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 29114562236bSHarry Wentland .enable_stream = dce110_enable_stream, 29124562236bSHarry Wentland .disable_stream = dce110_disable_stream, 29134562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 291441b49742SCharlene Liu .blank_stream = dce110_blank_stream, 29151a05873fSAnthony Koo .enable_audio_stream = dce110_enable_audio_stream, 29161a05873fSAnthony Koo .disable_audio_stream = dce110_disable_audio_stream, 29177f914a62SYongqiang Sun .disable_plane = dce110_power_down_fe, 29184562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 2919009114f6SAnthony Koo .interdependent_update_lock = NULL, 29201e461c37SAric Cyr .cursor_lock = dce_pipe_control_lock, 29219566b675SDmytro Laktyushkin .prepare_bandwidth = dce110_prepare_bandwidth, 29229566b675SDmytro Laktyushkin .optimize_bandwidth = dce110_optimize_bandwidth, 29234562236bSHarry Wentland .set_drr = set_drr, 292472ada5f7SEric Cook .get_position = get_position, 29254562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 292615e17335SCharlene Liu .setup_stereo = NULL, 292715e17335SCharlene Liu .set_avmute = dce110_set_avmute, 292841f97c07SHersen Wu .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 2929099303e9SPeikang Zhang .edp_backlight_control = dce110_edp_backlight_control, 29308a31820bSMartin Leung .edp_power_control = dce110_edp_power_control, 29318a31820bSMartin Leung .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 293233fd17d9SEric Yang .set_cursor_position = dce110_set_cursor_position, 29334b0e95d1SYongqiang Sun .set_cursor_attribute = dce110_set_cursor_attribute, 29344b0e95d1SYongqiang Sun .set_backlight_level = dce110_set_backlight_level, 29353ba01817SYongqiang Sun .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 2936474ac4a8SYongqiang Sun .set_pipe = dce110_set_pipe, 29374562236bSHarry Wentland }; 29384562236bSHarry Wentland 2939f42ea55bSAnthony Koo static const struct hwseq_private_funcs dce110_private_funcs = { 2940f42ea55bSAnthony Koo .init_pipes = init_pipes, 2941f42ea55bSAnthony Koo .update_plane_addr = update_plane_addr, 2942f42ea55bSAnthony Koo .set_input_transfer_func = dce110_set_input_transfer_func, 2943f42ea55bSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 2944f42ea55bSAnthony Koo .power_down = dce110_power_down, 2945f42ea55bSAnthony Koo .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 2946f42ea55bSAnthony Koo .enable_display_power_gating = dce110_enable_display_power_gating, 2947f42ea55bSAnthony Koo .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 2948f42ea55bSAnthony Koo .enable_stream_timing = dce110_enable_stream_timing, 2949f42ea55bSAnthony Koo .disable_stream_gating = NULL, 2950f42ea55bSAnthony Koo .enable_stream_gating = NULL, 2951f42ea55bSAnthony Koo .edp_backlight_control = dce110_edp_backlight_control, 2952f42ea55bSAnthony Koo }; 2953f42ea55bSAnthony Koo 2954c13b408bSDave Airlie void dce110_hw_sequencer_construct(struct dc *dc) 29554562236bSHarry Wentland { 29564562236bSHarry Wentland dc->hwss = dce110_funcs; 2957f42ea55bSAnthony Koo dc->hwseq->funcs = dce110_private_funcs; 29584562236bSHarry Wentland } 29594562236bSHarry Wentland 2960