14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland #include "dm_services.h" 264562236bSHarry Wentland #include "dc.h" 274562236bSHarry Wentland #include "dc_bios_types.h" 284562236bSHarry Wentland #include "core_types.h" 294562236bSHarry Wentland #include "core_status.h" 304562236bSHarry Wentland #include "resource.h" 314562236bSHarry Wentland #include "dm_helpers.h" 324562236bSHarry Wentland #include "dce110_hw_sequencer.h" 334562236bSHarry Wentland #include "dce110_timing_generator.h" 3498489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 354562236bSHarry Wentland 361663ae1cSBhawanpreet Lakha #ifdef ENABLE_FBC 371663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 381663ae1cSBhawanpreet Lakha #endif 391663ae1cSBhawanpreet Lakha 404562236bSHarry Wentland #include "bios/bios_parser_helper.h" 414562236bSHarry Wentland #include "timing_generator.h" 424562236bSHarry Wentland #include "mem_input.h" 434562236bSHarry Wentland #include "opp.h" 444562236bSHarry Wentland #include "ipp.h" 454562236bSHarry Wentland #include "transform.h" 464562236bSHarry Wentland #include "stream_encoder.h" 474562236bSHarry Wentland #include "link_encoder.h" 484562236bSHarry Wentland #include "clock_source.h" 495e7773a2SAnthony Koo #include "abm.h" 504562236bSHarry Wentland #include "audio.h" 514562236bSHarry Wentland #include "dce/dce_hwseq.h" 5208b16886SZeyu Fan #include "reg_helper.h" 534562236bSHarry Wentland 544562236bSHarry Wentland /* include DCE11 register header files */ 554562236bSHarry Wentland #include "dce/dce_11_0_d.h" 564562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 57e266fdf6SVitaly Prosyak #include "custom_float.h" 584562236bSHarry Wentland 594562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 604562236bSHarry Wentland uint32_t crtc; 614562236bSHarry Wentland }; 624562236bSHarry Wentland 634562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 644562236bSHarry Wentland { 654562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 664562236bSHarry Wentland }, 674562236bSHarry Wentland { 684562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 694562236bSHarry Wentland }, 704562236bSHarry Wentland { 714562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 724562236bSHarry Wentland }, 734562236bSHarry Wentland { 744562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 754562236bSHarry Wentland } 764562236bSHarry Wentland }; 774562236bSHarry Wentland 784562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 794562236bSHarry Wentland (reg + reg_offsets[id].blnd) 804562236bSHarry Wentland 814562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 824562236bSHarry Wentland (reg + reg_offsets[id].crtc) 834562236bSHarry Wentland 844562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 854562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 864562236bSHarry Wentland 874562236bSHarry Wentland /******************************************************************************* 884562236bSHarry Wentland * Private definitions 894562236bSHarry Wentland ******************************************************************************/ 904562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 914562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 924562236bSHarry Wentland { 934562236bSHarry Wentland uint32_t addr; 944562236bSHarry Wentland uint32_t value = 0; 954562236bSHarry Wentland uint32_t chunk_int = 0; 964562236bSHarry Wentland uint32_t chunk_mul = 0; 974562236bSHarry Wentland 984562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 994562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1004562236bSHarry Wentland 1014562236bSHarry Wentland set_reg_field_value( 1024562236bSHarry Wentland value, 1034562236bSHarry Wentland 0, 1044562236bSHarry Wentland DVMM_PTE_CONTROL, 1054562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1064562236bSHarry Wentland 1074562236bSHarry Wentland set_reg_field_value( 1084562236bSHarry Wentland value, 1094562236bSHarry Wentland 1, 1104562236bSHarry Wentland DVMM_PTE_CONTROL, 1114562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1124562236bSHarry Wentland 1134562236bSHarry Wentland set_reg_field_value( 1144562236bSHarry Wentland value, 1154562236bSHarry Wentland 1, 1164562236bSHarry Wentland DVMM_PTE_CONTROL, 1174562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1184562236bSHarry Wentland 1194562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1204562236bSHarry Wentland 1214562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1224562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1234562236bSHarry Wentland 1244562236bSHarry Wentland chunk_int = get_reg_field_value( 1254562236bSHarry Wentland value, 1264562236bSHarry Wentland DVMM_PTE_REQ, 1274562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1284562236bSHarry Wentland 1294562236bSHarry Wentland chunk_mul = get_reg_field_value( 1304562236bSHarry Wentland value, 1314562236bSHarry Wentland DVMM_PTE_REQ, 1324562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1334562236bSHarry Wentland 1344562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1354562236bSHarry Wentland 1364562236bSHarry Wentland set_reg_field_value( 1374562236bSHarry Wentland value, 1384562236bSHarry Wentland 255, 1394562236bSHarry Wentland DVMM_PTE_REQ, 1404562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1414562236bSHarry Wentland 1424562236bSHarry Wentland set_reg_field_value( 1434562236bSHarry Wentland value, 1444562236bSHarry Wentland 4, 1454562236bSHarry Wentland DVMM_PTE_REQ, 1464562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1474562236bSHarry Wentland 1484562236bSHarry Wentland set_reg_field_value( 1494562236bSHarry Wentland value, 1504562236bSHarry Wentland 4, 1514562236bSHarry Wentland DVMM_PTE_REQ, 1524562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1534562236bSHarry Wentland 1544562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1554562236bSHarry Wentland } 1564562236bSHarry Wentland } 1574562236bSHarry Wentland /**************************************************************************/ 1584562236bSHarry Wentland 1594562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1604562236bSHarry Wentland struct dc_context *ctx, 1614562236bSHarry Wentland bool clock_gating) 1624562236bSHarry Wentland { 1634562236bSHarry Wentland /*TODO*/ 1644562236bSHarry Wentland } 1654562236bSHarry Wentland 1664562236bSHarry Wentland static bool dce110_enable_display_power_gating( 1674562236bSHarry Wentland struct core_dc *dc, 1684562236bSHarry Wentland uint8_t controller_id, 1694562236bSHarry Wentland struct dc_bios *dcb, 1704562236bSHarry Wentland enum pipe_gating_control power_gating) 1714562236bSHarry Wentland { 1724562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 1734562236bSHarry Wentland enum bp_pipe_control_action cntl; 1744562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 1754562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1764562236bSHarry Wentland 1774562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1784562236bSHarry Wentland return true; 1794562236bSHarry Wentland 1804562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 1814562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 1824562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 1834562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 1844562236bSHarry Wentland else 1854562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 1864562236bSHarry Wentland 1874562236bSHarry Wentland if (controller_id == underlay_idx) 1884562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 1894562236bSHarry Wentland 1904562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 1914562236bSHarry Wentland 1924562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 1934562236bSHarry Wentland dcb, controller_id + 1, cntl); 1944562236bSHarry Wentland 1954562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 1964562236bSHarry Wentland * by default when command table is called 1974562236bSHarry Wentland * 1984562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 1994562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2004562236bSHarry Wentland * than 3. 2014562236bSHarry Wentland */ 2024562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2034562236bSHarry Wentland dm_write_reg(ctx, 2044562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2054562236bSHarry Wentland 0); 2064562236bSHarry Wentland } 2074562236bSHarry Wentland 2084562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2094562236bSHarry Wentland dce110_init_pte(ctx); 2104562236bSHarry Wentland 2114562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2124562236bSHarry Wentland return true; 2134562236bSHarry Wentland else 2144562236bSHarry Wentland return false; 2154562236bSHarry Wentland } 2164562236bSHarry Wentland 2174562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 218e12cfcb1SHarry Wentland const struct dc_surface *surface) 2194562236bSHarry Wentland { 2204562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2214562236bSHarry Wentland 222e12cfcb1SHarry Wentland switch (surface->format) { 2234562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2248693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2254562236bSHarry Wentland prescale_params->scale = 0x2020; 2264562236bSHarry Wentland break; 2274562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2284562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2294562236bSHarry Wentland prescale_params->scale = 0x2008; 2304562236bSHarry Wentland break; 2314562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2324562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2334562236bSHarry Wentland prescale_params->scale = 0x2000; 2344562236bSHarry Wentland break; 2354562236bSHarry Wentland default: 2364562236bSHarry Wentland ASSERT(false); 237d7194cf6SAric Cyr break; 2384562236bSHarry Wentland } 2394562236bSHarry Wentland } 2404562236bSHarry Wentland 241d7194cf6SAric Cyr static bool dce110_set_input_transfer_func( 242fb735a9fSAnthony Koo struct pipe_ctx *pipe_ctx, 243e12cfcb1SHarry Wentland const struct dc_surface *surface) 2444562236bSHarry Wentland { 245fb735a9fSAnthony Koo struct input_pixel_processor *ipp = pipe_ctx->ipp; 2467b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 24790e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 24890e508baSAnthony Koo bool result = true; 24990e508baSAnthony Koo 25090e508baSAnthony Koo if (ipp == NULL) 25190e508baSAnthony Koo return false; 25290e508baSAnthony Koo 253e12cfcb1SHarry Wentland if (surface->in_transfer_func) 254e12cfcb1SHarry Wentland tf = surface->in_transfer_func; 25590e508baSAnthony Koo 25690e508baSAnthony Koo build_prescale_params(&prescale_params, surface); 25790e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 25890e508baSAnthony Koo 259e12cfcb1SHarry Wentland if (surface->gamma_correction && dce_use_lut(surface)) 260e12cfcb1SHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, surface->gamma_correction); 261d7194cf6SAric Cyr 26290e508baSAnthony Koo if (tf == NULL) { 26390e508baSAnthony Koo /* Default case if no input transfer function specified */ 26490e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 265306dadf0SAmy Zhang IPP_DEGAMMA_MODE_HW_sRGB); 2667b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 2677b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 26890e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 26990e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 27090e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_sRGB); 27190e508baSAnthony Koo break; 27290e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 27390e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 27490e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_xvYCC); 27590e508baSAnthony Koo break; 27690e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 27790e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 27890e508baSAnthony Koo IPP_DEGAMMA_MODE_BYPASS); 27990e508baSAnthony Koo break; 28090e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 28190e508baSAnthony Koo result = false; 28290e508baSAnthony Koo break; 28390e508baSAnthony Koo default: 28490e508baSAnthony Koo result = false; 285d7194cf6SAric Cyr break; 28690e508baSAnthony Koo } 2877b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 28870063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 28990e508baSAnthony Koo } else { 29090e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 29190e508baSAnthony Koo result = false; 29290e508baSAnthony Koo } 29390e508baSAnthony Koo 29490e508baSAnthony Koo return result; 29590e508baSAnthony Koo } 29690e508baSAnthony Koo 297fcd2f4bfSAmy Zhang static bool convert_to_custom_float( 298fcd2f4bfSAmy Zhang struct pwl_result_data *rgb_resulted, 299fcd2f4bfSAmy Zhang struct curve_points *arr_points, 300fcd2f4bfSAmy Zhang uint32_t hw_points_num) 301fcd2f4bfSAmy Zhang { 302fcd2f4bfSAmy Zhang struct custom_float_format fmt; 303fcd2f4bfSAmy Zhang 304fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 305fcd2f4bfSAmy Zhang 306fcd2f4bfSAmy Zhang uint32_t i = 0; 307fcd2f4bfSAmy Zhang 308fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 309fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 310fcd2f4bfSAmy Zhang fmt.sign = true; 311fcd2f4bfSAmy Zhang 312fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 313fcd2f4bfSAmy Zhang arr_points[0].x, 314fcd2f4bfSAmy Zhang &fmt, 315fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 316fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 317fcd2f4bfSAmy Zhang return false; 318fcd2f4bfSAmy Zhang } 319fcd2f4bfSAmy Zhang 320fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 321fcd2f4bfSAmy Zhang arr_points[0].offset, 322fcd2f4bfSAmy Zhang &fmt, 323fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 324fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 325fcd2f4bfSAmy Zhang return false; 326fcd2f4bfSAmy Zhang } 327fcd2f4bfSAmy Zhang 328fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 329fcd2f4bfSAmy Zhang arr_points[0].slope, 330fcd2f4bfSAmy Zhang &fmt, 331fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 332fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 333fcd2f4bfSAmy Zhang return false; 334fcd2f4bfSAmy Zhang } 335fcd2f4bfSAmy Zhang 336fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 337fcd2f4bfSAmy Zhang fmt.sign = false; 338fcd2f4bfSAmy Zhang 339fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 340fcd2f4bfSAmy Zhang arr_points[1].x, 341fcd2f4bfSAmy Zhang &fmt, 342fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 343fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 344fcd2f4bfSAmy Zhang return false; 345fcd2f4bfSAmy Zhang } 346fcd2f4bfSAmy Zhang 347fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 348fcd2f4bfSAmy Zhang arr_points[1].y, 349fcd2f4bfSAmy Zhang &fmt, 350fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 351fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 352fcd2f4bfSAmy Zhang return false; 353fcd2f4bfSAmy Zhang } 354fcd2f4bfSAmy Zhang 355fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 356fcd2f4bfSAmy Zhang arr_points[2].slope, 357fcd2f4bfSAmy Zhang &fmt, 358fcd2f4bfSAmy Zhang &arr_points[2].custom_float_slope)) { 359fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 360fcd2f4bfSAmy Zhang return false; 361fcd2f4bfSAmy Zhang } 362fcd2f4bfSAmy Zhang 363fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 364fcd2f4bfSAmy Zhang fmt.sign = true; 365fcd2f4bfSAmy Zhang 366fcd2f4bfSAmy Zhang while (i != hw_points_num) { 367fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 368fcd2f4bfSAmy Zhang rgb->red, 369fcd2f4bfSAmy Zhang &fmt, 370fcd2f4bfSAmy Zhang &rgb->red_reg)) { 371fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 372fcd2f4bfSAmy Zhang return false; 373fcd2f4bfSAmy Zhang } 374fcd2f4bfSAmy Zhang 375fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 376fcd2f4bfSAmy Zhang rgb->green, 377fcd2f4bfSAmy Zhang &fmt, 378fcd2f4bfSAmy Zhang &rgb->green_reg)) { 379fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 380fcd2f4bfSAmy Zhang return false; 381fcd2f4bfSAmy Zhang } 382fcd2f4bfSAmy Zhang 383fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 384fcd2f4bfSAmy Zhang rgb->blue, 385fcd2f4bfSAmy Zhang &fmt, 386fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 387fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 388fcd2f4bfSAmy Zhang return false; 389fcd2f4bfSAmy Zhang } 390fcd2f4bfSAmy Zhang 391fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 392fcd2f4bfSAmy Zhang rgb->delta_red, 393fcd2f4bfSAmy Zhang &fmt, 394fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 395fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 396fcd2f4bfSAmy Zhang return false; 397fcd2f4bfSAmy Zhang } 398fcd2f4bfSAmy Zhang 399fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 400fcd2f4bfSAmy Zhang rgb->delta_green, 401fcd2f4bfSAmy Zhang &fmt, 402fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 403fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 404fcd2f4bfSAmy Zhang return false; 405fcd2f4bfSAmy Zhang } 406fcd2f4bfSAmy Zhang 407fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 408fcd2f4bfSAmy Zhang rgb->delta_blue, 409fcd2f4bfSAmy Zhang &fmt, 410fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 411fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 412fcd2f4bfSAmy Zhang return false; 413fcd2f4bfSAmy Zhang } 414fcd2f4bfSAmy Zhang 415fcd2f4bfSAmy Zhang ++rgb; 416fcd2f4bfSAmy Zhang ++i; 417fcd2f4bfSAmy Zhang } 418fcd2f4bfSAmy Zhang 419fcd2f4bfSAmy Zhang return true; 420fcd2f4bfSAmy Zhang } 421fcd2f4bfSAmy Zhang 422e266fdf6SVitaly Prosyak static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func 423fcd2f4bfSAmy Zhang *output_tf, struct pwl_params *regamma_params) 424fcd2f4bfSAmy Zhang { 42523ae4f8eSAmy Zhang struct curve_points *arr_points; 42623ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 42723ae4f8eSAmy Zhang struct pwl_result_data *rgb; 42823ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 429fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 430fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 431fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 432fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 433fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 434fcd2f4bfSAmy Zhang 435fcd2f4bfSAmy Zhang int32_t segment_start, segment_end; 43623ae4f8eSAmy Zhang uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; 43723ae4f8eSAmy Zhang 43870063a59SAmy Zhang if (output_tf == NULL || regamma_params == NULL || 43970063a59SAmy Zhang output_tf->type == TF_TYPE_BYPASS) 44023ae4f8eSAmy Zhang return false; 44123ae4f8eSAmy Zhang 44223ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 44323ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 44423ae4f8eSAmy Zhang hw_points = 0; 445fcd2f4bfSAmy Zhang 446fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 447fcd2f4bfSAmy Zhang 448fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 449534db198SAmy Zhang /* 16 segments 450fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 451fcd2f4bfSAmy Zhang */ 452fcd2f4bfSAmy Zhang segment_start = -11; 453fcd2f4bfSAmy Zhang segment_end = 5; 454fcd2f4bfSAmy Zhang 455534db198SAmy Zhang seg_distr[0] = 2; 456534db198SAmy Zhang seg_distr[1] = 2; 457534db198SAmy Zhang seg_distr[2] = 2; 458534db198SAmy Zhang seg_distr[3] = 2; 459534db198SAmy Zhang seg_distr[4] = 2; 460534db198SAmy Zhang seg_distr[5] = 2; 461534db198SAmy Zhang seg_distr[6] = 3; 462534db198SAmy Zhang seg_distr[7] = 4; 463534db198SAmy Zhang seg_distr[8] = 4; 464534db198SAmy Zhang seg_distr[9] = 4; 465534db198SAmy Zhang seg_distr[10] = 4; 466534db198SAmy Zhang seg_distr[11] = 5; 467534db198SAmy Zhang seg_distr[12] = 5; 468534db198SAmy Zhang seg_distr[13] = 5; 469534db198SAmy Zhang seg_distr[14] = 5; 470534db198SAmy Zhang seg_distr[15] = 5; 471534db198SAmy Zhang 472fcd2f4bfSAmy Zhang } else { 473534db198SAmy Zhang /* 10 segments 474fcd2f4bfSAmy Zhang * segment is from 2^-10 to 2^0 475fcd2f4bfSAmy Zhang */ 476fcd2f4bfSAmy Zhang segment_start = -10; 477fcd2f4bfSAmy Zhang segment_end = 0; 478534db198SAmy Zhang 479534db198SAmy Zhang seg_distr[0] = 3; 480534db198SAmy Zhang seg_distr[1] = 4; 481534db198SAmy Zhang seg_distr[2] = 4; 482534db198SAmy Zhang seg_distr[3] = 4; 483534db198SAmy Zhang seg_distr[4] = 4; 484534db198SAmy Zhang seg_distr[5] = 4; 485534db198SAmy Zhang seg_distr[6] = 4; 486534db198SAmy Zhang seg_distr[7] = 4; 487534db198SAmy Zhang seg_distr[8] = 5; 488534db198SAmy Zhang seg_distr[9] = 5; 489534db198SAmy Zhang seg_distr[10] = -1; 490534db198SAmy Zhang seg_distr[11] = -1; 491534db198SAmy Zhang seg_distr[12] = -1; 492534db198SAmy Zhang seg_distr[13] = -1; 493534db198SAmy Zhang seg_distr[14] = -1; 494534db198SAmy Zhang seg_distr[15] = -1; 495fcd2f4bfSAmy Zhang } 496fcd2f4bfSAmy Zhang 497534db198SAmy Zhang for (k = 0; k < 16; k++) { 498534db198SAmy Zhang if (seg_distr[k] != -1) 499534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 500534db198SAmy Zhang } 501534db198SAmy Zhang 502fcd2f4bfSAmy Zhang j = 0; 503534db198SAmy Zhang for (k = 0; k < (segment_end - segment_start); k++) { 504534db198SAmy Zhang increment = 32 / (1 << seg_distr[k]); 505534db198SAmy Zhang start_index = (segment_start + k + 25) * 32; 506534db198SAmy Zhang for (i = start_index; i < start_index + 32; i += increment) { 507534db198SAmy Zhang if (j == hw_points - 1) 508fcd2f4bfSAmy Zhang break; 509fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 510fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 511fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 512fcd2f4bfSAmy Zhang j++; 513fcd2f4bfSAmy Zhang } 514534db198SAmy Zhang } 515534db198SAmy Zhang 516534db198SAmy Zhang /* last point */ 517534db198SAmy Zhang start_index = (segment_end + 25) * 32; 518534db198SAmy Zhang rgb_resulted[hw_points - 1].red = 519534db198SAmy Zhang output_tf->tf_pts.red[start_index]; 520534db198SAmy Zhang rgb_resulted[hw_points - 1].green = 521534db198SAmy Zhang output_tf->tf_pts.green[start_index]; 522534db198SAmy Zhang rgb_resulted[hw_points - 1].blue = 523534db198SAmy Zhang output_tf->tf_pts.blue[start_index]; 524fcd2f4bfSAmy Zhang 525fcd2f4bfSAmy Zhang arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 526fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_start)); 527fcd2f4bfSAmy Zhang arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 528fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 529fcd2f4bfSAmy Zhang arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 530fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 531fcd2f4bfSAmy Zhang 532fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 533fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 534fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 535fcd2f4bfSAmy Zhang 536fcd2f4bfSAmy Zhang y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); 537fcd2f4bfSAmy Zhang 538fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 539fcd2f4bfSAmy Zhang arr_points[0].slope = dal_fixed31_32_div( 540fcd2f4bfSAmy Zhang arr_points[0].y, 541fcd2f4bfSAmy Zhang arr_points[0].x); 542fcd2f4bfSAmy Zhang 543fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 544fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 545fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 546fcd2f4bfSAmy Zhang 547fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 548fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 549fcd2f4bfSAmy Zhang */ 550fcd2f4bfSAmy Zhang y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); 551fcd2f4bfSAmy Zhang 552fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 553fcd2f4bfSAmy Zhang arr_points[2].y = y3_max; 554fcd2f4bfSAmy Zhang 555fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_zero; 556fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_zero; 557fcd2f4bfSAmy Zhang 558fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 559fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 560fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 561fcd2f4bfSAmy Zhang */ 562fcd2f4bfSAmy Zhang const struct fixed31_32 end_value = 563fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(125); 564fcd2f4bfSAmy Zhang 565fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_div( 566fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 567fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 568fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_div( 569fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 570fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 571fcd2f4bfSAmy Zhang } 572fcd2f4bfSAmy Zhang 573fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 574fcd2f4bfSAmy Zhang 575534db198SAmy Zhang i = 1; 576534db198SAmy Zhang for (k = 0; k < 16 && i < 16; k++) { 577534db198SAmy Zhang if (seg_distr[k] != -1) { 578534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 579534db198SAmy Zhang seg_distr[k]; 580534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 581534db198SAmy Zhang regamma_params->arr_curve_points[k]. 582534db198SAmy Zhang offset + (1 << seg_distr[k]); 583fcd2f4bfSAmy Zhang } 584534db198SAmy Zhang i++; 585534db198SAmy Zhang } 586534db198SAmy Zhang 587534db198SAmy Zhang if (seg_distr[k] != -1) 588534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 589534db198SAmy Zhang seg_distr[k]; 590fcd2f4bfSAmy Zhang 59123ae4f8eSAmy Zhang rgb = rgb_resulted; 59223ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 593fcd2f4bfSAmy Zhang 594fcd2f4bfSAmy Zhang i = 1; 595fcd2f4bfSAmy Zhang 596fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 597fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) 598fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 599fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) 600fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 601fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) 602fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 603fcd2f4bfSAmy Zhang 604fcd2f4bfSAmy Zhang rgb->delta_red = dal_fixed31_32_sub( 605fcd2f4bfSAmy Zhang rgb_plus_1->red, 606fcd2f4bfSAmy Zhang rgb->red); 607fcd2f4bfSAmy Zhang rgb->delta_green = dal_fixed31_32_sub( 608fcd2f4bfSAmy Zhang rgb_plus_1->green, 609fcd2f4bfSAmy Zhang rgb->green); 610fcd2f4bfSAmy Zhang rgb->delta_blue = dal_fixed31_32_sub( 611fcd2f4bfSAmy Zhang rgb_plus_1->blue, 612fcd2f4bfSAmy Zhang rgb->blue); 613fcd2f4bfSAmy Zhang 614fcd2f4bfSAmy Zhang ++rgb_plus_1; 615fcd2f4bfSAmy Zhang ++rgb; 616fcd2f4bfSAmy Zhang ++i; 617fcd2f4bfSAmy Zhang } 618fcd2f4bfSAmy Zhang 619fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 620fcd2f4bfSAmy Zhang 621fcd2f4bfSAmy Zhang return true; 622fcd2f4bfSAmy Zhang } 623fcd2f4bfSAmy Zhang 62490e508baSAnthony Koo static bool dce110_set_output_transfer_func( 62590e508baSAnthony Koo struct pipe_ctx *pipe_ctx, 62690e508baSAnthony Koo const struct core_stream *stream) 62790e508baSAnthony Koo { 628fb735a9fSAnthony Koo struct output_pixel_processor *opp = pipe_ctx->opp; 6294562236bSHarry Wentland 6304562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, true); 631974db151SDmytro Laktyushkin opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 6324562236bSHarry Wentland 633d7194cf6SAric Cyr if (stream->public.out_transfer_func && 634fcd2f4bfSAmy Zhang stream->public.out_transfer_func->type == 635fcd2f4bfSAmy Zhang TF_TYPE_PREDEFINED && 636fcd2f4bfSAmy Zhang stream->public.out_transfer_func->tf == 637fcd2f4bfSAmy Zhang TRANSFER_FUNCTION_SRGB) { 638d7194cf6SAric Cyr opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); 639fcd2f4bfSAmy Zhang } else if (dce110_translate_regamma_to_hw_format( 640974db151SDmytro Laktyushkin stream->public.out_transfer_func, &opp->regamma_params)) { 641974db151SDmytro Laktyushkin opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params); 6424562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); 6434562236bSHarry Wentland } else { 6444562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); 6454562236bSHarry Wentland } 6464562236bSHarry Wentland 6474562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, false); 6484562236bSHarry Wentland 649cc0cb445SLeon Elazar return true; 6504562236bSHarry Wentland } 6514562236bSHarry Wentland 6524562236bSHarry Wentland static enum dc_status bios_parser_crtc_source_select( 6534562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 6544562236bSHarry Wentland { 6554562236bSHarry Wentland struct dc_bios *dcb; 6564562236bSHarry Wentland /* call VBIOS table to set CRTC source for the HW 6574562236bSHarry Wentland * encoder block 6584562236bSHarry Wentland * note: video bios clears all FMT setting here. */ 6594562236bSHarry Wentland struct bp_crtc_source_select crtc_source_select = {0}; 660b73a22d3SHarry Wentland const struct dc_sink *sink = pipe_ctx->stream->sink; 6614562236bSHarry Wentland 6624562236bSHarry Wentland crtc_source_select.engine_id = pipe_ctx->stream_enc->id; 6634562236bSHarry Wentland crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1; 6644562236bSHarry Wentland /*TODO: Need to un-hardcode color depth, dp_audio and account for 6654562236bSHarry Wentland * the case where signal and sink signal is different (translator 6664562236bSHarry Wentland * encoder)*/ 6674562236bSHarry Wentland crtc_source_select.signal = pipe_ctx->stream->signal; 6684562236bSHarry Wentland crtc_source_select.enable_dp_audio = false; 6694562236bSHarry Wentland crtc_source_select.sink_signal = pipe_ctx->stream->signal; 6704562236bSHarry Wentland crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6714562236bSHarry Wentland 6724562236bSHarry Wentland dcb = sink->ctx->dc_bios; 6734562236bSHarry Wentland 6744562236bSHarry Wentland if (BP_RESULT_OK != dcb->funcs->crtc_source_select( 6754562236bSHarry Wentland dcb, 6764562236bSHarry Wentland &crtc_source_select)) { 6774562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 6784562236bSHarry Wentland } 6794562236bSHarry Wentland 6804562236bSHarry Wentland return DC_OK; 6814562236bSHarry Wentland } 6824562236bSHarry Wentland 6834562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6844562236bSHarry Wentland { 68586e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 68686e2e1beSHersen Wu 68786e2e1beSHersen Wu if (pipe_ctx->stream_enc == NULL) 68886e2e1beSHersen Wu return; /* this is not root pipe */ 68986e2e1beSHersen Wu 6904562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 6914562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_hdmi_info_packets( 6924562236bSHarry Wentland pipe_ctx->stream_enc, 6934562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 6944562236bSHarry Wentland else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6954562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_dp_info_packets( 6964562236bSHarry Wentland pipe_ctx->stream_enc, 6974562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 6984562236bSHarry Wentland } 6994562236bSHarry Wentland 7004562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 7014562236bSHarry Wentland { 7024562236bSHarry Wentland enum dc_lane_count lane_count = 703d0778ebfSHarry Wentland pipe_ctx->stream->sink->link->cur_link_settings.lane_count; 7044562236bSHarry Wentland 7054562236bSHarry Wentland struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; 706d0778ebfSHarry Wentland struct dc_link *link = pipe_ctx->stream->sink->link; 7074562236bSHarry Wentland 7084562236bSHarry Wentland /* 1. update AVI info frame (HDMI, DP) 7094562236bSHarry Wentland * we always need to update info frame 7104562236bSHarry Wentland */ 7114562236bSHarry Wentland uint32_t active_total_with_borders; 7124562236bSHarry Wentland uint32_t early_control = 0; 7134562236bSHarry Wentland struct timing_generator *tg = pipe_ctx->tg; 7144562236bSHarry Wentland 7154562236bSHarry Wentland /* TODOFPGA may change to hwss.update_info_frame */ 7164562236bSHarry Wentland dce110_update_info_frame(pipe_ctx); 7174562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 7184562236bSHarry Wentland active_total_with_borders = 7194562236bSHarry Wentland timing->h_addressable 7204562236bSHarry Wentland + timing->h_border_left 7214562236bSHarry Wentland + timing->h_border_right; 7224562236bSHarry Wentland 7234562236bSHarry Wentland if (lane_count != 0) 7244562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 7254562236bSHarry Wentland 7264562236bSHarry Wentland if (early_control == 0) 7274562236bSHarry Wentland early_control = lane_count; 7284562236bSHarry Wentland 7294562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 7304562236bSHarry Wentland 7314562236bSHarry Wentland /* enable audio only within mode set */ 7324562236bSHarry Wentland if (pipe_ctx->audio != NULL) { 7334562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7344562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc); 7354562236bSHarry Wentland } 7364562236bSHarry Wentland 7374562236bSHarry Wentland /* For MST, there are multiply stream go to only one link. 7384562236bSHarry Wentland * connect DIG back_end to front_end while enable_stream and 7394562236bSHarry Wentland * disconnect them during disable_stream 7404562236bSHarry Wentland * BY this, it is logic clean to separate stream and link */ 7414562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 7424562236bSHarry Wentland pipe_ctx->stream_enc->id, true); 7434562236bSHarry Wentland 7444562236bSHarry Wentland } 7454562236bSHarry Wentland 7464562236bSHarry Wentland void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 7474562236bSHarry Wentland { 7484562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 749d0778ebfSHarry Wentland struct dc_link *link = stream->sink->link; 7504562236bSHarry Wentland 7514562236bSHarry Wentland if (pipe_ctx->audio) { 7524562236bSHarry Wentland pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); 7534562236bSHarry Wentland 7544562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7554562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_disable( 7564562236bSHarry Wentland pipe_ctx->stream_enc); 7574562236bSHarry Wentland else 7584562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_disable( 7594562236bSHarry Wentland pipe_ctx->stream_enc); 7604562236bSHarry Wentland 7614562236bSHarry Wentland pipe_ctx->audio = NULL; 7624562236bSHarry Wentland 7634562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 7644562236bSHarry Wentland * add audio mode list change flag */ 7654562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 7664562236bSHarry Wentland * stream->stream_engine_id); 7674562236bSHarry Wentland */ 7684562236bSHarry Wentland } 7694562236bSHarry Wentland 7704562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 7714562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets( 7724562236bSHarry Wentland pipe_ctx->stream_enc); 7734562236bSHarry Wentland 7744562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7754562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_dp_info_packets( 7764562236bSHarry Wentland pipe_ctx->stream_enc); 7774562236bSHarry Wentland 7784562236bSHarry Wentland pipe_ctx->stream_enc->funcs->audio_mute_control( 7794562236bSHarry Wentland pipe_ctx->stream_enc, true); 7804562236bSHarry Wentland 7814562236bSHarry Wentland 7824562236bSHarry Wentland /* blank at encoder level */ 7834562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7844562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc); 7854562236bSHarry Wentland 7864562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 7874562236bSHarry Wentland link->link_enc, 7884562236bSHarry Wentland pipe_ctx->stream_enc->id, 7894562236bSHarry Wentland false); 7904562236bSHarry Wentland 7914562236bSHarry Wentland } 7924562236bSHarry Wentland 7934562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 7944562236bSHarry Wentland struct dc_link_settings *link_settings) 7954562236bSHarry Wentland { 7964562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 7974562236bSHarry Wentland 7984562236bSHarry Wentland /* only 3 items below are used by unblank */ 7996235b23cSTony Cheng params.pixel_clk_khz = 8004562236bSHarry Wentland pipe_ctx->stream->public.timing.pix_clk_khz; 8014562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 8024562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); 8034562236bSHarry Wentland } 8044562236bSHarry Wentland 80515e17335SCharlene Liu 80615e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 80715e17335SCharlene Liu { 80815e17335SCharlene Liu if (pipe_ctx != NULL && pipe_ctx->stream_enc != NULL) 80915e17335SCharlene Liu pipe_ctx->stream_enc->funcs->set_avmute(pipe_ctx->stream_enc, enable); 81015e17335SCharlene Liu } 81115e17335SCharlene Liu 8124562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 8134562236bSHarry Wentland { 8144562236bSHarry Wentland switch (crtc_id) { 8154562236bSHarry Wentland case CONTROLLER_ID_D0: 8164562236bSHarry Wentland return DTO_SOURCE_ID0; 8174562236bSHarry Wentland case CONTROLLER_ID_D1: 8184562236bSHarry Wentland return DTO_SOURCE_ID1; 8194562236bSHarry Wentland case CONTROLLER_ID_D2: 8204562236bSHarry Wentland return DTO_SOURCE_ID2; 8214562236bSHarry Wentland case CONTROLLER_ID_D3: 8224562236bSHarry Wentland return DTO_SOURCE_ID3; 8234562236bSHarry Wentland case CONTROLLER_ID_D4: 8244562236bSHarry Wentland return DTO_SOURCE_ID4; 8254562236bSHarry Wentland case CONTROLLER_ID_D5: 8264562236bSHarry Wentland return DTO_SOURCE_ID5; 8274562236bSHarry Wentland default: 8284562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 8294562236bSHarry Wentland } 8304562236bSHarry Wentland } 8314562236bSHarry Wentland 8324562236bSHarry Wentland static void build_audio_output( 8334562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 8344562236bSHarry Wentland struct audio_output *audio_output) 8354562236bSHarry Wentland { 8364562236bSHarry Wentland const struct core_stream *stream = pipe_ctx->stream; 8374562236bSHarry Wentland audio_output->engine_id = pipe_ctx->stream_enc->id; 8384562236bSHarry Wentland 8394562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 8404562236bSHarry Wentland 8414562236bSHarry Wentland /* audio_crtc_info */ 8424562236bSHarry Wentland 8434562236bSHarry Wentland audio_output->crtc_info.h_total = 8444562236bSHarry Wentland stream->public.timing.h_total; 8454562236bSHarry Wentland 8464562236bSHarry Wentland /* 8474562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 8484562236bSHarry Wentland * need to specify actual active signal portion 8494562236bSHarry Wentland */ 8504562236bSHarry Wentland audio_output->crtc_info.h_active = 8514562236bSHarry Wentland stream->public.timing.h_addressable 8524562236bSHarry Wentland + stream->public.timing.h_border_left 8534562236bSHarry Wentland + stream->public.timing.h_border_right; 8544562236bSHarry Wentland 8554562236bSHarry Wentland audio_output->crtc_info.v_active = 8564562236bSHarry Wentland stream->public.timing.v_addressable 8574562236bSHarry Wentland + stream->public.timing.v_border_top 8584562236bSHarry Wentland + stream->public.timing.v_border_bottom; 8594562236bSHarry Wentland 8604562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 8614562236bSHarry Wentland 8624562236bSHarry Wentland audio_output->crtc_info.interlaced = 8634562236bSHarry Wentland stream->public.timing.flags.INTERLACE; 8644562236bSHarry Wentland 8654562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 8664562236bSHarry Wentland (stream->public.timing.pix_clk_khz*1000)/ 8674562236bSHarry Wentland (stream->public.timing.h_total*stream->public.timing.v_total); 8684562236bSHarry Wentland 8694562236bSHarry Wentland audio_output->crtc_info.color_depth = 8704562236bSHarry Wentland stream->public.timing.display_color_depth; 8714562236bSHarry Wentland 8724562236bSHarry Wentland audio_output->crtc_info.requested_pixel_clock = 8734562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 8744562236bSHarry Wentland 8754562236bSHarry Wentland audio_output->crtc_info.calculated_pixel_clock = 8764562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 8774562236bSHarry Wentland 87887b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 87987b58768SCharlene Liu if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && 88087b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock == 88187b58768SCharlene Liu stream->public.timing.pix_clk_khz) { 88287b58768SCharlene Liu if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 88387b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock = 88487b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock/2; 88587b58768SCharlene Liu audio_output->crtc_info.calculated_pixel_clock = 88687b58768SCharlene Liu pipe_ctx->pix_clk_params.requested_pix_clk/2; 88787b58768SCharlene Liu 88887b58768SCharlene Liu } 88987b58768SCharlene Liu } 89087b58768SCharlene Liu 8914562236bSHarry Wentland if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 8924562236bSHarry Wentland pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 8934562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 8941a687574SDmytro Laktyushkin pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency( 8954562236bSHarry Wentland pipe_ctx->dis_clk); 8964562236bSHarry Wentland } 8974562236bSHarry Wentland 8984562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 8994562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 9004562236bSHarry Wentland 9014562236bSHarry Wentland audio_output->pll_info.dto_source = 9024562236bSHarry Wentland translate_to_dto_source( 9034562236bSHarry Wentland pipe_ctx->pipe_idx + 1); 9044562236bSHarry Wentland 9054562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 9064562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 9074562236bSHarry Wentland 9084562236bSHarry Wentland audio_output->pll_info.ss_percentage = 9094562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 9104562236bSHarry Wentland } 9114562236bSHarry Wentland 9124562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 9134562236bSHarry Wentland struct tg_color *color) 9144562236bSHarry Wentland { 9154562236bSHarry Wentland uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4; 9164562236bSHarry Wentland 9174562236bSHarry Wentland switch (pipe_ctx->scl_data.format) { 9184562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 9194562236bSHarry Wentland /* set boarder color to red */ 9204562236bSHarry Wentland color->color_r_cr = color_value; 9214562236bSHarry Wentland break; 9224562236bSHarry Wentland 9234562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 9244562236bSHarry Wentland /* set boarder color to blue */ 9254562236bSHarry Wentland color->color_b_cb = color_value; 9264562236bSHarry Wentland break; 92787449a90SAnthony Koo case PIXEL_FORMAT_420BPP8: 9284562236bSHarry Wentland /* set boarder color to green */ 9294562236bSHarry Wentland color->color_g_y = color_value; 9304562236bSHarry Wentland break; 93187449a90SAnthony Koo case PIXEL_FORMAT_420BPP10: 93287449a90SAnthony Koo /* set boarder color to yellow */ 93387449a90SAnthony Koo color->color_g_y = color_value; 93487449a90SAnthony Koo color->color_r_cr = color_value; 93587449a90SAnthony Koo break; 9364562236bSHarry Wentland case PIXEL_FORMAT_FP16: 9374562236bSHarry Wentland /* set boarder color to white */ 9384562236bSHarry Wentland color->color_r_cr = color_value; 9394562236bSHarry Wentland color->color_b_cb = color_value; 9404562236bSHarry Wentland color->color_g_y = color_value; 9414562236bSHarry Wentland break; 9424562236bSHarry Wentland default: 9434562236bSHarry Wentland break; 9444562236bSHarry Wentland } 9454562236bSHarry Wentland } 9464562236bSHarry Wentland 9474562236bSHarry Wentland static void program_scaler(const struct core_dc *dc, 9484562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 9494562236bSHarry Wentland { 9504562236bSHarry Wentland struct tg_color color = {0}; 9514562236bSHarry Wentland 952ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 953ff5ef992SAlex Deucher /* TOFPGA */ 954ff5ef992SAlex Deucher if (pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth == NULL) 955ff5ef992SAlex Deucher return; 956ff5ef992SAlex Deucher #endif 957ff5ef992SAlex Deucher 9584562236bSHarry Wentland if (dc->public.debug.surface_visual_confirm) 9594562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 9604562236bSHarry Wentland else 9614562236bSHarry Wentland color_space_to_black_color(dc, 9624562236bSHarry Wentland pipe_ctx->stream->public.output_color_space, 9634562236bSHarry Wentland &color); 9644562236bSHarry Wentland 9654562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( 9664562236bSHarry Wentland pipe_ctx->xfm, 9674562236bSHarry Wentland pipe_ctx->scl_data.lb_params.depth, 9684562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 9694562236bSHarry Wentland 9704562236bSHarry Wentland if (pipe_ctx->tg->funcs->set_overscan_blank_color) 9714562236bSHarry Wentland pipe_ctx->tg->funcs->set_overscan_blank_color( 9724562236bSHarry Wentland pipe_ctx->tg, 9734562236bSHarry Wentland &color); 9744562236bSHarry Wentland 9754562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, 9764562236bSHarry Wentland &pipe_ctx->scl_data); 9774562236bSHarry Wentland } 9784562236bSHarry Wentland 9794b5e7d62SHersen Wu static enum dc_status dce110_prog_pixclk_crtc_otg( 9804562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 9814562236bSHarry Wentland struct validate_context *context, 9824562236bSHarry Wentland struct core_dc *dc) 9834562236bSHarry Wentland { 9844562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 9854562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 9864562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 9874562236bSHarry Wentland struct tg_color black_color = {0}; 9884562236bSHarry Wentland 9894562236bSHarry Wentland if (!pipe_ctx_old->stream) { 9904562236bSHarry Wentland 9914562236bSHarry Wentland /* program blank color */ 9924562236bSHarry Wentland color_space_to_black_color(dc, 9934562236bSHarry Wentland stream->public.output_color_space, &black_color); 9944562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank_color( 9954562236bSHarry Wentland pipe_ctx->tg, 9964562236bSHarry Wentland &black_color); 9974b5e7d62SHersen Wu 9984562236bSHarry Wentland /* 9994562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 10004562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 10014562236bSHarry Wentland */ 10024562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 10034562236bSHarry Wentland 10044562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 10054562236bSHarry Wentland pipe_ctx->clock_source, 10064562236bSHarry Wentland &pipe_ctx->pix_clk_params, 10074562236bSHarry Wentland &pipe_ctx->pll_settings)) { 10084562236bSHarry Wentland BREAK_TO_DEBUGGER(); 10094562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 10104562236bSHarry Wentland } 10114562236bSHarry Wentland 10124562236bSHarry Wentland pipe_ctx->tg->funcs->program_timing( 10134562236bSHarry Wentland pipe_ctx->tg, 10144562236bSHarry Wentland &stream->public.timing, 10154562236bSHarry Wentland true); 101694267b3dSSylvia Tsai 101794267b3dSSylvia Tsai pipe_ctx->tg->funcs->set_static_screen_control( 101894267b3dSSylvia Tsai pipe_ctx->tg, 101994267b3dSSylvia Tsai 0x182); 10204562236bSHarry Wentland } 10214562236bSHarry Wentland 10224562236bSHarry Wentland if (!pipe_ctx_old->stream) { 10234562236bSHarry Wentland if (false == pipe_ctx->tg->funcs->enable_crtc( 10244562236bSHarry Wentland pipe_ctx->tg)) { 10254562236bSHarry Wentland BREAK_TO_DEBUGGER(); 10264562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 10274562236bSHarry Wentland } 10284562236bSHarry Wentland } 10294562236bSHarry Wentland 103094267b3dSSylvia Tsai 103194267b3dSSylvia Tsai 10324562236bSHarry Wentland return DC_OK; 10334562236bSHarry Wentland } 10344562236bSHarry Wentland 10354562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 10364562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 10374562236bSHarry Wentland struct validate_context *context, 10384562236bSHarry Wentland struct core_dc *dc) 10394562236bSHarry Wentland { 10404562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 10414562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 10424562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 10434562236bSHarry Wentland 10444562236bSHarry Wentland /* */ 10454562236bSHarry Wentland dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); 10464562236bSHarry Wentland 10474562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_dyn_expansion( 10484562236bSHarry Wentland pipe_ctx->opp, 10494562236bSHarry Wentland COLOR_SPACE_YCBCR601, 10504562236bSHarry Wentland stream->public.timing.display_color_depth, 10514562236bSHarry Wentland pipe_ctx->stream->signal); 10524562236bSHarry Wentland 1053181a888fSCharlene Liu /* FPGA does not program backend */ 1054181a888fSCharlene Liu if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 10554562236bSHarry Wentland pipe_ctx->opp->funcs->opp_program_fmt( 10564562236bSHarry Wentland pipe_ctx->opp, 10574562236bSHarry Wentland &stream->bit_depth_params, 10584562236bSHarry Wentland &stream->clamping); 10594562236bSHarry Wentland return DC_OK; 1060181a888fSCharlene Liu } 10614562236bSHarry Wentland /* TODO: move to stream encoder */ 10624562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 10634562236bSHarry Wentland if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { 10644562236bSHarry Wentland BREAK_TO_DEBUGGER(); 10654562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 10664562236bSHarry Wentland } 10674562236bSHarry Wentland 10684562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 10694562236bSHarry Wentland stream->sink->link->link_enc->funcs->setup( 10704562236bSHarry Wentland stream->sink->link->link_enc, 10714562236bSHarry Wentland pipe_ctx->stream->signal); 10724562236bSHarry Wentland 1073ab3c1798SVitaly Prosyak if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 1074ab3c1798SVitaly Prosyak pipe_ctx->stream_enc->funcs->setup_stereo_sync( 1075ab3c1798SVitaly Prosyak pipe_ctx->stream_enc, 1076ab3c1798SVitaly Prosyak pipe_ctx->tg->inst, 1077ab3c1798SVitaly Prosyak stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE); 1078ab3c1798SVitaly Prosyak 1079ab3c1798SVitaly Prosyak 1080181a888fSCharlene Liu /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ 1081181a888fSCharlene Liu pipe_ctx->opp->funcs->opp_program_fmt( 1082181a888fSCharlene Liu pipe_ctx->opp, 1083181a888fSCharlene Liu &stream->bit_depth_params, 1084181a888fSCharlene Liu &stream->clamping); 1085181a888fSCharlene Liu 10864562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10874562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( 10884562236bSHarry Wentland pipe_ctx->stream_enc, 10894562236bSHarry Wentland &stream->public.timing, 10904562236bSHarry Wentland stream->public.output_color_space); 10914562236bSHarry Wentland 10924562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 10934562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( 10944562236bSHarry Wentland pipe_ctx->stream_enc, 10954562236bSHarry Wentland &stream->public.timing, 10964562236bSHarry Wentland stream->phy_pix_clk, 10974562236bSHarry Wentland pipe_ctx->audio != NULL); 10984562236bSHarry Wentland 10994562236bSHarry Wentland if (dc_is_dvi_signal(pipe_ctx->stream->signal)) 11004562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( 11014562236bSHarry Wentland pipe_ctx->stream_enc, 11024562236bSHarry Wentland &stream->public.timing, 11034562236bSHarry Wentland (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? 11044562236bSHarry Wentland true : false); 11054562236bSHarry Wentland 110615e17335SCharlene Liu resource_build_info_frame(pipe_ctx); 110715e17335SCharlene Liu 11084562236bSHarry Wentland if (!pipe_ctx_old->stream) { 11094562236bSHarry Wentland core_link_enable_stream(pipe_ctx); 11104562236bSHarry Wentland 1111b3c64dffSCharlene Liu dce110_update_info_frame(pipe_ctx); 11124562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11134562236bSHarry Wentland dce110_unblank_stream(pipe_ctx, 1114d0778ebfSHarry Wentland &stream->sink->link->cur_link_settings); 11154562236bSHarry Wentland } 11164562236bSHarry Wentland 11174562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 11184562236bSHarry Wentland /* program_scaler and allocate_mem_input are not new asic */ 1119866294f8SHarry Wentland if ((!pipe_ctx_old || 1120866294f8SHarry Wentland memcmp(&pipe_ctx_old->scl_data, &pipe_ctx->scl_data, 1121866294f8SHarry Wentland sizeof(struct scaler_data)) != 0) && 1122866294f8SHarry Wentland pipe_ctx->surface) { 11234562236bSHarry Wentland program_scaler(dc, pipe_ctx); 1124866294f8SHarry Wentland } 11254562236bSHarry Wentland 11264562236bSHarry Wentland /* mst support - use total stream count */ 1127ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1128ff5ef992SAlex Deucher if (pipe_ctx->mi->funcs->allocate_mem_input != NULL) 1129ff5ef992SAlex Deucher #endif 11304562236bSHarry Wentland pipe_ctx->mi->funcs->allocate_mem_input( 11314562236bSHarry Wentland pipe_ctx->mi, 11324562236bSHarry Wentland stream->public.timing.h_total, 11334562236bSHarry Wentland stream->public.timing.v_total, 11344562236bSHarry Wentland stream->public.timing.pix_clk_khz, 1135ab2541b6SAric Cyr context->stream_count); 11364562236bSHarry Wentland 113794267b3dSSylvia Tsai pipe_ctx->stream->sink->link->psr_enabled = false; 113894267b3dSSylvia Tsai 11394562236bSHarry Wentland return DC_OK; 11404562236bSHarry Wentland } 11414562236bSHarry Wentland 11424562236bSHarry Wentland /******************************************************************************/ 11434562236bSHarry Wentland 11444562236bSHarry Wentland static void power_down_encoders(struct core_dc *dc) 11454562236bSHarry Wentland { 11464562236bSHarry Wentland int i; 11474562236bSHarry Wentland 11484562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 11494562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 11504562236bSHarry Wentland dc->links[i]->link_enc, SIGNAL_TYPE_NONE); 11514562236bSHarry Wentland } 11524562236bSHarry Wentland } 11534562236bSHarry Wentland 11544562236bSHarry Wentland static void power_down_controllers(struct core_dc *dc) 11554562236bSHarry Wentland { 11564562236bSHarry Wentland int i; 11574562236bSHarry Wentland 11584562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 11594562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 11604562236bSHarry Wentland dc->res_pool->timing_generators[i]); 11614562236bSHarry Wentland } 11624562236bSHarry Wentland } 11634562236bSHarry Wentland 11644562236bSHarry Wentland static void power_down_clock_sources(struct core_dc *dc) 11654562236bSHarry Wentland { 11664562236bSHarry Wentland int i; 11674562236bSHarry Wentland 11684562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 11694562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 11704562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 11714562236bSHarry Wentland 11724562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 11734562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 11744562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 11754562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 11764562236bSHarry Wentland } 11774562236bSHarry Wentland } 11784562236bSHarry Wentland 11794562236bSHarry Wentland static void power_down_all_hw_blocks(struct core_dc *dc) 11804562236bSHarry Wentland { 11814562236bSHarry Wentland power_down_encoders(dc); 11824562236bSHarry Wentland 11834562236bSHarry Wentland power_down_controllers(dc); 11844562236bSHarry Wentland 11854562236bSHarry Wentland power_down_clock_sources(dc); 11861663ae1cSBhawanpreet Lakha 11871663ae1cSBhawanpreet Lakha #ifdef ENABLE_FBC 11881663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 11891663ae1cSBhawanpreet Lakha #endif 11904562236bSHarry Wentland } 11914562236bSHarry Wentland 11924562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 11934562236bSHarry Wentland struct core_dc *dc) 11944562236bSHarry Wentland { 11954562236bSHarry Wentland int i; 11964562236bSHarry Wentland struct timing_generator *tg; 11974562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 11984562236bSHarry Wentland 11994562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 12004562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 12014562236bSHarry Wentland 12020a87425aSTony Cheng if (tg->funcs->disable_vga) 12034562236bSHarry Wentland tg->funcs->disable_vga(tg); 12044562236bSHarry Wentland 12054562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 12064562236bSHarry Wentland * powergating. */ 12074562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 12084562236bSHarry Wentland true); 12094562236bSHarry Wentland 1210cfe4645eSDmytro Laktyushkin dc->hwss.power_down_front_end(dc, i); 12114562236bSHarry Wentland } 12124562236bSHarry Wentland } 12134562236bSHarry Wentland 12144562236bSHarry Wentland /** 12154562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 12164562236bSHarry Wentland * 1. Power down all DC HW blocks 12174562236bSHarry Wentland * 2. Disable VGA engine on all controllers 12184562236bSHarry Wentland * 3. Enable power gating for controller 12194562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 12204562236bSHarry Wentland */ 12214562236bSHarry Wentland void dce110_enable_accelerated_mode(struct core_dc *dc) 12224562236bSHarry Wentland { 12234562236bSHarry Wentland power_down_all_hw_blocks(dc); 12244562236bSHarry Wentland 12254562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 12264562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 12274562236bSHarry Wentland } 12284562236bSHarry Wentland 12294562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 12304562236bSHarry Wentland struct bw_fixed blackout_duration, 12314562236bSHarry Wentland const struct core_stream *stream) 12324562236bSHarry Wentland { 12334562236bSHarry Wentland uint32_t total_dest_line_time_ns; 12344562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 12354562236bSHarry Wentland 12364562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 12374562236bSHarry Wentland 12384562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 12394562236bSHarry Wentland stream->public.timing.h_total / 12404562236bSHarry Wentland stream->public.timing.pix_clk_khz + 12414562236bSHarry Wentland pstate_blackout_duration_ns; 12424562236bSHarry Wentland 12434562236bSHarry Wentland return total_dest_line_time_ns; 12444562236bSHarry Wentland } 12454562236bSHarry Wentland 12464562236bSHarry Wentland void dce110_set_displaymarks( 12474562236bSHarry Wentland const struct core_dc *dc, 12484562236bSHarry Wentland struct validate_context *context) 12494562236bSHarry Wentland { 12504562236bSHarry Wentland uint8_t i, num_pipes; 12514562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 12524562236bSHarry Wentland 12534562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 12544562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 12554562236bSHarry Wentland uint32_t total_dest_line_time_ns; 12564562236bSHarry Wentland 12574562236bSHarry Wentland if (pipe_ctx->stream == NULL) 12584562236bSHarry Wentland continue; 12594562236bSHarry Wentland 12604562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 12614562236bSHarry Wentland dc->bw_vbios.blackout_duration, pipe_ctx->stream); 12624562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_display_marks( 12634562236bSHarry Wentland pipe_ctx->mi, 12649037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 12659037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 12669037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 12674562236bSHarry Wentland total_dest_line_time_ns); 12684562236bSHarry Wentland if (i == underlay_idx) { 12694562236bSHarry Wentland num_pipes++; 12704562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( 12714562236bSHarry Wentland pipe_ctx->mi, 12729037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 12739037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 12749037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 12754562236bSHarry Wentland total_dest_line_time_ns); 12764562236bSHarry Wentland } 12774562236bSHarry Wentland num_pipes++; 12784562236bSHarry Wentland } 12794562236bSHarry Wentland } 12804562236bSHarry Wentland 1281a2b8659dSTony Cheng static void set_safe_displaymarks( 1282a2b8659dSTony Cheng struct resource_context *res_ctx, 1283a2b8659dSTony Cheng const struct resource_pool *pool) 12844562236bSHarry Wentland { 12854562236bSHarry Wentland int i; 1286a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 12879037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 12884562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 12899037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 12904562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 12914562236bSHarry Wentland 12924562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 12934562236bSHarry Wentland if (res_ctx->pipe_ctx[i].stream == NULL) 12944562236bSHarry Wentland continue; 12954562236bSHarry Wentland 12964562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks( 12974562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 12984562236bSHarry Wentland nbp_marks, 12994562236bSHarry Wentland max_marks, 13004562236bSHarry Wentland max_marks, 13014562236bSHarry Wentland MAX_WATERMARK); 13024562236bSHarry Wentland if (i == underlay_idx) 13034562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks( 13044562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 13054562236bSHarry Wentland nbp_marks, 13064562236bSHarry Wentland max_marks, 13074562236bSHarry Wentland max_marks, 13084562236bSHarry Wentland MAX_WATERMARK); 13094562236bSHarry Wentland } 13104562236bSHarry Wentland } 13114562236bSHarry Wentland 13124562236bSHarry Wentland static void switch_dp_clock_sources( 13134562236bSHarry Wentland const struct core_dc *dc, 13144562236bSHarry Wentland struct resource_context *res_ctx) 13154562236bSHarry Wentland { 13164562236bSHarry Wentland uint8_t i; 13174562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 13184562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 13194562236bSHarry Wentland 13204562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 13214562236bSHarry Wentland continue; 13224562236bSHarry Wentland 13234562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 13244562236bSHarry Wentland struct clock_source *clk_src = 13254562236bSHarry Wentland resource_find_used_clk_src_for_sharing( 13264562236bSHarry Wentland res_ctx, pipe_ctx); 13274562236bSHarry Wentland 13284562236bSHarry Wentland if (clk_src && 13294562236bSHarry Wentland clk_src != pipe_ctx->clock_source) { 13304562236bSHarry Wentland resource_unreference_clock_source( 1331a2b8659dSTony Cheng res_ctx, dc->res_pool, 1332a2b8659dSTony Cheng &pipe_ctx->clock_source); 13334562236bSHarry Wentland pipe_ctx->clock_source = clk_src; 1334a2b8659dSTony Cheng resource_reference_clock_source( 1335a2b8659dSTony Cheng res_ctx, dc->res_pool, clk_src); 13364562236bSHarry Wentland 13374562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i); 13384562236bSHarry Wentland } 13394562236bSHarry Wentland } 13404562236bSHarry Wentland } 13414562236bSHarry Wentland } 13424562236bSHarry Wentland 13434562236bSHarry Wentland /******************************************************************************* 13444562236bSHarry Wentland * Public functions 13454562236bSHarry Wentland ******************************************************************************/ 13464562236bSHarry Wentland 13474562236bSHarry Wentland static void reset_single_pipe_hw_ctx( 13484562236bSHarry Wentland const struct core_dc *dc, 13494562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 13504562236bSHarry Wentland struct validate_context *context) 13514562236bSHarry Wentland { 13524562236bSHarry Wentland core_link_disable_stream(pipe_ctx); 13534b5e7d62SHersen Wu pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 13544b5e7d62SHersen Wu if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) { 13554562236bSHarry Wentland dm_error("DC: failed to blank crtc!\n"); 13564562236bSHarry Wentland BREAK_TO_DEBUGGER(); 13574562236bSHarry Wentland } 13584562236bSHarry Wentland pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); 13594562236bSHarry Wentland pipe_ctx->mi->funcs->free_mem_input( 1360ab2541b6SAric Cyr pipe_ctx->mi, context->stream_count); 1361a2b8659dSTony Cheng resource_unreference_clock_source(&context->res_ctx, dc->res_pool, 1362a2b8659dSTony Cheng &pipe_ctx->clock_source); 13634562236bSHarry Wentland 1364cfe4645eSDmytro Laktyushkin dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx->pipe_idx); 13654562236bSHarry Wentland 13664562236bSHarry Wentland pipe_ctx->stream = NULL; 13674562236bSHarry Wentland } 13684562236bSHarry Wentland 13694562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 13704562236bSHarry Wentland int num_pipes, int vmin, int vmax) 13714562236bSHarry Wentland { 13724562236bSHarry Wentland int i = 0; 13734562236bSHarry Wentland struct drr_params params = {0}; 13744562236bSHarry Wentland 13754562236bSHarry Wentland params.vertical_total_max = vmax; 13764562236bSHarry Wentland params.vertical_total_min = vmin; 13774562236bSHarry Wentland 13784562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 13794562236bSHarry Wentland * some GSL stuff 13804562236bSHarry Wentland */ 13814562236bSHarry Wentland 13824562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 13834562236bSHarry Wentland pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, ¶ms); 13844562236bSHarry Wentland } 13854562236bSHarry Wentland } 13864562236bSHarry Wentland 138772ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 138872ada5f7SEric Cook int num_pipes, 138972ada5f7SEric Cook struct crtc_position *position) 139072ada5f7SEric Cook { 139172ada5f7SEric Cook int i = 0; 139272ada5f7SEric Cook 139372ada5f7SEric Cook /* TODO: handle pipes > 1 139472ada5f7SEric Cook */ 139572ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 139672ada5f7SEric Cook pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position); 139772ada5f7SEric Cook } 139872ada5f7SEric Cook 13994562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 140094267b3dSSylvia Tsai int num_pipes, const struct dc_static_screen_events *events) 14014562236bSHarry Wentland { 14024562236bSHarry Wentland unsigned int i; 140394267b3dSSylvia Tsai unsigned int value = 0; 140494267b3dSSylvia Tsai 140594267b3dSSylvia Tsai if (events->overlay_update) 140694267b3dSSylvia Tsai value |= 0x100; 140794267b3dSSylvia Tsai if (events->surface_update) 140894267b3dSSylvia Tsai value |= 0x80; 140994267b3dSSylvia Tsai if (events->cursor_update) 141094267b3dSSylvia Tsai value |= 0x2; 14114562236bSHarry Wentland 1412c3aa1d67SBhawanpreet Lakha #ifdef ENABLE_FBC 1413c3aa1d67SBhawanpreet Lakha value |= 0x84; 1414c3aa1d67SBhawanpreet Lakha #endif 1415c3aa1d67SBhawanpreet Lakha 14164562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 14174562236bSHarry Wentland pipe_ctx[i]->tg->funcs-> 14184562236bSHarry Wentland set_static_screen_control(pipe_ctx[i]->tg, value); 14194562236bSHarry Wentland } 14204562236bSHarry Wentland 14214562236bSHarry Wentland /* unit: in_khz before mode set, get pixel clock from context. ASIC register 14224562236bSHarry Wentland * may not be programmed yet. 14234562236bSHarry Wentland * TODO: after mode set, pre_mode_set = false, 14244562236bSHarry Wentland * may read PLL register to get pixel clock 14254562236bSHarry Wentland */ 14264562236bSHarry Wentland static uint32_t get_max_pixel_clock_for_all_paths( 14274562236bSHarry Wentland struct core_dc *dc, 14284562236bSHarry Wentland struct validate_context *context, 14294562236bSHarry Wentland bool pre_mode_set) 14304562236bSHarry Wentland { 14314562236bSHarry Wentland uint32_t max_pix_clk = 0; 14324562236bSHarry Wentland int i; 14334562236bSHarry Wentland 14344562236bSHarry Wentland if (!pre_mode_set) { 14354562236bSHarry Wentland /* TODO: read ASIC register to get pixel clock */ 14364562236bSHarry Wentland ASSERT(0); 14374562236bSHarry Wentland } 14384562236bSHarry Wentland 14394562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 14404562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 14414562236bSHarry Wentland 14424562236bSHarry Wentland if (pipe_ctx->stream == NULL) 14434562236bSHarry Wentland continue; 14444562236bSHarry Wentland 14454562236bSHarry Wentland /* do not check under lay */ 14464562236bSHarry Wentland if (pipe_ctx->top_pipe) 14474562236bSHarry Wentland continue; 14484562236bSHarry Wentland 14494562236bSHarry Wentland if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk) 14504562236bSHarry Wentland max_pix_clk = 14514562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 14524562236bSHarry Wentland } 14534562236bSHarry Wentland 14544562236bSHarry Wentland if (max_pix_clk == 0) 14554562236bSHarry Wentland ASSERT(0); 14564562236bSHarry Wentland 14574562236bSHarry Wentland return max_pix_clk; 14584562236bSHarry Wentland } 14594562236bSHarry Wentland 14602c8ad2d5SAlex Deucher /* Find clock state based on clock requested. if clock value is 0, simply 14614562236bSHarry Wentland * set clock state as requested without finding clock state by clock value 14622c8ad2d5SAlex Deucher *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock. 14632c8ad2d5SAlex Deucher * 14642c8ad2d5SAlex Deucher * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value 14652c8ad2d5SAlex Deucher * etc support for dcn1.0 14664562236bSHarry Wentland */ 14674562236bSHarry Wentland static void apply_min_clocks( 14684562236bSHarry Wentland struct core_dc *dc, 14694562236bSHarry Wentland struct validate_context *context, 1470e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state *clocks_state, 14714562236bSHarry Wentland bool pre_mode_set) 14724562236bSHarry Wentland { 14734562236bSHarry Wentland struct state_dependent_clocks req_clocks = {0}; 14744562236bSHarry Wentland struct pipe_ctx *pipe_ctx; 14754562236bSHarry Wentland int i; 14764562236bSHarry Wentland 14774562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 14784562236bSHarry Wentland pipe_ctx = &context->res_ctx.pipe_ctx[i]; 14794562236bSHarry Wentland if (pipe_ctx->dis_clk != NULL) 14804562236bSHarry Wentland break; 14814562236bSHarry Wentland } 14824562236bSHarry Wentland 14834562236bSHarry Wentland if (!pre_mode_set) { 14844562236bSHarry Wentland /* set clock_state without verification */ 14855d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) { 14865d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 14875d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, *clocks_state); 14884562236bSHarry Wentland return; 14895d6d185fSDmytro Laktyushkin } 14904562236bSHarry Wentland 14912c8ad2d5SAlex Deucher /* TODO: This is incorrect. Figure out how to fix. */ 14922c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14932c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14942c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 14952c8ad2d5SAlex Deucher pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz, 14962c8ad2d5SAlex Deucher pre_mode_set, 14972c8ad2d5SAlex Deucher false); 14982c8ad2d5SAlex Deucher 14992c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 15002c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 15012c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 15022c8ad2d5SAlex Deucher pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz, 15032c8ad2d5SAlex Deucher pre_mode_set, 15042c8ad2d5SAlex Deucher false); 15052c8ad2d5SAlex Deucher 15062c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 15072c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 15082c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 15092c8ad2d5SAlex Deucher pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, 15102c8ad2d5SAlex Deucher pre_mode_set, 15112c8ad2d5SAlex Deucher false); 15122c8ad2d5SAlex Deucher return; 15134562236bSHarry Wentland } 15144562236bSHarry Wentland 15154562236bSHarry Wentland /* get the required state based on state dependent clocks: 15164562236bSHarry Wentland * display clock and pixel clock 15174562236bSHarry Wentland */ 15189037d802SDmytro Laktyushkin req_clocks.display_clk_khz = context->bw.dce.dispclk_khz; 15194562236bSHarry Wentland 15204562236bSHarry Wentland req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( 15214562236bSHarry Wentland dc, context, true); 15224562236bSHarry Wentland 15235d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) { 15245d6d185fSDmytro Laktyushkin *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state( 15255d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, &req_clocks); 15265d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 15274562236bSHarry Wentland pipe_ctx->dis_clk, *clocks_state); 15284562236bSHarry Wentland } else { 15292c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 15302c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 15312c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 15322c8ad2d5SAlex Deucher req_clocks.display_clk_khz, 15332c8ad2d5SAlex Deucher pre_mode_set, 15342c8ad2d5SAlex Deucher false); 15352c8ad2d5SAlex Deucher 15362c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 15372c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 15382c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 15392c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 15402c8ad2d5SAlex Deucher pre_mode_set, 15412c8ad2d5SAlex Deucher false); 15422c8ad2d5SAlex Deucher 15432c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 15442c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 15452c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 15462c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 15472c8ad2d5SAlex Deucher pre_mode_set, 15482c8ad2d5SAlex Deucher false); 15494562236bSHarry Wentland } 15504562236bSHarry Wentland } 15514562236bSHarry Wentland 15524562236bSHarry Wentland static enum dc_status apply_ctx_to_hw_fpga( 15534562236bSHarry Wentland struct core_dc *dc, 15544562236bSHarry Wentland struct validate_context *context) 15554562236bSHarry Wentland { 15564562236bSHarry Wentland enum dc_status status = DC_ERROR_UNEXPECTED; 15574562236bSHarry Wentland int i; 15584562236bSHarry Wentland 1559a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 15604562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15614562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15624562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15634562236bSHarry Wentland 15644562236bSHarry Wentland if (pipe_ctx->stream == NULL) 15654562236bSHarry Wentland continue; 15664562236bSHarry Wentland 15674562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) 15684562236bSHarry Wentland continue; 15694562236bSHarry Wentland 15704562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 15714562236bSHarry Wentland pipe_ctx, 15724562236bSHarry Wentland context, 15734562236bSHarry Wentland dc); 15744562236bSHarry Wentland 15754562236bSHarry Wentland if (status != DC_OK) 15764562236bSHarry Wentland return status; 15774562236bSHarry Wentland } 15784562236bSHarry Wentland 15794562236bSHarry Wentland return DC_OK; 15804562236bSHarry Wentland } 15814562236bSHarry Wentland 15824562236bSHarry Wentland static void reset_hw_ctx_wrap( 15834562236bSHarry Wentland struct core_dc *dc, 15844562236bSHarry Wentland struct validate_context *context) 15854562236bSHarry Wentland { 15864562236bSHarry Wentland int i; 15874562236bSHarry Wentland 15884562236bSHarry Wentland /* Reset old context */ 15894562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 1590a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 15914562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15924562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15934562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15944562236bSHarry Wentland 15954562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 15964562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 15974562236bSHarry Wentland * PHY when not already disabled. 15984562236bSHarry Wentland */ 15994562236bSHarry Wentland 16004562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 16014562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 16024562236bSHarry Wentland continue; 16034562236bSHarry Wentland 16044562236bSHarry Wentland if (!pipe_ctx->stream || 16054562236bSHarry Wentland pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 16064562236bSHarry Wentland reset_single_pipe_hw_ctx( 16074562236bSHarry Wentland dc, pipe_ctx_old, dc->current_context); 16084562236bSHarry Wentland } 16094562236bSHarry Wentland } 16104562236bSHarry Wentland 1611cf437593SDmytro Laktyushkin 16124562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 16134562236bSHarry Wentland struct core_dc *dc, 16144562236bSHarry Wentland struct validate_context *context) 16154562236bSHarry Wentland { 16164562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 16174562236bSHarry Wentland enum dc_status status; 16184562236bSHarry Wentland int i; 1619e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID; 16204562236bSHarry Wentland 16214562236bSHarry Wentland /* Reset old context */ 16224562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 16234562236bSHarry Wentland dc->hwss.reset_hw_ctx_wrap(dc, context); 16244562236bSHarry Wentland 16254562236bSHarry Wentland /* Skip applying if no targets */ 1626ab2541b6SAric Cyr if (context->stream_count <= 0) 16274562236bSHarry Wentland return DC_OK; 16284562236bSHarry Wentland 16294562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 16304562236bSHarry Wentland apply_ctx_to_hw_fpga(dc, context); 16314562236bSHarry Wentland return DC_OK; 16324562236bSHarry Wentland } 16334562236bSHarry Wentland 16344562236bSHarry Wentland /* Apply new context */ 16354562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 16364562236bSHarry Wentland 16374562236bSHarry Wentland /* below is for real asic only */ 1638a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 16394562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 16404562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 16414562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 16424562236bSHarry Wentland 16434562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 16444562236bSHarry Wentland continue; 16454562236bSHarry Wentland 16464562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 16474562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 16484562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 16494562236bSHarry Wentland pipe_ctx->clock_source, i); 16504562236bSHarry Wentland continue; 16514562236bSHarry Wentland } 16524562236bSHarry Wentland 16534562236bSHarry Wentland dc->hwss.enable_display_power_gating( 16544562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 16554562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 16564562236bSHarry Wentland } 16574562236bSHarry Wentland 1658a2b8659dSTony Cheng set_safe_displaymarks(&context->res_ctx, dc->res_pool); 16591663ae1cSBhawanpreet Lakha 16601663ae1cSBhawanpreet Lakha #ifdef ENABLE_FBC 16611663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 16621663ae1cSBhawanpreet Lakha #endif 16634562236bSHarry Wentland /*TODO: when pplib works*/ 16644562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, true); 16654562236bSHarry Wentland 1666ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1667c8210d5aSHarry Wentland if (dc->ctx->dce_version == DCN_VERSION_1_0) { 16689037d802SDmytro Laktyushkin if (context->bw.dcn.calc_clk.fclk_khz 1669c66a54dcSDmytro Laktyushkin > dc->current_context->bw.dcn.cur_clk.fclk_khz) { 1670ff5ef992SAlex Deucher struct dm_pp_clock_for_voltage_req clock; 1671ff5ef992SAlex Deucher 1672ff5ef992SAlex Deucher clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; 16739037d802SDmytro Laktyushkin clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; 1674ff5ef992SAlex Deucher dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); 1675c66a54dcSDmytro Laktyushkin dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; 1676c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; 1677ff5ef992SAlex Deucher } 16789037d802SDmytro Laktyushkin if (context->bw.dcn.calc_clk.dcfclk_khz 1679c66a54dcSDmytro Laktyushkin > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { 1680ff5ef992SAlex Deucher struct dm_pp_clock_for_voltage_req clock; 1681ff5ef992SAlex Deucher 1682ff5ef992SAlex Deucher clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; 16839037d802SDmytro Laktyushkin clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; 1684ff5ef992SAlex Deucher dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); 1685c66a54dcSDmytro Laktyushkin dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; 1686c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; 1687ff5ef992SAlex Deucher } 1688c66a54dcSDmytro Laktyushkin if (context->bw.dcn.calc_clk.dispclk_khz 1689c66a54dcSDmytro Laktyushkin > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { 1690c66a54dcSDmytro Laktyushkin dc->res_pool->display_clock->funcs->set_clock( 1691c66a54dcSDmytro Laktyushkin dc->res_pool->display_clock, 1692c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz); 1693c66a54dcSDmytro Laktyushkin dc->current_context->bw.dcn.cur_clk.dispclk_khz = 1694c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz; 1695c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.dispclk_khz = 1696c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz; 1697c66a54dcSDmytro Laktyushkin } 1698c66a54dcSDmytro Laktyushkin } else 1699ff5ef992SAlex Deucher #endif 17009037d802SDmytro Laktyushkin if (context->bw.dce.dispclk_khz 17019037d802SDmytro Laktyushkin > dc->current_context->bw.dce.dispclk_khz) { 1702a2b8659dSTony Cheng dc->res_pool->display_clock->funcs->set_clock( 1703a2b8659dSTony Cheng dc->res_pool->display_clock, 17049037d802SDmytro Laktyushkin context->bw.dce.dispclk_khz * 115 / 100); 17051ce71fcdSCharlene Liu } 1706ab8812a3SHersen Wu /* program audio wall clock. use HDMI as clock source if HDMI 1707ab8812a3SHersen Wu * audio active. Otherwise, use DP as clock source 1708ab8812a3SHersen Wu * first, loop to find any HDMI audio, if not, loop find DP audio 1709ab8812a3SHersen Wu */ 17104562236bSHarry Wentland /* Setup audio rate clock source */ 17114562236bSHarry Wentland /* Issue: 17124562236bSHarry Wentland * Audio lag happened on DP monitor when unplug a HDMI monitor 17134562236bSHarry Wentland * 17144562236bSHarry Wentland * Cause: 17154562236bSHarry Wentland * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 17164562236bSHarry Wentland * is set to either dto0 or dto1, audio should work fine. 17174562236bSHarry Wentland * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 17184562236bSHarry Wentland * set to dto0 will cause audio lag. 17194562236bSHarry Wentland * 17204562236bSHarry Wentland * Solution: 17214562236bSHarry Wentland * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 17224562236bSHarry Wentland * find first available pipe with audio, setup audio wall DTO per topology 17234562236bSHarry Wentland * instead of per pipe. 17244562236bSHarry Wentland */ 1725a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 1726ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1727ab8812a3SHersen Wu 1728ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1729ab8812a3SHersen Wu continue; 1730ab8812a3SHersen Wu 1731ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1732ab8812a3SHersen Wu continue; 1733ab8812a3SHersen Wu 1734ab8812a3SHersen Wu if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 1735ab8812a3SHersen Wu continue; 1736ab8812a3SHersen Wu 1737ab8812a3SHersen Wu if (pipe_ctx->audio != NULL) { 1738ab8812a3SHersen Wu struct audio_output audio_output; 1739ab8812a3SHersen Wu 1740ab8812a3SHersen Wu build_audio_output(pipe_ctx, &audio_output); 1741ab8812a3SHersen Wu 1742ab8812a3SHersen Wu pipe_ctx->audio->funcs->wall_dto_setup( 1743ab8812a3SHersen Wu pipe_ctx->audio, 1744ab8812a3SHersen Wu pipe_ctx->stream->signal, 1745ab8812a3SHersen Wu &audio_output.crtc_info, 1746ab8812a3SHersen Wu &audio_output.pll_info); 1747ab8812a3SHersen Wu break; 1748ab8812a3SHersen Wu } 1749ab8812a3SHersen Wu } 1750ab8812a3SHersen Wu 1751ab8812a3SHersen Wu /* no HDMI audio is found, try DP audio */ 1752a2b8659dSTony Cheng if (i == dc->res_pool->pipe_count) { 1753a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 1754ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1755ab8812a3SHersen Wu 1756ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1757ab8812a3SHersen Wu continue; 1758ab8812a3SHersen Wu 1759ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1760ab8812a3SHersen Wu continue; 1761ab8812a3SHersen Wu 1762ab8812a3SHersen Wu if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 1763ab8812a3SHersen Wu continue; 1764ab8812a3SHersen Wu 1765ab8812a3SHersen Wu if (pipe_ctx->audio != NULL) { 1766ab8812a3SHersen Wu struct audio_output audio_output; 1767ab8812a3SHersen Wu 1768ab8812a3SHersen Wu build_audio_output(pipe_ctx, &audio_output); 1769ab8812a3SHersen Wu 1770ab8812a3SHersen Wu pipe_ctx->audio->funcs->wall_dto_setup( 1771ab8812a3SHersen Wu pipe_ctx->audio, 1772ab8812a3SHersen Wu pipe_ctx->stream->signal, 1773ab8812a3SHersen Wu &audio_output.crtc_info, 1774ab8812a3SHersen Wu &audio_output.pll_info); 1775ab8812a3SHersen Wu break; 1776ab8812a3SHersen Wu } 1777ab8812a3SHersen Wu } 1778ab8812a3SHersen Wu } 1779ab8812a3SHersen Wu 1780a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 1781ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 1782ab8812a3SHersen Wu &dc->current_context->res_ctx.pipe_ctx[i]; 1783ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1784ab8812a3SHersen Wu 1785ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1786ab8812a3SHersen Wu continue; 1787ab8812a3SHersen Wu 1788ab8812a3SHersen Wu if (pipe_ctx->stream == pipe_ctx_old->stream) 1789ab8812a3SHersen Wu continue; 1790ab8812a3SHersen Wu 1791313bf4ffSYongqiang Sun if (pipe_ctx->stream && pipe_ctx_old->stream 1792313bf4ffSYongqiang Sun && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 1793313bf4ffSYongqiang Sun continue; 1794313bf4ffSYongqiang Sun 1795ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1796ab8812a3SHersen Wu continue; 1797ab8812a3SHersen Wu 1798ab8812a3SHersen Wu if (context->res_ctx.pipe_ctx[i].audio != NULL) { 1799ab8812a3SHersen Wu 18004562236bSHarry Wentland struct audio_output audio_output; 18014562236bSHarry Wentland 18024562236bSHarry Wentland build_audio_output(pipe_ctx, &audio_output); 18034562236bSHarry Wentland 18044562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 18054562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_setup( 18064562236bSHarry Wentland pipe_ctx->stream_enc, 18074562236bSHarry Wentland pipe_ctx->audio->inst, 18084562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 18094562236bSHarry Wentland else 18104562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_setup( 18114562236bSHarry Wentland pipe_ctx->stream_enc, 18124562236bSHarry Wentland pipe_ctx->audio->inst, 18134562236bSHarry Wentland &pipe_ctx->stream->public.audio_info, 18144562236bSHarry Wentland &audio_output.crtc_info); 18154562236bSHarry Wentland 18164562236bSHarry Wentland pipe_ctx->audio->funcs->az_configure( 18174562236bSHarry Wentland pipe_ctx->audio, 18184562236bSHarry Wentland pipe_ctx->stream->signal, 18194562236bSHarry Wentland &audio_output.crtc_info, 18204562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 18214562236bSHarry Wentland } 18224562236bSHarry Wentland 18234562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 18244562236bSHarry Wentland pipe_ctx, 18254562236bSHarry Wentland context, 18264562236bSHarry Wentland dc); 18274562236bSHarry Wentland 182818f7a1e4SYongqiang Sun if (dc->hwss.power_on_front_end) 182918f7a1e4SYongqiang Sun dc->hwss.power_on_front_end(dc, pipe_ctx, context); 183018f7a1e4SYongqiang Sun 18314562236bSHarry Wentland if (DC_OK != status) 18324562236bSHarry Wentland return status; 18334562236bSHarry Wentland } 18344562236bSHarry Wentland 1835cf437593SDmytro Laktyushkin dc->hwss.set_bandwidth(dc, context, true); 18364562236bSHarry Wentland 18374562236bSHarry Wentland /* to save power */ 18384562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, false); 18394562236bSHarry Wentland 18404562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, false); 18414562236bSHarry Wentland 18424562236bSHarry Wentland switch_dp_clock_sources(dc, &context->res_ctx); 18434562236bSHarry Wentland 1844cf437593SDmytro Laktyushkin 18454562236bSHarry Wentland return DC_OK; 18464562236bSHarry Wentland } 18474562236bSHarry Wentland 18484562236bSHarry Wentland /******************************************************************************* 18494562236bSHarry Wentland * Front End programming 18504562236bSHarry Wentland ******************************************************************************/ 18514562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 18524562236bSHarry Wentland { 18534562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 18544562236bSHarry Wentland 18554562236bSHarry Wentland default_adjust.force_hw_default = false; 18564562236bSHarry Wentland if (pipe_ctx->surface == NULL) 18574562236bSHarry Wentland default_adjust.in_color_space = COLOR_SPACE_SRGB; 18584562236bSHarry Wentland else 18594562236bSHarry Wentland default_adjust.in_color_space = 1860e12cfcb1SHarry Wentland pipe_ctx->surface->color_space; 18614562236bSHarry Wentland if (pipe_ctx->stream == NULL) 18624562236bSHarry Wentland default_adjust.out_color_space = COLOR_SPACE_SRGB; 18634562236bSHarry Wentland else 18644562236bSHarry Wentland default_adjust.out_color_space = 18654562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 18664562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 18674562236bSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; 18684562236bSHarry Wentland 18694562236bSHarry Wentland /* display color depth */ 18704562236bSHarry Wentland default_adjust.color_depth = 18714562236bSHarry Wentland pipe_ctx->stream->public.timing.display_color_depth; 18724562236bSHarry Wentland 18734562236bSHarry Wentland /* Lb color depth */ 18744562236bSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; 18754562236bSHarry Wentland 18764562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_default( 18774562236bSHarry Wentland pipe_ctx->opp, &default_adjust); 18784562236bSHarry Wentland } 18794562236bSHarry Wentland 1880b06b7680SLeon Elazar 1881b06b7680SLeon Elazar /******************************************************************************* 1882b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 1883b06b7680SLeon Elazar * Blender + CRTC 1884b06b7680SLeon Elazar * 1885b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 1886b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 1887b06b7680SLeon Elazar * 1888b06b7680SLeon Elazar * |----------------------------------------------- | 1889b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 1890b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 1891b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 1892b06b7680SLeon Elazar * |------------------------------------------------| 1893b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 1894b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 1895b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 1896b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 1897b06b7680SLeon Elazar * -------------------------------------------------| 1898b06b7680SLeon Elazar * 1899b06b7680SLeon Elazar ******************************************************************************/ 1900b06b7680SLeon Elazar static void program_surface_visibility(const struct core_dc *dc, 19014562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 19024562236bSHarry Wentland { 19034562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 1904b06b7680SLeon Elazar bool blank_target = false; 19054562236bSHarry Wentland 19064562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 1907b06b7680SLeon Elazar 1908b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 1909b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 1910b06b7680SLeon Elazar 1911e12cfcb1SHarry Wentland if (pipe_ctx->bottom_pipe->surface->visible) { 1912e12cfcb1SHarry Wentland if (pipe_ctx->surface->visible) 19134562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 19144562236bSHarry Wentland else 19154562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 1916b06b7680SLeon Elazar 1917e12cfcb1SHarry Wentland } else if (!pipe_ctx->surface->visible) 1918b06b7680SLeon Elazar blank_target = true; 1919b06b7680SLeon Elazar 1920e12cfcb1SHarry Wentland } else if (!pipe_ctx->surface->visible) 1921b06b7680SLeon Elazar blank_target = true; 1922b06b7680SLeon Elazar 19234562236bSHarry Wentland dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); 1924b06b7680SLeon Elazar pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target); 1925b06b7680SLeon Elazar 19264562236bSHarry Wentland } 19274562236bSHarry Wentland 19281bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 19291bf56e62SZeyu Fan { 19301bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 19311bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 19321bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 19331bf56e62SZeyu Fan 19341bf56e62SZeyu Fan 19351bf56e62SZeyu Fan if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 19361bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 19371bf56e62SZeyu Fan adjust.temperature_matrix[0] = 19381bf56e62SZeyu Fan pipe_ctx->stream-> 19391bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[0]; 19401bf56e62SZeyu Fan adjust.temperature_matrix[1] = 19411bf56e62SZeyu Fan pipe_ctx->stream-> 19421bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[1]; 19431bf56e62SZeyu Fan adjust.temperature_matrix[2] = 19441bf56e62SZeyu Fan pipe_ctx->stream-> 19451bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[2]; 19461bf56e62SZeyu Fan adjust.temperature_matrix[3] = 19471bf56e62SZeyu Fan pipe_ctx->stream-> 19481bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[4]; 19491bf56e62SZeyu Fan adjust.temperature_matrix[4] = 19501bf56e62SZeyu Fan pipe_ctx->stream-> 19511bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[5]; 19521bf56e62SZeyu Fan adjust.temperature_matrix[5] = 19531bf56e62SZeyu Fan pipe_ctx->stream-> 19541bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[6]; 19551bf56e62SZeyu Fan adjust.temperature_matrix[6] = 19561bf56e62SZeyu Fan pipe_ctx->stream-> 19571bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[8]; 19581bf56e62SZeyu Fan adjust.temperature_matrix[7] = 19591bf56e62SZeyu Fan pipe_ctx->stream-> 19601bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[9]; 19611bf56e62SZeyu Fan adjust.temperature_matrix[8] = 19621bf56e62SZeyu Fan pipe_ctx->stream-> 19631bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[10]; 19641bf56e62SZeyu Fan } 19651bf56e62SZeyu Fan 19661bf56e62SZeyu Fan pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 19671bf56e62SZeyu Fan } 19681bf56e62SZeyu Fan 19694562236bSHarry Wentland /** 19704562236bSHarry Wentland * TODO REMOVE, USE UPDATE INSTEAD 19714562236bSHarry Wentland */ 19724562236bSHarry Wentland static void set_plane_config( 19734562236bSHarry Wentland const struct core_dc *dc, 19744562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 19754562236bSHarry Wentland struct resource_context *res_ctx) 19764562236bSHarry Wentland { 19774562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 1978e12cfcb1SHarry Wentland struct dc_surface *surface = pipe_ctx->surface; 19794562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 19804562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 19814562236bSHarry Wentland unsigned int i; 19824562236bSHarry Wentland 19834562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 19844562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 19854562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 19864562236bSHarry Wentland 19874562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 19884562236bSHarry Wentland 19894562236bSHarry Wentland set_default_colors(pipe_ctx); 19904562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 19914562236bSHarry Wentland == true) { 19924562236bSHarry Wentland tbl_entry.color_space = 19934562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 19944562236bSHarry Wentland 19954562236bSHarry Wentland for (i = 0; i < 12; i++) 19964562236bSHarry Wentland tbl_entry.regval[i] = 19974562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 19984562236bSHarry Wentland 19994562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 20004562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 20014562236bSHarry Wentland } 20024562236bSHarry Wentland 20034562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 20044562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 20054562236bSHarry Wentland adjust.temperature_matrix[0] = 20064562236bSHarry Wentland pipe_ctx->stream-> 20074562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 20084562236bSHarry Wentland adjust.temperature_matrix[1] = 20094562236bSHarry Wentland pipe_ctx->stream-> 20104562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 20114562236bSHarry Wentland adjust.temperature_matrix[2] = 20124562236bSHarry Wentland pipe_ctx->stream-> 20134562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 20144562236bSHarry Wentland adjust.temperature_matrix[3] = 20154562236bSHarry Wentland pipe_ctx->stream-> 20164562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 20174562236bSHarry Wentland adjust.temperature_matrix[4] = 20184562236bSHarry Wentland pipe_ctx->stream-> 20194562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 20204562236bSHarry Wentland adjust.temperature_matrix[5] = 20214562236bSHarry Wentland pipe_ctx->stream-> 20224562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 20234562236bSHarry Wentland adjust.temperature_matrix[6] = 20244562236bSHarry Wentland pipe_ctx->stream-> 20254562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 20264562236bSHarry Wentland adjust.temperature_matrix[7] = 20274562236bSHarry Wentland pipe_ctx->stream-> 20284562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 20294562236bSHarry Wentland adjust.temperature_matrix[8] = 20304562236bSHarry Wentland pipe_ctx->stream-> 20314562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 20324562236bSHarry Wentland } 20334562236bSHarry Wentland 20344562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 20354562236bSHarry Wentland 20364562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 20374562236bSHarry Wentland program_scaler(dc, pipe_ctx); 20384562236bSHarry Wentland 2039b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 20404562236bSHarry Wentland 20414562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 20424562236bSHarry Wentland mi, 2043e12cfcb1SHarry Wentland surface->format, 2044e12cfcb1SHarry Wentland &surface->tiling_info, 2045e12cfcb1SHarry Wentland &surface->plane_size, 2046e12cfcb1SHarry Wentland surface->rotation, 20474562236bSHarry Wentland NULL, 20484b28b76bSDmytro Laktyushkin false); 20494b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 2050e12cfcb1SHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->surface->visible); 20514562236bSHarry Wentland 20524562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 20534562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 20544562236bSHarry Wentland pipe_ctx->mi, 2055e12cfcb1SHarry Wentland surface->format, 2056e12cfcb1SHarry Wentland &surface->tiling_info, 2057e12cfcb1SHarry Wentland surface->rotation); 20584562236bSHarry Wentland } 20594562236bSHarry Wentland 20604562236bSHarry Wentland static void update_plane_addr(const struct core_dc *dc, 20614562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 20624562236bSHarry Wentland { 2063e12cfcb1SHarry Wentland struct dc_surface *surface = pipe_ctx->surface; 20644562236bSHarry Wentland 20654562236bSHarry Wentland if (surface == NULL) 20664562236bSHarry Wentland return; 20674562236bSHarry Wentland 20684562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( 20694562236bSHarry Wentland pipe_ctx->mi, 2070e12cfcb1SHarry Wentland &surface->address, 2071e12cfcb1SHarry Wentland surface->flip_immediate); 20724562236bSHarry Wentland 2073e12cfcb1SHarry Wentland surface->status.requested_address = surface->address; 20744562236bSHarry Wentland } 20754562236bSHarry Wentland 20764562236bSHarry Wentland void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 20774562236bSHarry Wentland { 2078e12cfcb1SHarry Wentland struct dc_surface *surface = pipe_ctx->surface; 20794562236bSHarry Wentland 20804562236bSHarry Wentland if (surface == NULL) 20814562236bSHarry Wentland return; 20824562236bSHarry Wentland 20834562236bSHarry Wentland surface->status.is_flip_pending = 20844562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_is_flip_pending( 20854562236bSHarry Wentland pipe_ctx->mi); 20864562236bSHarry Wentland 2087e12cfcb1SHarry Wentland if (surface->status.is_flip_pending && !surface->visible) 20884562236bSHarry Wentland pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; 20894562236bSHarry Wentland 20904562236bSHarry Wentland surface->status.current_address = pipe_ctx->mi->current_address; 20917f5c22d1SVitaly Prosyak if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 20927f5c22d1SVitaly Prosyak pipe_ctx->tg->funcs->is_stereo_left_eye) { 20937f5c22d1SVitaly Prosyak surface->status.is_right_eye =\ 20947f5c22d1SVitaly Prosyak !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg); 20957f5c22d1SVitaly Prosyak } 20964562236bSHarry Wentland } 20974562236bSHarry Wentland 20984562236bSHarry Wentland void dce110_power_down(struct core_dc *dc) 20994562236bSHarry Wentland { 21004562236bSHarry Wentland power_down_all_hw_blocks(dc); 21014562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 21024562236bSHarry Wentland } 21034562236bSHarry Wentland 21044562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 21054562236bSHarry Wentland struct dc_context *dc_ctx, 21064562236bSHarry Wentland struct timing_generator *tg) 21074562236bSHarry Wentland { 21084562236bSHarry Wentland bool rc = false; 21094562236bSHarry Wentland 21104562236bSHarry Wentland /* To avoid endless loop we wait at most 21114562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 21124562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 21134562236bSHarry Wentland uint32_t i; 21144562236bSHarry Wentland 21154562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 21164562236bSHarry Wentland 21174562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 21184562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 21194562236bSHarry Wentland break; 21204562236bSHarry Wentland } 21214562236bSHarry Wentland 21224562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 21234562236bSHarry Wentland rc = true; 21244562236bSHarry Wentland /* usually occurs at i=1 */ 21254562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 21264562236bSHarry Wentland i); 21274562236bSHarry Wentland break; 21284562236bSHarry Wentland } 21294562236bSHarry Wentland 21304562236bSHarry Wentland /* Wait for one frame. */ 21314562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 21324562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 21334562236bSHarry Wentland } 21344562236bSHarry Wentland 21354562236bSHarry Wentland if (false == rc) 21364562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 21374562236bSHarry Wentland 21384562236bSHarry Wentland return rc; 21394562236bSHarry Wentland } 21404562236bSHarry Wentland 21414562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 21424562236bSHarry Wentland static void dce110_enable_timing_synchronization( 21434562236bSHarry Wentland struct core_dc *dc, 21444562236bSHarry Wentland int group_index, 21454562236bSHarry Wentland int group_size, 21464562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 21474562236bSHarry Wentland { 21484562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 21494562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 21504562236bSHarry Wentland int i; 21514562236bSHarry Wentland 21524562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 21534562236bSHarry Wentland 21544562236bSHarry Wentland /* Designate a single TG in the group as a master. 21554562236bSHarry Wentland * Since HW doesn't care which one, we always assign 21564562236bSHarry Wentland * the 1st one in the group. */ 21574562236bSHarry Wentland gsl_params.gsl_group = 0; 21584562236bSHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->tg->inst; 21594562236bSHarry Wentland 21604562236bSHarry Wentland for (i = 0; i < group_size; i++) 21614562236bSHarry Wentland grouped_pipes[i]->tg->funcs->setup_global_swap_lock( 21624562236bSHarry Wentland grouped_pipes[i]->tg, &gsl_params); 21634562236bSHarry Wentland 21644562236bSHarry Wentland /* Reset slave controllers on master VSync */ 21654562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 21664562236bSHarry Wentland 21674562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 21684562236bSHarry Wentland grouped_pipes[i]->tg->funcs->enable_reset_trigger( 21694562236bSHarry Wentland grouped_pipes[i]->tg, gsl_params.gsl_group); 21704562236bSHarry Wentland 21714562236bSHarry Wentland 21724562236bSHarry Wentland 21734562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 21744562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 21754562236bSHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg); 21764562236bSHarry Wentland /* Regardless of success of the wait above, remove the reset or 21774562236bSHarry Wentland * the driver will start timing out on Display requests. */ 21784562236bSHarry Wentland DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); 21794562236bSHarry Wentland grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg); 21804562236bSHarry Wentland } 21814562236bSHarry Wentland 21824562236bSHarry Wentland 21834562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 21844562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 21854562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 21864562236bSHarry Wentland for (i = 0; i < group_size; i++) 21874562236bSHarry Wentland grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg); 21884562236bSHarry Wentland 21894562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 21904562236bSHarry Wentland } 21914562236bSHarry Wentland 21924562236bSHarry Wentland static void init_hw(struct core_dc *dc) 21934562236bSHarry Wentland { 21944562236bSHarry Wentland int i; 21954562236bSHarry Wentland struct dc_bios *bp; 21964562236bSHarry Wentland struct transform *xfm; 21975e7773a2SAnthony Koo struct abm *abm; 21984562236bSHarry Wentland 21994562236bSHarry Wentland bp = dc->ctx->dc_bios; 22004562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 22014562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 22024562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 22034562236bSHarry Wentland 22044562236bSHarry Wentland dc->hwss.enable_display_power_gating( 22054562236bSHarry Wentland dc, i, bp, 22064562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 22074562236bSHarry Wentland dc->hwss.enable_display_power_gating( 22084562236bSHarry Wentland dc, i, bp, 22094562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 22104562236bSHarry Wentland dc->hwss.enable_display_pipe_clock_gating( 22114562236bSHarry Wentland dc->ctx, 22124562236bSHarry Wentland true); 22134562236bSHarry Wentland } 22144562236bSHarry Wentland 2215e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 22164562236bSHarry Wentland /***************************************/ 22174562236bSHarry Wentland 22184562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 22194562236bSHarry Wentland /****************************************/ 22204562236bSHarry Wentland /* Power up AND update implementation according to the 22214562236bSHarry Wentland * required signal (which may be different from the 22224562236bSHarry Wentland * default signal on connector). */ 2223d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 22244562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 22254562236bSHarry Wentland } 22264562236bSHarry Wentland 22274562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 22284562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 22294562236bSHarry Wentland 22304562236bSHarry Wentland tg->funcs->disable_vga(tg); 22314562236bSHarry Wentland 22324562236bSHarry Wentland /* Blank controller using driver code instead of 22334562236bSHarry Wentland * command table. */ 22344562236bSHarry Wentland tg->funcs->set_blank(tg, true); 22354b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 22364562236bSHarry Wentland } 22374562236bSHarry Wentland 22384562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 22394562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 22404562236bSHarry Wentland audio->funcs->hw_init(audio); 22414562236bSHarry Wentland } 22425e7773a2SAnthony Koo 22435e7773a2SAnthony Koo abm = dc->res_pool->abm; 22446728b30cSAnthony Koo if (abm != NULL) { 22456728b30cSAnthony Koo abm->funcs->init_backlight(abm); 22465e7773a2SAnthony Koo abm->funcs->abm_init(abm); 22474562236bSHarry Wentland } 22481663ae1cSBhawanpreet Lakha #ifdef ENABLE_FBC 22491663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 22501663ae1cSBhawanpreet Lakha #endif 22516728b30cSAnthony Koo } 22524562236bSHarry Wentland 225328f72454SJordan Lazare void dce110_fill_display_configs( 2254cf437593SDmytro Laktyushkin const struct validate_context *context, 2255cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg) 22564562236bSHarry Wentland { 2257cf437593SDmytro Laktyushkin int j; 2258cf437593SDmytro Laktyushkin int num_cfgs = 0; 2259cf437593SDmytro Laktyushkin 2260cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 2261cf437593SDmytro Laktyushkin int k; 2262cf437593SDmytro Laktyushkin 2263cf437593SDmytro Laktyushkin const struct core_stream *stream = context->streams[j]; 2264cf437593SDmytro Laktyushkin struct dm_pp_single_disp_config *cfg = 2265cf437593SDmytro Laktyushkin &pp_display_cfg->disp_configs[num_cfgs]; 2266cf437593SDmytro Laktyushkin const struct pipe_ctx *pipe_ctx = NULL; 2267cf437593SDmytro Laktyushkin 2268cf437593SDmytro Laktyushkin for (k = 0; k < MAX_PIPES; k++) 2269cf437593SDmytro Laktyushkin if (stream == context->res_ctx.pipe_ctx[k].stream) { 2270cf437593SDmytro Laktyushkin pipe_ctx = &context->res_ctx.pipe_ctx[k]; 2271cf437593SDmytro Laktyushkin break; 22724562236bSHarry Wentland } 22734562236bSHarry Wentland 2274cf437593SDmytro Laktyushkin ASSERT(pipe_ctx != NULL); 2275cf437593SDmytro Laktyushkin 2276cf437593SDmytro Laktyushkin num_cfgs++; 2277cf437593SDmytro Laktyushkin cfg->signal = pipe_ctx->stream->signal; 2278cf437593SDmytro Laktyushkin cfg->pipe_idx = pipe_ctx->pipe_idx; 2279cf437593SDmytro Laktyushkin cfg->src_height = stream->public.src.height; 2280cf437593SDmytro Laktyushkin cfg->src_width = stream->public.src.width; 2281cf437593SDmytro Laktyushkin cfg->ddi_channel_mapping = 2282cf437593SDmytro Laktyushkin stream->sink->link->ddi_channel_mapping.raw; 2283cf437593SDmytro Laktyushkin cfg->transmitter = 2284cf437593SDmytro Laktyushkin stream->sink->link->link_enc->transmitter; 2285cf437593SDmytro Laktyushkin cfg->link_settings.lane_count = 2286d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.lane_count; 2287cf437593SDmytro Laktyushkin cfg->link_settings.link_rate = 2288d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.link_rate; 2289cf437593SDmytro Laktyushkin cfg->link_settings.link_spread = 2290d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.link_spread; 2291cf437593SDmytro Laktyushkin cfg->sym_clock = stream->phy_pix_clk; 2292cf437593SDmytro Laktyushkin /* Round v_refresh*/ 2293cf437593SDmytro Laktyushkin cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; 2294cf437593SDmytro Laktyushkin cfg->v_refresh /= stream->public.timing.h_total; 2295cf437593SDmytro Laktyushkin cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) 2296cf437593SDmytro Laktyushkin / stream->public.timing.v_total; 2297cf437593SDmytro Laktyushkin } 2298cf437593SDmytro Laktyushkin 2299cf437593SDmytro Laktyushkin pp_display_cfg->display_count = num_cfgs; 2300cf437593SDmytro Laktyushkin } 2301cf437593SDmytro Laktyushkin 230228f72454SJordan Lazare uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) 2303cf437593SDmytro Laktyushkin { 2304cf437593SDmytro Laktyushkin uint8_t j; 2305cf437593SDmytro Laktyushkin uint32_t min_vertical_blank_time = -1; 2306cf437593SDmytro Laktyushkin 2307cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 2308cf437593SDmytro Laktyushkin const struct dc_stream *stream = &context->streams[j]->public; 2309cf437593SDmytro Laktyushkin uint32_t vertical_blank_in_pixels = 0; 2310cf437593SDmytro Laktyushkin uint32_t vertical_blank_time = 0; 2311cf437593SDmytro Laktyushkin 2312cf437593SDmytro Laktyushkin vertical_blank_in_pixels = stream->timing.h_total * 2313cf437593SDmytro Laktyushkin (stream->timing.v_total 2314cf437593SDmytro Laktyushkin - stream->timing.v_addressable); 2315cf437593SDmytro Laktyushkin 2316cf437593SDmytro Laktyushkin vertical_blank_time = vertical_blank_in_pixels 2317cf437593SDmytro Laktyushkin * 1000 / stream->timing.pix_clk_khz; 2318cf437593SDmytro Laktyushkin 2319cf437593SDmytro Laktyushkin if (min_vertical_blank_time > vertical_blank_time) 2320cf437593SDmytro Laktyushkin min_vertical_blank_time = vertical_blank_time; 2321cf437593SDmytro Laktyushkin } 2322cf437593SDmytro Laktyushkin 2323cf437593SDmytro Laktyushkin return min_vertical_blank_time; 2324cf437593SDmytro Laktyushkin } 2325cf437593SDmytro Laktyushkin 2326cf437593SDmytro Laktyushkin static int determine_sclk_from_bounding_box( 2327cf437593SDmytro Laktyushkin const struct core_dc *dc, 2328cf437593SDmytro Laktyushkin int required_sclk) 23294562236bSHarry Wentland { 23304562236bSHarry Wentland int i; 23314562236bSHarry Wentland 2332cf437593SDmytro Laktyushkin /* 2333cf437593SDmytro Laktyushkin * Some asics do not give us sclk levels, so we just report the actual 2334cf437593SDmytro Laktyushkin * required sclk 2335cf437593SDmytro Laktyushkin */ 2336cf437593SDmytro Laktyushkin if (dc->sclk_lvls.num_levels == 0) 2337cf437593SDmytro Laktyushkin return required_sclk; 23384562236bSHarry Wentland 2339cf437593SDmytro Laktyushkin for (i = 0; i < dc->sclk_lvls.num_levels; i++) { 2340cf437593SDmytro Laktyushkin if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) 2341cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[i]; 2342cf437593SDmytro Laktyushkin } 2343cf437593SDmytro Laktyushkin /* 2344cf437593SDmytro Laktyushkin * even maximum level could not satisfy requirement, this 2345cf437593SDmytro Laktyushkin * is unexpected at this stage, should have been caught at 2346cf437593SDmytro Laktyushkin * validation time 2347cf437593SDmytro Laktyushkin */ 2348cf437593SDmytro Laktyushkin ASSERT(0); 2349cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; 23504562236bSHarry Wentland } 23514562236bSHarry Wentland 2352cf437593SDmytro Laktyushkin static void pplib_apply_display_requirements( 2353cf437593SDmytro Laktyushkin struct core_dc *dc, 2354cf437593SDmytro Laktyushkin struct validate_context *context) 2355cf437593SDmytro Laktyushkin { 2356cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 2357cf437593SDmytro Laktyushkin 2358cf437593SDmytro Laktyushkin pp_display_cfg->all_displays_in_sync = 23599037d802SDmytro Laktyushkin context->bw.dce.all_displays_in_sync; 2360cf437593SDmytro Laktyushkin pp_display_cfg->nb_pstate_switch_disable = 23619037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_enable == false; 2362cf437593SDmytro Laktyushkin pp_display_cfg->cpu_cc6_disable = 23639037d802SDmytro Laktyushkin context->bw.dce.cpuc_state_change_enable == false; 2364cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_disable = 23659037d802SDmytro Laktyushkin context->bw.dce.cpup_state_change_enable == false; 2366cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_separation_time = 23679037d802SDmytro Laktyushkin context->bw.dce.blackout_recovery_time_us; 2368cf437593SDmytro Laktyushkin 23699037d802SDmytro Laktyushkin pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz 2370cf437593SDmytro Laktyushkin / MEMORY_TYPE_MULTIPLIER; 2371cf437593SDmytro Laktyushkin 2372cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( 2373cf437593SDmytro Laktyushkin dc, 23749037d802SDmytro Laktyushkin context->bw.dce.sclk_khz); 2375cf437593SDmytro Laktyushkin 2376cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_deep_sleep_khz 23779037d802SDmytro Laktyushkin = context->bw.dce.sclk_deep_sleep_khz; 2378cf437593SDmytro Laktyushkin 2379cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_us = 238028f72454SJordan Lazare dce110_get_min_vblank_time_us(context); 2381cf437593SDmytro Laktyushkin /* TODO: dce11.2*/ 2382cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; 2383cf437593SDmytro Laktyushkin 23849037d802SDmytro Laktyushkin pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz; 2385cf437593SDmytro Laktyushkin 238628f72454SJordan Lazare dce110_fill_display_configs(context, pp_display_cfg); 2387cf437593SDmytro Laktyushkin 2388cf437593SDmytro Laktyushkin /* TODO: is this still applicable?*/ 2389cf437593SDmytro Laktyushkin if (pp_display_cfg->display_count == 1) { 2390cf437593SDmytro Laktyushkin const struct dc_crtc_timing *timing = 2391cf437593SDmytro Laktyushkin &context->streams[0]->public.timing; 2392cf437593SDmytro Laktyushkin 2393cf437593SDmytro Laktyushkin pp_display_cfg->crtc_index = 2394cf437593SDmytro Laktyushkin pp_display_cfg->disp_configs[0].pipe_idx; 2395cf437593SDmytro Laktyushkin pp_display_cfg->line_time_in_us = timing->h_total * 1000 2396cf437593SDmytro Laktyushkin / timing->pix_clk_khz; 2397cf437593SDmytro Laktyushkin } 2398cf437593SDmytro Laktyushkin 2399cf437593SDmytro Laktyushkin if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( 2400cf437593SDmytro Laktyushkin struct dm_pp_display_configuration)) != 0) 2401cf437593SDmytro Laktyushkin dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); 2402cf437593SDmytro Laktyushkin 2403cf437593SDmytro Laktyushkin dc->prev_display_config = *pp_display_cfg; 2404cf437593SDmytro Laktyushkin } 2405cf437593SDmytro Laktyushkin 2406cf437593SDmytro Laktyushkin static void dce110_set_bandwidth( 2407cf437593SDmytro Laktyushkin struct core_dc *dc, 2408cf437593SDmytro Laktyushkin struct validate_context *context, 2409cf437593SDmytro Laktyushkin bool decrease_allowed) 2410cf437593SDmytro Laktyushkin { 24112180e7ccSDmytro Laktyushkin dce110_set_displaymarks(dc, context); 2412cf437593SDmytro Laktyushkin 24139037d802SDmytro Laktyushkin if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { 2414a2b8659dSTony Cheng dc->res_pool->display_clock->funcs->set_clock( 2415a2b8659dSTony Cheng dc->res_pool->display_clock, 24169037d802SDmytro Laktyushkin context->bw.dce.dispclk_khz * 115 / 100); 24179037d802SDmytro Laktyushkin dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; 2418cf437593SDmytro Laktyushkin } 2419cf437593SDmytro Laktyushkin 2420cf437593SDmytro Laktyushkin pplib_apply_display_requirements(dc, context); 24214562236bSHarry Wentland } 24224562236bSHarry Wentland 24234562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 24244562236bSHarry Wentland struct core_dc *dc, struct pipe_ctx *pipe_ctx) 24254562236bSHarry Wentland { 24264562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 24274562236bSHarry Wentland struct pipe_ctx *old_pipe = NULL; 2428e12cfcb1SHarry Wentland struct dc_surface *surface = pipe_ctx->surface; 24294562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 24304562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 24314562236bSHarry Wentland unsigned int i; 24324562236bSHarry Wentland 24334562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 24344562236bSHarry Wentland 24354562236bSHarry Wentland if (dc->current_context) 24364562236bSHarry Wentland old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 24374562236bSHarry Wentland 24384562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 24394562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 24404562236bSHarry Wentland 24414562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 24424562236bSHarry Wentland 24434562236bSHarry Wentland set_default_colors(pipe_ctx); 24444562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 24454562236bSHarry Wentland == true) { 24464562236bSHarry Wentland tbl_entry.color_space = 24474562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 24484562236bSHarry Wentland 24494562236bSHarry Wentland for (i = 0; i < 12; i++) 24504562236bSHarry Wentland tbl_entry.regval[i] = 24514562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 24524562236bSHarry Wentland 24534562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 24544562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 24554562236bSHarry Wentland } 24564562236bSHarry Wentland 24574562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 24584562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 24594562236bSHarry Wentland adjust.temperature_matrix[0] = 24604562236bSHarry Wentland pipe_ctx->stream-> 24614562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 24624562236bSHarry Wentland adjust.temperature_matrix[1] = 24634562236bSHarry Wentland pipe_ctx->stream-> 24644562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 24654562236bSHarry Wentland adjust.temperature_matrix[2] = 24664562236bSHarry Wentland pipe_ctx->stream-> 24674562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 24684562236bSHarry Wentland adjust.temperature_matrix[3] = 24694562236bSHarry Wentland pipe_ctx->stream-> 24704562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 24714562236bSHarry Wentland adjust.temperature_matrix[4] = 24724562236bSHarry Wentland pipe_ctx->stream-> 24734562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 24744562236bSHarry Wentland adjust.temperature_matrix[5] = 24754562236bSHarry Wentland pipe_ctx->stream-> 24764562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 24774562236bSHarry Wentland adjust.temperature_matrix[6] = 24784562236bSHarry Wentland pipe_ctx->stream-> 24794562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 24804562236bSHarry Wentland adjust.temperature_matrix[7] = 24814562236bSHarry Wentland pipe_ctx->stream-> 24824562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 24834562236bSHarry Wentland adjust.temperature_matrix[8] = 24844562236bSHarry Wentland pipe_ctx->stream-> 24854562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 24864562236bSHarry Wentland } 24874562236bSHarry Wentland 24884562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 24894562236bSHarry Wentland 24904562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2491c1473558SAndrey Grodzovsky 24924562236bSHarry Wentland program_scaler(dc, pipe_ctx); 24934562236bSHarry Wentland 24944562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 24954562236bSHarry Wentland mi, 2496e12cfcb1SHarry Wentland surface->format, 2497e12cfcb1SHarry Wentland &surface->tiling_info, 2498e12cfcb1SHarry Wentland &surface->plane_size, 2499e12cfcb1SHarry Wentland surface->rotation, 2500624d7c47SYongqiang Sun NULL, 25014b28b76bSDmytro Laktyushkin false); 25024b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 2503e12cfcb1SHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->surface->visible); 25044562236bSHarry Wentland 25054562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 25064562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 25074562236bSHarry Wentland pipe_ctx->mi, 2508e12cfcb1SHarry Wentland surface->format, 2509e12cfcb1SHarry Wentland &surface->tiling_info, 2510e12cfcb1SHarry Wentland surface->rotation); 25114562236bSHarry Wentland 25124562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 25134562236bSHarry Wentland "Pipe:%d 0x%x: addr hi:0x%x, " 25144562236bSHarry Wentland "addr low:0x%x, " 25154562236bSHarry Wentland "src: %d, %d, %d," 25164562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 25174562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 25184562236bSHarry Wentland pipe_ctx->pipe_idx, 25194562236bSHarry Wentland pipe_ctx->surface, 2520e12cfcb1SHarry Wentland pipe_ctx->surface->address.grph.addr.high_part, 2521e12cfcb1SHarry Wentland pipe_ctx->surface->address.grph.addr.low_part, 2522e12cfcb1SHarry Wentland pipe_ctx->surface->src_rect.x, 2523e12cfcb1SHarry Wentland pipe_ctx->surface->src_rect.y, 2524e12cfcb1SHarry Wentland pipe_ctx->surface->src_rect.width, 2525e12cfcb1SHarry Wentland pipe_ctx->surface->src_rect.height, 2526e12cfcb1SHarry Wentland pipe_ctx->surface->dst_rect.x, 2527e12cfcb1SHarry Wentland pipe_ctx->surface->dst_rect.y, 2528e12cfcb1SHarry Wentland pipe_ctx->surface->dst_rect.width, 2529e12cfcb1SHarry Wentland pipe_ctx->surface->dst_rect.height, 2530e12cfcb1SHarry Wentland pipe_ctx->surface->clip_rect.x, 2531e12cfcb1SHarry Wentland pipe_ctx->surface->clip_rect.y, 2532e12cfcb1SHarry Wentland pipe_ctx->surface->clip_rect.width, 2533e12cfcb1SHarry Wentland pipe_ctx->surface->clip_rect.height); 25344562236bSHarry Wentland 25354562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 25364562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 25374562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 25384562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 25394562236bSHarry Wentland pipe_ctx->pipe_idx, 25404562236bSHarry Wentland pipe_ctx->scl_data.viewport.width, 25414562236bSHarry Wentland pipe_ctx->scl_data.viewport.height, 25424562236bSHarry Wentland pipe_ctx->scl_data.viewport.x, 25434562236bSHarry Wentland pipe_ctx->scl_data.viewport.y, 25444562236bSHarry Wentland pipe_ctx->scl_data.recout.width, 25454562236bSHarry Wentland pipe_ctx->scl_data.recout.height, 25464562236bSHarry Wentland pipe_ctx->scl_data.recout.x, 25474562236bSHarry Wentland pipe_ctx->scl_data.recout.y); 25484562236bSHarry Wentland } 25494562236bSHarry Wentland 25504562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 25514562236bSHarry Wentland struct core_dc *dc, 2552e12cfcb1SHarry Wentland const struct dc_surface *surface, 25534562236bSHarry Wentland struct validate_context *context) 25544562236bSHarry Wentland { 25554562236bSHarry Wentland int i; 25564562236bSHarry Wentland 25574562236bSHarry Wentland /* TODO remove when removing the surface reset workaroud*/ 25584562236bSHarry Wentland if (!surface) 25594562236bSHarry Wentland return; 25604562236bSHarry Wentland 2561a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 25624562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 25634562236bSHarry Wentland 25644562236bSHarry Wentland if (pipe_ctx->surface != surface) 25654562236bSHarry Wentland continue; 25664562236bSHarry Wentland 25674562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 2568b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 25694562236bSHarry Wentland 25704562236bSHarry Wentland } 25714562236bSHarry Wentland } 25724562236bSHarry Wentland 2573cfe4645eSDmytro Laktyushkin static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) 25744562236bSHarry Wentland { 25757950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2576cfe4645eSDmytro Laktyushkin if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) 25774562236bSHarry Wentland return; 25784562236bSHarry Wentland 25794562236bSHarry Wentland dc->hwss.enable_display_power_gating( 2580cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2581cfe4645eSDmytro Laktyushkin 2582cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2583cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 25844562236bSHarry Wentland } 25854562236bSHarry Wentland 2586b6762f0cSEric Yang static void dce110_wait_for_mpcc_disconnect(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) 2587b6762f0cSEric Yang { 2588b6762f0cSEric Yang /* do nothing*/ 2589b6762f0cSEric Yang } 2590b6762f0cSEric Yang 25914562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 25921bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 25934562236bSHarry Wentland .init_hw = init_hw, 25944562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 25954562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 25964562236bSHarry Wentland .set_plane_config = set_plane_config, 25974562236bSHarry Wentland .update_plane_addr = update_plane_addr, 25984562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 2599d7194cf6SAric Cyr .set_input_transfer_func = dce110_set_input_transfer_func, 260090e508baSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 26014562236bSHarry Wentland .power_down = dce110_power_down, 26024562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 26034562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 26044562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 26054562236bSHarry Wentland .enable_stream = dce110_enable_stream, 26064562236bSHarry Wentland .disable_stream = dce110_disable_stream, 26074562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 26084562236bSHarry Wentland .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 26094562236bSHarry Wentland .enable_display_power_gating = dce110_enable_display_power_gating, 26104562236bSHarry Wentland .power_down_front_end = dce110_power_down_fe, 26114562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 26124562236bSHarry Wentland .set_bandwidth = dce110_set_bandwidth, 26134562236bSHarry Wentland .set_drr = set_drr, 261472ada5f7SEric Cook .get_position = get_position, 26154562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 26164562236bSHarry Wentland .reset_hw_ctx_wrap = reset_hw_ctx_wrap, 26174b5e7d62SHersen Wu .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, 261815e17335SCharlene Liu .setup_stereo = NULL, 261915e17335SCharlene Liu .set_avmute = dce110_set_avmute, 2620b6762f0cSEric Yang .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect 26214562236bSHarry Wentland }; 26224562236bSHarry Wentland 26234562236bSHarry Wentland bool dce110_hw_sequencer_construct(struct core_dc *dc) 26244562236bSHarry Wentland { 26254562236bSHarry Wentland dc->hwss = dce110_funcs; 26264562236bSHarry Wentland 26274562236bSHarry Wentland return true; 26284562236bSHarry Wentland } 26294562236bSHarry Wentland 2630