14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland #include "dm_services.h" 264562236bSHarry Wentland #include "dc.h" 274562236bSHarry Wentland #include "dc_bios_types.h" 284562236bSHarry Wentland #include "core_types.h" 294562236bSHarry Wentland #include "core_status.h" 304562236bSHarry Wentland #include "resource.h" 314562236bSHarry Wentland #include "hw_sequencer.h" 324562236bSHarry Wentland #include "dm_helpers.h" 334562236bSHarry Wentland #include "dce110_hw_sequencer.h" 344562236bSHarry Wentland #include "dce110_timing_generator.h" 354562236bSHarry Wentland 364562236bSHarry Wentland #include "bios/bios_parser_helper.h" 374562236bSHarry Wentland #include "timing_generator.h" 384562236bSHarry Wentland #include "mem_input.h" 394562236bSHarry Wentland #include "opp.h" 404562236bSHarry Wentland #include "ipp.h" 414562236bSHarry Wentland #include "transform.h" 424562236bSHarry Wentland #include "stream_encoder.h" 434562236bSHarry Wentland #include "link_encoder.h" 444562236bSHarry Wentland #include "clock_source.h" 455e7773a2SAnthony Koo #include "abm.h" 464562236bSHarry Wentland #include "audio.h" 474562236bSHarry Wentland #include "dce/dce_hwseq.h" 484562236bSHarry Wentland 494562236bSHarry Wentland /* include DCE11 register header files */ 504562236bSHarry Wentland #include "dce/dce_11_0_d.h" 514562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 52e266fdf6SVitaly Prosyak #include "custom_float.h" 534562236bSHarry Wentland 544562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 554562236bSHarry Wentland uint32_t crtc; 564562236bSHarry Wentland }; 574562236bSHarry Wentland 584562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 594562236bSHarry Wentland { 604562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 614562236bSHarry Wentland }, 624562236bSHarry Wentland { 634562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 644562236bSHarry Wentland }, 654562236bSHarry Wentland { 664562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 674562236bSHarry Wentland }, 684562236bSHarry Wentland { 694562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 704562236bSHarry Wentland } 714562236bSHarry Wentland }; 724562236bSHarry Wentland 734562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 744562236bSHarry Wentland (reg + reg_offsets[id].blnd) 754562236bSHarry Wentland 764562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 774562236bSHarry Wentland (reg + reg_offsets[id].crtc) 784562236bSHarry Wentland 794562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 804562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 814562236bSHarry Wentland 824562236bSHarry Wentland /******************************************************************************* 834562236bSHarry Wentland * Private definitions 844562236bSHarry Wentland ******************************************************************************/ 854562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 864562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 874562236bSHarry Wentland { 884562236bSHarry Wentland uint32_t addr; 894562236bSHarry Wentland uint32_t value = 0; 904562236bSHarry Wentland uint32_t chunk_int = 0; 914562236bSHarry Wentland uint32_t chunk_mul = 0; 924562236bSHarry Wentland 934562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 944562236bSHarry Wentland value = dm_read_reg(ctx, addr); 954562236bSHarry Wentland 964562236bSHarry Wentland set_reg_field_value( 974562236bSHarry Wentland value, 984562236bSHarry Wentland 0, 994562236bSHarry Wentland DVMM_PTE_CONTROL, 1004562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1014562236bSHarry Wentland 1024562236bSHarry Wentland set_reg_field_value( 1034562236bSHarry Wentland value, 1044562236bSHarry Wentland 1, 1054562236bSHarry Wentland DVMM_PTE_CONTROL, 1064562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1074562236bSHarry Wentland 1084562236bSHarry Wentland set_reg_field_value( 1094562236bSHarry Wentland value, 1104562236bSHarry Wentland 1, 1114562236bSHarry Wentland DVMM_PTE_CONTROL, 1124562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1134562236bSHarry Wentland 1144562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1154562236bSHarry Wentland 1164562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1174562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1184562236bSHarry Wentland 1194562236bSHarry Wentland chunk_int = get_reg_field_value( 1204562236bSHarry Wentland value, 1214562236bSHarry Wentland DVMM_PTE_REQ, 1224562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1234562236bSHarry Wentland 1244562236bSHarry Wentland chunk_mul = get_reg_field_value( 1254562236bSHarry Wentland value, 1264562236bSHarry Wentland DVMM_PTE_REQ, 1274562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1284562236bSHarry Wentland 1294562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1304562236bSHarry Wentland 1314562236bSHarry Wentland set_reg_field_value( 1324562236bSHarry Wentland value, 1334562236bSHarry Wentland 255, 1344562236bSHarry Wentland DVMM_PTE_REQ, 1354562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1364562236bSHarry Wentland 1374562236bSHarry Wentland set_reg_field_value( 1384562236bSHarry Wentland value, 1394562236bSHarry Wentland 4, 1404562236bSHarry Wentland DVMM_PTE_REQ, 1414562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1424562236bSHarry Wentland 1434562236bSHarry Wentland set_reg_field_value( 1444562236bSHarry Wentland value, 1454562236bSHarry Wentland 4, 1464562236bSHarry Wentland DVMM_PTE_REQ, 1474562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1484562236bSHarry Wentland 1494562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1504562236bSHarry Wentland } 1514562236bSHarry Wentland } 1524562236bSHarry Wentland /**************************************************************************/ 1534562236bSHarry Wentland 1544562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1554562236bSHarry Wentland struct dc_context *ctx, 1564562236bSHarry Wentland bool clock_gating) 1574562236bSHarry Wentland { 1584562236bSHarry Wentland /*TODO*/ 1594562236bSHarry Wentland } 1604562236bSHarry Wentland 1614562236bSHarry Wentland static bool dce110_enable_display_power_gating( 1624562236bSHarry Wentland struct core_dc *dc, 1634562236bSHarry Wentland uint8_t controller_id, 1644562236bSHarry Wentland struct dc_bios *dcb, 1654562236bSHarry Wentland enum pipe_gating_control power_gating) 1664562236bSHarry Wentland { 1674562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 1684562236bSHarry Wentland enum bp_pipe_control_action cntl; 1694562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 1704562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1714562236bSHarry Wentland 1724562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1734562236bSHarry Wentland return true; 1744562236bSHarry Wentland 1754562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 1764562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 1774562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 1784562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 1794562236bSHarry Wentland else 1804562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 1814562236bSHarry Wentland 1824562236bSHarry Wentland if (controller_id == underlay_idx) 1834562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 1844562236bSHarry Wentland 1854562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 1864562236bSHarry Wentland 1874562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 1884562236bSHarry Wentland dcb, controller_id + 1, cntl); 1894562236bSHarry Wentland 1904562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 1914562236bSHarry Wentland * by default when command table is called 1924562236bSHarry Wentland * 1934562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 1944562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 1954562236bSHarry Wentland * than 3. 1964562236bSHarry Wentland */ 1974562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 1984562236bSHarry Wentland dm_write_reg(ctx, 1994562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2004562236bSHarry Wentland 0); 2014562236bSHarry Wentland } 2024562236bSHarry Wentland 2034562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2044562236bSHarry Wentland dce110_init_pte(ctx); 2054562236bSHarry Wentland 2064562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2074562236bSHarry Wentland return true; 2084562236bSHarry Wentland else 2094562236bSHarry Wentland return false; 2104562236bSHarry Wentland } 2114562236bSHarry Wentland 2124562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2134562236bSHarry Wentland const struct core_surface *surface) 2144562236bSHarry Wentland { 2154562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2164562236bSHarry Wentland 2174562236bSHarry Wentland switch (surface->public.format) { 2184562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2198693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2204562236bSHarry Wentland prescale_params->scale = 0x2020; 2214562236bSHarry Wentland break; 2224562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2234562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2244562236bSHarry Wentland prescale_params->scale = 0x2008; 2254562236bSHarry Wentland break; 2264562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2274562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2284562236bSHarry Wentland prescale_params->scale = 0x2000; 2294562236bSHarry Wentland break; 2304562236bSHarry Wentland default: 2314562236bSHarry Wentland ASSERT(false); 232d7194cf6SAric Cyr break; 2334562236bSHarry Wentland } 2344562236bSHarry Wentland } 2354562236bSHarry Wentland 236d7194cf6SAric Cyr static bool dce110_set_input_transfer_func( 237fb735a9fSAnthony Koo struct pipe_ctx *pipe_ctx, 2384562236bSHarry Wentland const struct core_surface *surface) 2394562236bSHarry Wentland { 240fb735a9fSAnthony Koo struct input_pixel_processor *ipp = pipe_ctx->ipp; 24190e508baSAnthony Koo const struct core_transfer_func *tf = NULL; 24290e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 24390e508baSAnthony Koo bool result = true; 24490e508baSAnthony Koo 24590e508baSAnthony Koo if (ipp == NULL) 24690e508baSAnthony Koo return false; 24790e508baSAnthony Koo 24890e508baSAnthony Koo if (surface->public.in_transfer_func) 24990e508baSAnthony Koo tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func); 25090e508baSAnthony Koo 25190e508baSAnthony Koo build_prescale_params(&prescale_params, surface); 25290e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 25390e508baSAnthony Koo 254d7194cf6SAric Cyr if (surface->public.gamma_correction) 255d7194cf6SAric Cyr ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); 256d7194cf6SAric Cyr 25790e508baSAnthony Koo if (tf == NULL) { 25890e508baSAnthony Koo /* Default case if no input transfer function specified */ 25990e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 260306dadf0SAmy Zhang IPP_DEGAMMA_MODE_HW_sRGB); 26190e508baSAnthony Koo } else if (tf->public.type == TF_TYPE_PREDEFINED) { 26290e508baSAnthony Koo switch (tf->public.tf) { 26390e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 26490e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 26590e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_sRGB); 26690e508baSAnthony Koo break; 26790e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 26890e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 26990e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_xvYCC); 27090e508baSAnthony Koo break; 27190e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 27290e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 27390e508baSAnthony Koo IPP_DEGAMMA_MODE_BYPASS); 27490e508baSAnthony Koo break; 27590e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 27690e508baSAnthony Koo result = false; 27790e508baSAnthony Koo break; 27890e508baSAnthony Koo default: 27990e508baSAnthony Koo result = false; 280d7194cf6SAric Cyr break; 28190e508baSAnthony Koo } 28290e508baSAnthony Koo } else { 28390e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 28490e508baSAnthony Koo result = false; 28590e508baSAnthony Koo } 28690e508baSAnthony Koo 28790e508baSAnthony Koo return result; 28890e508baSAnthony Koo } 28990e508baSAnthony Koo 290fcd2f4bfSAmy Zhang static bool convert_to_custom_float( 291fcd2f4bfSAmy Zhang struct pwl_result_data *rgb_resulted, 292fcd2f4bfSAmy Zhang struct curve_points *arr_points, 293fcd2f4bfSAmy Zhang uint32_t hw_points_num) 294fcd2f4bfSAmy Zhang { 295fcd2f4bfSAmy Zhang struct custom_float_format fmt; 296fcd2f4bfSAmy Zhang 297fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 298fcd2f4bfSAmy Zhang 299fcd2f4bfSAmy Zhang uint32_t i = 0; 300fcd2f4bfSAmy Zhang 301fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 302fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 303fcd2f4bfSAmy Zhang fmt.sign = true; 304fcd2f4bfSAmy Zhang 305fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 306fcd2f4bfSAmy Zhang arr_points[0].x, 307fcd2f4bfSAmy Zhang &fmt, 308fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 309fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 310fcd2f4bfSAmy Zhang return false; 311fcd2f4bfSAmy Zhang } 312fcd2f4bfSAmy Zhang 313fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 314fcd2f4bfSAmy Zhang arr_points[0].offset, 315fcd2f4bfSAmy Zhang &fmt, 316fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 317fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 318fcd2f4bfSAmy Zhang return false; 319fcd2f4bfSAmy Zhang } 320fcd2f4bfSAmy Zhang 321fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 322fcd2f4bfSAmy Zhang arr_points[0].slope, 323fcd2f4bfSAmy Zhang &fmt, 324fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 325fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 326fcd2f4bfSAmy Zhang return false; 327fcd2f4bfSAmy Zhang } 328fcd2f4bfSAmy Zhang 329fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 330fcd2f4bfSAmy Zhang fmt.sign = false; 331fcd2f4bfSAmy Zhang 332fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 333fcd2f4bfSAmy Zhang arr_points[1].x, 334fcd2f4bfSAmy Zhang &fmt, 335fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 336fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 337fcd2f4bfSAmy Zhang return false; 338fcd2f4bfSAmy Zhang } 339fcd2f4bfSAmy Zhang 340fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 341fcd2f4bfSAmy Zhang arr_points[1].y, 342fcd2f4bfSAmy Zhang &fmt, 343fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 344fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 345fcd2f4bfSAmy Zhang return false; 346fcd2f4bfSAmy Zhang } 347fcd2f4bfSAmy Zhang 348fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 349fcd2f4bfSAmy Zhang arr_points[2].slope, 350fcd2f4bfSAmy Zhang &fmt, 351fcd2f4bfSAmy Zhang &arr_points[2].custom_float_slope)) { 352fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 353fcd2f4bfSAmy Zhang return false; 354fcd2f4bfSAmy Zhang } 355fcd2f4bfSAmy Zhang 356fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 357fcd2f4bfSAmy Zhang fmt.sign = true; 358fcd2f4bfSAmy Zhang 359fcd2f4bfSAmy Zhang while (i != hw_points_num) { 360fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 361fcd2f4bfSAmy Zhang rgb->red, 362fcd2f4bfSAmy Zhang &fmt, 363fcd2f4bfSAmy Zhang &rgb->red_reg)) { 364fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 365fcd2f4bfSAmy Zhang return false; 366fcd2f4bfSAmy Zhang } 367fcd2f4bfSAmy Zhang 368fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 369fcd2f4bfSAmy Zhang rgb->green, 370fcd2f4bfSAmy Zhang &fmt, 371fcd2f4bfSAmy Zhang &rgb->green_reg)) { 372fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 373fcd2f4bfSAmy Zhang return false; 374fcd2f4bfSAmy Zhang } 375fcd2f4bfSAmy Zhang 376fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 377fcd2f4bfSAmy Zhang rgb->blue, 378fcd2f4bfSAmy Zhang &fmt, 379fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 380fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 381fcd2f4bfSAmy Zhang return false; 382fcd2f4bfSAmy Zhang } 383fcd2f4bfSAmy Zhang 384fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 385fcd2f4bfSAmy Zhang rgb->delta_red, 386fcd2f4bfSAmy Zhang &fmt, 387fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 388fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 389fcd2f4bfSAmy Zhang return false; 390fcd2f4bfSAmy Zhang } 391fcd2f4bfSAmy Zhang 392fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 393fcd2f4bfSAmy Zhang rgb->delta_green, 394fcd2f4bfSAmy Zhang &fmt, 395fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 396fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 397fcd2f4bfSAmy Zhang return false; 398fcd2f4bfSAmy Zhang } 399fcd2f4bfSAmy Zhang 400fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 401fcd2f4bfSAmy Zhang rgb->delta_blue, 402fcd2f4bfSAmy Zhang &fmt, 403fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 404fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 405fcd2f4bfSAmy Zhang return false; 406fcd2f4bfSAmy Zhang } 407fcd2f4bfSAmy Zhang 408fcd2f4bfSAmy Zhang ++rgb; 409fcd2f4bfSAmy Zhang ++i; 410fcd2f4bfSAmy Zhang } 411fcd2f4bfSAmy Zhang 412fcd2f4bfSAmy Zhang return true; 413fcd2f4bfSAmy Zhang } 414fcd2f4bfSAmy Zhang 415e266fdf6SVitaly Prosyak static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func 416fcd2f4bfSAmy Zhang *output_tf, struct pwl_params *regamma_params) 417fcd2f4bfSAmy Zhang { 41823ae4f8eSAmy Zhang struct curve_points *arr_points; 41923ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 42023ae4f8eSAmy Zhang struct pwl_result_data *rgb; 42123ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 422fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 423fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 424fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 425fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 426fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 427fcd2f4bfSAmy Zhang 428fcd2f4bfSAmy Zhang int32_t segment_start, segment_end; 42923ae4f8eSAmy Zhang uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; 43023ae4f8eSAmy Zhang 43123ae4f8eSAmy Zhang if (output_tf == NULL || regamma_params == NULL) 43223ae4f8eSAmy Zhang return false; 43323ae4f8eSAmy Zhang 43423ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 43523ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 43623ae4f8eSAmy Zhang hw_points = 0; 437fcd2f4bfSAmy Zhang 438fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 439fcd2f4bfSAmy Zhang 440fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 441534db198SAmy Zhang /* 16 segments 442fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 443fcd2f4bfSAmy Zhang */ 444fcd2f4bfSAmy Zhang segment_start = -11; 445fcd2f4bfSAmy Zhang segment_end = 5; 446fcd2f4bfSAmy Zhang 447534db198SAmy Zhang seg_distr[0] = 2; 448534db198SAmy Zhang seg_distr[1] = 2; 449534db198SAmy Zhang seg_distr[2] = 2; 450534db198SAmy Zhang seg_distr[3] = 2; 451534db198SAmy Zhang seg_distr[4] = 2; 452534db198SAmy Zhang seg_distr[5] = 2; 453534db198SAmy Zhang seg_distr[6] = 3; 454534db198SAmy Zhang seg_distr[7] = 4; 455534db198SAmy Zhang seg_distr[8] = 4; 456534db198SAmy Zhang seg_distr[9] = 4; 457534db198SAmy Zhang seg_distr[10] = 4; 458534db198SAmy Zhang seg_distr[11] = 5; 459534db198SAmy Zhang seg_distr[12] = 5; 460534db198SAmy Zhang seg_distr[13] = 5; 461534db198SAmy Zhang seg_distr[14] = 5; 462534db198SAmy Zhang seg_distr[15] = 5; 463534db198SAmy Zhang 464fcd2f4bfSAmy Zhang } else { 465534db198SAmy Zhang /* 10 segments 466fcd2f4bfSAmy Zhang * segment is from 2^-10 to 2^0 467fcd2f4bfSAmy Zhang */ 468fcd2f4bfSAmy Zhang segment_start = -10; 469fcd2f4bfSAmy Zhang segment_end = 0; 470534db198SAmy Zhang 471534db198SAmy Zhang seg_distr[0] = 3; 472534db198SAmy Zhang seg_distr[1] = 4; 473534db198SAmy Zhang seg_distr[2] = 4; 474534db198SAmy Zhang seg_distr[3] = 4; 475534db198SAmy Zhang seg_distr[4] = 4; 476534db198SAmy Zhang seg_distr[5] = 4; 477534db198SAmy Zhang seg_distr[6] = 4; 478534db198SAmy Zhang seg_distr[7] = 4; 479534db198SAmy Zhang seg_distr[8] = 5; 480534db198SAmy Zhang seg_distr[9] = 5; 481534db198SAmy Zhang seg_distr[10] = -1; 482534db198SAmy Zhang seg_distr[11] = -1; 483534db198SAmy Zhang seg_distr[12] = -1; 484534db198SAmy Zhang seg_distr[13] = -1; 485534db198SAmy Zhang seg_distr[14] = -1; 486534db198SAmy Zhang seg_distr[15] = -1; 487fcd2f4bfSAmy Zhang } 488fcd2f4bfSAmy Zhang 489534db198SAmy Zhang for (k = 0; k < 16; k++) { 490534db198SAmy Zhang if (seg_distr[k] != -1) 491534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 492534db198SAmy Zhang } 493534db198SAmy Zhang 494fcd2f4bfSAmy Zhang j = 0; 495534db198SAmy Zhang for (k = 0; k < (segment_end - segment_start); k++) { 496534db198SAmy Zhang increment = 32 / (1 << seg_distr[k]); 497534db198SAmy Zhang start_index = (segment_start + k + 25) * 32; 498534db198SAmy Zhang for (i = start_index; i < start_index + 32; i += increment) { 499534db198SAmy Zhang if (j == hw_points - 1) 500fcd2f4bfSAmy Zhang break; 501fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 502fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 503fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 504fcd2f4bfSAmy Zhang j++; 505fcd2f4bfSAmy Zhang } 506534db198SAmy Zhang } 507534db198SAmy Zhang 508534db198SAmy Zhang /* last point */ 509534db198SAmy Zhang start_index = (segment_end + 25) * 32; 510534db198SAmy Zhang rgb_resulted[hw_points - 1].red = 511534db198SAmy Zhang output_tf->tf_pts.red[start_index]; 512534db198SAmy Zhang rgb_resulted[hw_points - 1].green = 513534db198SAmy Zhang output_tf->tf_pts.green[start_index]; 514534db198SAmy Zhang rgb_resulted[hw_points - 1].blue = 515534db198SAmy Zhang output_tf->tf_pts.blue[start_index]; 516fcd2f4bfSAmy Zhang 517fcd2f4bfSAmy Zhang arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 518fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_start)); 519fcd2f4bfSAmy Zhang arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 520fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 521fcd2f4bfSAmy Zhang arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 522fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 523fcd2f4bfSAmy Zhang 524fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 525fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 526fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 527fcd2f4bfSAmy Zhang 528fcd2f4bfSAmy Zhang y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); 529fcd2f4bfSAmy Zhang 530fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 531fcd2f4bfSAmy Zhang arr_points[0].slope = dal_fixed31_32_div( 532fcd2f4bfSAmy Zhang arr_points[0].y, 533fcd2f4bfSAmy Zhang arr_points[0].x); 534fcd2f4bfSAmy Zhang 535fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 536fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 537fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 538fcd2f4bfSAmy Zhang 539fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 540fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 541fcd2f4bfSAmy Zhang */ 542fcd2f4bfSAmy Zhang y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); 543fcd2f4bfSAmy Zhang 544fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 545fcd2f4bfSAmy Zhang arr_points[2].y = y3_max; 546fcd2f4bfSAmy Zhang 547fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_zero; 548fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_zero; 549fcd2f4bfSAmy Zhang 550fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 551fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 552fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 553fcd2f4bfSAmy Zhang */ 554fcd2f4bfSAmy Zhang const struct fixed31_32 end_value = 555fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(125); 556fcd2f4bfSAmy Zhang 557fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_div( 558fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 559fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 560fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_div( 561fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 562fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 563fcd2f4bfSAmy Zhang } 564fcd2f4bfSAmy Zhang 565fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 566fcd2f4bfSAmy Zhang 567534db198SAmy Zhang i = 1; 568534db198SAmy Zhang for (k = 0; k < 16 && i < 16; k++) { 569534db198SAmy Zhang if (seg_distr[k] != -1) { 570534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 571534db198SAmy Zhang seg_distr[k]; 572534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 573534db198SAmy Zhang regamma_params->arr_curve_points[k]. 574534db198SAmy Zhang offset + (1 << seg_distr[k]); 575fcd2f4bfSAmy Zhang } 576534db198SAmy Zhang i++; 577534db198SAmy Zhang } 578534db198SAmy Zhang 579534db198SAmy Zhang if (seg_distr[k] != -1) 580534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 581534db198SAmy Zhang seg_distr[k]; 582fcd2f4bfSAmy Zhang 58323ae4f8eSAmy Zhang rgb = rgb_resulted; 58423ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 585fcd2f4bfSAmy Zhang 586fcd2f4bfSAmy Zhang i = 1; 587fcd2f4bfSAmy Zhang 588fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 589fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) 590fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 591fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) 592fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 593fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) 594fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 595fcd2f4bfSAmy Zhang 596fcd2f4bfSAmy Zhang rgb->delta_red = dal_fixed31_32_sub( 597fcd2f4bfSAmy Zhang rgb_plus_1->red, 598fcd2f4bfSAmy Zhang rgb->red); 599fcd2f4bfSAmy Zhang rgb->delta_green = dal_fixed31_32_sub( 600fcd2f4bfSAmy Zhang rgb_plus_1->green, 601fcd2f4bfSAmy Zhang rgb->green); 602fcd2f4bfSAmy Zhang rgb->delta_blue = dal_fixed31_32_sub( 603fcd2f4bfSAmy Zhang rgb_plus_1->blue, 604fcd2f4bfSAmy Zhang rgb->blue); 605fcd2f4bfSAmy Zhang 606fcd2f4bfSAmy Zhang ++rgb_plus_1; 607fcd2f4bfSAmy Zhang ++rgb; 608fcd2f4bfSAmy Zhang ++i; 609fcd2f4bfSAmy Zhang } 610fcd2f4bfSAmy Zhang 611fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 612fcd2f4bfSAmy Zhang 613fcd2f4bfSAmy Zhang return true; 614fcd2f4bfSAmy Zhang } 615fcd2f4bfSAmy Zhang 61690e508baSAnthony Koo static bool dce110_set_output_transfer_func( 61790e508baSAnthony Koo struct pipe_ctx *pipe_ctx, 61890e508baSAnthony Koo const struct core_surface *surface, /* Surface - To be removed */ 61990e508baSAnthony Koo const struct core_stream *stream) 62090e508baSAnthony Koo { 621fb735a9fSAnthony Koo struct output_pixel_processor *opp = pipe_ctx->opp; 6224562236bSHarry Wentland 6234562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, true); 624cc0cb445SLeon Elazar opp->regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM; 6254562236bSHarry Wentland 626d7194cf6SAric Cyr if (stream->public.out_transfer_func && 627fcd2f4bfSAmy Zhang stream->public.out_transfer_func->type == 628fcd2f4bfSAmy Zhang TF_TYPE_PREDEFINED && 629fcd2f4bfSAmy Zhang stream->public.out_transfer_func->tf == 630fcd2f4bfSAmy Zhang TRANSFER_FUNCTION_SRGB) { 631d7194cf6SAric Cyr opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); 632fcd2f4bfSAmy Zhang } else if (dce110_translate_regamma_to_hw_format( 633cc0cb445SLeon Elazar stream->public.out_transfer_func, opp->regamma_params)) { 634cc0cb445SLeon Elazar opp->funcs->opp_program_regamma_pwl(opp, opp->regamma_params); 6354562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); 6364562236bSHarry Wentland } else { 6374562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); 6384562236bSHarry Wentland } 6394562236bSHarry Wentland 6404562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, false); 6414562236bSHarry Wentland 642cc0cb445SLeon Elazar return true; 6434562236bSHarry Wentland } 6444562236bSHarry Wentland 6454562236bSHarry Wentland static enum dc_status bios_parser_crtc_source_select( 6464562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 6474562236bSHarry Wentland { 6484562236bSHarry Wentland struct dc_bios *dcb; 6494562236bSHarry Wentland /* call VBIOS table to set CRTC source for the HW 6504562236bSHarry Wentland * encoder block 6514562236bSHarry Wentland * note: video bios clears all FMT setting here. */ 6524562236bSHarry Wentland struct bp_crtc_source_select crtc_source_select = {0}; 6534562236bSHarry Wentland const struct core_sink *sink = pipe_ctx->stream->sink; 6544562236bSHarry Wentland 6554562236bSHarry Wentland crtc_source_select.engine_id = pipe_ctx->stream_enc->id; 6564562236bSHarry Wentland crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1; 6574562236bSHarry Wentland /*TODO: Need to un-hardcode color depth, dp_audio and account for 6584562236bSHarry Wentland * the case where signal and sink signal is different (translator 6594562236bSHarry Wentland * encoder)*/ 6604562236bSHarry Wentland crtc_source_select.signal = pipe_ctx->stream->signal; 6614562236bSHarry Wentland crtc_source_select.enable_dp_audio = false; 6624562236bSHarry Wentland crtc_source_select.sink_signal = pipe_ctx->stream->signal; 6634562236bSHarry Wentland crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6644562236bSHarry Wentland 6654562236bSHarry Wentland dcb = sink->ctx->dc_bios; 6664562236bSHarry Wentland 6674562236bSHarry Wentland if (BP_RESULT_OK != dcb->funcs->crtc_source_select( 6684562236bSHarry Wentland dcb, 6694562236bSHarry Wentland &crtc_source_select)) { 6704562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 6714562236bSHarry Wentland } 6724562236bSHarry Wentland 6734562236bSHarry Wentland return DC_OK; 6744562236bSHarry Wentland } 6754562236bSHarry Wentland 6764562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6774562236bSHarry Wentland { 67886e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 67986e2e1beSHersen Wu 68086e2e1beSHersen Wu if (pipe_ctx->stream_enc == NULL) 68186e2e1beSHersen Wu return; /* this is not root pipe */ 68286e2e1beSHersen Wu 6834562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 6844562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_hdmi_info_packets( 6854562236bSHarry Wentland pipe_ctx->stream_enc, 6864562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 6874562236bSHarry Wentland else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6884562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_dp_info_packets( 6894562236bSHarry Wentland pipe_ctx->stream_enc, 6904562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 6914562236bSHarry Wentland } 6924562236bSHarry Wentland 6934562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6944562236bSHarry Wentland { 6954562236bSHarry Wentland enum dc_lane_count lane_count = 6964562236bSHarry Wentland pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count; 6974562236bSHarry Wentland 6984562236bSHarry Wentland struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; 6994562236bSHarry Wentland struct core_link *link = pipe_ctx->stream->sink->link; 7004562236bSHarry Wentland 7014562236bSHarry Wentland /* 1. update AVI info frame (HDMI, DP) 7024562236bSHarry Wentland * we always need to update info frame 7034562236bSHarry Wentland */ 7044562236bSHarry Wentland uint32_t active_total_with_borders; 7054562236bSHarry Wentland uint32_t early_control = 0; 7064562236bSHarry Wentland struct timing_generator *tg = pipe_ctx->tg; 7074562236bSHarry Wentland 7084562236bSHarry Wentland /* TODOFPGA may change to hwss.update_info_frame */ 7094562236bSHarry Wentland dce110_update_info_frame(pipe_ctx); 7104562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 7114562236bSHarry Wentland active_total_with_borders = 7124562236bSHarry Wentland timing->h_addressable 7134562236bSHarry Wentland + timing->h_border_left 7144562236bSHarry Wentland + timing->h_border_right; 7154562236bSHarry Wentland 7164562236bSHarry Wentland if (lane_count != 0) 7174562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 7184562236bSHarry Wentland 7194562236bSHarry Wentland if (early_control == 0) 7204562236bSHarry Wentland early_control = lane_count; 7214562236bSHarry Wentland 7224562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 7234562236bSHarry Wentland 7244562236bSHarry Wentland /* enable audio only within mode set */ 7254562236bSHarry Wentland if (pipe_ctx->audio != NULL) { 7264562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7274562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc); 7284562236bSHarry Wentland } 7294562236bSHarry Wentland 7304562236bSHarry Wentland /* For MST, there are multiply stream go to only one link. 7314562236bSHarry Wentland * connect DIG back_end to front_end while enable_stream and 7324562236bSHarry Wentland * disconnect them during disable_stream 7334562236bSHarry Wentland * BY this, it is logic clean to separate stream and link */ 7344562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 7354562236bSHarry Wentland pipe_ctx->stream_enc->id, true); 7364562236bSHarry Wentland 7374562236bSHarry Wentland } 7384562236bSHarry Wentland 7394562236bSHarry Wentland void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 7404562236bSHarry Wentland { 7414562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 7424562236bSHarry Wentland struct core_link *link = stream->sink->link; 7434562236bSHarry Wentland 7444562236bSHarry Wentland if (pipe_ctx->audio) { 7454562236bSHarry Wentland pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); 7464562236bSHarry Wentland 7474562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7484562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_disable( 7494562236bSHarry Wentland pipe_ctx->stream_enc); 7504562236bSHarry Wentland else 7514562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_disable( 7524562236bSHarry Wentland pipe_ctx->stream_enc); 7534562236bSHarry Wentland 7544562236bSHarry Wentland pipe_ctx->audio = NULL; 7554562236bSHarry Wentland 7564562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 7574562236bSHarry Wentland * add audio mode list change flag */ 7584562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 7594562236bSHarry Wentland * stream->stream_engine_id); 7604562236bSHarry Wentland */ 7614562236bSHarry Wentland } 7624562236bSHarry Wentland 7634562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 7644562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets( 7654562236bSHarry Wentland pipe_ctx->stream_enc); 7664562236bSHarry Wentland 7674562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7684562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_dp_info_packets( 7694562236bSHarry Wentland pipe_ctx->stream_enc); 7704562236bSHarry Wentland 7714562236bSHarry Wentland pipe_ctx->stream_enc->funcs->audio_mute_control( 7724562236bSHarry Wentland pipe_ctx->stream_enc, true); 7734562236bSHarry Wentland 7744562236bSHarry Wentland 7754562236bSHarry Wentland /* blank at encoder level */ 7764562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7774562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc); 7784562236bSHarry Wentland 7794562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 7804562236bSHarry Wentland link->link_enc, 7814562236bSHarry Wentland pipe_ctx->stream_enc->id, 7824562236bSHarry Wentland false); 7834562236bSHarry Wentland 7844562236bSHarry Wentland } 7854562236bSHarry Wentland 7864562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 7874562236bSHarry Wentland struct dc_link_settings *link_settings) 7884562236bSHarry Wentland { 7894562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 7904562236bSHarry Wentland 7914562236bSHarry Wentland /* only 3 items below are used by unblank */ 7926235b23cSTony Cheng params.pixel_clk_khz = 7934562236bSHarry Wentland pipe_ctx->stream->public.timing.pix_clk_khz; 7944562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 7954562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); 7964562236bSHarry Wentland } 7974562236bSHarry Wentland 7984562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 7994562236bSHarry Wentland { 8004562236bSHarry Wentland switch (crtc_id) { 8014562236bSHarry Wentland case CONTROLLER_ID_D0: 8024562236bSHarry Wentland return DTO_SOURCE_ID0; 8034562236bSHarry Wentland case CONTROLLER_ID_D1: 8044562236bSHarry Wentland return DTO_SOURCE_ID1; 8054562236bSHarry Wentland case CONTROLLER_ID_D2: 8064562236bSHarry Wentland return DTO_SOURCE_ID2; 8074562236bSHarry Wentland case CONTROLLER_ID_D3: 8084562236bSHarry Wentland return DTO_SOURCE_ID3; 8094562236bSHarry Wentland case CONTROLLER_ID_D4: 8104562236bSHarry Wentland return DTO_SOURCE_ID4; 8114562236bSHarry Wentland case CONTROLLER_ID_D5: 8124562236bSHarry Wentland return DTO_SOURCE_ID5; 8134562236bSHarry Wentland default: 8144562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 8154562236bSHarry Wentland } 8164562236bSHarry Wentland } 8174562236bSHarry Wentland 8184562236bSHarry Wentland static void build_audio_output( 8194562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 8204562236bSHarry Wentland struct audio_output *audio_output) 8214562236bSHarry Wentland { 8224562236bSHarry Wentland const struct core_stream *stream = pipe_ctx->stream; 8234562236bSHarry Wentland audio_output->engine_id = pipe_ctx->stream_enc->id; 8244562236bSHarry Wentland 8254562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 8264562236bSHarry Wentland 8274562236bSHarry Wentland /* audio_crtc_info */ 8284562236bSHarry Wentland 8294562236bSHarry Wentland audio_output->crtc_info.h_total = 8304562236bSHarry Wentland stream->public.timing.h_total; 8314562236bSHarry Wentland 8324562236bSHarry Wentland /* 8334562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 8344562236bSHarry Wentland * need to specify actual active signal portion 8354562236bSHarry Wentland */ 8364562236bSHarry Wentland audio_output->crtc_info.h_active = 8374562236bSHarry Wentland stream->public.timing.h_addressable 8384562236bSHarry Wentland + stream->public.timing.h_border_left 8394562236bSHarry Wentland + stream->public.timing.h_border_right; 8404562236bSHarry Wentland 8414562236bSHarry Wentland audio_output->crtc_info.v_active = 8424562236bSHarry Wentland stream->public.timing.v_addressable 8434562236bSHarry Wentland + stream->public.timing.v_border_top 8444562236bSHarry Wentland + stream->public.timing.v_border_bottom; 8454562236bSHarry Wentland 8464562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 8474562236bSHarry Wentland 8484562236bSHarry Wentland audio_output->crtc_info.interlaced = 8494562236bSHarry Wentland stream->public.timing.flags.INTERLACE; 8504562236bSHarry Wentland 8514562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 8524562236bSHarry Wentland (stream->public.timing.pix_clk_khz*1000)/ 8534562236bSHarry Wentland (stream->public.timing.h_total*stream->public.timing.v_total); 8544562236bSHarry Wentland 8554562236bSHarry Wentland audio_output->crtc_info.color_depth = 8564562236bSHarry Wentland stream->public.timing.display_color_depth; 8574562236bSHarry Wentland 8584562236bSHarry Wentland audio_output->crtc_info.requested_pixel_clock = 8594562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 8604562236bSHarry Wentland 8614562236bSHarry Wentland /* 8624562236bSHarry Wentland * TODO - Investigate why calculated pixel clk has to be 8634562236bSHarry Wentland * requested pixel clk 8644562236bSHarry Wentland */ 8654562236bSHarry Wentland audio_output->crtc_info.calculated_pixel_clock = 8664562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 8674562236bSHarry Wentland 8684562236bSHarry Wentland if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 8694562236bSHarry Wentland pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 8704562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 8711a687574SDmytro Laktyushkin pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency( 8724562236bSHarry Wentland pipe_ctx->dis_clk); 8734562236bSHarry Wentland } 8744562236bSHarry Wentland 8754562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 8764562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 8774562236bSHarry Wentland 8784562236bSHarry Wentland audio_output->pll_info.dto_source = 8794562236bSHarry Wentland translate_to_dto_source( 8804562236bSHarry Wentland pipe_ctx->pipe_idx + 1); 8814562236bSHarry Wentland 8824562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 8834562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 8844562236bSHarry Wentland 8854562236bSHarry Wentland audio_output->pll_info.ss_percentage = 8864562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 8874562236bSHarry Wentland } 8884562236bSHarry Wentland 8894562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 8904562236bSHarry Wentland struct tg_color *color) 8914562236bSHarry Wentland { 8924562236bSHarry Wentland uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4; 8934562236bSHarry Wentland 8944562236bSHarry Wentland switch (pipe_ctx->scl_data.format) { 8954562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 8964562236bSHarry Wentland /* set boarder color to red */ 8974562236bSHarry Wentland color->color_r_cr = color_value; 8984562236bSHarry Wentland break; 8994562236bSHarry Wentland 9004562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 9014562236bSHarry Wentland /* set boarder color to blue */ 9024562236bSHarry Wentland color->color_b_cb = color_value; 9034562236bSHarry Wentland break; 9044562236bSHarry Wentland case PIXEL_FORMAT_420BPP12: 9054562236bSHarry Wentland /* set boarder color to green */ 9064562236bSHarry Wentland color->color_g_y = color_value; 9074562236bSHarry Wentland break; 9084562236bSHarry Wentland case PIXEL_FORMAT_FP16: 9094562236bSHarry Wentland /* set boarder color to white */ 9104562236bSHarry Wentland color->color_r_cr = color_value; 9114562236bSHarry Wentland color->color_b_cb = color_value; 9124562236bSHarry Wentland color->color_g_y = color_value; 9134562236bSHarry Wentland break; 9144562236bSHarry Wentland default: 9154562236bSHarry Wentland break; 9164562236bSHarry Wentland } 9174562236bSHarry Wentland } 9184562236bSHarry Wentland 9194562236bSHarry Wentland static void program_scaler(const struct core_dc *dc, 9204562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 9214562236bSHarry Wentland { 9224562236bSHarry Wentland struct tg_color color = {0}; 9234562236bSHarry Wentland 9244562236bSHarry Wentland if (dc->public.debug.surface_visual_confirm) 9254562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 9264562236bSHarry Wentland else 9274562236bSHarry Wentland color_space_to_black_color(dc, 9284562236bSHarry Wentland pipe_ctx->stream->public.output_color_space, 9294562236bSHarry Wentland &color); 9304562236bSHarry Wentland 9314562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( 9324562236bSHarry Wentland pipe_ctx->xfm, 9334562236bSHarry Wentland pipe_ctx->scl_data.lb_params.depth, 9344562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 9354562236bSHarry Wentland 9364562236bSHarry Wentland if (pipe_ctx->tg->funcs->set_overscan_blank_color) 9374562236bSHarry Wentland pipe_ctx->tg->funcs->set_overscan_blank_color( 9384562236bSHarry Wentland pipe_ctx->tg, 9394562236bSHarry Wentland &color); 9404562236bSHarry Wentland 9414562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, 9424562236bSHarry Wentland &pipe_ctx->scl_data); 9434562236bSHarry Wentland } 9444562236bSHarry Wentland 9454b5e7d62SHersen Wu static enum dc_status dce110_prog_pixclk_crtc_otg( 9464562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 9474562236bSHarry Wentland struct validate_context *context, 9484562236bSHarry Wentland struct core_dc *dc) 9494562236bSHarry Wentland { 9504562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 9514562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 9524562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 9534562236bSHarry Wentland struct tg_color black_color = {0}; 9544562236bSHarry Wentland 9554562236bSHarry Wentland if (!pipe_ctx_old->stream) { 9564562236bSHarry Wentland 9574562236bSHarry Wentland /* program blank color */ 9584562236bSHarry Wentland color_space_to_black_color(dc, 9594562236bSHarry Wentland stream->public.output_color_space, &black_color); 9604562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank_color( 9614562236bSHarry Wentland pipe_ctx->tg, 9624562236bSHarry Wentland &black_color); 9634b5e7d62SHersen Wu 9644562236bSHarry Wentland /* 9654562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 9664562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 9674562236bSHarry Wentland */ 9684562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 9694562236bSHarry Wentland 9704562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 9714562236bSHarry Wentland pipe_ctx->clock_source, 9724562236bSHarry Wentland &pipe_ctx->pix_clk_params, 9734562236bSHarry Wentland &pipe_ctx->pll_settings)) { 9744562236bSHarry Wentland BREAK_TO_DEBUGGER(); 9754562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 9764562236bSHarry Wentland } 9774562236bSHarry Wentland 9784562236bSHarry Wentland pipe_ctx->tg->funcs->program_timing( 9794562236bSHarry Wentland pipe_ctx->tg, 9804562236bSHarry Wentland &stream->public.timing, 9814562236bSHarry Wentland true); 9824562236bSHarry Wentland } 9834562236bSHarry Wentland 9844562236bSHarry Wentland if (!pipe_ctx_old->stream) { 9854562236bSHarry Wentland if (false == pipe_ctx->tg->funcs->enable_crtc( 9864562236bSHarry Wentland pipe_ctx->tg)) { 9874562236bSHarry Wentland BREAK_TO_DEBUGGER(); 9884562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 9894562236bSHarry Wentland } 9904562236bSHarry Wentland } 9914562236bSHarry Wentland 9924562236bSHarry Wentland return DC_OK; 9934562236bSHarry Wentland } 9944562236bSHarry Wentland 9954562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 9964562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 9974562236bSHarry Wentland struct validate_context *context, 9984562236bSHarry Wentland struct core_dc *dc) 9994562236bSHarry Wentland { 10004562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 10014562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 10024562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 10034562236bSHarry Wentland 10044562236bSHarry Wentland /* */ 10054562236bSHarry Wentland dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); 10064562236bSHarry Wentland 10074562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_dyn_expansion( 10084562236bSHarry Wentland pipe_ctx->opp, 10094562236bSHarry Wentland COLOR_SPACE_YCBCR601, 10104562236bSHarry Wentland stream->public.timing.display_color_depth, 10114562236bSHarry Wentland pipe_ctx->stream->signal); 10124562236bSHarry Wentland 10134562236bSHarry Wentland pipe_ctx->opp->funcs->opp_program_fmt( 10144562236bSHarry Wentland pipe_ctx->opp, 10154562236bSHarry Wentland &stream->bit_depth_params, 10164562236bSHarry Wentland &stream->clamping); 10174562236bSHarry Wentland 10184562236bSHarry Wentland /* FPGA does not program backend */ 10194562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 10204562236bSHarry Wentland return DC_OK; 10214562236bSHarry Wentland 10224562236bSHarry Wentland /* TODO: move to stream encoder */ 10234562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 10244562236bSHarry Wentland if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { 10254562236bSHarry Wentland BREAK_TO_DEBUGGER(); 10264562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 10274562236bSHarry Wentland } 10284562236bSHarry Wentland 10294562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 10304562236bSHarry Wentland stream->sink->link->link_enc->funcs->setup( 10314562236bSHarry Wentland stream->sink->link->link_enc, 10324562236bSHarry Wentland pipe_ctx->stream->signal); 10334562236bSHarry Wentland 10344562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10354562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( 10364562236bSHarry Wentland pipe_ctx->stream_enc, 10374562236bSHarry Wentland &stream->public.timing, 10384562236bSHarry Wentland stream->public.output_color_space); 10394562236bSHarry Wentland 10404562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 10414562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( 10424562236bSHarry Wentland pipe_ctx->stream_enc, 10434562236bSHarry Wentland &stream->public.timing, 10444562236bSHarry Wentland stream->phy_pix_clk, 10454562236bSHarry Wentland pipe_ctx->audio != NULL); 10464562236bSHarry Wentland 10474562236bSHarry Wentland if (dc_is_dvi_signal(pipe_ctx->stream->signal)) 10484562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( 10494562236bSHarry Wentland pipe_ctx->stream_enc, 10504562236bSHarry Wentland &stream->public.timing, 10514562236bSHarry Wentland (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? 10524562236bSHarry Wentland true : false); 10534562236bSHarry Wentland 10544562236bSHarry Wentland if (!pipe_ctx_old->stream) { 10554562236bSHarry Wentland core_link_enable_stream(pipe_ctx); 10564562236bSHarry Wentland 1057b3c64dffSCharlene Liu resource_build_info_frame(pipe_ctx); 1058b3c64dffSCharlene Liu dce110_update_info_frame(pipe_ctx); 10594562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10604562236bSHarry Wentland dce110_unblank_stream(pipe_ctx, 10614562236bSHarry Wentland &stream->sink->link->public.cur_link_settings); 10624562236bSHarry Wentland } 10634562236bSHarry Wentland 10644562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 10654562236bSHarry Wentland /* program_scaler and allocate_mem_input are not new asic */ 10664562236bSHarry Wentland if (!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data, 10674562236bSHarry Wentland &pipe_ctx->scl_data, 10684562236bSHarry Wentland sizeof(struct scaler_data)) != 0) 10694562236bSHarry Wentland program_scaler(dc, pipe_ctx); 10704562236bSHarry Wentland 10714562236bSHarry Wentland /* mst support - use total stream count */ 10724562236bSHarry Wentland pipe_ctx->mi->funcs->allocate_mem_input( 10734562236bSHarry Wentland pipe_ctx->mi, 10744562236bSHarry Wentland stream->public.timing.h_total, 10754562236bSHarry Wentland stream->public.timing.v_total, 10764562236bSHarry Wentland stream->public.timing.pix_clk_khz, 1077ab2541b6SAric Cyr context->stream_count); 10784562236bSHarry Wentland 10794562236bSHarry Wentland return DC_OK; 10804562236bSHarry Wentland } 10814562236bSHarry Wentland 10824562236bSHarry Wentland /******************************************************************************/ 10834562236bSHarry Wentland 10844562236bSHarry Wentland static void power_down_encoders(struct core_dc *dc) 10854562236bSHarry Wentland { 10864562236bSHarry Wentland int i; 10874562236bSHarry Wentland 10884562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 10894562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 10904562236bSHarry Wentland dc->links[i]->link_enc, SIGNAL_TYPE_NONE); 10914562236bSHarry Wentland } 10924562236bSHarry Wentland } 10934562236bSHarry Wentland 10944562236bSHarry Wentland static void power_down_controllers(struct core_dc *dc) 10954562236bSHarry Wentland { 10964562236bSHarry Wentland int i; 10974562236bSHarry Wentland 10984562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 10994562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 11004562236bSHarry Wentland dc->res_pool->timing_generators[i]); 11014562236bSHarry Wentland } 11024562236bSHarry Wentland } 11034562236bSHarry Wentland 11044562236bSHarry Wentland static void power_down_clock_sources(struct core_dc *dc) 11054562236bSHarry Wentland { 11064562236bSHarry Wentland int i; 11074562236bSHarry Wentland 11084562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 11094562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 11104562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 11114562236bSHarry Wentland 11124562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 11134562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 11144562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 11154562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 11164562236bSHarry Wentland } 11174562236bSHarry Wentland } 11184562236bSHarry Wentland 11194562236bSHarry Wentland static void power_down_all_hw_blocks(struct core_dc *dc) 11204562236bSHarry Wentland { 11214562236bSHarry Wentland power_down_encoders(dc); 11224562236bSHarry Wentland 11234562236bSHarry Wentland power_down_controllers(dc); 11244562236bSHarry Wentland 11254562236bSHarry Wentland power_down_clock_sources(dc); 11264562236bSHarry Wentland } 11274562236bSHarry Wentland 11284562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 11294562236bSHarry Wentland struct core_dc *dc) 11304562236bSHarry Wentland { 11314562236bSHarry Wentland int i; 11324562236bSHarry Wentland struct timing_generator *tg; 11334562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 11344562236bSHarry Wentland 11354562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 11364562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 11374562236bSHarry Wentland 11384562236bSHarry Wentland tg->funcs->disable_vga(tg); 11394562236bSHarry Wentland 11404562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 11414562236bSHarry Wentland * powergating. */ 11424562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 11434562236bSHarry Wentland true); 11444562236bSHarry Wentland 11454562236bSHarry Wentland dc->hwss.power_down_front_end( 11464562236bSHarry Wentland dc, &dc->current_context->res_ctx.pipe_ctx[i]); 11474562236bSHarry Wentland } 11484562236bSHarry Wentland } 11494562236bSHarry Wentland 11504562236bSHarry Wentland /** 11514562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 11524562236bSHarry Wentland * 1. Power down all DC HW blocks 11534562236bSHarry Wentland * 2. Disable VGA engine on all controllers 11544562236bSHarry Wentland * 3. Enable power gating for controller 11554562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 11564562236bSHarry Wentland */ 11574562236bSHarry Wentland void dce110_enable_accelerated_mode(struct core_dc *dc) 11584562236bSHarry Wentland { 11594562236bSHarry Wentland power_down_all_hw_blocks(dc); 11604562236bSHarry Wentland 11614562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 11624562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 11634562236bSHarry Wentland } 11644562236bSHarry Wentland 11654562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 11664562236bSHarry Wentland struct bw_fixed blackout_duration, 11674562236bSHarry Wentland const struct core_stream *stream) 11684562236bSHarry Wentland { 11694562236bSHarry Wentland uint32_t total_dest_line_time_ns; 11704562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 11714562236bSHarry Wentland 11724562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 11734562236bSHarry Wentland 11744562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 11754562236bSHarry Wentland stream->public.timing.h_total / 11764562236bSHarry Wentland stream->public.timing.pix_clk_khz + 11774562236bSHarry Wentland pstate_blackout_duration_ns; 11784562236bSHarry Wentland 11794562236bSHarry Wentland return total_dest_line_time_ns; 11804562236bSHarry Wentland } 11814562236bSHarry Wentland 11824562236bSHarry Wentland /* get the index of the pipe_ctx if there were no gaps in the pipe_ctx array*/ 11834562236bSHarry Wentland int get_bw_result_idx( 11844562236bSHarry Wentland struct resource_context *res_ctx, 11854562236bSHarry Wentland int pipe_idx) 11864562236bSHarry Wentland { 11874562236bSHarry Wentland int i, collapsed_idx; 11884562236bSHarry Wentland 11894562236bSHarry Wentland if (res_ctx->pipe_ctx[pipe_idx].top_pipe) 11904562236bSHarry Wentland return 3; 11914562236bSHarry Wentland 11924562236bSHarry Wentland collapsed_idx = 0; 11934562236bSHarry Wentland for (i = 0; i < pipe_idx; i++) { 11944562236bSHarry Wentland if (res_ctx->pipe_ctx[i].stream) 11954562236bSHarry Wentland collapsed_idx++; 11964562236bSHarry Wentland } 11974562236bSHarry Wentland 11984562236bSHarry Wentland return collapsed_idx; 11994562236bSHarry Wentland } 12004562236bSHarry Wentland 12014562236bSHarry Wentland static bool is_watermark_set_a_greater( 12024562236bSHarry Wentland const struct bw_watermarks *set_a, 12034562236bSHarry Wentland const struct bw_watermarks *set_b) 12044562236bSHarry Wentland { 12054562236bSHarry Wentland if (set_a->a_mark > set_b->a_mark 12064562236bSHarry Wentland || set_a->b_mark > set_b->b_mark 12074562236bSHarry Wentland || set_a->c_mark > set_b->c_mark 12084562236bSHarry Wentland || set_a->d_mark > set_b->d_mark) 12094562236bSHarry Wentland return true; 12104562236bSHarry Wentland return false; 12114562236bSHarry Wentland } 12124562236bSHarry Wentland 12134562236bSHarry Wentland static bool did_watermarks_increase( 12144562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 12154562236bSHarry Wentland struct validate_context *context, 12164562236bSHarry Wentland struct validate_context *old_context) 12174562236bSHarry Wentland { 12184562236bSHarry Wentland int collapsed_pipe_idx = get_bw_result_idx(&context->res_ctx, 12194562236bSHarry Wentland pipe_ctx->pipe_idx); 12204562236bSHarry Wentland int old_collapsed_pipe_idx = get_bw_result_idx(&old_context->res_ctx, 12214562236bSHarry Wentland pipe_ctx->pipe_idx); 12224562236bSHarry Wentland struct pipe_ctx *old_pipe_ctx = &old_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 12234562236bSHarry Wentland 12244562236bSHarry Wentland if (!old_pipe_ctx->stream) 12254562236bSHarry Wentland return true; 12264562236bSHarry Wentland 12274562236bSHarry Wentland if (is_watermark_set_a_greater( 12284562236bSHarry Wentland &context->bw_results.nbp_state_change_wm_ns[collapsed_pipe_idx], 12294562236bSHarry Wentland &old_context->bw_results.nbp_state_change_wm_ns[old_collapsed_pipe_idx])) 12304562236bSHarry Wentland return true; 12314562236bSHarry Wentland if (is_watermark_set_a_greater( 12324562236bSHarry Wentland &context->bw_results.stutter_exit_wm_ns[collapsed_pipe_idx], 12334562236bSHarry Wentland &old_context->bw_results.stutter_exit_wm_ns[old_collapsed_pipe_idx])) 12344562236bSHarry Wentland return true; 12354562236bSHarry Wentland if (is_watermark_set_a_greater( 12364562236bSHarry Wentland &context->bw_results.urgent_wm_ns[collapsed_pipe_idx], 12374562236bSHarry Wentland &old_context->bw_results.urgent_wm_ns[old_collapsed_pipe_idx])) 12384562236bSHarry Wentland return true; 12394562236bSHarry Wentland 12404562236bSHarry Wentland return false; 12414562236bSHarry Wentland } 12424562236bSHarry Wentland 12434562236bSHarry Wentland static void program_wm_for_pipe(struct core_dc *dc, 12444562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 12454562236bSHarry Wentland struct validate_context *context) 12464562236bSHarry Wentland { 12474562236bSHarry Wentland int total_dest_line_time_ns = compute_pstate_blackout_duration( 12484562236bSHarry Wentland dc->bw_vbios.blackout_duration, 12494562236bSHarry Wentland pipe_ctx->stream); 12504562236bSHarry Wentland int bw_result_idx = get_bw_result_idx(&context->res_ctx, 12514562236bSHarry Wentland pipe_ctx->pipe_idx); 12524562236bSHarry Wentland 12534562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_display_marks( 12544562236bSHarry Wentland pipe_ctx->mi, 12554562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[bw_result_idx], 12564562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[bw_result_idx], 12574562236bSHarry Wentland context->bw_results.urgent_wm_ns[bw_result_idx], 12584562236bSHarry Wentland total_dest_line_time_ns); 12594562236bSHarry Wentland 12604562236bSHarry Wentland if (pipe_ctx->top_pipe) 12614562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( 12624562236bSHarry Wentland pipe_ctx->mi, 12634562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[bw_result_idx + 1], 12644562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[bw_result_idx + 1], 12654562236bSHarry Wentland context->bw_results.urgent_wm_ns[bw_result_idx + 1], 12664562236bSHarry Wentland total_dest_line_time_ns); 12674562236bSHarry Wentland } 12684562236bSHarry Wentland 12694562236bSHarry Wentland void dce110_set_displaymarks( 12704562236bSHarry Wentland const struct core_dc *dc, 12714562236bSHarry Wentland struct validate_context *context) 12724562236bSHarry Wentland { 12734562236bSHarry Wentland uint8_t i, num_pipes; 12744562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 12754562236bSHarry Wentland 12764562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 12774562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 12784562236bSHarry Wentland uint32_t total_dest_line_time_ns; 12794562236bSHarry Wentland 12804562236bSHarry Wentland if (pipe_ctx->stream == NULL) 12814562236bSHarry Wentland continue; 12824562236bSHarry Wentland 12834562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 12844562236bSHarry Wentland dc->bw_vbios.blackout_duration, pipe_ctx->stream); 12854562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_display_marks( 12864562236bSHarry Wentland pipe_ctx->mi, 12874562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[num_pipes], 12884562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[num_pipes], 12894562236bSHarry Wentland context->bw_results.urgent_wm_ns[num_pipes], 12904562236bSHarry Wentland total_dest_line_time_ns); 12914562236bSHarry Wentland if (i == underlay_idx) { 12924562236bSHarry Wentland num_pipes++; 12934562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( 12944562236bSHarry Wentland pipe_ctx->mi, 12954562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[num_pipes], 12964562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[num_pipes], 12974562236bSHarry Wentland context->bw_results.urgent_wm_ns[num_pipes], 12984562236bSHarry Wentland total_dest_line_time_ns); 12994562236bSHarry Wentland } 13004562236bSHarry Wentland num_pipes++; 13014562236bSHarry Wentland } 13024562236bSHarry Wentland } 13034562236bSHarry Wentland 13044562236bSHarry Wentland static void set_safe_displaymarks(struct resource_context *res_ctx) 13054562236bSHarry Wentland { 13064562236bSHarry Wentland int i; 13074562236bSHarry Wentland int underlay_idx = res_ctx->pool->underlay_pipe_index; 13084562236bSHarry Wentland struct bw_watermarks max_marks = { 13094562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 13104562236bSHarry Wentland struct bw_watermarks nbp_marks = { 13114562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 13124562236bSHarry Wentland 13134562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 13144562236bSHarry Wentland if (res_ctx->pipe_ctx[i].stream == NULL) 13154562236bSHarry Wentland continue; 13164562236bSHarry Wentland 13174562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks( 13184562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 13194562236bSHarry Wentland nbp_marks, 13204562236bSHarry Wentland max_marks, 13214562236bSHarry Wentland max_marks, 13224562236bSHarry Wentland MAX_WATERMARK); 13234562236bSHarry Wentland if (i == underlay_idx) 13244562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks( 13254562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 13264562236bSHarry Wentland nbp_marks, 13274562236bSHarry Wentland max_marks, 13284562236bSHarry Wentland max_marks, 13294562236bSHarry Wentland MAX_WATERMARK); 13304562236bSHarry Wentland } 13314562236bSHarry Wentland } 13324562236bSHarry Wentland 13334562236bSHarry Wentland static void switch_dp_clock_sources( 13344562236bSHarry Wentland const struct core_dc *dc, 13354562236bSHarry Wentland struct resource_context *res_ctx) 13364562236bSHarry Wentland { 13374562236bSHarry Wentland uint8_t i; 13384562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 13394562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 13404562236bSHarry Wentland 13414562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 13424562236bSHarry Wentland continue; 13434562236bSHarry Wentland 13444562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 13454562236bSHarry Wentland struct clock_source *clk_src = 13464562236bSHarry Wentland resource_find_used_clk_src_for_sharing( 13474562236bSHarry Wentland res_ctx, pipe_ctx); 13484562236bSHarry Wentland 13494562236bSHarry Wentland if (clk_src && 13504562236bSHarry Wentland clk_src != pipe_ctx->clock_source) { 13514562236bSHarry Wentland resource_unreference_clock_source( 13528c737fccSYongqiang Sun res_ctx, &pipe_ctx->clock_source); 13534562236bSHarry Wentland pipe_ctx->clock_source = clk_src; 13544562236bSHarry Wentland resource_reference_clock_source(res_ctx, clk_src); 13554562236bSHarry Wentland 13564562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i); 13574562236bSHarry Wentland } 13584562236bSHarry Wentland } 13594562236bSHarry Wentland } 13604562236bSHarry Wentland } 13614562236bSHarry Wentland 13624562236bSHarry Wentland /******************************************************************************* 13634562236bSHarry Wentland * Public functions 13644562236bSHarry Wentland ******************************************************************************/ 13654562236bSHarry Wentland 13664562236bSHarry Wentland static void reset_single_pipe_hw_ctx( 13674562236bSHarry Wentland const struct core_dc *dc, 13684562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 13694562236bSHarry Wentland struct validate_context *context) 13704562236bSHarry Wentland { 13714562236bSHarry Wentland core_link_disable_stream(pipe_ctx); 13724b5e7d62SHersen Wu pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 13734b5e7d62SHersen Wu if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) { 13744562236bSHarry Wentland dm_error("DC: failed to blank crtc!\n"); 13754562236bSHarry Wentland BREAK_TO_DEBUGGER(); 13764562236bSHarry Wentland } 13774562236bSHarry Wentland pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); 13784562236bSHarry Wentland pipe_ctx->mi->funcs->free_mem_input( 1379ab2541b6SAric Cyr pipe_ctx->mi, context->stream_count); 13804562236bSHarry Wentland resource_unreference_clock_source( 13818c737fccSYongqiang Sun &context->res_ctx, &pipe_ctx->clock_source); 13824562236bSHarry Wentland 13834562236bSHarry Wentland dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx); 13844562236bSHarry Wentland 13854562236bSHarry Wentland pipe_ctx->stream = NULL; 13864562236bSHarry Wentland } 13874562236bSHarry Wentland 13884562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 13894562236bSHarry Wentland int num_pipes, int vmin, int vmax) 13904562236bSHarry Wentland { 13914562236bSHarry Wentland int i = 0; 13924562236bSHarry Wentland struct drr_params params = {0}; 13934562236bSHarry Wentland 13944562236bSHarry Wentland params.vertical_total_max = vmax; 13954562236bSHarry Wentland params.vertical_total_min = vmin; 13964562236bSHarry Wentland 13974562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 13984562236bSHarry Wentland * some GSL stuff 13994562236bSHarry Wentland */ 14004562236bSHarry Wentland 14014562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 14024562236bSHarry Wentland pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, ¶ms); 14034562236bSHarry Wentland } 14044562236bSHarry Wentland } 14054562236bSHarry Wentland 14064562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 14074562236bSHarry Wentland int num_pipes, int value) 14084562236bSHarry Wentland { 14094562236bSHarry Wentland unsigned int i; 14104562236bSHarry Wentland 14114562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 14124562236bSHarry Wentland pipe_ctx[i]->tg->funcs-> 14134562236bSHarry Wentland set_static_screen_control(pipe_ctx[i]->tg, value); 14144562236bSHarry Wentland } 14154562236bSHarry Wentland 14164562236bSHarry Wentland /* unit: in_khz before mode set, get pixel clock from context. ASIC register 14174562236bSHarry Wentland * may not be programmed yet. 14184562236bSHarry Wentland * TODO: after mode set, pre_mode_set = false, 14194562236bSHarry Wentland * may read PLL register to get pixel clock 14204562236bSHarry Wentland */ 14214562236bSHarry Wentland static uint32_t get_max_pixel_clock_for_all_paths( 14224562236bSHarry Wentland struct core_dc *dc, 14234562236bSHarry Wentland struct validate_context *context, 14244562236bSHarry Wentland bool pre_mode_set) 14254562236bSHarry Wentland { 14264562236bSHarry Wentland uint32_t max_pix_clk = 0; 14274562236bSHarry Wentland int i; 14284562236bSHarry Wentland 14294562236bSHarry Wentland if (!pre_mode_set) { 14304562236bSHarry Wentland /* TODO: read ASIC register to get pixel clock */ 14314562236bSHarry Wentland ASSERT(0); 14324562236bSHarry Wentland } 14334562236bSHarry Wentland 14344562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 14354562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 14364562236bSHarry Wentland 14374562236bSHarry Wentland if (pipe_ctx->stream == NULL) 14384562236bSHarry Wentland continue; 14394562236bSHarry Wentland 14404562236bSHarry Wentland /* do not check under lay */ 14414562236bSHarry Wentland if (pipe_ctx->top_pipe) 14424562236bSHarry Wentland continue; 14434562236bSHarry Wentland 14444562236bSHarry Wentland if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk) 14454562236bSHarry Wentland max_pix_clk = 14464562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 14474562236bSHarry Wentland } 14484562236bSHarry Wentland 14494562236bSHarry Wentland if (max_pix_clk == 0) 14504562236bSHarry Wentland ASSERT(0); 14514562236bSHarry Wentland 14524562236bSHarry Wentland return max_pix_clk; 14534562236bSHarry Wentland } 14544562236bSHarry Wentland 14554562236bSHarry Wentland /* 14564562236bSHarry Wentland * Find clock state based on clock requested. if clock value is 0, simply 14574562236bSHarry Wentland * set clock state as requested without finding clock state by clock value 14584562236bSHarry Wentland */ 14594562236bSHarry Wentland static void apply_min_clocks( 14604562236bSHarry Wentland struct core_dc *dc, 14614562236bSHarry Wentland struct validate_context *context, 1462e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state *clocks_state, 14634562236bSHarry Wentland bool pre_mode_set) 14644562236bSHarry Wentland { 14654562236bSHarry Wentland struct state_dependent_clocks req_clocks = {0}; 14664562236bSHarry Wentland struct pipe_ctx *pipe_ctx; 14674562236bSHarry Wentland int i; 14684562236bSHarry Wentland 14694562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 14704562236bSHarry Wentland pipe_ctx = &context->res_ctx.pipe_ctx[i]; 14714562236bSHarry Wentland if (pipe_ctx->dis_clk != NULL) 14724562236bSHarry Wentland break; 14734562236bSHarry Wentland } 14744562236bSHarry Wentland 14754562236bSHarry Wentland if (!pre_mode_set) { 14764562236bSHarry Wentland /* set clock_state without verification */ 14775d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) { 14785d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 14795d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, *clocks_state); 14804562236bSHarry Wentland return; 14815d6d185fSDmytro Laktyushkin } 14824562236bSHarry Wentland 14834562236bSHarry Wentland /* TODOFPGA */ 14844562236bSHarry Wentland } 14854562236bSHarry Wentland 14864562236bSHarry Wentland /* get the required state based on state dependent clocks: 14874562236bSHarry Wentland * display clock and pixel clock 14884562236bSHarry Wentland */ 1489a99240d5SDmytro Laktyushkin req_clocks.display_clk_khz = context->dispclk_khz; 14904562236bSHarry Wentland 14914562236bSHarry Wentland req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( 14924562236bSHarry Wentland dc, context, true); 14934562236bSHarry Wentland 14945d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) { 14955d6d185fSDmytro Laktyushkin *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state( 14965d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, &req_clocks); 14975d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 14984562236bSHarry Wentland pipe_ctx->dis_clk, *clocks_state); 14994562236bSHarry Wentland } else { 15004562236bSHarry Wentland } 15014562236bSHarry Wentland } 15024562236bSHarry Wentland 15034562236bSHarry Wentland static enum dc_status apply_ctx_to_hw_fpga( 15044562236bSHarry Wentland struct core_dc *dc, 15054562236bSHarry Wentland struct validate_context *context) 15064562236bSHarry Wentland { 15074562236bSHarry Wentland enum dc_status status = DC_ERROR_UNEXPECTED; 15084562236bSHarry Wentland int i; 15094562236bSHarry Wentland 15104562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 15114562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15124562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15134562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15144562236bSHarry Wentland 15154562236bSHarry Wentland if (pipe_ctx->stream == NULL) 15164562236bSHarry Wentland continue; 15174562236bSHarry Wentland 15184562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) 15194562236bSHarry Wentland continue; 15204562236bSHarry Wentland 15214562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 15224562236bSHarry Wentland pipe_ctx, 15234562236bSHarry Wentland context, 15244562236bSHarry Wentland dc); 15254562236bSHarry Wentland 15264562236bSHarry Wentland if (status != DC_OK) 15274562236bSHarry Wentland return status; 15284562236bSHarry Wentland } 15294562236bSHarry Wentland 15304562236bSHarry Wentland return DC_OK; 15314562236bSHarry Wentland } 15324562236bSHarry Wentland 15334562236bSHarry Wentland static void reset_hw_ctx_wrap( 15344562236bSHarry Wentland struct core_dc *dc, 15354562236bSHarry Wentland struct validate_context *context) 15364562236bSHarry Wentland { 15374562236bSHarry Wentland int i; 15384562236bSHarry Wentland 15394562236bSHarry Wentland /* Reset old context */ 15404562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 15414562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 15424562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15434562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15444562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15454562236bSHarry Wentland 15464562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 15474562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 15484562236bSHarry Wentland * PHY when not already disabled. 15494562236bSHarry Wentland */ 15504562236bSHarry Wentland 15514562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 15524562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 15534562236bSHarry Wentland continue; 15544562236bSHarry Wentland 15554562236bSHarry Wentland if (!pipe_ctx->stream || 15564562236bSHarry Wentland pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 15574562236bSHarry Wentland reset_single_pipe_hw_ctx( 15584562236bSHarry Wentland dc, pipe_ctx_old, dc->current_context); 15594562236bSHarry Wentland } 15604562236bSHarry Wentland } 15614562236bSHarry Wentland 15624562236bSHarry Wentland /*TODO: const validate_context*/ 15634562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 15644562236bSHarry Wentland struct core_dc *dc, 15654562236bSHarry Wentland struct validate_context *context) 15664562236bSHarry Wentland { 15674562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 15684562236bSHarry Wentland enum dc_status status; 15694562236bSHarry Wentland int i; 1570e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID; 15714562236bSHarry Wentland 15724562236bSHarry Wentland /* Reset old context */ 15734562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 15744562236bSHarry Wentland dc->hwss.reset_hw_ctx_wrap(dc, context); 15754562236bSHarry Wentland 15764562236bSHarry Wentland /* Skip applying if no targets */ 1577ab2541b6SAric Cyr if (context->stream_count <= 0) 15784562236bSHarry Wentland return DC_OK; 15794562236bSHarry Wentland 15804562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 15814562236bSHarry Wentland apply_ctx_to_hw_fpga(dc, context); 15824562236bSHarry Wentland return DC_OK; 15834562236bSHarry Wentland } 15844562236bSHarry Wentland 15854562236bSHarry Wentland /* Apply new context */ 15864562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 15874562236bSHarry Wentland 15884562236bSHarry Wentland /* below is for real asic only */ 15894562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 15904562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15914562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15924562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15934562236bSHarry Wentland 15944562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 15954562236bSHarry Wentland continue; 15964562236bSHarry Wentland 15974562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 15984562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 15994562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 16004562236bSHarry Wentland pipe_ctx->clock_source, i); 16014562236bSHarry Wentland continue; 16024562236bSHarry Wentland } 16034562236bSHarry Wentland 16044562236bSHarry Wentland dc->hwss.enable_display_power_gating( 16054562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 16064562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 16074562236bSHarry Wentland } 16084562236bSHarry Wentland 16094562236bSHarry Wentland set_safe_displaymarks(&context->res_ctx); 16104562236bSHarry Wentland /*TODO: when pplib works*/ 16114562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, true); 16124562236bSHarry Wentland 1613a99240d5SDmytro Laktyushkin if (context->dispclk_khz 1614a99240d5SDmytro Laktyushkin > dc->current_context->dispclk_khz) 16151a687574SDmytro Laktyushkin context->res_ctx.pool->display_clock->funcs->set_clock( 16161a687574SDmytro Laktyushkin context->res_ctx.pool->display_clock, 1617a99240d5SDmytro Laktyushkin context->dispclk_khz * 115 / 100); 16184562236bSHarry Wentland 1619ab8812a3SHersen Wu /* program audio wall clock. use HDMI as clock source if HDMI 1620ab8812a3SHersen Wu * audio active. Otherwise, use DP as clock source 1621ab8812a3SHersen Wu * first, loop to find any HDMI audio, if not, loop find DP audio 1622ab8812a3SHersen Wu */ 16234562236bSHarry Wentland /* Setup audio rate clock source */ 16244562236bSHarry Wentland /* Issue: 16254562236bSHarry Wentland * Audio lag happened on DP monitor when unplug a HDMI monitor 16264562236bSHarry Wentland * 16274562236bSHarry Wentland * Cause: 16284562236bSHarry Wentland * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 16294562236bSHarry Wentland * is set to either dto0 or dto1, audio should work fine. 16304562236bSHarry Wentland * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 16314562236bSHarry Wentland * set to dto0 will cause audio lag. 16324562236bSHarry Wentland * 16334562236bSHarry Wentland * Solution: 16344562236bSHarry Wentland * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 16354562236bSHarry Wentland * find first available pipe with audio, setup audio wall DTO per topology 16364562236bSHarry Wentland * instead of per pipe. 16374562236bSHarry Wentland */ 1638ab8812a3SHersen Wu for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 1639ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1640ab8812a3SHersen Wu 1641ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1642ab8812a3SHersen Wu continue; 1643ab8812a3SHersen Wu 1644ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1645ab8812a3SHersen Wu continue; 1646ab8812a3SHersen Wu 1647ab8812a3SHersen Wu if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 1648ab8812a3SHersen Wu continue; 1649ab8812a3SHersen Wu 1650ab8812a3SHersen Wu if (pipe_ctx->audio != NULL) { 1651ab8812a3SHersen Wu struct audio_output audio_output; 1652ab8812a3SHersen Wu 1653ab8812a3SHersen Wu build_audio_output(pipe_ctx, &audio_output); 1654ab8812a3SHersen Wu 1655ab8812a3SHersen Wu pipe_ctx->audio->funcs->wall_dto_setup( 1656ab8812a3SHersen Wu pipe_ctx->audio, 1657ab8812a3SHersen Wu pipe_ctx->stream->signal, 1658ab8812a3SHersen Wu &audio_output.crtc_info, 1659ab8812a3SHersen Wu &audio_output.pll_info); 1660ab8812a3SHersen Wu break; 1661ab8812a3SHersen Wu } 1662ab8812a3SHersen Wu } 1663ab8812a3SHersen Wu 1664ab8812a3SHersen Wu /* no HDMI audio is found, try DP audio */ 1665ab8812a3SHersen Wu if (i == context->res_ctx.pool->pipe_count) { 1666ab8812a3SHersen Wu for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 1667ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1668ab8812a3SHersen Wu 1669ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1670ab8812a3SHersen Wu continue; 1671ab8812a3SHersen Wu 1672ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1673ab8812a3SHersen Wu continue; 1674ab8812a3SHersen Wu 1675ab8812a3SHersen Wu if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 1676ab8812a3SHersen Wu continue; 1677ab8812a3SHersen Wu 1678ab8812a3SHersen Wu if (pipe_ctx->audio != NULL) { 1679ab8812a3SHersen Wu struct audio_output audio_output; 1680ab8812a3SHersen Wu 1681ab8812a3SHersen Wu build_audio_output(pipe_ctx, &audio_output); 1682ab8812a3SHersen Wu 1683ab8812a3SHersen Wu pipe_ctx->audio->funcs->wall_dto_setup( 1684ab8812a3SHersen Wu pipe_ctx->audio, 1685ab8812a3SHersen Wu pipe_ctx->stream->signal, 1686ab8812a3SHersen Wu &audio_output.crtc_info, 1687ab8812a3SHersen Wu &audio_output.pll_info); 1688ab8812a3SHersen Wu break; 1689ab8812a3SHersen Wu } 1690ab8812a3SHersen Wu } 1691ab8812a3SHersen Wu } 1692ab8812a3SHersen Wu 1693ab8812a3SHersen Wu for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 1694ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 1695ab8812a3SHersen Wu &dc->current_context->res_ctx.pipe_ctx[i]; 1696ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1697ab8812a3SHersen Wu 1698ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1699ab8812a3SHersen Wu continue; 1700ab8812a3SHersen Wu 1701ab8812a3SHersen Wu if (pipe_ctx->stream == pipe_ctx_old->stream) 1702ab8812a3SHersen Wu continue; 1703ab8812a3SHersen Wu 1704ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1705ab8812a3SHersen Wu continue; 1706ab8812a3SHersen Wu 1707ab8812a3SHersen Wu if (context->res_ctx.pipe_ctx[i].audio != NULL) { 1708ab8812a3SHersen Wu 17094562236bSHarry Wentland struct audio_output audio_output; 17104562236bSHarry Wentland 17114562236bSHarry Wentland build_audio_output(pipe_ctx, &audio_output); 17124562236bSHarry Wentland 17134562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 17144562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_setup( 17154562236bSHarry Wentland pipe_ctx->stream_enc, 17164562236bSHarry Wentland pipe_ctx->audio->inst, 17174562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 17184562236bSHarry Wentland else 17194562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_setup( 17204562236bSHarry Wentland pipe_ctx->stream_enc, 17214562236bSHarry Wentland pipe_ctx->audio->inst, 17224562236bSHarry Wentland &pipe_ctx->stream->public.audio_info, 17234562236bSHarry Wentland &audio_output.crtc_info); 17244562236bSHarry Wentland 17254562236bSHarry Wentland pipe_ctx->audio->funcs->az_configure( 17264562236bSHarry Wentland pipe_ctx->audio, 17274562236bSHarry Wentland pipe_ctx->stream->signal, 17284562236bSHarry Wentland &audio_output.crtc_info, 17294562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 17304562236bSHarry Wentland } 17314562236bSHarry Wentland 17324562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 17334562236bSHarry Wentland pipe_ctx, 17344562236bSHarry Wentland context, 17354562236bSHarry Wentland dc); 17364562236bSHarry Wentland 17374562236bSHarry Wentland if (DC_OK != status) 17384562236bSHarry Wentland return status; 17394562236bSHarry Wentland } 17404562236bSHarry Wentland 17414562236bSHarry Wentland dc->hwss.set_displaymarks(dc, context); 17424562236bSHarry Wentland 17434562236bSHarry Wentland /* to save power */ 17444562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, false); 17454562236bSHarry Wentland 17464562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, false); 17474562236bSHarry Wentland 17484562236bSHarry Wentland switch_dp_clock_sources(dc, &context->res_ctx); 17494562236bSHarry Wentland 17504562236bSHarry Wentland return DC_OK; 17514562236bSHarry Wentland } 17524562236bSHarry Wentland 17534562236bSHarry Wentland /******************************************************************************* 17544562236bSHarry Wentland * Front End programming 17554562236bSHarry Wentland ******************************************************************************/ 17564562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 17574562236bSHarry Wentland { 17584562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 17594562236bSHarry Wentland 17604562236bSHarry Wentland default_adjust.force_hw_default = false; 17614562236bSHarry Wentland if (pipe_ctx->surface == NULL) 17624562236bSHarry Wentland default_adjust.in_color_space = COLOR_SPACE_SRGB; 17634562236bSHarry Wentland else 17644562236bSHarry Wentland default_adjust.in_color_space = 17654562236bSHarry Wentland pipe_ctx->surface->public.color_space; 17664562236bSHarry Wentland if (pipe_ctx->stream == NULL) 17674562236bSHarry Wentland default_adjust.out_color_space = COLOR_SPACE_SRGB; 17684562236bSHarry Wentland else 17694562236bSHarry Wentland default_adjust.out_color_space = 17704562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 17714562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 17724562236bSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; 17734562236bSHarry Wentland 17744562236bSHarry Wentland /* display color depth */ 17754562236bSHarry Wentland default_adjust.color_depth = 17764562236bSHarry Wentland pipe_ctx->stream->public.timing.display_color_depth; 17774562236bSHarry Wentland 17784562236bSHarry Wentland /* Lb color depth */ 17794562236bSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; 17804562236bSHarry Wentland 17814562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_default( 17824562236bSHarry Wentland pipe_ctx->opp, &default_adjust); 17834562236bSHarry Wentland } 17844562236bSHarry Wentland 1785b06b7680SLeon Elazar 1786b06b7680SLeon Elazar /******************************************************************************* 1787b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 1788b06b7680SLeon Elazar * Blender + CRTC 1789b06b7680SLeon Elazar * 1790b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 1791b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 1792b06b7680SLeon Elazar * 1793b06b7680SLeon Elazar * |----------------------------------------------- | 1794b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 1795b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 1796b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 1797b06b7680SLeon Elazar * |------------------------------------------------| 1798b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 1799b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 1800b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 1801b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 1802b06b7680SLeon Elazar * -------------------------------------------------| 1803b06b7680SLeon Elazar * 1804b06b7680SLeon Elazar ******************************************************************************/ 1805b06b7680SLeon Elazar static void program_surface_visibility(const struct core_dc *dc, 18064562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 18074562236bSHarry Wentland { 18084562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 1809b06b7680SLeon Elazar bool blank_target = false; 18104562236bSHarry Wentland 18114562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 1812b06b7680SLeon Elazar 1813b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 1814b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 1815b06b7680SLeon Elazar 18164562236bSHarry Wentland if (pipe_ctx->bottom_pipe->surface->public.visible) { 18174562236bSHarry Wentland if (pipe_ctx->surface->public.visible) 18184562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 18194562236bSHarry Wentland else 18204562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 1821b06b7680SLeon Elazar 1822b06b7680SLeon Elazar } else if (!pipe_ctx->surface->public.visible) 1823b06b7680SLeon Elazar blank_target = true; 1824b06b7680SLeon Elazar 1825b06b7680SLeon Elazar } else if (!pipe_ctx->surface->public.visible) 1826b06b7680SLeon Elazar blank_target = true; 1827b06b7680SLeon Elazar 18284562236bSHarry Wentland dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); 1829b06b7680SLeon Elazar pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target); 1830b06b7680SLeon Elazar 18314562236bSHarry Wentland } 18324562236bSHarry Wentland 18334562236bSHarry Wentland /** 18344562236bSHarry Wentland * TODO REMOVE, USE UPDATE INSTEAD 18354562236bSHarry Wentland */ 18364562236bSHarry Wentland static void set_plane_config( 18374562236bSHarry Wentland const struct core_dc *dc, 18384562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 18394562236bSHarry Wentland struct resource_context *res_ctx) 18404562236bSHarry Wentland { 18414562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 18424562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 18434562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 18444562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 18454562236bSHarry Wentland unsigned int i; 18464562236bSHarry Wentland 18474562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 18484562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 18494562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 18504562236bSHarry Wentland 18514562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 18524562236bSHarry Wentland 18534562236bSHarry Wentland set_default_colors(pipe_ctx); 18544562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 18554562236bSHarry Wentland == true) { 18564562236bSHarry Wentland tbl_entry.color_space = 18574562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 18584562236bSHarry Wentland 18594562236bSHarry Wentland for (i = 0; i < 12; i++) 18604562236bSHarry Wentland tbl_entry.regval[i] = 18614562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 18624562236bSHarry Wentland 18634562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 18644562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 18654562236bSHarry Wentland } 18664562236bSHarry Wentland 18674562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 18684562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 18694562236bSHarry Wentland adjust.temperature_matrix[0] = 18704562236bSHarry Wentland pipe_ctx->stream-> 18714562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 18724562236bSHarry Wentland adjust.temperature_matrix[1] = 18734562236bSHarry Wentland pipe_ctx->stream-> 18744562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 18754562236bSHarry Wentland adjust.temperature_matrix[2] = 18764562236bSHarry Wentland pipe_ctx->stream-> 18774562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 18784562236bSHarry Wentland adjust.temperature_matrix[3] = 18794562236bSHarry Wentland pipe_ctx->stream-> 18804562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 18814562236bSHarry Wentland adjust.temperature_matrix[4] = 18824562236bSHarry Wentland pipe_ctx->stream-> 18834562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 18844562236bSHarry Wentland adjust.temperature_matrix[5] = 18854562236bSHarry Wentland pipe_ctx->stream-> 18864562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 18874562236bSHarry Wentland adjust.temperature_matrix[6] = 18884562236bSHarry Wentland pipe_ctx->stream-> 18894562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 18904562236bSHarry Wentland adjust.temperature_matrix[7] = 18914562236bSHarry Wentland pipe_ctx->stream-> 18924562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 18934562236bSHarry Wentland adjust.temperature_matrix[8] = 18944562236bSHarry Wentland pipe_ctx->stream-> 18954562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 18964562236bSHarry Wentland } 18974562236bSHarry Wentland 18984562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 18994562236bSHarry Wentland 19004562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 19014562236bSHarry Wentland program_scaler(dc, pipe_ctx); 19024562236bSHarry Wentland 1903b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 19044562236bSHarry Wentland 19054562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 19064562236bSHarry Wentland mi, 19074562236bSHarry Wentland surface->public.format, 19084562236bSHarry Wentland &surface->public.tiling_info, 19094562236bSHarry Wentland &surface->public.plane_size, 19104562236bSHarry Wentland surface->public.rotation, 19114562236bSHarry Wentland NULL, 1912624d7c47SYongqiang Sun false, 1913624d7c47SYongqiang Sun pipe_ctx->surface->public.visible); 19144562236bSHarry Wentland 19154562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 19164562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 19174562236bSHarry Wentland pipe_ctx->mi, 19184562236bSHarry Wentland surface->public.format, 19194562236bSHarry Wentland &surface->public.tiling_info, 19204562236bSHarry Wentland surface->public.rotation); 19214562236bSHarry Wentland } 19224562236bSHarry Wentland 19234562236bSHarry Wentland static void update_plane_addr(const struct core_dc *dc, 19244562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 19254562236bSHarry Wentland { 19264562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 19274562236bSHarry Wentland 19284562236bSHarry Wentland if (surface == NULL) 19294562236bSHarry Wentland return; 19304562236bSHarry Wentland 19314562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( 19324562236bSHarry Wentland pipe_ctx->mi, 19334562236bSHarry Wentland &surface->public.address, 19344562236bSHarry Wentland surface->public.flip_immediate); 19354562236bSHarry Wentland 19364562236bSHarry Wentland surface->status.requested_address = surface->public.address; 19374562236bSHarry Wentland } 19384562236bSHarry Wentland 19394562236bSHarry Wentland void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 19404562236bSHarry Wentland { 19414562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 19424562236bSHarry Wentland 19434562236bSHarry Wentland if (surface == NULL) 19444562236bSHarry Wentland return; 19454562236bSHarry Wentland 19464562236bSHarry Wentland surface->status.is_flip_pending = 19474562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_is_flip_pending( 19484562236bSHarry Wentland pipe_ctx->mi); 19494562236bSHarry Wentland 19504562236bSHarry Wentland if (surface->status.is_flip_pending && !surface->public.visible) 19514562236bSHarry Wentland pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; 19524562236bSHarry Wentland 19534562236bSHarry Wentland surface->status.current_address = pipe_ctx->mi->current_address; 19544562236bSHarry Wentland } 19554562236bSHarry Wentland 19564562236bSHarry Wentland void dce110_power_down(struct core_dc *dc) 19574562236bSHarry Wentland { 19584562236bSHarry Wentland power_down_all_hw_blocks(dc); 19594562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 19604562236bSHarry Wentland } 19614562236bSHarry Wentland 19624562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 19634562236bSHarry Wentland struct dc_context *dc_ctx, 19644562236bSHarry Wentland struct timing_generator *tg) 19654562236bSHarry Wentland { 19664562236bSHarry Wentland bool rc = false; 19674562236bSHarry Wentland 19684562236bSHarry Wentland /* To avoid endless loop we wait at most 19694562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 19704562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 19714562236bSHarry Wentland uint32_t i; 19724562236bSHarry Wentland 19734562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 19744562236bSHarry Wentland 19754562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 19764562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 19774562236bSHarry Wentland break; 19784562236bSHarry Wentland } 19794562236bSHarry Wentland 19804562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 19814562236bSHarry Wentland rc = true; 19824562236bSHarry Wentland /* usually occurs at i=1 */ 19834562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 19844562236bSHarry Wentland i); 19854562236bSHarry Wentland break; 19864562236bSHarry Wentland } 19874562236bSHarry Wentland 19884562236bSHarry Wentland /* Wait for one frame. */ 19894562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 19904562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 19914562236bSHarry Wentland } 19924562236bSHarry Wentland 19934562236bSHarry Wentland if (false == rc) 19944562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 19954562236bSHarry Wentland 19964562236bSHarry Wentland return rc; 19974562236bSHarry Wentland } 19984562236bSHarry Wentland 19994562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 20004562236bSHarry Wentland static void dce110_enable_timing_synchronization( 20014562236bSHarry Wentland struct core_dc *dc, 20024562236bSHarry Wentland int group_index, 20034562236bSHarry Wentland int group_size, 20044562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 20054562236bSHarry Wentland { 20064562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 20074562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 20084562236bSHarry Wentland int i; 20094562236bSHarry Wentland 20104562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 20114562236bSHarry Wentland 20124562236bSHarry Wentland /* Designate a single TG in the group as a master. 20134562236bSHarry Wentland * Since HW doesn't care which one, we always assign 20144562236bSHarry Wentland * the 1st one in the group. */ 20154562236bSHarry Wentland gsl_params.gsl_group = 0; 20164562236bSHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->tg->inst; 20174562236bSHarry Wentland 20184562236bSHarry Wentland for (i = 0; i < group_size; i++) 20194562236bSHarry Wentland grouped_pipes[i]->tg->funcs->setup_global_swap_lock( 20204562236bSHarry Wentland grouped_pipes[i]->tg, &gsl_params); 20214562236bSHarry Wentland 20224562236bSHarry Wentland /* Reset slave controllers on master VSync */ 20234562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 20244562236bSHarry Wentland 20254562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 20264562236bSHarry Wentland grouped_pipes[i]->tg->funcs->enable_reset_trigger( 20274562236bSHarry Wentland grouped_pipes[i]->tg, gsl_params.gsl_group); 20284562236bSHarry Wentland 20294562236bSHarry Wentland 20304562236bSHarry Wentland 20314562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 20324562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 20334562236bSHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg); 20344562236bSHarry Wentland /* Regardless of success of the wait above, remove the reset or 20354562236bSHarry Wentland * the driver will start timing out on Display requests. */ 20364562236bSHarry Wentland DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); 20374562236bSHarry Wentland grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg); 20384562236bSHarry Wentland } 20394562236bSHarry Wentland 20404562236bSHarry Wentland 20414562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 20424562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 20434562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 20444562236bSHarry Wentland for (i = 0; i < group_size; i++) 20454562236bSHarry Wentland grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg); 20464562236bSHarry Wentland 20474562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 20484562236bSHarry Wentland } 20494562236bSHarry Wentland 20504562236bSHarry Wentland static void init_hw(struct core_dc *dc) 20514562236bSHarry Wentland { 20524562236bSHarry Wentland int i; 20534562236bSHarry Wentland struct dc_bios *bp; 20544562236bSHarry Wentland struct transform *xfm; 20555e7773a2SAnthony Koo struct abm *abm; 20564562236bSHarry Wentland 20574562236bSHarry Wentland bp = dc->ctx->dc_bios; 20584562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 20594562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 20604562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 20614562236bSHarry Wentland 20624562236bSHarry Wentland dc->hwss.enable_display_power_gating( 20634562236bSHarry Wentland dc, i, bp, 20644562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 20654562236bSHarry Wentland dc->hwss.enable_display_power_gating( 20664562236bSHarry Wentland dc, i, bp, 20674562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 20684562236bSHarry Wentland dc->hwss.enable_display_pipe_clock_gating( 20694562236bSHarry Wentland dc->ctx, 20704562236bSHarry Wentland true); 20714562236bSHarry Wentland } 20724562236bSHarry Wentland 20734562236bSHarry Wentland dce_clock_gating_power_up(dc->hwseq, false);; 20744562236bSHarry Wentland /***************************************/ 20754562236bSHarry Wentland 20764562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 20774562236bSHarry Wentland /****************************************/ 20784562236bSHarry Wentland /* Power up AND update implementation according to the 20794562236bSHarry Wentland * required signal (which may be different from the 20804562236bSHarry Wentland * default signal on connector). */ 20814562236bSHarry Wentland struct core_link *link = dc->links[i]; 20824562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 20834562236bSHarry Wentland } 20844562236bSHarry Wentland 20854562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 20864562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 20874562236bSHarry Wentland 20884562236bSHarry Wentland tg->funcs->disable_vga(tg); 20894562236bSHarry Wentland 20904562236bSHarry Wentland /* Blank controller using driver code instead of 20914562236bSHarry Wentland * command table. */ 20924562236bSHarry Wentland tg->funcs->set_blank(tg, true); 20934b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 20944562236bSHarry Wentland } 20954562236bSHarry Wentland 20964562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 20974562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 20984562236bSHarry Wentland audio->funcs->hw_init(audio); 20994562236bSHarry Wentland } 21005e7773a2SAnthony Koo 21015e7773a2SAnthony Koo abm = dc->res_pool->abm; 21026728b30cSAnthony Koo if (abm != NULL) { 21036728b30cSAnthony Koo abm->funcs->init_backlight(abm); 21045e7773a2SAnthony Koo abm->funcs->abm_init(abm); 21054562236bSHarry Wentland } 21066728b30cSAnthony Koo } 21074562236bSHarry Wentland 21084562236bSHarry Wentland /* TODO: move this to apply_ctx_tohw some how?*/ 21094562236bSHarry Wentland static void dce110_power_on_pipe_if_needed( 21104562236bSHarry Wentland struct core_dc *dc, 21114562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 21124562236bSHarry Wentland struct validate_context *context) 21134562236bSHarry Wentland { 21144562236bSHarry Wentland struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 21154562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 21164562236bSHarry Wentland struct tg_color black_color = {0}; 21174562236bSHarry Wentland 21184562236bSHarry Wentland if (!old_pipe_ctx->stream && pipe_ctx->stream) { 21194562236bSHarry Wentland dc->hwss.enable_display_power_gating( 21204562236bSHarry Wentland dc, 21214562236bSHarry Wentland pipe_ctx->pipe_idx, 21224562236bSHarry Wentland dcb, PIPE_GATING_CONTROL_DISABLE); 21234562236bSHarry Wentland 21244562236bSHarry Wentland /* 21254562236bSHarry Wentland * This is for powering on underlay, so crtc does not 21264562236bSHarry Wentland * need to be enabled 21274562236bSHarry Wentland */ 21284562236bSHarry Wentland 21294562236bSHarry Wentland pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, 21304562236bSHarry Wentland &pipe_ctx->stream->public.timing, 21314562236bSHarry Wentland false); 21324562236bSHarry Wentland 21334562236bSHarry Wentland pipe_ctx->tg->funcs->enable_advanced_request( 21344562236bSHarry Wentland pipe_ctx->tg, 21354562236bSHarry Wentland true, 21364562236bSHarry Wentland &pipe_ctx->stream->public.timing); 21374562236bSHarry Wentland 21384562236bSHarry Wentland pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, 21394562236bSHarry Wentland pipe_ctx->stream->public.timing.h_total, 21404562236bSHarry Wentland pipe_ctx->stream->public.timing.v_total, 21414562236bSHarry Wentland pipe_ctx->stream->public.timing.pix_clk_khz, 2142ab2541b6SAric Cyr context->stream_count); 21434562236bSHarry Wentland 21444562236bSHarry Wentland /* TODO unhardcode*/ 21454562236bSHarry Wentland color_space_to_black_color(dc, 21464562236bSHarry Wentland COLOR_SPACE_YCBCR601, &black_color); 21474562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank_color( 21484562236bSHarry Wentland pipe_ctx->tg, 21494562236bSHarry Wentland &black_color); 21504562236bSHarry Wentland } 21514562236bSHarry Wentland } 21524562236bSHarry Wentland 21534562236bSHarry Wentland static void dce110_increase_watermarks_for_pipe( 21544562236bSHarry Wentland struct core_dc *dc, 21554562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 21564562236bSHarry Wentland struct validate_context *context) 21574562236bSHarry Wentland { 21584562236bSHarry Wentland if (did_watermarks_increase(pipe_ctx, context, dc->current_context)) 21594562236bSHarry Wentland program_wm_for_pipe(dc, pipe_ctx, context); 21604562236bSHarry Wentland } 21614562236bSHarry Wentland 21624562236bSHarry Wentland static void dce110_set_bandwidth(struct core_dc *dc) 21634562236bSHarry Wentland { 21644562236bSHarry Wentland int i; 21654562236bSHarry Wentland 21664562236bSHarry Wentland for (i = 0; i < dc->current_context->res_ctx.pool->pipe_count; i++) { 21674562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; 21684562236bSHarry Wentland 21694562236bSHarry Wentland if (!pipe_ctx->stream) 21704562236bSHarry Wentland continue; 21714562236bSHarry Wentland 21724562236bSHarry Wentland program_wm_for_pipe(dc, pipe_ctx, dc->current_context); 21734562236bSHarry Wentland } 21744562236bSHarry Wentland 21751a687574SDmytro Laktyushkin dc->current_context->res_ctx.pool->display_clock->funcs->set_clock( 21761a687574SDmytro Laktyushkin dc->current_context->res_ctx.pool->display_clock, 2177a99240d5SDmytro Laktyushkin dc->current_context->dispclk_khz * 115 / 100); 21784562236bSHarry Wentland } 21794562236bSHarry Wentland 21804562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 21814562236bSHarry Wentland struct core_dc *dc, struct pipe_ctx *pipe_ctx) 21824562236bSHarry Wentland { 21834562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 21844562236bSHarry Wentland struct pipe_ctx *old_pipe = NULL; 21854562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 21864562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 21874562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 21884562236bSHarry Wentland unsigned int i; 21894562236bSHarry Wentland 21904562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 21914562236bSHarry Wentland 21924562236bSHarry Wentland if (dc->current_context) 21934562236bSHarry Wentland old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 21944562236bSHarry Wentland 21954562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 21964562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 21974562236bSHarry Wentland 21984562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 21994562236bSHarry Wentland 22004562236bSHarry Wentland set_default_colors(pipe_ctx); 22014562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 22024562236bSHarry Wentland == true) { 22034562236bSHarry Wentland tbl_entry.color_space = 22044562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 22054562236bSHarry Wentland 22064562236bSHarry Wentland for (i = 0; i < 12; i++) 22074562236bSHarry Wentland tbl_entry.regval[i] = 22084562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 22094562236bSHarry Wentland 22104562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 22114562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 22124562236bSHarry Wentland } 22134562236bSHarry Wentland 22144562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 22154562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 22164562236bSHarry Wentland adjust.temperature_matrix[0] = 22174562236bSHarry Wentland pipe_ctx->stream-> 22184562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 22194562236bSHarry Wentland adjust.temperature_matrix[1] = 22204562236bSHarry Wentland pipe_ctx->stream-> 22214562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 22224562236bSHarry Wentland adjust.temperature_matrix[2] = 22234562236bSHarry Wentland pipe_ctx->stream-> 22244562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 22254562236bSHarry Wentland adjust.temperature_matrix[3] = 22264562236bSHarry Wentland pipe_ctx->stream-> 22274562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 22284562236bSHarry Wentland adjust.temperature_matrix[4] = 22294562236bSHarry Wentland pipe_ctx->stream-> 22304562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 22314562236bSHarry Wentland adjust.temperature_matrix[5] = 22324562236bSHarry Wentland pipe_ctx->stream-> 22334562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 22344562236bSHarry Wentland adjust.temperature_matrix[6] = 22354562236bSHarry Wentland pipe_ctx->stream-> 22364562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 22374562236bSHarry Wentland adjust.temperature_matrix[7] = 22384562236bSHarry Wentland pipe_ctx->stream-> 22394562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 22404562236bSHarry Wentland adjust.temperature_matrix[8] = 22414562236bSHarry Wentland pipe_ctx->stream-> 22424562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 22434562236bSHarry Wentland } 22444562236bSHarry Wentland 22454562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 22464562236bSHarry Wentland 22474562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 22484562236bSHarry Wentland if (old_pipe && memcmp(&old_pipe->scl_data, 22494562236bSHarry Wentland &pipe_ctx->scl_data, 22504562236bSHarry Wentland sizeof(struct scaler_data)) != 0) 22514562236bSHarry Wentland program_scaler(dc, pipe_ctx); 22524562236bSHarry Wentland 22534562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 22544562236bSHarry Wentland mi, 22554562236bSHarry Wentland surface->public.format, 22564562236bSHarry Wentland &surface->public.tiling_info, 22574562236bSHarry Wentland &surface->public.plane_size, 22584562236bSHarry Wentland surface->public.rotation, 2259624d7c47SYongqiang Sun NULL, 22604562236bSHarry Wentland false, 2261624d7c47SYongqiang Sun pipe_ctx->surface->public.visible); 22624562236bSHarry Wentland 22634562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 22644562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 22654562236bSHarry Wentland pipe_ctx->mi, 22664562236bSHarry Wentland surface->public.format, 22674562236bSHarry Wentland &surface->public.tiling_info, 22684562236bSHarry Wentland surface->public.rotation); 22694562236bSHarry Wentland 22704562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 22714562236bSHarry Wentland "Pipe:%d 0x%x: addr hi:0x%x, " 22724562236bSHarry Wentland "addr low:0x%x, " 22734562236bSHarry Wentland "src: %d, %d, %d," 22744562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 22754562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 22764562236bSHarry Wentland pipe_ctx->pipe_idx, 22774562236bSHarry Wentland pipe_ctx->surface, 22784562236bSHarry Wentland pipe_ctx->surface->public.address.grph.addr.high_part, 22794562236bSHarry Wentland pipe_ctx->surface->public.address.grph.addr.low_part, 22804562236bSHarry Wentland pipe_ctx->surface->public.src_rect.x, 22814562236bSHarry Wentland pipe_ctx->surface->public.src_rect.y, 22824562236bSHarry Wentland pipe_ctx->surface->public.src_rect.width, 22834562236bSHarry Wentland pipe_ctx->surface->public.src_rect.height, 22844562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.x, 22854562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.y, 22864562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.width, 22874562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.height, 22884562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.x, 22894562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.y, 22904562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.width, 22914562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.height); 22924562236bSHarry Wentland 22934562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 22944562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 22954562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 22964562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 22974562236bSHarry Wentland pipe_ctx->pipe_idx, 22984562236bSHarry Wentland pipe_ctx->scl_data.viewport.width, 22994562236bSHarry Wentland pipe_ctx->scl_data.viewport.height, 23004562236bSHarry Wentland pipe_ctx->scl_data.viewport.x, 23014562236bSHarry Wentland pipe_ctx->scl_data.viewport.y, 23024562236bSHarry Wentland pipe_ctx->scl_data.recout.width, 23034562236bSHarry Wentland pipe_ctx->scl_data.recout.height, 23044562236bSHarry Wentland pipe_ctx->scl_data.recout.x, 23054562236bSHarry Wentland pipe_ctx->scl_data.recout.y); 23064562236bSHarry Wentland } 23074562236bSHarry Wentland 23084562236bSHarry Wentland static void dce110_prepare_pipe_for_context( 23094562236bSHarry Wentland struct core_dc *dc, 23104562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 23114562236bSHarry Wentland struct validate_context *context) 23124562236bSHarry Wentland { 23134562236bSHarry Wentland dce110_power_on_pipe_if_needed(dc, pipe_ctx, context); 2314fb735a9fSAnthony Koo dc->hwss.increase_watermarks_for_pipe(dc, pipe_ctx, context); 23154562236bSHarry Wentland } 23164562236bSHarry Wentland 23174562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 23184562236bSHarry Wentland struct core_dc *dc, 23194562236bSHarry Wentland struct core_surface *surface, 23204562236bSHarry Wentland struct validate_context *context) 23214562236bSHarry Wentland { 23224562236bSHarry Wentland int i; 23234562236bSHarry Wentland 23244562236bSHarry Wentland /* TODO remove when removing the surface reset workaroud*/ 23254562236bSHarry Wentland if (!surface) 23264562236bSHarry Wentland return; 23274562236bSHarry Wentland 23284562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 23294562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 23304562236bSHarry Wentland 23314562236bSHarry Wentland if (pipe_ctx->surface != surface) 23324562236bSHarry Wentland continue; 23334562236bSHarry Wentland 23344562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 2335b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 23364562236bSHarry Wentland 23374562236bSHarry Wentland } 23384562236bSHarry Wentland } 23394562236bSHarry Wentland 23404562236bSHarry Wentland static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) 23414562236bSHarry Wentland { 23424562236bSHarry Wentland int i; 23434562236bSHarry Wentland 23444562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) 23454562236bSHarry Wentland if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe) 23464562236bSHarry Wentland break; 23474562236bSHarry Wentland 23484562236bSHarry Wentland if (i == dc->res_pool->pipe_count) 23494562236bSHarry Wentland return; 23504562236bSHarry Wentland 23514562236bSHarry Wentland dc->hwss.enable_display_power_gating( 23524562236bSHarry Wentland dc, i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 23534562236bSHarry Wentland if (pipe->xfm) 23544562236bSHarry Wentland pipe->xfm->funcs->transform_reset(pipe->xfm); 23554562236bSHarry Wentland memset(&pipe->scl_data, 0, sizeof(struct scaler_data)); 23564562236bSHarry Wentland } 23574562236bSHarry Wentland 23584562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 23594562236bSHarry Wentland .init_hw = init_hw, 23604562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 23614562236bSHarry Wentland .prepare_pipe_for_context = dce110_prepare_pipe_for_context, 23624562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 23634562236bSHarry Wentland .set_plane_config = set_plane_config, 23644562236bSHarry Wentland .update_plane_addr = update_plane_addr, 23654562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 2366d7194cf6SAric Cyr .set_input_transfer_func = dce110_set_input_transfer_func, 236790e508baSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 23684562236bSHarry Wentland .power_down = dce110_power_down, 23694562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 23704562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 23714562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 23724562236bSHarry Wentland .enable_stream = dce110_enable_stream, 23734562236bSHarry Wentland .disable_stream = dce110_disable_stream, 23744562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 23754562236bSHarry Wentland .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 23764562236bSHarry Wentland .enable_display_power_gating = dce110_enable_display_power_gating, 23774562236bSHarry Wentland .power_down_front_end = dce110_power_down_fe, 23784562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 23794562236bSHarry Wentland .set_displaymarks = dce110_set_displaymarks, 23804562236bSHarry Wentland .increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe, 23814562236bSHarry Wentland .set_bandwidth = dce110_set_bandwidth, 23824562236bSHarry Wentland .set_drr = set_drr, 23834562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 23844562236bSHarry Wentland .reset_hw_ctx_wrap = reset_hw_ctx_wrap, 23854b5e7d62SHersen Wu .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, 23864562236bSHarry Wentland }; 23874562236bSHarry Wentland 23884562236bSHarry Wentland bool dce110_hw_sequencer_construct(struct core_dc *dc) 23894562236bSHarry Wentland { 23904562236bSHarry Wentland dc->hwss = dce110_funcs; 23914562236bSHarry Wentland 23924562236bSHarry Wentland return true; 23934562236bSHarry Wentland } 23944562236bSHarry Wentland 2395