14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland #include "dm_services.h" 264562236bSHarry Wentland #include "dc.h" 274562236bSHarry Wentland #include "dc_bios_types.h" 284562236bSHarry Wentland #include "core_types.h" 294562236bSHarry Wentland #include "core_status.h" 304562236bSHarry Wentland #include "resource.h" 314562236bSHarry Wentland #include "hw_sequencer.h" 324562236bSHarry Wentland #include "dm_helpers.h" 334562236bSHarry Wentland #include "dce110_hw_sequencer.h" 344562236bSHarry Wentland #include "dce110_timing_generator.h" 354562236bSHarry Wentland 364562236bSHarry Wentland #include "bios/bios_parser_helper.h" 374562236bSHarry Wentland #include "timing_generator.h" 384562236bSHarry Wentland #include "mem_input.h" 394562236bSHarry Wentland #include "opp.h" 404562236bSHarry Wentland #include "ipp.h" 414562236bSHarry Wentland #include "transform.h" 424562236bSHarry Wentland #include "stream_encoder.h" 434562236bSHarry Wentland #include "link_encoder.h" 444562236bSHarry Wentland #include "clock_source.h" 455e7773a2SAnthony Koo #include "abm.h" 464562236bSHarry Wentland #include "audio.h" 474562236bSHarry Wentland #include "dce/dce_hwseq.h" 484562236bSHarry Wentland 494562236bSHarry Wentland /* include DCE11 register header files */ 504562236bSHarry Wentland #include "dce/dce_11_0_d.h" 514562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 524562236bSHarry Wentland 534562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 544562236bSHarry Wentland uint32_t crtc; 554562236bSHarry Wentland }; 564562236bSHarry Wentland 574562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 584562236bSHarry Wentland { 594562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 604562236bSHarry Wentland }, 614562236bSHarry Wentland { 624562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 634562236bSHarry Wentland }, 644562236bSHarry Wentland { 654562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 664562236bSHarry Wentland }, 674562236bSHarry Wentland { 684562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 694562236bSHarry Wentland } 704562236bSHarry Wentland }; 714562236bSHarry Wentland 724562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 734562236bSHarry Wentland (reg + reg_offsets[id].blnd) 744562236bSHarry Wentland 754562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 764562236bSHarry Wentland (reg + reg_offsets[id].crtc) 774562236bSHarry Wentland 784562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 794562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 804562236bSHarry Wentland 814562236bSHarry Wentland /******************************************************************************* 824562236bSHarry Wentland * Private definitions 834562236bSHarry Wentland ******************************************************************************/ 844562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 854562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 864562236bSHarry Wentland { 874562236bSHarry Wentland uint32_t addr; 884562236bSHarry Wentland uint32_t value = 0; 894562236bSHarry Wentland uint32_t chunk_int = 0; 904562236bSHarry Wentland uint32_t chunk_mul = 0; 914562236bSHarry Wentland 924562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 934562236bSHarry Wentland value = dm_read_reg(ctx, addr); 944562236bSHarry Wentland 954562236bSHarry Wentland set_reg_field_value( 964562236bSHarry Wentland value, 974562236bSHarry Wentland 0, 984562236bSHarry Wentland DVMM_PTE_CONTROL, 994562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1004562236bSHarry Wentland 1014562236bSHarry Wentland set_reg_field_value( 1024562236bSHarry Wentland value, 1034562236bSHarry Wentland 1, 1044562236bSHarry Wentland DVMM_PTE_CONTROL, 1054562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1064562236bSHarry Wentland 1074562236bSHarry Wentland set_reg_field_value( 1084562236bSHarry Wentland value, 1094562236bSHarry Wentland 1, 1104562236bSHarry Wentland DVMM_PTE_CONTROL, 1114562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1124562236bSHarry Wentland 1134562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1144562236bSHarry Wentland 1154562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1164562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1174562236bSHarry Wentland 1184562236bSHarry Wentland chunk_int = get_reg_field_value( 1194562236bSHarry Wentland value, 1204562236bSHarry Wentland DVMM_PTE_REQ, 1214562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1224562236bSHarry Wentland 1234562236bSHarry Wentland chunk_mul = get_reg_field_value( 1244562236bSHarry Wentland value, 1254562236bSHarry Wentland DVMM_PTE_REQ, 1264562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1274562236bSHarry Wentland 1284562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1294562236bSHarry Wentland 1304562236bSHarry Wentland set_reg_field_value( 1314562236bSHarry Wentland value, 1324562236bSHarry Wentland 255, 1334562236bSHarry Wentland DVMM_PTE_REQ, 1344562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1354562236bSHarry Wentland 1364562236bSHarry Wentland set_reg_field_value( 1374562236bSHarry Wentland value, 1384562236bSHarry Wentland 4, 1394562236bSHarry Wentland DVMM_PTE_REQ, 1404562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1414562236bSHarry Wentland 1424562236bSHarry Wentland set_reg_field_value( 1434562236bSHarry Wentland value, 1444562236bSHarry Wentland 4, 1454562236bSHarry Wentland DVMM_PTE_REQ, 1464562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1474562236bSHarry Wentland 1484562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1494562236bSHarry Wentland } 1504562236bSHarry Wentland } 1514562236bSHarry Wentland /**************************************************************************/ 1524562236bSHarry Wentland 1534562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1544562236bSHarry Wentland struct dc_context *ctx, 1554562236bSHarry Wentland bool clock_gating) 1564562236bSHarry Wentland { 1574562236bSHarry Wentland /*TODO*/ 1584562236bSHarry Wentland } 1594562236bSHarry Wentland 1604562236bSHarry Wentland static bool dce110_enable_display_power_gating( 1614562236bSHarry Wentland struct core_dc *dc, 1624562236bSHarry Wentland uint8_t controller_id, 1634562236bSHarry Wentland struct dc_bios *dcb, 1644562236bSHarry Wentland enum pipe_gating_control power_gating) 1654562236bSHarry Wentland { 1664562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 1674562236bSHarry Wentland enum bp_pipe_control_action cntl; 1684562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 1694562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1704562236bSHarry Wentland 1714562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1724562236bSHarry Wentland return true; 1734562236bSHarry Wentland 1744562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 1754562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 1764562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 1774562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 1784562236bSHarry Wentland else 1794562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 1804562236bSHarry Wentland 1814562236bSHarry Wentland if (controller_id == underlay_idx) 1824562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 1834562236bSHarry Wentland 1844562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 1854562236bSHarry Wentland 1864562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 1874562236bSHarry Wentland dcb, controller_id + 1, cntl); 1884562236bSHarry Wentland 1894562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 1904562236bSHarry Wentland * by default when command table is called 1914562236bSHarry Wentland * 1924562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 1934562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 1944562236bSHarry Wentland * than 3. 1954562236bSHarry Wentland */ 1964562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 1974562236bSHarry Wentland dm_write_reg(ctx, 1984562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 1994562236bSHarry Wentland 0); 2004562236bSHarry Wentland } 2014562236bSHarry Wentland 2024562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2034562236bSHarry Wentland dce110_init_pte(ctx); 2044562236bSHarry Wentland 2054562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2064562236bSHarry Wentland return true; 2074562236bSHarry Wentland else 2084562236bSHarry Wentland return false; 2094562236bSHarry Wentland } 2104562236bSHarry Wentland 2114562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2124562236bSHarry Wentland const struct core_surface *surface) 2134562236bSHarry Wentland { 2144562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2154562236bSHarry Wentland 2164562236bSHarry Wentland switch (surface->public.format) { 2174562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2188693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2194562236bSHarry Wentland prescale_params->scale = 0x2020; 2204562236bSHarry Wentland break; 2214562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2224562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2234562236bSHarry Wentland prescale_params->scale = 0x2008; 2244562236bSHarry Wentland break; 2254562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2264562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2274562236bSHarry Wentland prescale_params->scale = 0x2000; 2284562236bSHarry Wentland break; 2294562236bSHarry Wentland default: 2304562236bSHarry Wentland ASSERT(false); 231d7194cf6SAric Cyr break; 2324562236bSHarry Wentland } 2334562236bSHarry Wentland } 2344562236bSHarry Wentland 235d7194cf6SAric Cyr static bool dce110_set_input_transfer_func( 236fb735a9fSAnthony Koo struct pipe_ctx *pipe_ctx, 2374562236bSHarry Wentland const struct core_surface *surface) 2384562236bSHarry Wentland { 239fb735a9fSAnthony Koo struct input_pixel_processor *ipp = pipe_ctx->ipp; 24090e508baSAnthony Koo const struct core_transfer_func *tf = NULL; 24190e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 24290e508baSAnthony Koo bool result = true; 24390e508baSAnthony Koo 24490e508baSAnthony Koo if (ipp == NULL) 24590e508baSAnthony Koo return false; 24690e508baSAnthony Koo 24790e508baSAnthony Koo if (surface->public.in_transfer_func) 24890e508baSAnthony Koo tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func); 24990e508baSAnthony Koo 25090e508baSAnthony Koo build_prescale_params(&prescale_params, surface); 25190e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 25290e508baSAnthony Koo 253d7194cf6SAric Cyr if (surface->public.gamma_correction) 254d7194cf6SAric Cyr ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); 255d7194cf6SAric Cyr 25690e508baSAnthony Koo if (tf == NULL) { 25790e508baSAnthony Koo /* Default case if no input transfer function specified */ 25890e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 259306dadf0SAmy Zhang IPP_DEGAMMA_MODE_HW_sRGB); 26090e508baSAnthony Koo } else if (tf->public.type == TF_TYPE_PREDEFINED) { 26190e508baSAnthony Koo switch (tf->public.tf) { 26290e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 26390e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 26490e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_sRGB); 26590e508baSAnthony Koo break; 26690e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 26790e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 26890e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_xvYCC); 26990e508baSAnthony Koo break; 27090e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 27190e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 27290e508baSAnthony Koo IPP_DEGAMMA_MODE_BYPASS); 27390e508baSAnthony Koo break; 27490e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 27590e508baSAnthony Koo result = false; 27690e508baSAnthony Koo break; 27790e508baSAnthony Koo default: 27890e508baSAnthony Koo result = false; 279d7194cf6SAric Cyr break; 28090e508baSAnthony Koo } 28190e508baSAnthony Koo } else { 28290e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 28390e508baSAnthony Koo result = false; 28490e508baSAnthony Koo } 28590e508baSAnthony Koo 28690e508baSAnthony Koo return result; 28790e508baSAnthony Koo } 28890e508baSAnthony Koo 289fcd2f4bfSAmy Zhang static bool build_custom_float( 290fcd2f4bfSAmy Zhang struct fixed31_32 value, 291fcd2f4bfSAmy Zhang const struct custom_float_format *format, 292fcd2f4bfSAmy Zhang bool *negative, 293fcd2f4bfSAmy Zhang uint32_t *mantissa, 294fcd2f4bfSAmy Zhang uint32_t *exponenta) 295fcd2f4bfSAmy Zhang { 296fcd2f4bfSAmy Zhang uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; 297fcd2f4bfSAmy Zhang 298fcd2f4bfSAmy Zhang const struct fixed31_32 mantissa_constant_plus_max_fraction = 299fcd2f4bfSAmy Zhang dal_fixed31_32_from_fraction( 300fcd2f4bfSAmy Zhang (1LL << (format->mantissa_bits + 1)) - 1, 301fcd2f4bfSAmy Zhang 1LL << format->mantissa_bits); 302fcd2f4bfSAmy Zhang 303fcd2f4bfSAmy Zhang struct fixed31_32 mantiss; 304fcd2f4bfSAmy Zhang 305fcd2f4bfSAmy Zhang if (dal_fixed31_32_eq( 306fcd2f4bfSAmy Zhang value, 307fcd2f4bfSAmy Zhang dal_fixed31_32_zero)) { 308fcd2f4bfSAmy Zhang *negative = false; 309fcd2f4bfSAmy Zhang *mantissa = 0; 310fcd2f4bfSAmy Zhang *exponenta = 0; 311fcd2f4bfSAmy Zhang return true; 312fcd2f4bfSAmy Zhang } 313fcd2f4bfSAmy Zhang 314fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt( 315fcd2f4bfSAmy Zhang value, 316fcd2f4bfSAmy Zhang dal_fixed31_32_zero)) { 317fcd2f4bfSAmy Zhang *negative = format->sign; 318fcd2f4bfSAmy Zhang value = dal_fixed31_32_neg(value); 319fcd2f4bfSAmy Zhang } else { 320fcd2f4bfSAmy Zhang *negative = false; 321fcd2f4bfSAmy Zhang } 322fcd2f4bfSAmy Zhang 323fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt( 324fcd2f4bfSAmy Zhang value, 325fcd2f4bfSAmy Zhang dal_fixed31_32_one)) { 326fcd2f4bfSAmy Zhang uint32_t i = 1; 327fcd2f4bfSAmy Zhang 328fcd2f4bfSAmy Zhang do { 329fcd2f4bfSAmy Zhang value = dal_fixed31_32_shl(value, 1); 330fcd2f4bfSAmy Zhang ++i; 331fcd2f4bfSAmy Zhang } while (dal_fixed31_32_lt( 332fcd2f4bfSAmy Zhang value, 333fcd2f4bfSAmy Zhang dal_fixed31_32_one)); 334fcd2f4bfSAmy Zhang 335fcd2f4bfSAmy Zhang --i; 336fcd2f4bfSAmy Zhang 337fcd2f4bfSAmy Zhang if (exp_offset <= i) { 338fcd2f4bfSAmy Zhang *mantissa = 0; 339fcd2f4bfSAmy Zhang *exponenta = 0; 340fcd2f4bfSAmy Zhang return true; 341fcd2f4bfSAmy Zhang } 342fcd2f4bfSAmy Zhang 343fcd2f4bfSAmy Zhang *exponenta = exp_offset - i; 344fcd2f4bfSAmy Zhang } else if (dal_fixed31_32_le( 345fcd2f4bfSAmy Zhang mantissa_constant_plus_max_fraction, 346fcd2f4bfSAmy Zhang value)) { 347fcd2f4bfSAmy Zhang uint32_t i = 1; 348fcd2f4bfSAmy Zhang 349fcd2f4bfSAmy Zhang do { 350fcd2f4bfSAmy Zhang value = dal_fixed31_32_shr(value, 1); 351fcd2f4bfSAmy Zhang ++i; 352fcd2f4bfSAmy Zhang } while (dal_fixed31_32_lt( 353fcd2f4bfSAmy Zhang mantissa_constant_plus_max_fraction, 354fcd2f4bfSAmy Zhang value)); 355fcd2f4bfSAmy Zhang 356fcd2f4bfSAmy Zhang *exponenta = exp_offset + i - 1; 357fcd2f4bfSAmy Zhang } else { 358fcd2f4bfSAmy Zhang *exponenta = exp_offset; 359fcd2f4bfSAmy Zhang } 360fcd2f4bfSAmy Zhang 361fcd2f4bfSAmy Zhang mantiss = dal_fixed31_32_sub( 362fcd2f4bfSAmy Zhang value, 363fcd2f4bfSAmy Zhang dal_fixed31_32_one); 364fcd2f4bfSAmy Zhang 365fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt( 366fcd2f4bfSAmy Zhang mantiss, 367fcd2f4bfSAmy Zhang dal_fixed31_32_zero) || 368fcd2f4bfSAmy Zhang dal_fixed31_32_lt( 369fcd2f4bfSAmy Zhang dal_fixed31_32_one, 370fcd2f4bfSAmy Zhang mantiss)) 371fcd2f4bfSAmy Zhang mantiss = dal_fixed31_32_zero; 372fcd2f4bfSAmy Zhang else 373fcd2f4bfSAmy Zhang mantiss = dal_fixed31_32_shl( 374fcd2f4bfSAmy Zhang mantiss, 375fcd2f4bfSAmy Zhang format->mantissa_bits); 376fcd2f4bfSAmy Zhang 377fcd2f4bfSAmy Zhang *mantissa = dal_fixed31_32_floor(mantiss); 378fcd2f4bfSAmy Zhang 379fcd2f4bfSAmy Zhang return true; 380fcd2f4bfSAmy Zhang } 381fcd2f4bfSAmy Zhang 382fcd2f4bfSAmy Zhang static bool setup_custom_float( 383fcd2f4bfSAmy Zhang const struct custom_float_format *format, 384fcd2f4bfSAmy Zhang bool negative, 385fcd2f4bfSAmy Zhang uint32_t mantissa, 386fcd2f4bfSAmy Zhang uint32_t exponenta, 387fcd2f4bfSAmy Zhang uint32_t *result) 388fcd2f4bfSAmy Zhang { 389fcd2f4bfSAmy Zhang uint32_t i = 0; 390fcd2f4bfSAmy Zhang uint32_t j = 0; 391fcd2f4bfSAmy Zhang 392fcd2f4bfSAmy Zhang uint32_t value = 0; 393fcd2f4bfSAmy Zhang 394fcd2f4bfSAmy Zhang /* verification code: 395fcd2f4bfSAmy Zhang * once calculation is ok we can remove it 396fcd2f4bfSAmy Zhang */ 397fcd2f4bfSAmy Zhang 398fcd2f4bfSAmy Zhang const uint32_t mantissa_mask = 399fcd2f4bfSAmy Zhang (1 << (format->mantissa_bits + 1)) - 1; 400fcd2f4bfSAmy Zhang 401fcd2f4bfSAmy Zhang const uint32_t exponenta_mask = 402fcd2f4bfSAmy Zhang (1 << (format->exponenta_bits + 1)) - 1; 403fcd2f4bfSAmy Zhang 404fcd2f4bfSAmy Zhang if (mantissa & ~mantissa_mask) { 405fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 406fcd2f4bfSAmy Zhang mantissa = mantissa_mask; 407fcd2f4bfSAmy Zhang } 408fcd2f4bfSAmy Zhang 409fcd2f4bfSAmy Zhang if (exponenta & ~exponenta_mask) { 410fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 411fcd2f4bfSAmy Zhang exponenta = exponenta_mask; 412fcd2f4bfSAmy Zhang } 413fcd2f4bfSAmy Zhang 414fcd2f4bfSAmy Zhang /* end of verification code */ 415fcd2f4bfSAmy Zhang 416fcd2f4bfSAmy Zhang while (i < format->mantissa_bits) { 417fcd2f4bfSAmy Zhang uint32_t mask = 1 << i; 418fcd2f4bfSAmy Zhang 419fcd2f4bfSAmy Zhang if (mantissa & mask) 420fcd2f4bfSAmy Zhang value |= mask; 421fcd2f4bfSAmy Zhang 422fcd2f4bfSAmy Zhang ++i; 423fcd2f4bfSAmy Zhang } 424fcd2f4bfSAmy Zhang 425fcd2f4bfSAmy Zhang while (j < format->exponenta_bits) { 426fcd2f4bfSAmy Zhang uint32_t mask = 1 << j; 427fcd2f4bfSAmy Zhang 428fcd2f4bfSAmy Zhang if (exponenta & mask) 429fcd2f4bfSAmy Zhang value |= mask << i; 430fcd2f4bfSAmy Zhang 431fcd2f4bfSAmy Zhang ++j; 432fcd2f4bfSAmy Zhang } 433fcd2f4bfSAmy Zhang 434fcd2f4bfSAmy Zhang if (negative && format->sign) 435fcd2f4bfSAmy Zhang value |= 1 << (i + j); 436fcd2f4bfSAmy Zhang 437fcd2f4bfSAmy Zhang *result = value; 438fcd2f4bfSAmy Zhang 439fcd2f4bfSAmy Zhang return true; 440fcd2f4bfSAmy Zhang } 441fcd2f4bfSAmy Zhang 442fcd2f4bfSAmy Zhang static bool convert_to_custom_float_format( 443fcd2f4bfSAmy Zhang struct fixed31_32 value, 444fcd2f4bfSAmy Zhang const struct custom_float_format *format, 445fcd2f4bfSAmy Zhang uint32_t *result) 446fcd2f4bfSAmy Zhang { 447fcd2f4bfSAmy Zhang uint32_t mantissa; 448fcd2f4bfSAmy Zhang uint32_t exponenta; 449fcd2f4bfSAmy Zhang bool negative; 450fcd2f4bfSAmy Zhang 451fcd2f4bfSAmy Zhang return build_custom_float( 452fcd2f4bfSAmy Zhang value, format, &negative, &mantissa, &exponenta) && 453fcd2f4bfSAmy Zhang setup_custom_float( 454fcd2f4bfSAmy Zhang format, negative, mantissa, exponenta, result); 455fcd2f4bfSAmy Zhang } 456fcd2f4bfSAmy Zhang 457fcd2f4bfSAmy Zhang static bool convert_to_custom_float( 458fcd2f4bfSAmy Zhang struct pwl_result_data *rgb_resulted, 459fcd2f4bfSAmy Zhang struct curve_points *arr_points, 460fcd2f4bfSAmy Zhang uint32_t hw_points_num) 461fcd2f4bfSAmy Zhang { 462fcd2f4bfSAmy Zhang struct custom_float_format fmt; 463fcd2f4bfSAmy Zhang 464fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 465fcd2f4bfSAmy Zhang 466fcd2f4bfSAmy Zhang uint32_t i = 0; 467fcd2f4bfSAmy Zhang 468fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 469fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 470fcd2f4bfSAmy Zhang fmt.sign = true; 471fcd2f4bfSAmy Zhang 472fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 473fcd2f4bfSAmy Zhang arr_points[0].x, 474fcd2f4bfSAmy Zhang &fmt, 475fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 476fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 477fcd2f4bfSAmy Zhang return false; 478fcd2f4bfSAmy Zhang } 479fcd2f4bfSAmy Zhang 480fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 481fcd2f4bfSAmy Zhang arr_points[0].offset, 482fcd2f4bfSAmy Zhang &fmt, 483fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 484fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 485fcd2f4bfSAmy Zhang return false; 486fcd2f4bfSAmy Zhang } 487fcd2f4bfSAmy Zhang 488fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 489fcd2f4bfSAmy Zhang arr_points[0].slope, 490fcd2f4bfSAmy Zhang &fmt, 491fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 492fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 493fcd2f4bfSAmy Zhang return false; 494fcd2f4bfSAmy Zhang } 495fcd2f4bfSAmy Zhang 496fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 497fcd2f4bfSAmy Zhang fmt.sign = false; 498fcd2f4bfSAmy Zhang 499fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 500fcd2f4bfSAmy Zhang arr_points[1].x, 501fcd2f4bfSAmy Zhang &fmt, 502fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 503fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 504fcd2f4bfSAmy Zhang return false; 505fcd2f4bfSAmy Zhang } 506fcd2f4bfSAmy Zhang 507fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 508fcd2f4bfSAmy Zhang arr_points[1].y, 509fcd2f4bfSAmy Zhang &fmt, 510fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 511fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 512fcd2f4bfSAmy Zhang return false; 513fcd2f4bfSAmy Zhang } 514fcd2f4bfSAmy Zhang 515fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 516fcd2f4bfSAmy Zhang arr_points[2].slope, 517fcd2f4bfSAmy Zhang &fmt, 518fcd2f4bfSAmy Zhang &arr_points[2].custom_float_slope)) { 519fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 520fcd2f4bfSAmy Zhang return false; 521fcd2f4bfSAmy Zhang } 522fcd2f4bfSAmy Zhang 523fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 524fcd2f4bfSAmy Zhang fmt.sign = true; 525fcd2f4bfSAmy Zhang 526fcd2f4bfSAmy Zhang while (i != hw_points_num) { 527fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 528fcd2f4bfSAmy Zhang rgb->red, 529fcd2f4bfSAmy Zhang &fmt, 530fcd2f4bfSAmy Zhang &rgb->red_reg)) { 531fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 532fcd2f4bfSAmy Zhang return false; 533fcd2f4bfSAmy Zhang } 534fcd2f4bfSAmy Zhang 535fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 536fcd2f4bfSAmy Zhang rgb->green, 537fcd2f4bfSAmy Zhang &fmt, 538fcd2f4bfSAmy Zhang &rgb->green_reg)) { 539fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 540fcd2f4bfSAmy Zhang return false; 541fcd2f4bfSAmy Zhang } 542fcd2f4bfSAmy Zhang 543fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 544fcd2f4bfSAmy Zhang rgb->blue, 545fcd2f4bfSAmy Zhang &fmt, 546fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 547fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 548fcd2f4bfSAmy Zhang return false; 549fcd2f4bfSAmy Zhang } 550fcd2f4bfSAmy Zhang 551fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 552fcd2f4bfSAmy Zhang rgb->delta_red, 553fcd2f4bfSAmy Zhang &fmt, 554fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 555fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 556fcd2f4bfSAmy Zhang return false; 557fcd2f4bfSAmy Zhang } 558fcd2f4bfSAmy Zhang 559fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 560fcd2f4bfSAmy Zhang rgb->delta_green, 561fcd2f4bfSAmy Zhang &fmt, 562fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 563fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 564fcd2f4bfSAmy Zhang return false; 565fcd2f4bfSAmy Zhang } 566fcd2f4bfSAmy Zhang 567fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 568fcd2f4bfSAmy Zhang rgb->delta_blue, 569fcd2f4bfSAmy Zhang &fmt, 570fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 571fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 572fcd2f4bfSAmy Zhang return false; 573fcd2f4bfSAmy Zhang } 574fcd2f4bfSAmy Zhang 575fcd2f4bfSAmy Zhang ++rgb; 576fcd2f4bfSAmy Zhang ++i; 577fcd2f4bfSAmy Zhang } 578fcd2f4bfSAmy Zhang 579fcd2f4bfSAmy Zhang return true; 580fcd2f4bfSAmy Zhang } 581fcd2f4bfSAmy Zhang 5827ec6b963SYongqiang Sun bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func 583fcd2f4bfSAmy Zhang *output_tf, struct pwl_params *regamma_params) 584fcd2f4bfSAmy Zhang { 58523ae4f8eSAmy Zhang struct curve_points *arr_points; 58623ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 58723ae4f8eSAmy Zhang struct pwl_result_data *rgb; 58823ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 589fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 590fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 591fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 592fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 593fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 594fcd2f4bfSAmy Zhang 595fcd2f4bfSAmy Zhang int32_t segment_start, segment_end; 59623ae4f8eSAmy Zhang uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; 59723ae4f8eSAmy Zhang 59823ae4f8eSAmy Zhang if (output_tf == NULL || regamma_params == NULL) 59923ae4f8eSAmy Zhang return false; 60023ae4f8eSAmy Zhang 60123ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 60223ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 60323ae4f8eSAmy Zhang hw_points = 0; 604fcd2f4bfSAmy Zhang 605fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 606fcd2f4bfSAmy Zhang 607fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 608534db198SAmy Zhang /* 16 segments 609fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 610fcd2f4bfSAmy Zhang */ 611fcd2f4bfSAmy Zhang segment_start = -11; 612fcd2f4bfSAmy Zhang segment_end = 5; 613fcd2f4bfSAmy Zhang 614534db198SAmy Zhang seg_distr[0] = 2; 615534db198SAmy Zhang seg_distr[1] = 2; 616534db198SAmy Zhang seg_distr[2] = 2; 617534db198SAmy Zhang seg_distr[3] = 2; 618534db198SAmy Zhang seg_distr[4] = 2; 619534db198SAmy Zhang seg_distr[5] = 2; 620534db198SAmy Zhang seg_distr[6] = 3; 621534db198SAmy Zhang seg_distr[7] = 4; 622534db198SAmy Zhang seg_distr[8] = 4; 623534db198SAmy Zhang seg_distr[9] = 4; 624534db198SAmy Zhang seg_distr[10] = 4; 625534db198SAmy Zhang seg_distr[11] = 5; 626534db198SAmy Zhang seg_distr[12] = 5; 627534db198SAmy Zhang seg_distr[13] = 5; 628534db198SAmy Zhang seg_distr[14] = 5; 629534db198SAmy Zhang seg_distr[15] = 5; 630534db198SAmy Zhang 631fcd2f4bfSAmy Zhang } else { 632534db198SAmy Zhang /* 10 segments 633fcd2f4bfSAmy Zhang * segment is from 2^-10 to 2^0 634fcd2f4bfSAmy Zhang */ 635fcd2f4bfSAmy Zhang segment_start = -10; 636fcd2f4bfSAmy Zhang segment_end = 0; 637534db198SAmy Zhang 638534db198SAmy Zhang seg_distr[0] = 3; 639534db198SAmy Zhang seg_distr[1] = 4; 640534db198SAmy Zhang seg_distr[2] = 4; 641534db198SAmy Zhang seg_distr[3] = 4; 642534db198SAmy Zhang seg_distr[4] = 4; 643534db198SAmy Zhang seg_distr[5] = 4; 644534db198SAmy Zhang seg_distr[6] = 4; 645534db198SAmy Zhang seg_distr[7] = 4; 646534db198SAmy Zhang seg_distr[8] = 5; 647534db198SAmy Zhang seg_distr[9] = 5; 648534db198SAmy Zhang seg_distr[10] = -1; 649534db198SAmy Zhang seg_distr[11] = -1; 650534db198SAmy Zhang seg_distr[12] = -1; 651534db198SAmy Zhang seg_distr[13] = -1; 652534db198SAmy Zhang seg_distr[14] = -1; 653534db198SAmy Zhang seg_distr[15] = -1; 654fcd2f4bfSAmy Zhang } 655fcd2f4bfSAmy Zhang 656534db198SAmy Zhang for (k = 0; k < 16; k++) { 657534db198SAmy Zhang if (seg_distr[k] != -1) 658534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 659534db198SAmy Zhang } 660534db198SAmy Zhang 661fcd2f4bfSAmy Zhang j = 0; 662534db198SAmy Zhang for (k = 0; k < (segment_end - segment_start); k++) { 663534db198SAmy Zhang increment = 32 / (1 << seg_distr[k]); 664534db198SAmy Zhang start_index = (segment_start + k + 25) * 32; 665534db198SAmy Zhang for (i = start_index; i < start_index + 32; i += increment) { 666534db198SAmy Zhang if (j == hw_points - 1) 667fcd2f4bfSAmy Zhang break; 668fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 669fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 670fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 671fcd2f4bfSAmy Zhang j++; 672fcd2f4bfSAmy Zhang } 673534db198SAmy Zhang } 674534db198SAmy Zhang 675534db198SAmy Zhang /* last point */ 676534db198SAmy Zhang start_index = (segment_end + 25) * 32; 677534db198SAmy Zhang rgb_resulted[hw_points - 1].red = 678534db198SAmy Zhang output_tf->tf_pts.red[start_index]; 679534db198SAmy Zhang rgb_resulted[hw_points - 1].green = 680534db198SAmy Zhang output_tf->tf_pts.green[start_index]; 681534db198SAmy Zhang rgb_resulted[hw_points - 1].blue = 682534db198SAmy Zhang output_tf->tf_pts.blue[start_index]; 683fcd2f4bfSAmy Zhang 684fcd2f4bfSAmy Zhang arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 685fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_start)); 686fcd2f4bfSAmy Zhang arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 687fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 688fcd2f4bfSAmy Zhang arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 689fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 690fcd2f4bfSAmy Zhang 691fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 692fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 693fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 694fcd2f4bfSAmy Zhang 695fcd2f4bfSAmy Zhang y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); 696fcd2f4bfSAmy Zhang 697fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 698fcd2f4bfSAmy Zhang arr_points[0].slope = dal_fixed31_32_div( 699fcd2f4bfSAmy Zhang arr_points[0].y, 700fcd2f4bfSAmy Zhang arr_points[0].x); 701fcd2f4bfSAmy Zhang 702fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 703fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 704fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 705fcd2f4bfSAmy Zhang 706fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 707fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 708fcd2f4bfSAmy Zhang */ 709fcd2f4bfSAmy Zhang y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); 710fcd2f4bfSAmy Zhang 711fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 712fcd2f4bfSAmy Zhang arr_points[2].y = y3_max; 713fcd2f4bfSAmy Zhang 714fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_zero; 715fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_zero; 716fcd2f4bfSAmy Zhang 717fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 718fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 719fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 720fcd2f4bfSAmy Zhang */ 721fcd2f4bfSAmy Zhang const struct fixed31_32 end_value = 722fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(125); 723fcd2f4bfSAmy Zhang 724fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_div( 725fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 726fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 727fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_div( 728fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 729fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 730fcd2f4bfSAmy Zhang } 731fcd2f4bfSAmy Zhang 732fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 733fcd2f4bfSAmy Zhang 734534db198SAmy Zhang i = 1; 735534db198SAmy Zhang for (k = 0; k < 16 && i < 16; k++) { 736534db198SAmy Zhang if (seg_distr[k] != -1) { 737534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 738534db198SAmy Zhang seg_distr[k]; 739534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 740534db198SAmy Zhang regamma_params->arr_curve_points[k]. 741534db198SAmy Zhang offset + (1 << seg_distr[k]); 742fcd2f4bfSAmy Zhang } 743534db198SAmy Zhang i++; 744534db198SAmy Zhang } 745534db198SAmy Zhang 746534db198SAmy Zhang if (seg_distr[k] != -1) 747534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 748534db198SAmy Zhang seg_distr[k]; 749fcd2f4bfSAmy Zhang 75023ae4f8eSAmy Zhang rgb = rgb_resulted; 75123ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 752fcd2f4bfSAmy Zhang 753fcd2f4bfSAmy Zhang i = 1; 754fcd2f4bfSAmy Zhang 755fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 756fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) 757fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 758fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) 759fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 760fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) 761fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 762fcd2f4bfSAmy Zhang 763fcd2f4bfSAmy Zhang rgb->delta_red = dal_fixed31_32_sub( 764fcd2f4bfSAmy Zhang rgb_plus_1->red, 765fcd2f4bfSAmy Zhang rgb->red); 766fcd2f4bfSAmy Zhang rgb->delta_green = dal_fixed31_32_sub( 767fcd2f4bfSAmy Zhang rgb_plus_1->green, 768fcd2f4bfSAmy Zhang rgb->green); 769fcd2f4bfSAmy Zhang rgb->delta_blue = dal_fixed31_32_sub( 770fcd2f4bfSAmy Zhang rgb_plus_1->blue, 771fcd2f4bfSAmy Zhang rgb->blue); 772fcd2f4bfSAmy Zhang 773fcd2f4bfSAmy Zhang ++rgb_plus_1; 774fcd2f4bfSAmy Zhang ++rgb; 775fcd2f4bfSAmy Zhang ++i; 776fcd2f4bfSAmy Zhang } 777fcd2f4bfSAmy Zhang 778fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 779fcd2f4bfSAmy Zhang 780fcd2f4bfSAmy Zhang return true; 781fcd2f4bfSAmy Zhang } 782fcd2f4bfSAmy Zhang 78390e508baSAnthony Koo static bool dce110_set_output_transfer_func( 78490e508baSAnthony Koo struct pipe_ctx *pipe_ctx, 78590e508baSAnthony Koo const struct core_surface *surface, /* Surface - To be removed */ 78690e508baSAnthony Koo const struct core_stream *stream) 78790e508baSAnthony Koo { 788fb735a9fSAnthony Koo struct output_pixel_processor *opp = pipe_ctx->opp; 7894562236bSHarry Wentland 7904562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, true); 791cc0cb445SLeon Elazar opp->regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM; 7924562236bSHarry Wentland 793d7194cf6SAric Cyr if (stream->public.out_transfer_func && 794fcd2f4bfSAmy Zhang stream->public.out_transfer_func->type == 795fcd2f4bfSAmy Zhang TF_TYPE_PREDEFINED && 796fcd2f4bfSAmy Zhang stream->public.out_transfer_func->tf == 797fcd2f4bfSAmy Zhang TRANSFER_FUNCTION_SRGB) { 798d7194cf6SAric Cyr opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); 799fcd2f4bfSAmy Zhang } else if (dce110_translate_regamma_to_hw_format( 800cc0cb445SLeon Elazar stream->public.out_transfer_func, opp->regamma_params)) { 801cc0cb445SLeon Elazar opp->funcs->opp_program_regamma_pwl(opp, opp->regamma_params); 8024562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); 8034562236bSHarry Wentland } else { 8044562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); 8054562236bSHarry Wentland } 8064562236bSHarry Wentland 8074562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, false); 8084562236bSHarry Wentland 809cc0cb445SLeon Elazar return true; 8104562236bSHarry Wentland } 8114562236bSHarry Wentland 8124562236bSHarry Wentland static enum dc_status bios_parser_crtc_source_select( 8134562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 8144562236bSHarry Wentland { 8154562236bSHarry Wentland struct dc_bios *dcb; 8164562236bSHarry Wentland /* call VBIOS table to set CRTC source for the HW 8174562236bSHarry Wentland * encoder block 8184562236bSHarry Wentland * note: video bios clears all FMT setting here. */ 8194562236bSHarry Wentland struct bp_crtc_source_select crtc_source_select = {0}; 8204562236bSHarry Wentland const struct core_sink *sink = pipe_ctx->stream->sink; 8214562236bSHarry Wentland 8224562236bSHarry Wentland crtc_source_select.engine_id = pipe_ctx->stream_enc->id; 8234562236bSHarry Wentland crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1; 8244562236bSHarry Wentland /*TODO: Need to un-hardcode color depth, dp_audio and account for 8254562236bSHarry Wentland * the case where signal and sink signal is different (translator 8264562236bSHarry Wentland * encoder)*/ 8274562236bSHarry Wentland crtc_source_select.signal = pipe_ctx->stream->signal; 8284562236bSHarry Wentland crtc_source_select.enable_dp_audio = false; 8294562236bSHarry Wentland crtc_source_select.sink_signal = pipe_ctx->stream->signal; 8304562236bSHarry Wentland crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 8314562236bSHarry Wentland 8324562236bSHarry Wentland dcb = sink->ctx->dc_bios; 8334562236bSHarry Wentland 8344562236bSHarry Wentland if (BP_RESULT_OK != dcb->funcs->crtc_source_select( 8354562236bSHarry Wentland dcb, 8364562236bSHarry Wentland &crtc_source_select)) { 8374562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 8384562236bSHarry Wentland } 8394562236bSHarry Wentland 8404562236bSHarry Wentland return DC_OK; 8414562236bSHarry Wentland } 8424562236bSHarry Wentland 8434562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 8444562236bSHarry Wentland { 84586e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 84686e2e1beSHersen Wu 84786e2e1beSHersen Wu if (pipe_ctx->stream_enc == NULL) 84886e2e1beSHersen Wu return; /* this is not root pipe */ 84986e2e1beSHersen Wu 8504562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 8514562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_hdmi_info_packets( 8524562236bSHarry Wentland pipe_ctx->stream_enc, 8534562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 8544562236bSHarry Wentland else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 8554562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_dp_info_packets( 8564562236bSHarry Wentland pipe_ctx->stream_enc, 8574562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 8584562236bSHarry Wentland } 8594562236bSHarry Wentland 8604562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 8614562236bSHarry Wentland { 8624562236bSHarry Wentland enum dc_lane_count lane_count = 8634562236bSHarry Wentland pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count; 8644562236bSHarry Wentland 8654562236bSHarry Wentland struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; 8664562236bSHarry Wentland struct core_link *link = pipe_ctx->stream->sink->link; 8674562236bSHarry Wentland 8684562236bSHarry Wentland /* 1. update AVI info frame (HDMI, DP) 8694562236bSHarry Wentland * we always need to update info frame 8704562236bSHarry Wentland */ 8714562236bSHarry Wentland uint32_t active_total_with_borders; 8724562236bSHarry Wentland uint32_t early_control = 0; 8734562236bSHarry Wentland struct timing_generator *tg = pipe_ctx->tg; 8744562236bSHarry Wentland 8754562236bSHarry Wentland /* TODOFPGA may change to hwss.update_info_frame */ 8764562236bSHarry Wentland dce110_update_info_frame(pipe_ctx); 8774562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 8784562236bSHarry Wentland active_total_with_borders = 8794562236bSHarry Wentland timing->h_addressable 8804562236bSHarry Wentland + timing->h_border_left 8814562236bSHarry Wentland + timing->h_border_right; 8824562236bSHarry Wentland 8834562236bSHarry Wentland if (lane_count != 0) 8844562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 8854562236bSHarry Wentland 8864562236bSHarry Wentland if (early_control == 0) 8874562236bSHarry Wentland early_control = lane_count; 8884562236bSHarry Wentland 8894562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 8904562236bSHarry Wentland 8914562236bSHarry Wentland /* enable audio only within mode set */ 8924562236bSHarry Wentland if (pipe_ctx->audio != NULL) { 8934562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 8944562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc); 8954562236bSHarry Wentland } 8964562236bSHarry Wentland 8974562236bSHarry Wentland /* For MST, there are multiply stream go to only one link. 8984562236bSHarry Wentland * connect DIG back_end to front_end while enable_stream and 8994562236bSHarry Wentland * disconnect them during disable_stream 9004562236bSHarry Wentland * BY this, it is logic clean to separate stream and link */ 9014562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 9024562236bSHarry Wentland pipe_ctx->stream_enc->id, true); 9034562236bSHarry Wentland 9044562236bSHarry Wentland } 9054562236bSHarry Wentland 9064562236bSHarry Wentland void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 9074562236bSHarry Wentland { 9084562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 9094562236bSHarry Wentland struct core_link *link = stream->sink->link; 9104562236bSHarry Wentland 9114562236bSHarry Wentland if (pipe_ctx->audio) { 9124562236bSHarry Wentland pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); 9134562236bSHarry Wentland 9144562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 9154562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_disable( 9164562236bSHarry Wentland pipe_ctx->stream_enc); 9174562236bSHarry Wentland else 9184562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_disable( 9194562236bSHarry Wentland pipe_ctx->stream_enc); 9204562236bSHarry Wentland 9214562236bSHarry Wentland pipe_ctx->audio = NULL; 9224562236bSHarry Wentland 9234562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 9244562236bSHarry Wentland * add audio mode list change flag */ 9254562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 9264562236bSHarry Wentland * stream->stream_engine_id); 9274562236bSHarry Wentland */ 9284562236bSHarry Wentland } 9294562236bSHarry Wentland 9304562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 9314562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets( 9324562236bSHarry Wentland pipe_ctx->stream_enc); 9334562236bSHarry Wentland 9344562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 9354562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_dp_info_packets( 9364562236bSHarry Wentland pipe_ctx->stream_enc); 9374562236bSHarry Wentland 9384562236bSHarry Wentland pipe_ctx->stream_enc->funcs->audio_mute_control( 9394562236bSHarry Wentland pipe_ctx->stream_enc, true); 9404562236bSHarry Wentland 9414562236bSHarry Wentland 9424562236bSHarry Wentland /* blank at encoder level */ 9434562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 9444562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc); 9454562236bSHarry Wentland 9464562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 9474562236bSHarry Wentland link->link_enc, 9484562236bSHarry Wentland pipe_ctx->stream_enc->id, 9494562236bSHarry Wentland false); 9504562236bSHarry Wentland 9514562236bSHarry Wentland } 9524562236bSHarry Wentland 9534562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 9544562236bSHarry Wentland struct dc_link_settings *link_settings) 9554562236bSHarry Wentland { 9564562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 9574562236bSHarry Wentland 9584562236bSHarry Wentland /* only 3 items below are used by unblank */ 9596235b23cSTony Cheng params.pixel_clk_khz = 9604562236bSHarry Wentland pipe_ctx->stream->public.timing.pix_clk_khz; 9614562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 9624562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); 9634562236bSHarry Wentland } 9644562236bSHarry Wentland 9654562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 9664562236bSHarry Wentland { 9674562236bSHarry Wentland switch (crtc_id) { 9684562236bSHarry Wentland case CONTROLLER_ID_D0: 9694562236bSHarry Wentland return DTO_SOURCE_ID0; 9704562236bSHarry Wentland case CONTROLLER_ID_D1: 9714562236bSHarry Wentland return DTO_SOURCE_ID1; 9724562236bSHarry Wentland case CONTROLLER_ID_D2: 9734562236bSHarry Wentland return DTO_SOURCE_ID2; 9744562236bSHarry Wentland case CONTROLLER_ID_D3: 9754562236bSHarry Wentland return DTO_SOURCE_ID3; 9764562236bSHarry Wentland case CONTROLLER_ID_D4: 9774562236bSHarry Wentland return DTO_SOURCE_ID4; 9784562236bSHarry Wentland case CONTROLLER_ID_D5: 9794562236bSHarry Wentland return DTO_SOURCE_ID5; 9804562236bSHarry Wentland default: 9814562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 9824562236bSHarry Wentland } 9834562236bSHarry Wentland } 9844562236bSHarry Wentland 9854562236bSHarry Wentland static void build_audio_output( 9864562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 9874562236bSHarry Wentland struct audio_output *audio_output) 9884562236bSHarry Wentland { 9894562236bSHarry Wentland const struct core_stream *stream = pipe_ctx->stream; 9904562236bSHarry Wentland audio_output->engine_id = pipe_ctx->stream_enc->id; 9914562236bSHarry Wentland 9924562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 9934562236bSHarry Wentland 9944562236bSHarry Wentland /* audio_crtc_info */ 9954562236bSHarry Wentland 9964562236bSHarry Wentland audio_output->crtc_info.h_total = 9974562236bSHarry Wentland stream->public.timing.h_total; 9984562236bSHarry Wentland 9994562236bSHarry Wentland /* 10004562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 10014562236bSHarry Wentland * need to specify actual active signal portion 10024562236bSHarry Wentland */ 10034562236bSHarry Wentland audio_output->crtc_info.h_active = 10044562236bSHarry Wentland stream->public.timing.h_addressable 10054562236bSHarry Wentland + stream->public.timing.h_border_left 10064562236bSHarry Wentland + stream->public.timing.h_border_right; 10074562236bSHarry Wentland 10084562236bSHarry Wentland audio_output->crtc_info.v_active = 10094562236bSHarry Wentland stream->public.timing.v_addressable 10104562236bSHarry Wentland + stream->public.timing.v_border_top 10114562236bSHarry Wentland + stream->public.timing.v_border_bottom; 10124562236bSHarry Wentland 10134562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 10144562236bSHarry Wentland 10154562236bSHarry Wentland audio_output->crtc_info.interlaced = 10164562236bSHarry Wentland stream->public.timing.flags.INTERLACE; 10174562236bSHarry Wentland 10184562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 10194562236bSHarry Wentland (stream->public.timing.pix_clk_khz*1000)/ 10204562236bSHarry Wentland (stream->public.timing.h_total*stream->public.timing.v_total); 10214562236bSHarry Wentland 10224562236bSHarry Wentland audio_output->crtc_info.color_depth = 10234562236bSHarry Wentland stream->public.timing.display_color_depth; 10244562236bSHarry Wentland 10254562236bSHarry Wentland audio_output->crtc_info.requested_pixel_clock = 10264562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 10274562236bSHarry Wentland 10284562236bSHarry Wentland /* 10294562236bSHarry Wentland * TODO - Investigate why calculated pixel clk has to be 10304562236bSHarry Wentland * requested pixel clk 10314562236bSHarry Wentland */ 10324562236bSHarry Wentland audio_output->crtc_info.calculated_pixel_clock = 10334562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 10344562236bSHarry Wentland 10354562236bSHarry Wentland if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 10364562236bSHarry Wentland pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 10374562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 10381a687574SDmytro Laktyushkin pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency( 10394562236bSHarry Wentland pipe_ctx->dis_clk); 10404562236bSHarry Wentland } 10414562236bSHarry Wentland 10424562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 10434562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 10444562236bSHarry Wentland 10454562236bSHarry Wentland audio_output->pll_info.dto_source = 10464562236bSHarry Wentland translate_to_dto_source( 10474562236bSHarry Wentland pipe_ctx->pipe_idx + 1); 10484562236bSHarry Wentland 10494562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 10504562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 10514562236bSHarry Wentland 10524562236bSHarry Wentland audio_output->pll_info.ss_percentage = 10534562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 10544562236bSHarry Wentland } 10554562236bSHarry Wentland 10564562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 10574562236bSHarry Wentland struct tg_color *color) 10584562236bSHarry Wentland { 10594562236bSHarry Wentland uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4; 10604562236bSHarry Wentland 10614562236bSHarry Wentland switch (pipe_ctx->scl_data.format) { 10624562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 10634562236bSHarry Wentland /* set boarder color to red */ 10644562236bSHarry Wentland color->color_r_cr = color_value; 10654562236bSHarry Wentland break; 10664562236bSHarry Wentland 10674562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 10684562236bSHarry Wentland /* set boarder color to blue */ 10694562236bSHarry Wentland color->color_b_cb = color_value; 10704562236bSHarry Wentland break; 10714562236bSHarry Wentland case PIXEL_FORMAT_420BPP12: 10724562236bSHarry Wentland /* set boarder color to green */ 10734562236bSHarry Wentland color->color_g_y = color_value; 10744562236bSHarry Wentland break; 10754562236bSHarry Wentland case PIXEL_FORMAT_FP16: 10764562236bSHarry Wentland /* set boarder color to white */ 10774562236bSHarry Wentland color->color_r_cr = color_value; 10784562236bSHarry Wentland color->color_b_cb = color_value; 10794562236bSHarry Wentland color->color_g_y = color_value; 10804562236bSHarry Wentland break; 10814562236bSHarry Wentland default: 10824562236bSHarry Wentland break; 10834562236bSHarry Wentland } 10844562236bSHarry Wentland } 10854562236bSHarry Wentland 10864562236bSHarry Wentland static void program_scaler(const struct core_dc *dc, 10874562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 10884562236bSHarry Wentland { 10894562236bSHarry Wentland struct tg_color color = {0}; 10904562236bSHarry Wentland 10914562236bSHarry Wentland if (dc->public.debug.surface_visual_confirm) 10924562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 10934562236bSHarry Wentland else 10944562236bSHarry Wentland color_space_to_black_color(dc, 10954562236bSHarry Wentland pipe_ctx->stream->public.output_color_space, 10964562236bSHarry Wentland &color); 10974562236bSHarry Wentland 10984562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( 10994562236bSHarry Wentland pipe_ctx->xfm, 11004562236bSHarry Wentland pipe_ctx->scl_data.lb_params.depth, 11014562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 11024562236bSHarry Wentland 11034562236bSHarry Wentland if (pipe_ctx->tg->funcs->set_overscan_blank_color) 11044562236bSHarry Wentland pipe_ctx->tg->funcs->set_overscan_blank_color( 11054562236bSHarry Wentland pipe_ctx->tg, 11064562236bSHarry Wentland &color); 11074562236bSHarry Wentland 11084562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, 11094562236bSHarry Wentland &pipe_ctx->scl_data); 11104562236bSHarry Wentland } 11114562236bSHarry Wentland 11124b5e7d62SHersen Wu static enum dc_status dce110_prog_pixclk_crtc_otg( 11134562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 11144562236bSHarry Wentland struct validate_context *context, 11154562236bSHarry Wentland struct core_dc *dc) 11164562236bSHarry Wentland { 11174562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 11184562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 11194562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 11204562236bSHarry Wentland struct tg_color black_color = {0}; 11214562236bSHarry Wentland 11224562236bSHarry Wentland if (!pipe_ctx_old->stream) { 11234562236bSHarry Wentland 11244562236bSHarry Wentland /* program blank color */ 11254562236bSHarry Wentland color_space_to_black_color(dc, 11264562236bSHarry Wentland stream->public.output_color_space, &black_color); 11274562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank_color( 11284562236bSHarry Wentland pipe_ctx->tg, 11294562236bSHarry Wentland &black_color); 11304b5e7d62SHersen Wu 11314562236bSHarry Wentland /* 11324562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 11334562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 11344562236bSHarry Wentland */ 11354562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 11364562236bSHarry Wentland 11374562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 11384562236bSHarry Wentland pipe_ctx->clock_source, 11394562236bSHarry Wentland &pipe_ctx->pix_clk_params, 11404562236bSHarry Wentland &pipe_ctx->pll_settings)) { 11414562236bSHarry Wentland BREAK_TO_DEBUGGER(); 11424562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 11434562236bSHarry Wentland } 11444562236bSHarry Wentland 11454562236bSHarry Wentland pipe_ctx->tg->funcs->program_timing( 11464562236bSHarry Wentland pipe_ctx->tg, 11474562236bSHarry Wentland &stream->public.timing, 11484562236bSHarry Wentland true); 11494562236bSHarry Wentland } 11504562236bSHarry Wentland 11514562236bSHarry Wentland if (!pipe_ctx_old->stream) { 11524562236bSHarry Wentland if (false == pipe_ctx->tg->funcs->enable_crtc( 11534562236bSHarry Wentland pipe_ctx->tg)) { 11544562236bSHarry Wentland BREAK_TO_DEBUGGER(); 11554562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 11564562236bSHarry Wentland } 11574562236bSHarry Wentland } 11584562236bSHarry Wentland 11594562236bSHarry Wentland return DC_OK; 11604562236bSHarry Wentland } 11614562236bSHarry Wentland 11624562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 11634562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 11644562236bSHarry Wentland struct validate_context *context, 11654562236bSHarry Wentland struct core_dc *dc) 11664562236bSHarry Wentland { 11674562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 11684562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 11694562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 11704562236bSHarry Wentland 11714562236bSHarry Wentland /* */ 11724562236bSHarry Wentland dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); 11734562236bSHarry Wentland 11744562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_dyn_expansion( 11754562236bSHarry Wentland pipe_ctx->opp, 11764562236bSHarry Wentland COLOR_SPACE_YCBCR601, 11774562236bSHarry Wentland stream->public.timing.display_color_depth, 11784562236bSHarry Wentland pipe_ctx->stream->signal); 11794562236bSHarry Wentland 11804562236bSHarry Wentland pipe_ctx->opp->funcs->opp_program_fmt( 11814562236bSHarry Wentland pipe_ctx->opp, 11824562236bSHarry Wentland &stream->bit_depth_params, 11834562236bSHarry Wentland &stream->clamping); 11844562236bSHarry Wentland 11854562236bSHarry Wentland /* FPGA does not program backend */ 11864562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 11874562236bSHarry Wentland return DC_OK; 11884562236bSHarry Wentland 11894562236bSHarry Wentland /* TODO: move to stream encoder */ 11904562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 11914562236bSHarry Wentland if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { 11924562236bSHarry Wentland BREAK_TO_DEBUGGER(); 11934562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 11944562236bSHarry Wentland } 11954562236bSHarry Wentland 11964562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 11974562236bSHarry Wentland stream->sink->link->link_enc->funcs->setup( 11984562236bSHarry Wentland stream->sink->link->link_enc, 11994562236bSHarry Wentland pipe_ctx->stream->signal); 12004562236bSHarry Wentland 12014562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 12024562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( 12034562236bSHarry Wentland pipe_ctx->stream_enc, 12044562236bSHarry Wentland &stream->public.timing, 12054562236bSHarry Wentland stream->public.output_color_space); 12064562236bSHarry Wentland 12074562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 12084562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( 12094562236bSHarry Wentland pipe_ctx->stream_enc, 12104562236bSHarry Wentland &stream->public.timing, 12114562236bSHarry Wentland stream->phy_pix_clk, 12124562236bSHarry Wentland pipe_ctx->audio != NULL); 12134562236bSHarry Wentland 12144562236bSHarry Wentland if (dc_is_dvi_signal(pipe_ctx->stream->signal)) 12154562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( 12164562236bSHarry Wentland pipe_ctx->stream_enc, 12174562236bSHarry Wentland &stream->public.timing, 12184562236bSHarry Wentland (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? 12194562236bSHarry Wentland true : false); 12204562236bSHarry Wentland 12214562236bSHarry Wentland if (!pipe_ctx_old->stream) { 12224562236bSHarry Wentland core_link_enable_stream(pipe_ctx); 12234562236bSHarry Wentland 12244562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 12254562236bSHarry Wentland dce110_unblank_stream(pipe_ctx, 12264562236bSHarry Wentland &stream->sink->link->public.cur_link_settings); 12274562236bSHarry Wentland } 12284562236bSHarry Wentland 12294562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 12304562236bSHarry Wentland /* program_scaler and allocate_mem_input are not new asic */ 12314562236bSHarry Wentland if (!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data, 12324562236bSHarry Wentland &pipe_ctx->scl_data, 12334562236bSHarry Wentland sizeof(struct scaler_data)) != 0) 12344562236bSHarry Wentland program_scaler(dc, pipe_ctx); 12354562236bSHarry Wentland 12364562236bSHarry Wentland /* mst support - use total stream count */ 12374562236bSHarry Wentland pipe_ctx->mi->funcs->allocate_mem_input( 12384562236bSHarry Wentland pipe_ctx->mi, 12394562236bSHarry Wentland stream->public.timing.h_total, 12404562236bSHarry Wentland stream->public.timing.v_total, 12414562236bSHarry Wentland stream->public.timing.pix_clk_khz, 1242ab2541b6SAric Cyr context->stream_count); 12434562236bSHarry Wentland 12444562236bSHarry Wentland return DC_OK; 12454562236bSHarry Wentland } 12464562236bSHarry Wentland 12474562236bSHarry Wentland /******************************************************************************/ 12484562236bSHarry Wentland 12494562236bSHarry Wentland static void power_down_encoders(struct core_dc *dc) 12504562236bSHarry Wentland { 12514562236bSHarry Wentland int i; 12524562236bSHarry Wentland 12534562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 12544562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 12554562236bSHarry Wentland dc->links[i]->link_enc, SIGNAL_TYPE_NONE); 12564562236bSHarry Wentland } 12574562236bSHarry Wentland } 12584562236bSHarry Wentland 12594562236bSHarry Wentland static void power_down_controllers(struct core_dc *dc) 12604562236bSHarry Wentland { 12614562236bSHarry Wentland int i; 12624562236bSHarry Wentland 12634562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 12644562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 12654562236bSHarry Wentland dc->res_pool->timing_generators[i]); 12664562236bSHarry Wentland } 12674562236bSHarry Wentland } 12684562236bSHarry Wentland 12694562236bSHarry Wentland static void power_down_clock_sources(struct core_dc *dc) 12704562236bSHarry Wentland { 12714562236bSHarry Wentland int i; 12724562236bSHarry Wentland 12734562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 12744562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 12754562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 12764562236bSHarry Wentland 12774562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 12784562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 12794562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 12804562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 12814562236bSHarry Wentland } 12824562236bSHarry Wentland } 12834562236bSHarry Wentland 12844562236bSHarry Wentland static void power_down_all_hw_blocks(struct core_dc *dc) 12854562236bSHarry Wentland { 12864562236bSHarry Wentland power_down_encoders(dc); 12874562236bSHarry Wentland 12884562236bSHarry Wentland power_down_controllers(dc); 12894562236bSHarry Wentland 12904562236bSHarry Wentland power_down_clock_sources(dc); 12914562236bSHarry Wentland } 12924562236bSHarry Wentland 12934562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 12944562236bSHarry Wentland struct core_dc *dc) 12954562236bSHarry Wentland { 12964562236bSHarry Wentland int i; 12974562236bSHarry Wentland struct timing_generator *tg; 12984562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 12994562236bSHarry Wentland 13004562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 13014562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 13024562236bSHarry Wentland 13034562236bSHarry Wentland tg->funcs->disable_vga(tg); 13044562236bSHarry Wentland 13054562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 13064562236bSHarry Wentland * powergating. */ 13074562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 13084562236bSHarry Wentland true); 13094562236bSHarry Wentland 13104562236bSHarry Wentland dc->hwss.power_down_front_end( 13114562236bSHarry Wentland dc, &dc->current_context->res_ctx.pipe_ctx[i]); 13124562236bSHarry Wentland } 13134562236bSHarry Wentland } 13144562236bSHarry Wentland 13154562236bSHarry Wentland /** 13164562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 13174562236bSHarry Wentland * 1. Power down all DC HW blocks 13184562236bSHarry Wentland * 2. Disable VGA engine on all controllers 13194562236bSHarry Wentland * 3. Enable power gating for controller 13204562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 13214562236bSHarry Wentland */ 13224562236bSHarry Wentland void dce110_enable_accelerated_mode(struct core_dc *dc) 13234562236bSHarry Wentland { 13244562236bSHarry Wentland power_down_all_hw_blocks(dc); 13254562236bSHarry Wentland 13264562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 13274562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 13284562236bSHarry Wentland } 13294562236bSHarry Wentland 13304562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 13314562236bSHarry Wentland struct bw_fixed blackout_duration, 13324562236bSHarry Wentland const struct core_stream *stream) 13334562236bSHarry Wentland { 13344562236bSHarry Wentland uint32_t total_dest_line_time_ns; 13354562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 13364562236bSHarry Wentland 13374562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 13384562236bSHarry Wentland 13394562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 13404562236bSHarry Wentland stream->public.timing.h_total / 13414562236bSHarry Wentland stream->public.timing.pix_clk_khz + 13424562236bSHarry Wentland pstate_blackout_duration_ns; 13434562236bSHarry Wentland 13444562236bSHarry Wentland return total_dest_line_time_ns; 13454562236bSHarry Wentland } 13464562236bSHarry Wentland 13474562236bSHarry Wentland /* get the index of the pipe_ctx if there were no gaps in the pipe_ctx array*/ 13484562236bSHarry Wentland int get_bw_result_idx( 13494562236bSHarry Wentland struct resource_context *res_ctx, 13504562236bSHarry Wentland int pipe_idx) 13514562236bSHarry Wentland { 13524562236bSHarry Wentland int i, collapsed_idx; 13534562236bSHarry Wentland 13544562236bSHarry Wentland if (res_ctx->pipe_ctx[pipe_idx].top_pipe) 13554562236bSHarry Wentland return 3; 13564562236bSHarry Wentland 13574562236bSHarry Wentland collapsed_idx = 0; 13584562236bSHarry Wentland for (i = 0; i < pipe_idx; i++) { 13594562236bSHarry Wentland if (res_ctx->pipe_ctx[i].stream) 13604562236bSHarry Wentland collapsed_idx++; 13614562236bSHarry Wentland } 13624562236bSHarry Wentland 13634562236bSHarry Wentland return collapsed_idx; 13644562236bSHarry Wentland } 13654562236bSHarry Wentland 13664562236bSHarry Wentland static bool is_watermark_set_a_greater( 13674562236bSHarry Wentland const struct bw_watermarks *set_a, 13684562236bSHarry Wentland const struct bw_watermarks *set_b) 13694562236bSHarry Wentland { 13704562236bSHarry Wentland if (set_a->a_mark > set_b->a_mark 13714562236bSHarry Wentland || set_a->b_mark > set_b->b_mark 13724562236bSHarry Wentland || set_a->c_mark > set_b->c_mark 13734562236bSHarry Wentland || set_a->d_mark > set_b->d_mark) 13744562236bSHarry Wentland return true; 13754562236bSHarry Wentland return false; 13764562236bSHarry Wentland } 13774562236bSHarry Wentland 13784562236bSHarry Wentland static bool did_watermarks_increase( 13794562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 13804562236bSHarry Wentland struct validate_context *context, 13814562236bSHarry Wentland struct validate_context *old_context) 13824562236bSHarry Wentland { 13834562236bSHarry Wentland int collapsed_pipe_idx = get_bw_result_idx(&context->res_ctx, 13844562236bSHarry Wentland pipe_ctx->pipe_idx); 13854562236bSHarry Wentland int old_collapsed_pipe_idx = get_bw_result_idx(&old_context->res_ctx, 13864562236bSHarry Wentland pipe_ctx->pipe_idx); 13874562236bSHarry Wentland struct pipe_ctx *old_pipe_ctx = &old_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 13884562236bSHarry Wentland 13894562236bSHarry Wentland if (!old_pipe_ctx->stream) 13904562236bSHarry Wentland return true; 13914562236bSHarry Wentland 13924562236bSHarry Wentland if (is_watermark_set_a_greater( 13934562236bSHarry Wentland &context->bw_results.nbp_state_change_wm_ns[collapsed_pipe_idx], 13944562236bSHarry Wentland &old_context->bw_results.nbp_state_change_wm_ns[old_collapsed_pipe_idx])) 13954562236bSHarry Wentland return true; 13964562236bSHarry Wentland if (is_watermark_set_a_greater( 13974562236bSHarry Wentland &context->bw_results.stutter_exit_wm_ns[collapsed_pipe_idx], 13984562236bSHarry Wentland &old_context->bw_results.stutter_exit_wm_ns[old_collapsed_pipe_idx])) 13994562236bSHarry Wentland return true; 14004562236bSHarry Wentland if (is_watermark_set_a_greater( 14014562236bSHarry Wentland &context->bw_results.urgent_wm_ns[collapsed_pipe_idx], 14024562236bSHarry Wentland &old_context->bw_results.urgent_wm_ns[old_collapsed_pipe_idx])) 14034562236bSHarry Wentland return true; 14044562236bSHarry Wentland 14054562236bSHarry Wentland return false; 14064562236bSHarry Wentland } 14074562236bSHarry Wentland 14084562236bSHarry Wentland static void program_wm_for_pipe(struct core_dc *dc, 14094562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 14104562236bSHarry Wentland struct validate_context *context) 14114562236bSHarry Wentland { 14124562236bSHarry Wentland int total_dest_line_time_ns = compute_pstate_blackout_duration( 14134562236bSHarry Wentland dc->bw_vbios.blackout_duration, 14144562236bSHarry Wentland pipe_ctx->stream); 14154562236bSHarry Wentland int bw_result_idx = get_bw_result_idx(&context->res_ctx, 14164562236bSHarry Wentland pipe_ctx->pipe_idx); 14174562236bSHarry Wentland 14184562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_display_marks( 14194562236bSHarry Wentland pipe_ctx->mi, 14204562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[bw_result_idx], 14214562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[bw_result_idx], 14224562236bSHarry Wentland context->bw_results.urgent_wm_ns[bw_result_idx], 14234562236bSHarry Wentland total_dest_line_time_ns); 14244562236bSHarry Wentland 14254562236bSHarry Wentland if (pipe_ctx->top_pipe) 14264562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( 14274562236bSHarry Wentland pipe_ctx->mi, 14284562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[bw_result_idx + 1], 14294562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[bw_result_idx + 1], 14304562236bSHarry Wentland context->bw_results.urgent_wm_ns[bw_result_idx + 1], 14314562236bSHarry Wentland total_dest_line_time_ns); 14324562236bSHarry Wentland } 14334562236bSHarry Wentland 14344562236bSHarry Wentland void dce110_set_displaymarks( 14354562236bSHarry Wentland const struct core_dc *dc, 14364562236bSHarry Wentland struct validate_context *context) 14374562236bSHarry Wentland { 14384562236bSHarry Wentland uint8_t i, num_pipes; 14394562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 14404562236bSHarry Wentland 14414562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 14424562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 14434562236bSHarry Wentland uint32_t total_dest_line_time_ns; 14444562236bSHarry Wentland 14454562236bSHarry Wentland if (pipe_ctx->stream == NULL) 14464562236bSHarry Wentland continue; 14474562236bSHarry Wentland 14484562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 14494562236bSHarry Wentland dc->bw_vbios.blackout_duration, pipe_ctx->stream); 14504562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_display_marks( 14514562236bSHarry Wentland pipe_ctx->mi, 14524562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[num_pipes], 14534562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[num_pipes], 14544562236bSHarry Wentland context->bw_results.urgent_wm_ns[num_pipes], 14554562236bSHarry Wentland total_dest_line_time_ns); 14564562236bSHarry Wentland if (i == underlay_idx) { 14574562236bSHarry Wentland num_pipes++; 14584562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( 14594562236bSHarry Wentland pipe_ctx->mi, 14604562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[num_pipes], 14614562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[num_pipes], 14624562236bSHarry Wentland context->bw_results.urgent_wm_ns[num_pipes], 14634562236bSHarry Wentland total_dest_line_time_ns); 14644562236bSHarry Wentland } 14654562236bSHarry Wentland num_pipes++; 14664562236bSHarry Wentland } 14674562236bSHarry Wentland } 14684562236bSHarry Wentland 14694562236bSHarry Wentland static void set_safe_displaymarks(struct resource_context *res_ctx) 14704562236bSHarry Wentland { 14714562236bSHarry Wentland int i; 14724562236bSHarry Wentland int underlay_idx = res_ctx->pool->underlay_pipe_index; 14734562236bSHarry Wentland struct bw_watermarks max_marks = { 14744562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 14754562236bSHarry Wentland struct bw_watermarks nbp_marks = { 14764562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 14774562236bSHarry Wentland 14784562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 14794562236bSHarry Wentland if (res_ctx->pipe_ctx[i].stream == NULL) 14804562236bSHarry Wentland continue; 14814562236bSHarry Wentland 14824562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks( 14834562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 14844562236bSHarry Wentland nbp_marks, 14854562236bSHarry Wentland max_marks, 14864562236bSHarry Wentland max_marks, 14874562236bSHarry Wentland MAX_WATERMARK); 14884562236bSHarry Wentland if (i == underlay_idx) 14894562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks( 14904562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 14914562236bSHarry Wentland nbp_marks, 14924562236bSHarry Wentland max_marks, 14934562236bSHarry Wentland max_marks, 14944562236bSHarry Wentland MAX_WATERMARK); 14954562236bSHarry Wentland } 14964562236bSHarry Wentland } 14974562236bSHarry Wentland 14984562236bSHarry Wentland static void switch_dp_clock_sources( 14994562236bSHarry Wentland const struct core_dc *dc, 15004562236bSHarry Wentland struct resource_context *res_ctx) 15014562236bSHarry Wentland { 15024562236bSHarry Wentland uint8_t i; 15034562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 15044562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 15054562236bSHarry Wentland 15064562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 15074562236bSHarry Wentland continue; 15084562236bSHarry Wentland 15094562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 15104562236bSHarry Wentland struct clock_source *clk_src = 15114562236bSHarry Wentland resource_find_used_clk_src_for_sharing( 15124562236bSHarry Wentland res_ctx, pipe_ctx); 15134562236bSHarry Wentland 15144562236bSHarry Wentland if (clk_src && 15154562236bSHarry Wentland clk_src != pipe_ctx->clock_source) { 15164562236bSHarry Wentland resource_unreference_clock_source( 15178c737fccSYongqiang Sun res_ctx, &pipe_ctx->clock_source); 15184562236bSHarry Wentland pipe_ctx->clock_source = clk_src; 15194562236bSHarry Wentland resource_reference_clock_source(res_ctx, clk_src); 15204562236bSHarry Wentland 15214562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i); 15224562236bSHarry Wentland } 15234562236bSHarry Wentland } 15244562236bSHarry Wentland } 15254562236bSHarry Wentland } 15264562236bSHarry Wentland 15274562236bSHarry Wentland /******************************************************************************* 15284562236bSHarry Wentland * Public functions 15294562236bSHarry Wentland ******************************************************************************/ 15304562236bSHarry Wentland 15314562236bSHarry Wentland static void reset_single_pipe_hw_ctx( 15324562236bSHarry Wentland const struct core_dc *dc, 15334562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 15344562236bSHarry Wentland struct validate_context *context) 15354562236bSHarry Wentland { 15364562236bSHarry Wentland core_link_disable_stream(pipe_ctx); 15374b5e7d62SHersen Wu pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 15384b5e7d62SHersen Wu if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) { 15394562236bSHarry Wentland dm_error("DC: failed to blank crtc!\n"); 15404562236bSHarry Wentland BREAK_TO_DEBUGGER(); 15414562236bSHarry Wentland } 15424562236bSHarry Wentland pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); 15434562236bSHarry Wentland pipe_ctx->mi->funcs->free_mem_input( 1544ab2541b6SAric Cyr pipe_ctx->mi, context->stream_count); 15454562236bSHarry Wentland resource_unreference_clock_source( 15468c737fccSYongqiang Sun &context->res_ctx, &pipe_ctx->clock_source); 15474562236bSHarry Wentland 15484562236bSHarry Wentland dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx); 15494562236bSHarry Wentland 15504562236bSHarry Wentland pipe_ctx->stream = NULL; 15514562236bSHarry Wentland } 15524562236bSHarry Wentland 15534562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 15544562236bSHarry Wentland int num_pipes, int vmin, int vmax) 15554562236bSHarry Wentland { 15564562236bSHarry Wentland int i = 0; 15574562236bSHarry Wentland struct drr_params params = {0}; 15584562236bSHarry Wentland 15594562236bSHarry Wentland params.vertical_total_max = vmax; 15604562236bSHarry Wentland params.vertical_total_min = vmin; 15614562236bSHarry Wentland 15624562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 15634562236bSHarry Wentland * some GSL stuff 15644562236bSHarry Wentland */ 15654562236bSHarry Wentland 15664562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 15674562236bSHarry Wentland pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, ¶ms); 15684562236bSHarry Wentland } 15694562236bSHarry Wentland } 15704562236bSHarry Wentland 15714562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 15724562236bSHarry Wentland int num_pipes, int value) 15734562236bSHarry Wentland { 15744562236bSHarry Wentland unsigned int i; 15754562236bSHarry Wentland 15764562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 15774562236bSHarry Wentland pipe_ctx[i]->tg->funcs-> 15784562236bSHarry Wentland set_static_screen_control(pipe_ctx[i]->tg, value); 15794562236bSHarry Wentland } 15804562236bSHarry Wentland 15814562236bSHarry Wentland /* unit: in_khz before mode set, get pixel clock from context. ASIC register 15824562236bSHarry Wentland * may not be programmed yet. 15834562236bSHarry Wentland * TODO: after mode set, pre_mode_set = false, 15844562236bSHarry Wentland * may read PLL register to get pixel clock 15854562236bSHarry Wentland */ 15864562236bSHarry Wentland static uint32_t get_max_pixel_clock_for_all_paths( 15874562236bSHarry Wentland struct core_dc *dc, 15884562236bSHarry Wentland struct validate_context *context, 15894562236bSHarry Wentland bool pre_mode_set) 15904562236bSHarry Wentland { 15914562236bSHarry Wentland uint32_t max_pix_clk = 0; 15924562236bSHarry Wentland int i; 15934562236bSHarry Wentland 15944562236bSHarry Wentland if (!pre_mode_set) { 15954562236bSHarry Wentland /* TODO: read ASIC register to get pixel clock */ 15964562236bSHarry Wentland ASSERT(0); 15974562236bSHarry Wentland } 15984562236bSHarry Wentland 15994562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 16004562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 16014562236bSHarry Wentland 16024562236bSHarry Wentland if (pipe_ctx->stream == NULL) 16034562236bSHarry Wentland continue; 16044562236bSHarry Wentland 16054562236bSHarry Wentland /* do not check under lay */ 16064562236bSHarry Wentland if (pipe_ctx->top_pipe) 16074562236bSHarry Wentland continue; 16084562236bSHarry Wentland 16094562236bSHarry Wentland if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk) 16104562236bSHarry Wentland max_pix_clk = 16114562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 16124562236bSHarry Wentland } 16134562236bSHarry Wentland 16144562236bSHarry Wentland if (max_pix_clk == 0) 16154562236bSHarry Wentland ASSERT(0); 16164562236bSHarry Wentland 16174562236bSHarry Wentland return max_pix_clk; 16184562236bSHarry Wentland } 16194562236bSHarry Wentland 16204562236bSHarry Wentland /* 16214562236bSHarry Wentland * Find clock state based on clock requested. if clock value is 0, simply 16224562236bSHarry Wentland * set clock state as requested without finding clock state by clock value 16234562236bSHarry Wentland */ 16244562236bSHarry Wentland static void apply_min_clocks( 16254562236bSHarry Wentland struct core_dc *dc, 16264562236bSHarry Wentland struct validate_context *context, 1627e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state *clocks_state, 16284562236bSHarry Wentland bool pre_mode_set) 16294562236bSHarry Wentland { 16304562236bSHarry Wentland struct state_dependent_clocks req_clocks = {0}; 16314562236bSHarry Wentland struct pipe_ctx *pipe_ctx; 16324562236bSHarry Wentland int i; 16334562236bSHarry Wentland 16344562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 16354562236bSHarry Wentland pipe_ctx = &context->res_ctx.pipe_ctx[i]; 16364562236bSHarry Wentland if (pipe_ctx->dis_clk != NULL) 16374562236bSHarry Wentland break; 16384562236bSHarry Wentland } 16394562236bSHarry Wentland 16404562236bSHarry Wentland if (!pre_mode_set) { 16414562236bSHarry Wentland /* set clock_state without verification */ 16425d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) { 16435d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 16445d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, *clocks_state); 16454562236bSHarry Wentland return; 16465d6d185fSDmytro Laktyushkin } 16474562236bSHarry Wentland 16484562236bSHarry Wentland /* TODOFPGA */ 16494562236bSHarry Wentland } 16504562236bSHarry Wentland 16514562236bSHarry Wentland /* get the required state based on state dependent clocks: 16524562236bSHarry Wentland * display clock and pixel clock 16534562236bSHarry Wentland */ 1654a99240d5SDmytro Laktyushkin req_clocks.display_clk_khz = context->dispclk_khz; 16554562236bSHarry Wentland 16564562236bSHarry Wentland req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( 16574562236bSHarry Wentland dc, context, true); 16584562236bSHarry Wentland 16595d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) { 16605d6d185fSDmytro Laktyushkin *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state( 16615d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, &req_clocks); 16625d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 16634562236bSHarry Wentland pipe_ctx->dis_clk, *clocks_state); 16644562236bSHarry Wentland } else { 16654562236bSHarry Wentland } 16664562236bSHarry Wentland } 16674562236bSHarry Wentland 16684562236bSHarry Wentland static enum dc_status apply_ctx_to_hw_fpga( 16694562236bSHarry Wentland struct core_dc *dc, 16704562236bSHarry Wentland struct validate_context *context) 16714562236bSHarry Wentland { 16724562236bSHarry Wentland enum dc_status status = DC_ERROR_UNEXPECTED; 16734562236bSHarry Wentland int i; 16744562236bSHarry Wentland 16754562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 16764562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 16774562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 16784562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 16794562236bSHarry Wentland 16804562236bSHarry Wentland if (pipe_ctx->stream == NULL) 16814562236bSHarry Wentland continue; 16824562236bSHarry Wentland 16834562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) 16844562236bSHarry Wentland continue; 16854562236bSHarry Wentland 16864562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 16874562236bSHarry Wentland pipe_ctx, 16884562236bSHarry Wentland context, 16894562236bSHarry Wentland dc); 16904562236bSHarry Wentland 16914562236bSHarry Wentland if (status != DC_OK) 16924562236bSHarry Wentland return status; 16934562236bSHarry Wentland } 16944562236bSHarry Wentland 16954562236bSHarry Wentland return DC_OK; 16964562236bSHarry Wentland } 16974562236bSHarry Wentland 16984562236bSHarry Wentland static void reset_hw_ctx_wrap( 16994562236bSHarry Wentland struct core_dc *dc, 17004562236bSHarry Wentland struct validate_context *context) 17014562236bSHarry Wentland { 17024562236bSHarry Wentland int i; 17034562236bSHarry Wentland 17044562236bSHarry Wentland /* Reset old context */ 17054562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 17064562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 17074562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 17084562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 17094562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 17104562236bSHarry Wentland 17114562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 17124562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 17134562236bSHarry Wentland * PHY when not already disabled. 17144562236bSHarry Wentland */ 17154562236bSHarry Wentland 17164562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 17174562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 17184562236bSHarry Wentland continue; 17194562236bSHarry Wentland 17204562236bSHarry Wentland if (!pipe_ctx->stream || 17214562236bSHarry Wentland pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 17224562236bSHarry Wentland reset_single_pipe_hw_ctx( 17234562236bSHarry Wentland dc, pipe_ctx_old, dc->current_context); 17244562236bSHarry Wentland } 17254562236bSHarry Wentland } 17264562236bSHarry Wentland 17274562236bSHarry Wentland /*TODO: const validate_context*/ 17284562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 17294562236bSHarry Wentland struct core_dc *dc, 17304562236bSHarry Wentland struct validate_context *context) 17314562236bSHarry Wentland { 17324562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 17334562236bSHarry Wentland enum dc_status status; 17344562236bSHarry Wentland int i; 17354562236bSHarry Wentland bool programmed_audio_dto = false; 1736e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID; 17374562236bSHarry Wentland 17384562236bSHarry Wentland /* Reset old context */ 17394562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 17404562236bSHarry Wentland dc->hwss.reset_hw_ctx_wrap(dc, context); 17414562236bSHarry Wentland 17424562236bSHarry Wentland /* Skip applying if no targets */ 1743ab2541b6SAric Cyr if (context->stream_count <= 0) 17444562236bSHarry Wentland return DC_OK; 17454562236bSHarry Wentland 17464562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 17474562236bSHarry Wentland apply_ctx_to_hw_fpga(dc, context); 17484562236bSHarry Wentland return DC_OK; 17494562236bSHarry Wentland } 17504562236bSHarry Wentland 17514562236bSHarry Wentland /* Apply new context */ 17524562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 17534562236bSHarry Wentland 17544562236bSHarry Wentland /* below is for real asic only */ 17554562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 17564562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 17574562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 17584562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 17594562236bSHarry Wentland 17604562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 17614562236bSHarry Wentland continue; 17624562236bSHarry Wentland 17634562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 17644562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 17654562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 17664562236bSHarry Wentland pipe_ctx->clock_source, i); 17674562236bSHarry Wentland continue; 17684562236bSHarry Wentland } 17694562236bSHarry Wentland 17704562236bSHarry Wentland dc->hwss.enable_display_power_gating( 17714562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 17724562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 17734562236bSHarry Wentland } 17744562236bSHarry Wentland 17754562236bSHarry Wentland set_safe_displaymarks(&context->res_ctx); 17764562236bSHarry Wentland /*TODO: when pplib works*/ 17774562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, true); 17784562236bSHarry Wentland 1779a99240d5SDmytro Laktyushkin if (context->dispclk_khz 1780a99240d5SDmytro Laktyushkin > dc->current_context->dispclk_khz) 17811a687574SDmytro Laktyushkin context->res_ctx.pool->display_clock->funcs->set_clock( 17821a687574SDmytro Laktyushkin context->res_ctx.pool->display_clock, 1783a99240d5SDmytro Laktyushkin context->dispclk_khz * 115 / 100); 17844562236bSHarry Wentland 17854562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 17864562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 17874562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 17884562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 17894562236bSHarry Wentland 17904562236bSHarry Wentland if (pipe_ctx->stream == NULL) 17914562236bSHarry Wentland continue; 17924562236bSHarry Wentland 17934562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) 17944562236bSHarry Wentland continue; 17954562236bSHarry Wentland 17964562236bSHarry Wentland if (pipe_ctx->top_pipe) 17974562236bSHarry Wentland continue; 17984562236bSHarry Wentland 17994562236bSHarry Wentland if (context->res_ctx.pipe_ctx[i].audio != NULL) { 18004562236bSHarry Wentland /* Setup audio rate clock source */ 18014562236bSHarry Wentland /* Issue: 18024562236bSHarry Wentland * Audio lag happened on DP monitor when unplug a HDMI monitor 18034562236bSHarry Wentland * 18044562236bSHarry Wentland * Cause: 18054562236bSHarry Wentland * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 18064562236bSHarry Wentland * is set to either dto0 or dto1, audio should work fine. 18074562236bSHarry Wentland * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 18084562236bSHarry Wentland * set to dto0 will cause audio lag. 18094562236bSHarry Wentland * 18104562236bSHarry Wentland * Solution: 18114562236bSHarry Wentland * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 18124562236bSHarry Wentland * find first available pipe with audio, setup audio wall DTO per topology 18134562236bSHarry Wentland * instead of per pipe. 18144562236bSHarry Wentland */ 18154562236bSHarry Wentland struct audio_output audio_output; 18164562236bSHarry Wentland 18174562236bSHarry Wentland build_audio_output(pipe_ctx, &audio_output); 18184562236bSHarry Wentland 18194562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 18204562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_setup( 18214562236bSHarry Wentland pipe_ctx->stream_enc, 18224562236bSHarry Wentland pipe_ctx->audio->inst, 18234562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 18244562236bSHarry Wentland else 18254562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_setup( 18264562236bSHarry Wentland pipe_ctx->stream_enc, 18274562236bSHarry Wentland pipe_ctx->audio->inst, 18284562236bSHarry Wentland &pipe_ctx->stream->public.audio_info, 18294562236bSHarry Wentland &audio_output.crtc_info); 18304562236bSHarry Wentland 18314562236bSHarry Wentland pipe_ctx->audio->funcs->az_configure( 18324562236bSHarry Wentland pipe_ctx->audio, 18334562236bSHarry Wentland pipe_ctx->stream->signal, 18344562236bSHarry Wentland &audio_output.crtc_info, 18354562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 18364562236bSHarry Wentland 18374562236bSHarry Wentland if (!programmed_audio_dto) { 18384562236bSHarry Wentland pipe_ctx->audio->funcs->wall_dto_setup( 18394562236bSHarry Wentland pipe_ctx->audio, 18404562236bSHarry Wentland pipe_ctx->stream->signal, 18414562236bSHarry Wentland &audio_output.crtc_info, 18424562236bSHarry Wentland &audio_output.pll_info); 18434562236bSHarry Wentland programmed_audio_dto = true; 18444562236bSHarry Wentland } 18454562236bSHarry Wentland } 18464562236bSHarry Wentland 18474562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 18484562236bSHarry Wentland pipe_ctx, 18494562236bSHarry Wentland context, 18504562236bSHarry Wentland dc); 18514562236bSHarry Wentland 18524562236bSHarry Wentland if (DC_OK != status) 18534562236bSHarry Wentland return status; 18544562236bSHarry Wentland } 18554562236bSHarry Wentland 18564562236bSHarry Wentland dc->hwss.set_displaymarks(dc, context); 18574562236bSHarry Wentland 18584562236bSHarry Wentland /* to save power */ 18594562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, false); 18604562236bSHarry Wentland 18614562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, false); 18624562236bSHarry Wentland 18634562236bSHarry Wentland switch_dp_clock_sources(dc, &context->res_ctx); 18644562236bSHarry Wentland 18654562236bSHarry Wentland return DC_OK; 18664562236bSHarry Wentland } 18674562236bSHarry Wentland 18684562236bSHarry Wentland /******************************************************************************* 18694562236bSHarry Wentland * Front End programming 18704562236bSHarry Wentland ******************************************************************************/ 18714562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 18724562236bSHarry Wentland { 18734562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 18744562236bSHarry Wentland 18754562236bSHarry Wentland default_adjust.force_hw_default = false; 18764562236bSHarry Wentland if (pipe_ctx->surface == NULL) 18774562236bSHarry Wentland default_adjust.in_color_space = COLOR_SPACE_SRGB; 18784562236bSHarry Wentland else 18794562236bSHarry Wentland default_adjust.in_color_space = 18804562236bSHarry Wentland pipe_ctx->surface->public.color_space; 18814562236bSHarry Wentland if (pipe_ctx->stream == NULL) 18824562236bSHarry Wentland default_adjust.out_color_space = COLOR_SPACE_SRGB; 18834562236bSHarry Wentland else 18844562236bSHarry Wentland default_adjust.out_color_space = 18854562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 18864562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 18874562236bSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; 18884562236bSHarry Wentland 18894562236bSHarry Wentland /* display color depth */ 18904562236bSHarry Wentland default_adjust.color_depth = 18914562236bSHarry Wentland pipe_ctx->stream->public.timing.display_color_depth; 18924562236bSHarry Wentland 18934562236bSHarry Wentland /* Lb color depth */ 18944562236bSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; 18954562236bSHarry Wentland 18964562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_default( 18974562236bSHarry Wentland pipe_ctx->opp, &default_adjust); 18984562236bSHarry Wentland } 18994562236bSHarry Wentland 1900b06b7680SLeon Elazar 1901b06b7680SLeon Elazar /******************************************************************************* 1902b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 1903b06b7680SLeon Elazar * Blender + CRTC 1904b06b7680SLeon Elazar * 1905b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 1906b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 1907b06b7680SLeon Elazar * 1908b06b7680SLeon Elazar * |----------------------------------------------- | 1909b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 1910b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 1911b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 1912b06b7680SLeon Elazar * |------------------------------------------------| 1913b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 1914b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 1915b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 1916b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 1917b06b7680SLeon Elazar * -------------------------------------------------| 1918b06b7680SLeon Elazar * 1919b06b7680SLeon Elazar ******************************************************************************/ 1920b06b7680SLeon Elazar static void program_surface_visibility(const struct core_dc *dc, 19214562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 19224562236bSHarry Wentland { 19234562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 1924b06b7680SLeon Elazar bool blank_target = false; 19254562236bSHarry Wentland 19264562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 1927b06b7680SLeon Elazar 1928b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 1929b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 1930b06b7680SLeon Elazar 19314562236bSHarry Wentland if (pipe_ctx->bottom_pipe->surface->public.visible) { 19324562236bSHarry Wentland if (pipe_ctx->surface->public.visible) 19334562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 19344562236bSHarry Wentland else 19354562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 1936b06b7680SLeon Elazar 1937b06b7680SLeon Elazar } else if (!pipe_ctx->surface->public.visible) 1938b06b7680SLeon Elazar blank_target = true; 1939b06b7680SLeon Elazar 1940b06b7680SLeon Elazar } else if (!pipe_ctx->surface->public.visible) 1941b06b7680SLeon Elazar blank_target = true; 1942b06b7680SLeon Elazar 19434562236bSHarry Wentland dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); 1944b06b7680SLeon Elazar pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target); 1945b06b7680SLeon Elazar 19464562236bSHarry Wentland } 19474562236bSHarry Wentland 19484562236bSHarry Wentland /** 19494562236bSHarry Wentland * TODO REMOVE, USE UPDATE INSTEAD 19504562236bSHarry Wentland */ 19514562236bSHarry Wentland static void set_plane_config( 19524562236bSHarry Wentland const struct core_dc *dc, 19534562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 19544562236bSHarry Wentland struct resource_context *res_ctx) 19554562236bSHarry Wentland { 19564562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 19574562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 19584562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 19594562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 19604562236bSHarry Wentland unsigned int i; 19614562236bSHarry Wentland 19624562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 19634562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 19644562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 19654562236bSHarry Wentland 19664562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 19674562236bSHarry Wentland 19684562236bSHarry Wentland set_default_colors(pipe_ctx); 19694562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 19704562236bSHarry Wentland == true) { 19714562236bSHarry Wentland tbl_entry.color_space = 19724562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 19734562236bSHarry Wentland 19744562236bSHarry Wentland for (i = 0; i < 12; i++) 19754562236bSHarry Wentland tbl_entry.regval[i] = 19764562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 19774562236bSHarry Wentland 19784562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 19794562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 19804562236bSHarry Wentland } 19814562236bSHarry Wentland 19824562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 19834562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 19844562236bSHarry Wentland adjust.temperature_matrix[0] = 19854562236bSHarry Wentland pipe_ctx->stream-> 19864562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 19874562236bSHarry Wentland adjust.temperature_matrix[1] = 19884562236bSHarry Wentland pipe_ctx->stream-> 19894562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 19904562236bSHarry Wentland adjust.temperature_matrix[2] = 19914562236bSHarry Wentland pipe_ctx->stream-> 19924562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 19934562236bSHarry Wentland adjust.temperature_matrix[3] = 19944562236bSHarry Wentland pipe_ctx->stream-> 19954562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 19964562236bSHarry Wentland adjust.temperature_matrix[4] = 19974562236bSHarry Wentland pipe_ctx->stream-> 19984562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 19994562236bSHarry Wentland adjust.temperature_matrix[5] = 20004562236bSHarry Wentland pipe_ctx->stream-> 20014562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 20024562236bSHarry Wentland adjust.temperature_matrix[6] = 20034562236bSHarry Wentland pipe_ctx->stream-> 20044562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 20054562236bSHarry Wentland adjust.temperature_matrix[7] = 20064562236bSHarry Wentland pipe_ctx->stream-> 20074562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 20084562236bSHarry Wentland adjust.temperature_matrix[8] = 20094562236bSHarry Wentland pipe_ctx->stream-> 20104562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 20114562236bSHarry Wentland } 20124562236bSHarry Wentland 20134562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 20144562236bSHarry Wentland 20154562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 20164562236bSHarry Wentland program_scaler(dc, pipe_ctx); 20174562236bSHarry Wentland 2018b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 20194562236bSHarry Wentland 20204562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 20214562236bSHarry Wentland mi, 20224562236bSHarry Wentland surface->public.format, 20234562236bSHarry Wentland &surface->public.tiling_info, 20244562236bSHarry Wentland &surface->public.plane_size, 20254562236bSHarry Wentland surface->public.rotation, 20264562236bSHarry Wentland NULL, 2027624d7c47SYongqiang Sun false, 2028624d7c47SYongqiang Sun pipe_ctx->surface->public.visible); 20294562236bSHarry Wentland 20304562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 20314562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 20324562236bSHarry Wentland pipe_ctx->mi, 20334562236bSHarry Wentland surface->public.format, 20344562236bSHarry Wentland &surface->public.tiling_info, 20354562236bSHarry Wentland surface->public.rotation); 20364562236bSHarry Wentland } 20374562236bSHarry Wentland 20384562236bSHarry Wentland static void update_plane_addr(const struct core_dc *dc, 20394562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 20404562236bSHarry Wentland { 20414562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 20424562236bSHarry Wentland 20434562236bSHarry Wentland if (surface == NULL) 20444562236bSHarry Wentland return; 20454562236bSHarry Wentland 20464562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( 20474562236bSHarry Wentland pipe_ctx->mi, 20484562236bSHarry Wentland &surface->public.address, 20494562236bSHarry Wentland surface->public.flip_immediate); 20504562236bSHarry Wentland 20514562236bSHarry Wentland surface->status.requested_address = surface->public.address; 20524562236bSHarry Wentland } 20534562236bSHarry Wentland 20544562236bSHarry Wentland void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 20554562236bSHarry Wentland { 20564562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 20574562236bSHarry Wentland 20584562236bSHarry Wentland if (surface == NULL) 20594562236bSHarry Wentland return; 20604562236bSHarry Wentland 20614562236bSHarry Wentland surface->status.is_flip_pending = 20624562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_is_flip_pending( 20634562236bSHarry Wentland pipe_ctx->mi); 20644562236bSHarry Wentland 20654562236bSHarry Wentland if (surface->status.is_flip_pending && !surface->public.visible) 20664562236bSHarry Wentland pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; 20674562236bSHarry Wentland 20684562236bSHarry Wentland surface->status.current_address = pipe_ctx->mi->current_address; 20694562236bSHarry Wentland } 20704562236bSHarry Wentland 20714562236bSHarry Wentland void dce110_power_down(struct core_dc *dc) 20724562236bSHarry Wentland { 20734562236bSHarry Wentland power_down_all_hw_blocks(dc); 20744562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 20754562236bSHarry Wentland } 20764562236bSHarry Wentland 20774562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 20784562236bSHarry Wentland struct dc_context *dc_ctx, 20794562236bSHarry Wentland struct timing_generator *tg) 20804562236bSHarry Wentland { 20814562236bSHarry Wentland bool rc = false; 20824562236bSHarry Wentland 20834562236bSHarry Wentland /* To avoid endless loop we wait at most 20844562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 20854562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 20864562236bSHarry Wentland uint32_t i; 20874562236bSHarry Wentland 20884562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 20894562236bSHarry Wentland 20904562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 20914562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 20924562236bSHarry Wentland break; 20934562236bSHarry Wentland } 20944562236bSHarry Wentland 20954562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 20964562236bSHarry Wentland rc = true; 20974562236bSHarry Wentland /* usually occurs at i=1 */ 20984562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 20994562236bSHarry Wentland i); 21004562236bSHarry Wentland break; 21014562236bSHarry Wentland } 21024562236bSHarry Wentland 21034562236bSHarry Wentland /* Wait for one frame. */ 21044562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 21054562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 21064562236bSHarry Wentland } 21074562236bSHarry Wentland 21084562236bSHarry Wentland if (false == rc) 21094562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 21104562236bSHarry Wentland 21114562236bSHarry Wentland return rc; 21124562236bSHarry Wentland } 21134562236bSHarry Wentland 21144562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 21154562236bSHarry Wentland static void dce110_enable_timing_synchronization( 21164562236bSHarry Wentland struct core_dc *dc, 21174562236bSHarry Wentland int group_index, 21184562236bSHarry Wentland int group_size, 21194562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 21204562236bSHarry Wentland { 21214562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 21224562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 21234562236bSHarry Wentland int i; 21244562236bSHarry Wentland 21254562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 21264562236bSHarry Wentland 21274562236bSHarry Wentland /* Designate a single TG in the group as a master. 21284562236bSHarry Wentland * Since HW doesn't care which one, we always assign 21294562236bSHarry Wentland * the 1st one in the group. */ 21304562236bSHarry Wentland gsl_params.gsl_group = 0; 21314562236bSHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->tg->inst; 21324562236bSHarry Wentland 21334562236bSHarry Wentland for (i = 0; i < group_size; i++) 21344562236bSHarry Wentland grouped_pipes[i]->tg->funcs->setup_global_swap_lock( 21354562236bSHarry Wentland grouped_pipes[i]->tg, &gsl_params); 21364562236bSHarry Wentland 21374562236bSHarry Wentland /* Reset slave controllers on master VSync */ 21384562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 21394562236bSHarry Wentland 21404562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 21414562236bSHarry Wentland grouped_pipes[i]->tg->funcs->enable_reset_trigger( 21424562236bSHarry Wentland grouped_pipes[i]->tg, gsl_params.gsl_group); 21434562236bSHarry Wentland 21444562236bSHarry Wentland 21454562236bSHarry Wentland 21464562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 21474562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 21484562236bSHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg); 21494562236bSHarry Wentland /* Regardless of success of the wait above, remove the reset or 21504562236bSHarry Wentland * the driver will start timing out on Display requests. */ 21514562236bSHarry Wentland DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); 21524562236bSHarry Wentland grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg); 21534562236bSHarry Wentland } 21544562236bSHarry Wentland 21554562236bSHarry Wentland 21564562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 21574562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 21584562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 21594562236bSHarry Wentland for (i = 0; i < group_size; i++) 21604562236bSHarry Wentland grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg); 21614562236bSHarry Wentland 21624562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 21634562236bSHarry Wentland } 21644562236bSHarry Wentland 21654562236bSHarry Wentland static void init_hw(struct core_dc *dc) 21664562236bSHarry Wentland { 21674562236bSHarry Wentland int i; 21684562236bSHarry Wentland struct dc_bios *bp; 21694562236bSHarry Wentland struct transform *xfm; 21705e7773a2SAnthony Koo struct abm *abm; 21714562236bSHarry Wentland 21724562236bSHarry Wentland bp = dc->ctx->dc_bios; 21734562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 21744562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 21754562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 21764562236bSHarry Wentland 21774562236bSHarry Wentland dc->hwss.enable_display_power_gating( 21784562236bSHarry Wentland dc, i, bp, 21794562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 21804562236bSHarry Wentland dc->hwss.enable_display_power_gating( 21814562236bSHarry Wentland dc, i, bp, 21824562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 21834562236bSHarry Wentland dc->hwss.enable_display_pipe_clock_gating( 21844562236bSHarry Wentland dc->ctx, 21854562236bSHarry Wentland true); 21864562236bSHarry Wentland } 21874562236bSHarry Wentland 21884562236bSHarry Wentland dce_clock_gating_power_up(dc->hwseq, false);; 21894562236bSHarry Wentland /***************************************/ 21904562236bSHarry Wentland 21914562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 21924562236bSHarry Wentland /****************************************/ 21934562236bSHarry Wentland /* Power up AND update implementation according to the 21944562236bSHarry Wentland * required signal (which may be different from the 21954562236bSHarry Wentland * default signal on connector). */ 21964562236bSHarry Wentland struct core_link *link = dc->links[i]; 21974562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 21984562236bSHarry Wentland } 21994562236bSHarry Wentland 22004562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 22014562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 22024562236bSHarry Wentland 22034562236bSHarry Wentland tg->funcs->disable_vga(tg); 22044562236bSHarry Wentland 22054562236bSHarry Wentland /* Blank controller using driver code instead of 22064562236bSHarry Wentland * command table. */ 22074562236bSHarry Wentland tg->funcs->set_blank(tg, true); 22084b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 22094562236bSHarry Wentland } 22104562236bSHarry Wentland 22114562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 22124562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 22134562236bSHarry Wentland audio->funcs->hw_init(audio); 22144562236bSHarry Wentland } 22155e7773a2SAnthony Koo 22165e7773a2SAnthony Koo abm = dc->res_pool->abm; 22176728b30cSAnthony Koo if (abm != NULL) { 22186728b30cSAnthony Koo abm->funcs->init_backlight(abm); 22195e7773a2SAnthony Koo abm->funcs->abm_init(abm); 22204562236bSHarry Wentland } 22216728b30cSAnthony Koo } 22224562236bSHarry Wentland 22234562236bSHarry Wentland /* TODO: move this to apply_ctx_tohw some how?*/ 22244562236bSHarry Wentland static void dce110_power_on_pipe_if_needed( 22254562236bSHarry Wentland struct core_dc *dc, 22264562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 22274562236bSHarry Wentland struct validate_context *context) 22284562236bSHarry Wentland { 22294562236bSHarry Wentland struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 22304562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 22314562236bSHarry Wentland struct tg_color black_color = {0}; 22324562236bSHarry Wentland 22334562236bSHarry Wentland if (!old_pipe_ctx->stream && pipe_ctx->stream) { 22344562236bSHarry Wentland dc->hwss.enable_display_power_gating( 22354562236bSHarry Wentland dc, 22364562236bSHarry Wentland pipe_ctx->pipe_idx, 22374562236bSHarry Wentland dcb, PIPE_GATING_CONTROL_DISABLE); 22384562236bSHarry Wentland 22394562236bSHarry Wentland /* 22404562236bSHarry Wentland * This is for powering on underlay, so crtc does not 22414562236bSHarry Wentland * need to be enabled 22424562236bSHarry Wentland */ 22434562236bSHarry Wentland 22444562236bSHarry Wentland pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, 22454562236bSHarry Wentland &pipe_ctx->stream->public.timing, 22464562236bSHarry Wentland false); 22474562236bSHarry Wentland 22484562236bSHarry Wentland pipe_ctx->tg->funcs->enable_advanced_request( 22494562236bSHarry Wentland pipe_ctx->tg, 22504562236bSHarry Wentland true, 22514562236bSHarry Wentland &pipe_ctx->stream->public.timing); 22524562236bSHarry Wentland 22534562236bSHarry Wentland pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, 22544562236bSHarry Wentland pipe_ctx->stream->public.timing.h_total, 22554562236bSHarry Wentland pipe_ctx->stream->public.timing.v_total, 22564562236bSHarry Wentland pipe_ctx->stream->public.timing.pix_clk_khz, 2257ab2541b6SAric Cyr context->stream_count); 22584562236bSHarry Wentland 22594562236bSHarry Wentland /* TODO unhardcode*/ 22604562236bSHarry Wentland color_space_to_black_color(dc, 22614562236bSHarry Wentland COLOR_SPACE_YCBCR601, &black_color); 22624562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank_color( 22634562236bSHarry Wentland pipe_ctx->tg, 22644562236bSHarry Wentland &black_color); 22654562236bSHarry Wentland } 22664562236bSHarry Wentland } 22674562236bSHarry Wentland 22684562236bSHarry Wentland static void dce110_increase_watermarks_for_pipe( 22694562236bSHarry Wentland struct core_dc *dc, 22704562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 22714562236bSHarry Wentland struct validate_context *context) 22724562236bSHarry Wentland { 22734562236bSHarry Wentland if (did_watermarks_increase(pipe_ctx, context, dc->current_context)) 22744562236bSHarry Wentland program_wm_for_pipe(dc, pipe_ctx, context); 22754562236bSHarry Wentland } 22764562236bSHarry Wentland 22774562236bSHarry Wentland static void dce110_set_bandwidth(struct core_dc *dc) 22784562236bSHarry Wentland { 22794562236bSHarry Wentland int i; 22804562236bSHarry Wentland 22814562236bSHarry Wentland for (i = 0; i < dc->current_context->res_ctx.pool->pipe_count; i++) { 22824562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; 22834562236bSHarry Wentland 22844562236bSHarry Wentland if (!pipe_ctx->stream) 22854562236bSHarry Wentland continue; 22864562236bSHarry Wentland 22874562236bSHarry Wentland program_wm_for_pipe(dc, pipe_ctx, dc->current_context); 22884562236bSHarry Wentland } 22894562236bSHarry Wentland 22901a687574SDmytro Laktyushkin dc->current_context->res_ctx.pool->display_clock->funcs->set_clock( 22911a687574SDmytro Laktyushkin dc->current_context->res_ctx.pool->display_clock, 2292a99240d5SDmytro Laktyushkin dc->current_context->dispclk_khz * 115 / 100); 22934562236bSHarry Wentland } 22944562236bSHarry Wentland 22954562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 22964562236bSHarry Wentland struct core_dc *dc, struct pipe_ctx *pipe_ctx) 22974562236bSHarry Wentland { 22984562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 22994562236bSHarry Wentland struct pipe_ctx *old_pipe = NULL; 23004562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 23014562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 23024562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 23034562236bSHarry Wentland unsigned int i; 23044562236bSHarry Wentland 23054562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 23064562236bSHarry Wentland 23074562236bSHarry Wentland if (dc->current_context) 23084562236bSHarry Wentland old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 23094562236bSHarry Wentland 23104562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 23114562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 23124562236bSHarry Wentland 23134562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 23144562236bSHarry Wentland 23154562236bSHarry Wentland set_default_colors(pipe_ctx); 23164562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 23174562236bSHarry Wentland == true) { 23184562236bSHarry Wentland tbl_entry.color_space = 23194562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 23204562236bSHarry Wentland 23214562236bSHarry Wentland for (i = 0; i < 12; i++) 23224562236bSHarry Wentland tbl_entry.regval[i] = 23234562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 23244562236bSHarry Wentland 23254562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 23264562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 23274562236bSHarry Wentland } 23284562236bSHarry Wentland 23294562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 23304562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 23314562236bSHarry Wentland adjust.temperature_matrix[0] = 23324562236bSHarry Wentland pipe_ctx->stream-> 23334562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 23344562236bSHarry Wentland adjust.temperature_matrix[1] = 23354562236bSHarry Wentland pipe_ctx->stream-> 23364562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 23374562236bSHarry Wentland adjust.temperature_matrix[2] = 23384562236bSHarry Wentland pipe_ctx->stream-> 23394562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 23404562236bSHarry Wentland adjust.temperature_matrix[3] = 23414562236bSHarry Wentland pipe_ctx->stream-> 23424562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 23434562236bSHarry Wentland adjust.temperature_matrix[4] = 23444562236bSHarry Wentland pipe_ctx->stream-> 23454562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 23464562236bSHarry Wentland adjust.temperature_matrix[5] = 23474562236bSHarry Wentland pipe_ctx->stream-> 23484562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 23494562236bSHarry Wentland adjust.temperature_matrix[6] = 23504562236bSHarry Wentland pipe_ctx->stream-> 23514562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 23524562236bSHarry Wentland adjust.temperature_matrix[7] = 23534562236bSHarry Wentland pipe_ctx->stream-> 23544562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 23554562236bSHarry Wentland adjust.temperature_matrix[8] = 23564562236bSHarry Wentland pipe_ctx->stream-> 23574562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 23584562236bSHarry Wentland } 23594562236bSHarry Wentland 23604562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 23614562236bSHarry Wentland 23624562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 23634562236bSHarry Wentland if (old_pipe && memcmp(&old_pipe->scl_data, 23644562236bSHarry Wentland &pipe_ctx->scl_data, 23654562236bSHarry Wentland sizeof(struct scaler_data)) != 0) 23664562236bSHarry Wentland program_scaler(dc, pipe_ctx); 23674562236bSHarry Wentland 23684562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 23694562236bSHarry Wentland mi, 23704562236bSHarry Wentland surface->public.format, 23714562236bSHarry Wentland &surface->public.tiling_info, 23724562236bSHarry Wentland &surface->public.plane_size, 23734562236bSHarry Wentland surface->public.rotation, 2374624d7c47SYongqiang Sun NULL, 23754562236bSHarry Wentland false, 2376624d7c47SYongqiang Sun pipe_ctx->surface->public.visible); 23774562236bSHarry Wentland 23784562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 23794562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 23804562236bSHarry Wentland pipe_ctx->mi, 23814562236bSHarry Wentland surface->public.format, 23824562236bSHarry Wentland &surface->public.tiling_info, 23834562236bSHarry Wentland surface->public.rotation); 23844562236bSHarry Wentland 23854562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 23864562236bSHarry Wentland "Pipe:%d 0x%x: addr hi:0x%x, " 23874562236bSHarry Wentland "addr low:0x%x, " 23884562236bSHarry Wentland "src: %d, %d, %d," 23894562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 23904562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 23914562236bSHarry Wentland pipe_ctx->pipe_idx, 23924562236bSHarry Wentland pipe_ctx->surface, 23934562236bSHarry Wentland pipe_ctx->surface->public.address.grph.addr.high_part, 23944562236bSHarry Wentland pipe_ctx->surface->public.address.grph.addr.low_part, 23954562236bSHarry Wentland pipe_ctx->surface->public.src_rect.x, 23964562236bSHarry Wentland pipe_ctx->surface->public.src_rect.y, 23974562236bSHarry Wentland pipe_ctx->surface->public.src_rect.width, 23984562236bSHarry Wentland pipe_ctx->surface->public.src_rect.height, 23994562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.x, 24004562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.y, 24014562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.width, 24024562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.height, 24034562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.x, 24044562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.y, 24054562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.width, 24064562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.height); 24074562236bSHarry Wentland 24084562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 24094562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 24104562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 24114562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 24124562236bSHarry Wentland pipe_ctx->pipe_idx, 24134562236bSHarry Wentland pipe_ctx->scl_data.viewport.width, 24144562236bSHarry Wentland pipe_ctx->scl_data.viewport.height, 24154562236bSHarry Wentland pipe_ctx->scl_data.viewport.x, 24164562236bSHarry Wentland pipe_ctx->scl_data.viewport.y, 24174562236bSHarry Wentland pipe_ctx->scl_data.recout.width, 24184562236bSHarry Wentland pipe_ctx->scl_data.recout.height, 24194562236bSHarry Wentland pipe_ctx->scl_data.recout.x, 24204562236bSHarry Wentland pipe_ctx->scl_data.recout.y); 24214562236bSHarry Wentland } 24224562236bSHarry Wentland 24234562236bSHarry Wentland static void dce110_prepare_pipe_for_context( 24244562236bSHarry Wentland struct core_dc *dc, 24254562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 24264562236bSHarry Wentland struct validate_context *context) 24274562236bSHarry Wentland { 24284562236bSHarry Wentland dce110_power_on_pipe_if_needed(dc, pipe_ctx, context); 2429fb735a9fSAnthony Koo dc->hwss.increase_watermarks_for_pipe(dc, pipe_ctx, context); 24304562236bSHarry Wentland } 24314562236bSHarry Wentland 24324562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 24334562236bSHarry Wentland struct core_dc *dc, 24344562236bSHarry Wentland struct core_surface *surface, 24354562236bSHarry Wentland struct validate_context *context) 24364562236bSHarry Wentland { 24374562236bSHarry Wentland int i; 24384562236bSHarry Wentland 24394562236bSHarry Wentland /* TODO remove when removing the surface reset workaroud*/ 24404562236bSHarry Wentland if (!surface) 24414562236bSHarry Wentland return; 24424562236bSHarry Wentland 24434562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 24444562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 24454562236bSHarry Wentland 24464562236bSHarry Wentland if (pipe_ctx->surface != surface) 24474562236bSHarry Wentland continue; 24484562236bSHarry Wentland 24494562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 2450b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 24514562236bSHarry Wentland 24524562236bSHarry Wentland } 24534562236bSHarry Wentland } 24544562236bSHarry Wentland 24554562236bSHarry Wentland static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) 24564562236bSHarry Wentland { 24574562236bSHarry Wentland int i; 24584562236bSHarry Wentland 24594562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) 24604562236bSHarry Wentland if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe) 24614562236bSHarry Wentland break; 24624562236bSHarry Wentland 24634562236bSHarry Wentland if (i == dc->res_pool->pipe_count) 24644562236bSHarry Wentland return; 24654562236bSHarry Wentland 24664562236bSHarry Wentland dc->hwss.enable_display_power_gating( 24674562236bSHarry Wentland dc, i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 24684562236bSHarry Wentland if (pipe->xfm) 24694562236bSHarry Wentland pipe->xfm->funcs->transform_reset(pipe->xfm); 24704562236bSHarry Wentland memset(&pipe->scl_data, 0, sizeof(struct scaler_data)); 24714562236bSHarry Wentland } 24724562236bSHarry Wentland 24734562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 24744562236bSHarry Wentland .init_hw = init_hw, 24754562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 24764562236bSHarry Wentland .prepare_pipe_for_context = dce110_prepare_pipe_for_context, 24774562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 24784562236bSHarry Wentland .set_plane_config = set_plane_config, 24794562236bSHarry Wentland .update_plane_addr = update_plane_addr, 24804562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 2481d7194cf6SAric Cyr .set_input_transfer_func = dce110_set_input_transfer_func, 248290e508baSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 24834562236bSHarry Wentland .power_down = dce110_power_down, 24844562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 24854562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 24864562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 24874562236bSHarry Wentland .enable_stream = dce110_enable_stream, 24884562236bSHarry Wentland .disable_stream = dce110_disable_stream, 24894562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 24904562236bSHarry Wentland .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 24914562236bSHarry Wentland .enable_display_power_gating = dce110_enable_display_power_gating, 24924562236bSHarry Wentland .power_down_front_end = dce110_power_down_fe, 24934562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 24944562236bSHarry Wentland .set_displaymarks = dce110_set_displaymarks, 24954562236bSHarry Wentland .increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe, 24964562236bSHarry Wentland .set_bandwidth = dce110_set_bandwidth, 24974562236bSHarry Wentland .set_drr = set_drr, 24984562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 24994562236bSHarry Wentland .reset_hw_ctx_wrap = reset_hw_ctx_wrap, 25004b5e7d62SHersen Wu .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, 25014562236bSHarry Wentland }; 25024562236bSHarry Wentland 25034562236bSHarry Wentland bool dce110_hw_sequencer_construct(struct core_dc *dc) 25044562236bSHarry Wentland { 25054562236bSHarry Wentland dc->hwss = dce110_funcs; 25064562236bSHarry Wentland 25074562236bSHarry Wentland return true; 25084562236bSHarry Wentland } 25094562236bSHarry Wentland 2510