14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 25c366be54SSam Ravnborg 26c366be54SSam Ravnborg #include <linux/delay.h> 27c366be54SSam Ravnborg 284562236bSHarry Wentland #include "dm_services.h" 294562236bSHarry Wentland #include "dc.h" 304562236bSHarry Wentland #include "dc_bios_types.h" 314562236bSHarry Wentland #include "core_types.h" 324562236bSHarry Wentland #include "core_status.h" 334562236bSHarry Wentland #include "resource.h" 344562236bSHarry Wentland #include "dm_helpers.h" 354562236bSHarry Wentland #include "dce110_timing_generator.h" 3698489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 3787401969SAndrew Jiang #include "gpio_service_interface.h" 384562236bSHarry Wentland 391663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 401663ae1cSBhawanpreet Lakha 414562236bSHarry Wentland #include "bios/bios_parser_helper.h" 424562236bSHarry Wentland #include "timing_generator.h" 434562236bSHarry Wentland #include "mem_input.h" 444562236bSHarry Wentland #include "opp.h" 454562236bSHarry Wentland #include "ipp.h" 464562236bSHarry Wentland #include "transform.h" 474562236bSHarry Wentland #include "stream_encoder.h" 484562236bSHarry Wentland #include "link_encoder.h" 4987401969SAndrew Jiang #include "link_hwss.h" 50f9fc6f39SMichael Strauss #include "dc_link_dp.h" 518fe44c08SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 5264b1d0e8SNicholas Kazlauskas #include "dccg.h" 5364b1d0e8SNicholas Kazlauskas #endif 544562236bSHarry Wentland #include "clock_source.h" 55dc88b4a6SEric Yang #include "clk_mgr.h" 565e7773a2SAnthony Koo #include "abm.h" 574562236bSHarry Wentland #include "audio.h" 5808b16886SZeyu Fan #include "reg_helper.h" 59d4caa72eSAnthony Koo #include "panel_cntl.h" 604562236bSHarry Wentland 614562236bSHarry Wentland /* include DCE11 register header files */ 624562236bSHarry Wentland #include "dce/dce_11_0_d.h" 634562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 64e266fdf6SVitaly Prosyak #include "custom_float.h" 654562236bSHarry Wentland 664cac1e6dSYongqiang Sun #include "atomfirmware.h" 674cac1e6dSYongqiang Sun 68a76eb7d3SLee Jones #include "dcn10/dcn10_hw_sequencer.h" 696e4a14ccSLee Jones 7078c77382SAnthony Koo #define GAMMA_HW_POINTS_NUM 256 7178c77382SAnthony Koo 7287401969SAndrew Jiang /* 7387401969SAndrew Jiang * All values are in milliseconds; 7487401969SAndrew Jiang * For eDP, after power-up/power/down, 7587401969SAndrew Jiang * 300/500 msec max. delay from LCDVCC to black video generation 7687401969SAndrew Jiang */ 7787401969SAndrew Jiang #define PANEL_POWER_UP_TIMEOUT 300 7887401969SAndrew Jiang #define PANEL_POWER_DOWN_TIMEOUT 500 7987401969SAndrew Jiang #define HPD_CHECK_INTERVAL 10 8096577cf8SHersen Wu #define OLED_POST_T7_DELAY 100 8196577cf8SHersen Wu #define OLED_PRE_T11_DELAY 150 8287401969SAndrew Jiang 835eefbc40SYue Hin Lau #define CTX \ 845eefbc40SYue Hin Lau hws->ctx 855d4b05ddSBhawanpreet Lakha 865d4b05ddSBhawanpreet Lakha #define DC_LOGGER_INIT() 875d4b05ddSBhawanpreet Lakha 885eefbc40SYue Hin Lau #define REG(reg)\ 895eefbc40SYue Hin Lau hws->regs->reg 905eefbc40SYue Hin Lau 915eefbc40SYue Hin Lau #undef FN 925eefbc40SYue Hin Lau #define FN(reg_name, field_name) \ 935eefbc40SYue Hin Lau hws->shifts->field_name, hws->masks->field_name 945eefbc40SYue Hin Lau 954562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 964562236bSHarry Wentland uint32_t crtc; 974562236bSHarry Wentland }; 984562236bSHarry Wentland 994562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 1004562236bSHarry Wentland { 1014562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1024562236bSHarry Wentland }, 1034562236bSHarry Wentland { 1044562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1054562236bSHarry Wentland }, 1064562236bSHarry Wentland { 1074562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1084562236bSHarry Wentland }, 1094562236bSHarry Wentland { 1104562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1114562236bSHarry Wentland } 1124562236bSHarry Wentland }; 1134562236bSHarry Wentland 1144562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 1154562236bSHarry Wentland (reg + reg_offsets[id].blnd) 1164562236bSHarry Wentland 1174562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 1184562236bSHarry Wentland (reg + reg_offsets[id].crtc) 1194562236bSHarry Wentland 1204562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 1214562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 1224562236bSHarry Wentland 1234562236bSHarry Wentland /******************************************************************************* 1244562236bSHarry Wentland * Private definitions 1254562236bSHarry Wentland ******************************************************************************/ 1264562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 1274562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 1284562236bSHarry Wentland { 1294562236bSHarry Wentland uint32_t addr; 1304562236bSHarry Wentland uint32_t value = 0; 1314562236bSHarry Wentland uint32_t chunk_int = 0; 1324562236bSHarry Wentland uint32_t chunk_mul = 0; 1334562236bSHarry Wentland 1344562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 1354562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1364562236bSHarry Wentland 1374562236bSHarry Wentland set_reg_field_value( 1384562236bSHarry Wentland value, 1394562236bSHarry Wentland 0, 1404562236bSHarry Wentland DVMM_PTE_CONTROL, 1414562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1424562236bSHarry Wentland 1434562236bSHarry Wentland set_reg_field_value( 1444562236bSHarry Wentland value, 1454562236bSHarry Wentland 1, 1464562236bSHarry Wentland DVMM_PTE_CONTROL, 1474562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1484562236bSHarry Wentland 1494562236bSHarry Wentland set_reg_field_value( 1504562236bSHarry Wentland value, 1514562236bSHarry Wentland 1, 1524562236bSHarry Wentland DVMM_PTE_CONTROL, 1534562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1544562236bSHarry Wentland 1554562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1564562236bSHarry Wentland 1574562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1584562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1594562236bSHarry Wentland 1604562236bSHarry Wentland chunk_int = get_reg_field_value( 1614562236bSHarry Wentland value, 1624562236bSHarry Wentland DVMM_PTE_REQ, 1634562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1644562236bSHarry Wentland 1654562236bSHarry Wentland chunk_mul = get_reg_field_value( 1664562236bSHarry Wentland value, 1674562236bSHarry Wentland DVMM_PTE_REQ, 1684562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1694562236bSHarry Wentland 1704562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1714562236bSHarry Wentland 1724562236bSHarry Wentland set_reg_field_value( 1734562236bSHarry Wentland value, 1744562236bSHarry Wentland 255, 1754562236bSHarry Wentland DVMM_PTE_REQ, 1764562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1774562236bSHarry Wentland 1784562236bSHarry Wentland set_reg_field_value( 1794562236bSHarry Wentland value, 1804562236bSHarry Wentland 4, 1814562236bSHarry Wentland DVMM_PTE_REQ, 1824562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1834562236bSHarry Wentland 1844562236bSHarry Wentland set_reg_field_value( 1854562236bSHarry Wentland value, 1864562236bSHarry Wentland 4, 1874562236bSHarry Wentland DVMM_PTE_REQ, 1884562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1894562236bSHarry Wentland 1904562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1914562236bSHarry Wentland } 1924562236bSHarry Wentland } 1934562236bSHarry Wentland /**************************************************************************/ 1944562236bSHarry Wentland 1954562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1964562236bSHarry Wentland struct dc_context *ctx, 1974562236bSHarry Wentland bool clock_gating) 1984562236bSHarry Wentland { 1994562236bSHarry Wentland /*TODO*/ 2004562236bSHarry Wentland } 2014562236bSHarry Wentland 2024562236bSHarry Wentland static bool dce110_enable_display_power_gating( 203fb3466a4SBhawanpreet Lakha struct dc *dc, 2044562236bSHarry Wentland uint8_t controller_id, 2054562236bSHarry Wentland struct dc_bios *dcb, 2064562236bSHarry Wentland enum pipe_gating_control power_gating) 2074562236bSHarry Wentland { 2084562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 2094562236bSHarry Wentland enum bp_pipe_control_action cntl; 2104562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 2114562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 2124562236bSHarry Wentland 2134562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 2144562236bSHarry Wentland return true; 2154562236bSHarry Wentland 2164562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 2174562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 2184562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 2194562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 2204562236bSHarry Wentland else 2214562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 2224562236bSHarry Wentland 2234562236bSHarry Wentland if (controller_id == underlay_idx) 2244562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 2254562236bSHarry Wentland 2264562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 2274562236bSHarry Wentland 2284562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 2294562236bSHarry Wentland dcb, controller_id + 1, cntl); 2304562236bSHarry Wentland 2314562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 2324562236bSHarry Wentland * by default when command table is called 2334562236bSHarry Wentland * 2344562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 2354562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2364562236bSHarry Wentland * than 3. 2374562236bSHarry Wentland */ 2384562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2394562236bSHarry Wentland dm_write_reg(ctx, 2404562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2414562236bSHarry Wentland 0); 2424562236bSHarry Wentland } 2434562236bSHarry Wentland 2444562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2454562236bSHarry Wentland dce110_init_pte(ctx); 2464562236bSHarry Wentland 2474562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2484562236bSHarry Wentland return true; 2494562236bSHarry Wentland else 2504562236bSHarry Wentland return false; 2514562236bSHarry Wentland } 2524562236bSHarry Wentland 2534562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2543be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2554562236bSHarry Wentland { 2564562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2574562236bSHarry Wentland 2583be5262eSHarry Wentland switch (plane_state->format) { 2591352c779SNicholas Kazlauskas case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2601352c779SNicholas Kazlauskas prescale_params->scale = 0x2082; 2611352c779SNicholas Kazlauskas break; 2624562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2638693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2644562236bSHarry Wentland prescale_params->scale = 0x2020; 2654562236bSHarry Wentland break; 2664562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2674562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2684562236bSHarry Wentland prescale_params->scale = 0x2008; 2694562236bSHarry Wentland break; 2704562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 271050cd3d6SMario Kleiner case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 2724562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2734562236bSHarry Wentland prescale_params->scale = 0x2000; 2744562236bSHarry Wentland break; 2754562236bSHarry Wentland default: 2764562236bSHarry Wentland ASSERT(false); 277d7194cf6SAric Cyr break; 2784562236bSHarry Wentland } 2794562236bSHarry Wentland } 2804562236bSHarry Wentland 281a6114e85SHarry Wentland static bool 28278c77382SAnthony Koo dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 2833be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2844562236bSHarry Wentland { 28586a66c4eSHarry Wentland struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2867b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 28790e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 28890e508baSAnthony Koo bool result = true; 28990e508baSAnthony Koo 29090e508baSAnthony Koo if (ipp == NULL) 29190e508baSAnthony Koo return false; 29290e508baSAnthony Koo 2933be5262eSHarry Wentland if (plane_state->in_transfer_func) 2943be5262eSHarry Wentland tf = plane_state->in_transfer_func; 29590e508baSAnthony Koo 2963be5262eSHarry Wentland build_prescale_params(&prescale_params, plane_state); 29790e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 29890e508baSAnthony Koo 29984ffa801SLeo (Sunpeng) Li if (plane_state->gamma_correction && 30084ffa801SLeo (Sunpeng) Li !plane_state->gamma_correction->is_identity && 30184ffa801SLeo (Sunpeng) Li dce_use_lut(plane_state->format)) 3023be5262eSHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 303d7194cf6SAric Cyr 30490e508baSAnthony Koo if (tf == NULL) { 30590e508baSAnthony Koo /* Default case if no input transfer function specified */ 306a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 3077b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 3087b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 30990e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 310a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 31190e508baSAnthony Koo break; 31290e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 313a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 31490e508baSAnthony Koo break; 31590e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 316a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 31790e508baSAnthony Koo break; 31890e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 31990e508baSAnthony Koo default: 32090e508baSAnthony Koo result = false; 321d7194cf6SAric Cyr break; 32290e508baSAnthony Koo } 3237b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 32470063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 32590e508baSAnthony Koo } else { 32690e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 32790e508baSAnthony Koo result = false; 32890e508baSAnthony Koo } 32990e508baSAnthony Koo 33090e508baSAnthony Koo return result; 33190e508baSAnthony Koo } 33290e508baSAnthony Koo 333bd1be8e8SHarry Wentland static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 334fcd2f4bfSAmy Zhang struct curve_points *arr_points, 335fcd2f4bfSAmy Zhang uint32_t hw_points_num) 336fcd2f4bfSAmy Zhang { 337fcd2f4bfSAmy Zhang struct custom_float_format fmt; 338fcd2f4bfSAmy Zhang 339fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 340fcd2f4bfSAmy Zhang 341fcd2f4bfSAmy Zhang uint32_t i = 0; 342fcd2f4bfSAmy Zhang 343fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 344fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 345fcd2f4bfSAmy Zhang fmt.sign = true; 346fcd2f4bfSAmy Zhang 347bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 348fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 349fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 350fcd2f4bfSAmy Zhang return false; 351fcd2f4bfSAmy Zhang } 352fcd2f4bfSAmy Zhang 353bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 354fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 355fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 356fcd2f4bfSAmy Zhang return false; 357fcd2f4bfSAmy Zhang } 358fcd2f4bfSAmy Zhang 359bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 360fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 361fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 362fcd2f4bfSAmy Zhang return false; 363fcd2f4bfSAmy Zhang } 364fcd2f4bfSAmy Zhang 365fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 366fcd2f4bfSAmy Zhang fmt.sign = false; 367fcd2f4bfSAmy Zhang 368bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 369fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 370fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 371fcd2f4bfSAmy Zhang return false; 372fcd2f4bfSAmy Zhang } 373fcd2f4bfSAmy Zhang 374bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 375fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 376fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 377fcd2f4bfSAmy Zhang return false; 378fcd2f4bfSAmy Zhang } 379fcd2f4bfSAmy Zhang 3804d06ccd0SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 3814d06ccd0SHarry Wentland &arr_points[1].custom_float_slope)) { 382fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 383fcd2f4bfSAmy Zhang return false; 384fcd2f4bfSAmy Zhang } 385fcd2f4bfSAmy Zhang 386fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 387fcd2f4bfSAmy Zhang fmt.sign = true; 388fcd2f4bfSAmy Zhang 389fcd2f4bfSAmy Zhang while (i != hw_points_num) { 390bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->red, &fmt, 391fcd2f4bfSAmy Zhang &rgb->red_reg)) { 392fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 393fcd2f4bfSAmy Zhang return false; 394fcd2f4bfSAmy Zhang } 395fcd2f4bfSAmy Zhang 396bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->green, &fmt, 397fcd2f4bfSAmy Zhang &rgb->green_reg)) { 398fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 399fcd2f4bfSAmy Zhang return false; 400fcd2f4bfSAmy Zhang } 401fcd2f4bfSAmy Zhang 402bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->blue, &fmt, 403fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 404fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 405fcd2f4bfSAmy Zhang return false; 406fcd2f4bfSAmy Zhang } 407fcd2f4bfSAmy Zhang 408bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 409fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 410fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 411fcd2f4bfSAmy Zhang return false; 412fcd2f4bfSAmy Zhang } 413fcd2f4bfSAmy Zhang 414bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 415fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 416fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 417fcd2f4bfSAmy Zhang return false; 418fcd2f4bfSAmy Zhang } 419fcd2f4bfSAmy Zhang 420bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 421fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 422fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 423fcd2f4bfSAmy Zhang return false; 424fcd2f4bfSAmy Zhang } 425fcd2f4bfSAmy Zhang 426fcd2f4bfSAmy Zhang ++rgb; 427fcd2f4bfSAmy Zhang ++i; 428fcd2f4bfSAmy Zhang } 429fcd2f4bfSAmy Zhang 430fcd2f4bfSAmy Zhang return true; 431fcd2f4bfSAmy Zhang } 432fcd2f4bfSAmy Zhang 43308616da5SLeo (Sunpeng) Li #define MAX_LOW_POINT 25 4348f8372c7SKrunoslav Kovac #define NUMBER_REGIONS 16 4358f8372c7SKrunoslav Kovac #define NUMBER_SW_SEGMENTS 16 4368f8372c7SKrunoslav Kovac 437b310b081SHarry Wentland static bool 438b310b081SHarry Wentland dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 439b310b081SHarry Wentland struct pwl_params *regamma_params) 440fcd2f4bfSAmy Zhang { 44123ae4f8eSAmy Zhang struct curve_points *arr_points; 44223ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 44323ae4f8eSAmy Zhang struct pwl_result_data *rgb; 44423ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 445fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 446fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 447fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 448fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 449fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 450fcd2f4bfSAmy Zhang 4518f8372c7SKrunoslav Kovac int32_t region_start, region_end; 4528f8372c7SKrunoslav Kovac uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 45323ae4f8eSAmy Zhang 454b310b081SHarry Wentland if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 45523ae4f8eSAmy Zhang return false; 45623ae4f8eSAmy Zhang 45723ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 45823ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 45923ae4f8eSAmy Zhang hw_points = 0; 460fcd2f4bfSAmy Zhang 461fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 462fcd2f4bfSAmy Zhang 463fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 464534db198SAmy Zhang /* 16 segments 465fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 466fcd2f4bfSAmy Zhang */ 46708616da5SLeo (Sunpeng) Li region_start = -11; 46808616da5SLeo (Sunpeng) Li region_end = region_start + NUMBER_REGIONS; 469fcd2f4bfSAmy Zhang 4708f8372c7SKrunoslav Kovac for (i = 0; i < NUMBER_REGIONS; i++) 4718f8372c7SKrunoslav Kovac seg_distr[i] = 4; 472534db198SAmy Zhang 473fcd2f4bfSAmy Zhang } else { 474534db198SAmy Zhang /* 10 segments 475fc6de1c5SLeo (Sunpeng) Li * segment is from 2^-10 to 2^1 476fc6de1c5SLeo (Sunpeng) Li * We include an extra segment for range [2^0, 2^1). This is to 477fc6de1c5SLeo (Sunpeng) Li * ensure that colors with normalized values of 1 don't miss the 478fc6de1c5SLeo (Sunpeng) Li * LUT. 479fcd2f4bfSAmy Zhang */ 4808f8372c7SKrunoslav Kovac region_start = -10; 481fc6de1c5SLeo (Sunpeng) Li region_end = 1; 482534db198SAmy Zhang 4838f8372c7SKrunoslav Kovac seg_distr[0] = 4; 484534db198SAmy Zhang seg_distr[1] = 4; 485534db198SAmy Zhang seg_distr[2] = 4; 486534db198SAmy Zhang seg_distr[3] = 4; 487534db198SAmy Zhang seg_distr[4] = 4; 488534db198SAmy Zhang seg_distr[5] = 4; 489534db198SAmy Zhang seg_distr[6] = 4; 490534db198SAmy Zhang seg_distr[7] = 4; 4918f8372c7SKrunoslav Kovac seg_distr[8] = 4; 4928f8372c7SKrunoslav Kovac seg_distr[9] = 4; 493fc6de1c5SLeo (Sunpeng) Li seg_distr[10] = 0; 494534db198SAmy Zhang seg_distr[11] = -1; 495534db198SAmy Zhang seg_distr[12] = -1; 496534db198SAmy Zhang seg_distr[13] = -1; 497534db198SAmy Zhang seg_distr[14] = -1; 498534db198SAmy Zhang seg_distr[15] = -1; 499fcd2f4bfSAmy Zhang } 500fcd2f4bfSAmy Zhang 501534db198SAmy Zhang for (k = 0; k < 16; k++) { 502534db198SAmy Zhang if (seg_distr[k] != -1) 503534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 504534db198SAmy Zhang } 505534db198SAmy Zhang 506fcd2f4bfSAmy Zhang j = 0; 5078f8372c7SKrunoslav Kovac for (k = 0; k < (region_end - region_start); k++) { 508ec47734aSLeo (Sunpeng) Li increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 5098f8372c7SKrunoslav Kovac start_index = (region_start + k + MAX_LOW_POINT) * 5108f8372c7SKrunoslav Kovac NUMBER_SW_SEGMENTS; 5118f8372c7SKrunoslav Kovac for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 5128f8372c7SKrunoslav Kovac i += increment) { 513534db198SAmy Zhang if (j == hw_points - 1) 514fcd2f4bfSAmy Zhang break; 515fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 516fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 517fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 518fcd2f4bfSAmy Zhang j++; 519fcd2f4bfSAmy Zhang } 520534db198SAmy Zhang } 521534db198SAmy Zhang 522534db198SAmy Zhang /* last point */ 5238f8372c7SKrunoslav Kovac start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 524b310b081SHarry Wentland rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 525b310b081SHarry Wentland rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 526b310b081SHarry Wentland rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 527fcd2f4bfSAmy Zhang 528eb0e5154SDmytro Laktyushkin arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 529eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_start)); 530eb0e5154SDmytro Laktyushkin arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 531eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_end)); 532fcd2f4bfSAmy Zhang 533fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 534fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 535fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 536fcd2f4bfSAmy Zhang 537eb0e5154SDmytro Laktyushkin y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 538fcd2f4bfSAmy Zhang 539fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 540eb0e5154SDmytro Laktyushkin arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 541fcd2f4bfSAmy Zhang arr_points[0].x); 542fcd2f4bfSAmy Zhang 543fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 544fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 545fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 546fcd2f4bfSAmy Zhang 547fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 548fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 549fcd2f4bfSAmy Zhang */ 550eb0e5154SDmytro Laktyushkin y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 551fcd2f4bfSAmy Zhang 552fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 553fcd2f4bfSAmy Zhang 554eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_zero; 555fcd2f4bfSAmy Zhang 556fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 557fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 558fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 559fcd2f4bfSAmy Zhang */ 560eb0e5154SDmytro Laktyushkin const struct fixed31_32 end_value = dc_fixpt_from_int(125); 561fcd2f4bfSAmy Zhang 562eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_div( 563eb0e5154SDmytro Laktyushkin dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 564eb0e5154SDmytro Laktyushkin dc_fixpt_sub(end_value, arr_points[1].x)); 565fcd2f4bfSAmy Zhang } 566fcd2f4bfSAmy Zhang 567fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 568fcd2f4bfSAmy Zhang 56969133b89SAric Cyr k = 0; 57069133b89SAric Cyr for (i = 1; i < 16; i++) { 571534db198SAmy Zhang if (seg_distr[k] != -1) { 572b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 573534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 574b310b081SHarry Wentland regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 575fcd2f4bfSAmy Zhang } 57669133b89SAric Cyr k++; 577534db198SAmy Zhang } 578534db198SAmy Zhang 579534db198SAmy Zhang if (seg_distr[k] != -1) 580b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 581fcd2f4bfSAmy Zhang 58223ae4f8eSAmy Zhang rgb = rgb_resulted; 58323ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 584fcd2f4bfSAmy Zhang 585fcd2f4bfSAmy Zhang i = 1; 586fcd2f4bfSAmy Zhang 587fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 588eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 589fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 590eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 591fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 592eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 593fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 594fcd2f4bfSAmy Zhang 595eb0e5154SDmytro Laktyushkin rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 596eb0e5154SDmytro Laktyushkin rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 597eb0e5154SDmytro Laktyushkin rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 598fcd2f4bfSAmy Zhang 599fcd2f4bfSAmy Zhang ++rgb_plus_1; 600fcd2f4bfSAmy Zhang ++rgb; 601fcd2f4bfSAmy Zhang ++i; 602fcd2f4bfSAmy Zhang } 603fcd2f4bfSAmy Zhang 604fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 605fcd2f4bfSAmy Zhang 606fcd2f4bfSAmy Zhang return true; 607fcd2f4bfSAmy Zhang } 608fcd2f4bfSAmy Zhang 609a6114e85SHarry Wentland static bool 61078c77382SAnthony Koo dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 6110971c40eSHarry Wentland const struct dc_stream_state *stream) 61290e508baSAnthony Koo { 61386a66c4eSHarry Wentland struct transform *xfm = pipe_ctx->plane_res.xfm; 6144562236bSHarry Wentland 6157a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, true); 6167a09f5beSYue Hin Lau xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 6174562236bSHarry Wentland 6184fa086b9SLeo (Sunpeng) Li if (stream->out_transfer_func && 619efd52204SHarry Wentland stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 620efd52204SHarry Wentland stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 6217a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 622efd52204SHarry Wentland } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 623efd52204SHarry Wentland &xfm->regamma_params)) { 6247a09f5beSYue Hin Lau xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 6257a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 6264562236bSHarry Wentland } else { 6277a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 6284562236bSHarry Wentland } 6294562236bSHarry Wentland 6307a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, false); 6314562236bSHarry Wentland 632cc0cb445SLeon Elazar return true; 6334562236bSHarry Wentland } 6344562236bSHarry Wentland 6354562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6364562236bSHarry Wentland { 63702553f57SEric Bernstein bool is_hdmi_tmds; 6386f0db2dcSKrunoslav Kovac bool is_dp; 6396f0db2dcSKrunoslav Kovac 64086e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 64186e2e1beSHersen Wu 6428e9c4c8cSHarry Wentland if (pipe_ctx->stream_res.stream_enc == NULL) 64386e2e1beSHersen Wu return; /* this is not root pipe */ 64486e2e1beSHersen Wu 64502553f57SEric Bernstein is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 6466f0db2dcSKrunoslav Kovac is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 6476f0db2dcSKrunoslav Kovac 64802553f57SEric Bernstein if (!is_hdmi_tmds && !is_dp) 6496f0db2dcSKrunoslav Kovac return; 6506f0db2dcSKrunoslav Kovac 65102553f57SEric Bernstein if (is_hdmi_tmds) 6528e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 6538e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 65496c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6556f0db2dcSKrunoslav Kovac else 6568e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 6578e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 65896c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6594562236bSHarry Wentland } 6604562236bSHarry Wentland 6614562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6624562236bSHarry Wentland { 6634562236bSHarry Wentland enum dc_lane_count lane_count = 664ceb3dbb4SJun Lei pipe_ctx->stream->link->cur_link_settings.lane_count; 6654fa086b9SLeo (Sunpeng) Li struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 666ceb3dbb4SJun Lei struct dc_link *link = pipe_ctx->stream->link; 667f42ea55bSAnthony Koo const struct dc *dc = link->dc; 668f215a57dSEric Yang 6694562236bSHarry Wentland uint32_t active_total_with_borders; 6704562236bSHarry Wentland uint32_t early_control = 0; 6716b670fa9SHarry Wentland struct timing_generator *tg = pipe_ctx->stream_res.tg; 6724562236bSHarry Wentland 673f215a57dSEric Yang /* For MST, there are multiply stream go to only one link. 674f215a57dSEric Yang * connect DIG back_end to front_end while enable_stream and 675f215a57dSEric Yang * disconnect them during disable_stream 676f215a57dSEric Yang * BY this, it is logic clean to separate stream and link */ 677f215a57dSEric Yang link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 678f215a57dSEric Yang pipe_ctx->stream_res.stream_enc->id, true); 679f215a57dSEric Yang 680f42ea55bSAnthony Koo dc->hwss.update_info_frame(pipe_ctx); 681f215a57dSEric Yang 6824562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 6834562236bSHarry Wentland active_total_with_borders = 6844562236bSHarry Wentland timing->h_addressable 6854562236bSHarry Wentland + timing->h_border_left 6864562236bSHarry Wentland + timing->h_border_right; 6874562236bSHarry Wentland 6884562236bSHarry Wentland if (lane_count != 0) 6894562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 6904562236bSHarry Wentland 6914562236bSHarry Wentland if (early_control == 0) 6924562236bSHarry Wentland early_control = lane_count; 6934562236bSHarry Wentland 6944562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 6954562236bSHarry Wentland 6964562236bSHarry Wentland /* enable audio only within mode set */ 697afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 6984562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6998e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 7004562236bSHarry Wentland } 7014562236bSHarry Wentland 702f215a57dSEric Yang 703f215a57dSEric Yang 7044562236bSHarry Wentland 7054562236bSHarry Wentland } 7064562236bSHarry Wentland 7075eefbc40SYue Hin Lau static enum bp_result link_transmitter_control( 70887401969SAndrew Jiang struct dc_bios *bios, 7095eefbc40SYue Hin Lau struct bp_transmitter_control *cntl) 7105eefbc40SYue Hin Lau { 7115eefbc40SYue Hin Lau enum bp_result result; 7125eefbc40SYue Hin Lau 71387401969SAndrew Jiang result = bios->funcs->transmitter_control(bios, cntl); 7145eefbc40SYue Hin Lau 7155eefbc40SYue Hin Lau return result; 7165eefbc40SYue Hin Lau } 7175eefbc40SYue Hin Lau 71887401969SAndrew Jiang /* 71987401969SAndrew Jiang * @brief 72087401969SAndrew Jiang * eDP only. 72187401969SAndrew Jiang */ 7228a31820bSMartin Leung void dce110_edp_wait_for_hpd_ready( 723069d418fSAndrew Jiang struct dc_link *link, 72487401969SAndrew Jiang bool power_up) 72587401969SAndrew Jiang { 726069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 727069d418fSAndrew Jiang struct graphics_object_id connector = link->link_enc->connector; 72887401969SAndrew Jiang struct gpio *hpd; 7296798d042SLewis Huang struct dc_sink *sink = link->local_sink; 73087401969SAndrew Jiang bool edp_hpd_high = false; 73187401969SAndrew Jiang uint32_t time_elapsed = 0; 73287401969SAndrew Jiang uint32_t timeout = power_up ? 73387401969SAndrew Jiang PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 73487401969SAndrew Jiang 73587401969SAndrew Jiang if (dal_graphics_object_id_get_connector_id(connector) 73687401969SAndrew Jiang != CONNECTOR_ID_EDP) { 73787401969SAndrew Jiang BREAK_TO_DEBUGGER(); 73887401969SAndrew Jiang return; 73987401969SAndrew Jiang } 74087401969SAndrew Jiang 74187401969SAndrew Jiang if (!power_up) 74287401969SAndrew Jiang /* 74387401969SAndrew Jiang * From KV, we will not HPD low after turning off VCC - 74487401969SAndrew Jiang * instead, we will check the SW timer in power_up(). 74587401969SAndrew Jiang */ 74687401969SAndrew Jiang return; 74787401969SAndrew Jiang 74887401969SAndrew Jiang /* 74987401969SAndrew Jiang * When we power on/off the eDP panel, 75087401969SAndrew Jiang * we need to wait until SENSE bit is high/low. 75187401969SAndrew Jiang */ 75287401969SAndrew Jiang 75387401969SAndrew Jiang /* obtain HPD */ 75487401969SAndrew Jiang /* TODO what to do with this? */ 75587401969SAndrew Jiang hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 75687401969SAndrew Jiang 75787401969SAndrew Jiang if (!hpd) { 75887401969SAndrew Jiang BREAK_TO_DEBUGGER(); 75987401969SAndrew Jiang return; 76087401969SAndrew Jiang } 76187401969SAndrew Jiang 7626798d042SLewis Huang if (sink != NULL) { 7636798d042SLewis Huang if (sink->edid_caps.panel_patch.extra_t3_ms > 0) { 7646798d042SLewis Huang int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms; 7656798d042SLewis Huang 7666798d042SLewis Huang msleep(extra_t3_in_ms); 7676798d042SLewis Huang } 7686798d042SLewis Huang } 7696798d042SLewis Huang 77087401969SAndrew Jiang dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 77187401969SAndrew Jiang 77287401969SAndrew Jiang /* wait until timeout or panel detected */ 77387401969SAndrew Jiang 77487401969SAndrew Jiang do { 77587401969SAndrew Jiang uint32_t detected = 0; 77687401969SAndrew Jiang 77787401969SAndrew Jiang dal_gpio_get_value(hpd, &detected); 77887401969SAndrew Jiang 77987401969SAndrew Jiang if (!(detected ^ power_up)) { 78087401969SAndrew Jiang edp_hpd_high = true; 78187401969SAndrew Jiang break; 78287401969SAndrew Jiang } 78387401969SAndrew Jiang 78487401969SAndrew Jiang msleep(HPD_CHECK_INTERVAL); 78587401969SAndrew Jiang 78687401969SAndrew Jiang time_elapsed += HPD_CHECK_INTERVAL; 78787401969SAndrew Jiang } while (time_elapsed < timeout); 78887401969SAndrew Jiang 78987401969SAndrew Jiang dal_gpio_close(hpd); 79087401969SAndrew Jiang 79187401969SAndrew Jiang dal_gpio_destroy_irq(&hpd); 79287401969SAndrew Jiang 79387401969SAndrew Jiang if (false == edp_hpd_high) { 7941296423bSBhawanpreet Lakha DC_LOG_ERROR( 79587401969SAndrew Jiang "%s: wait timed out!\n", __func__); 79687401969SAndrew Jiang } 79787401969SAndrew Jiang } 79887401969SAndrew Jiang 7998a31820bSMartin Leung void dce110_edp_power_control( 800069d418fSAndrew Jiang struct dc_link *link, 80187401969SAndrew Jiang bool power_up) 80287401969SAndrew Jiang { 803069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 80487401969SAndrew Jiang struct bp_transmitter_control cntl = { 0 }; 80587401969SAndrew Jiang enum bp_result bp_result; 80606ddcee4SJake Wang uint8_t panel_instance; 80787401969SAndrew Jiang 80887401969SAndrew Jiang 809069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 81087401969SAndrew Jiang != CONNECTOR_ID_EDP) { 81187401969SAndrew Jiang BREAK_TO_DEBUGGER(); 81287401969SAndrew Jiang return; 81387401969SAndrew Jiang } 81487401969SAndrew Jiang 815ffadb9d6SAnthony Koo if (!link->panel_cntl) 816904fb6e0SAnthony Koo return; 817d4caa72eSAnthony Koo if (power_up != 818d4caa72eSAnthony Koo link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 819172c9b77SAshley Thomas 82078d5d04dSCharlene Liu unsigned long long current_ts = dm_get_timestamp(ctx); 821172c9b77SAshley Thomas unsigned long long time_since_edp_poweroff_ms = 82293ed1814SHugo Hu div64_u64(dm_get_elapse_time_in_ns( 82378d5d04dSCharlene Liu ctx, 82478d5d04dSCharlene Liu current_ts, 82593ed1814SHugo Hu link->link_trace.time_stamp.edp_poweroff), 1000000); 826172c9b77SAshley Thomas unsigned long long time_since_edp_poweron_ms = 827172c9b77SAshley Thomas div64_u64(dm_get_elapse_time_in_ns( 828172c9b77SAshley Thomas ctx, 829172c9b77SAshley Thomas current_ts, 830172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron), 1000000); 831172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 832172c9b77SAshley Thomas "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 833172c9b77SAshley Thomas __func__, 834172c9b77SAshley Thomas power_up, 835172c9b77SAshley Thomas current_ts, 836172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 837172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron, 838172c9b77SAshley Thomas time_since_edp_poweroff_ms, 839172c9b77SAshley Thomas time_since_edp_poweron_ms); 84078d5d04dSCharlene Liu 841172c9b77SAshley Thomas /* Send VBIOS command to prompt eDP panel power */ 842172c9b77SAshley Thomas if (power_up) { 843172c9b77SAshley Thomas /* edp requires a min of 500ms from LCDVDD off to on */ 844172c9b77SAshley Thomas unsigned long long remaining_min_edp_poweroff_time_ms = 500; 845ff587987SHugo Hu 846172c9b77SAshley Thomas /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 8476c4fff06SYue Hin Lau if (link->local_sink != NULL) 848172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms += 849172c9b77SAshley Thomas link->local_sink->edid_caps.panel_patch.extra_t12_ms; 85078d5d04dSCharlene Liu 851172c9b77SAshley Thomas /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 852172c9b77SAshley Thomas if (link->link_trace.time_stamp.edp_poweroff != 0) { 853172c9b77SAshley Thomas if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 854172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 855172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 856172c9b77SAshley Thomas else 857172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 0; 85878d5d04dSCharlene Liu } 85978d5d04dSCharlene Liu 860172c9b77SAshley Thomas if (remaining_min_edp_poweroff_time_ms) { 861172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 862172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 863172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 864172c9b77SAshley Thomas msleep(remaining_min_edp_poweroff_time_ms); 865172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 866172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 867172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 868172c9b77SAshley Thomas dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 869172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 870172c9b77SAshley Thomas } else { 871172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 872172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 873172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 874172c9b77SAshley Thomas } 87578d5d04dSCharlene Liu } 87687401969SAndrew Jiang 8771296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 878172c9b77SAshley Thomas "%s: BEGIN: Panel Power action: %s\n", 87987401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 88087401969SAndrew Jiang 88187401969SAndrew Jiang cntl.action = power_up ? 88287401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_ON : 88387401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_OFF; 884069d418fSAndrew Jiang cntl.transmitter = link->link_enc->transmitter; 885069d418fSAndrew Jiang cntl.connector_obj_id = link->link_enc->connector; 88687401969SAndrew Jiang cntl.coherent = false; 88787401969SAndrew Jiang cntl.lanes_number = LANE_COUNT_FOUR; 888069d418fSAndrew Jiang cntl.hpd_sel = link->link_enc->hpd_source; 88906ddcee4SJake Wang panel_instance = link->panel_cntl->inst; 8908a0e210cSChris Park 8918a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 8928a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 8938a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) 8948a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 89506ddcee4SJake Wang LVTMA_CONTROL_POWER_ON, 89606ddcee4SJake Wang panel_instance); 8978a0e210cSChris Park else 8988a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 89906ddcee4SJake Wang LVTMA_CONTROL_POWER_OFF, 90006ddcee4SJake Wang panel_instance); 9018a0e210cSChris Park } 9028a0e210cSChris Park 90387401969SAndrew Jiang bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 90487401969SAndrew Jiang 905172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 906172c9b77SAshley Thomas "%s: END: Panel Power action: %s bp_result=%u\n", 907172c9b77SAshley Thomas __func__, (power_up ? "On":"Off"), 908172c9b77SAshley Thomas bp_result); 909172c9b77SAshley Thomas 91078d5d04dSCharlene Liu if (!power_up) 91178d5d04dSCharlene Liu /*save driver power off time stamp*/ 91278d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 91378d5d04dSCharlene Liu else 91478d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 91578d5d04dSCharlene Liu 916172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 917172c9b77SAshley Thomas "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 918172c9b77SAshley Thomas __func__, 919172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 920172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron); 921172c9b77SAshley Thomas 92287401969SAndrew Jiang if (bp_result != BP_RESULT_OK) 9231296423bSBhawanpreet Lakha DC_LOG_ERROR( 92487401969SAndrew Jiang "%s: Panel Power bp_result: %d\n", 92587401969SAndrew Jiang __func__, bp_result); 92687401969SAndrew Jiang } else { 9271296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 92887401969SAndrew Jiang "%s: Skipping Panel Power action: %s\n", 92987401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 93087401969SAndrew Jiang } 93187401969SAndrew Jiang } 9325eefbc40SYue Hin Lau 933cf3a2627SJun Lei void dce110_edp_wait_for_T12( 934cf3a2627SJun Lei struct dc_link *link) 935cf3a2627SJun Lei { 936cf3a2627SJun Lei struct dc_context *ctx = link->ctx; 937cf3a2627SJun Lei 938cf3a2627SJun Lei if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 939cf3a2627SJun Lei != CONNECTOR_ID_EDP) { 940cf3a2627SJun Lei BREAK_TO_DEBUGGER(); 941cf3a2627SJun Lei return; 942cf3a2627SJun Lei } 943cf3a2627SJun Lei 944cf3a2627SJun Lei if (!link->panel_cntl) 945cf3a2627SJun Lei return; 946cf3a2627SJun Lei 947cf3a2627SJun Lei if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 948cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff != 0) { 949cf3a2627SJun Lei unsigned int t12_duration = 500; // Default T12 as per spec 950cf3a2627SJun Lei unsigned long long current_ts = dm_get_timestamp(ctx); 951cf3a2627SJun Lei unsigned long long time_since_edp_poweroff_ms = 952cf3a2627SJun Lei div64_u64(dm_get_elapse_time_in_ns( 953cf3a2627SJun Lei ctx, 954cf3a2627SJun Lei current_ts, 955cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff), 1000000); 956cf3a2627SJun Lei 957cf3a2627SJun Lei t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12 958cf3a2627SJun Lei 959cf3a2627SJun Lei if (time_since_edp_poweroff_ms < t12_duration) 960cf3a2627SJun Lei msleep(t12_duration - time_since_edp_poweroff_ms); 961cf3a2627SJun Lei } 962cf3a2627SJun Lei } 963cf3a2627SJun Lei 9645eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 9655eefbc40SYue Hin Lau /* 9665eefbc40SYue Hin Lau * @brief 9675eefbc40SYue Hin Lau * eDP only. Control the backlight of the eDP panel 9685eefbc40SYue Hin Lau */ 9698a31820bSMartin Leung void dce110_edp_backlight_control( 9705eefbc40SYue Hin Lau struct dc_link *link, 9715eefbc40SYue Hin Lau bool enable) 9725eefbc40SYue Hin Lau { 973069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 9745eefbc40SYue Hin Lau struct bp_transmitter_control cntl = { 0 }; 97506ddcee4SJake Wang uint8_t panel_instance; 9765eefbc40SYue Hin Lau 977069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 9785eefbc40SYue Hin Lau != CONNECTOR_ID_EDP) { 9795eefbc40SYue Hin Lau BREAK_TO_DEBUGGER(); 9805eefbc40SYue Hin Lau return; 9815eefbc40SYue Hin Lau } 9825eefbc40SYue Hin Lau 983014427adSSherry if (link->panel_cntl) { 984014427adSSherry bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 985014427adSSherry 986014427adSSherry if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 9871296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 988014427adSSherry "%s: panel already powered up/off. Do nothing.\n", 9895eefbc40SYue Hin Lau __func__); 9905eefbc40SYue Hin Lau return; 9915eefbc40SYue Hin Lau } 992014427adSSherry } 9935eefbc40SYue Hin Lau 9945eefbc40SYue Hin Lau /* Send VBIOS command to control eDP panel backlight */ 9955eefbc40SYue Hin Lau 9961296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 9975eefbc40SYue Hin Lau "%s: backlight action: %s\n", 9985eefbc40SYue Hin Lau __func__, (enable ? "On":"Off")); 9995eefbc40SYue Hin Lau 10005eefbc40SYue Hin Lau cntl.action = enable ? 10015eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_ON : 10025eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_OFF; 100387401969SAndrew Jiang 10045eefbc40SYue Hin Lau /*cntl.engine_id = ctx->engine;*/ 10055eefbc40SYue Hin Lau cntl.transmitter = link->link_enc->transmitter; 10065eefbc40SYue Hin Lau cntl.connector_obj_id = link->link_enc->connector; 10075eefbc40SYue Hin Lau /*todo: unhardcode*/ 10085eefbc40SYue Hin Lau cntl.lanes_number = LANE_COUNT_FOUR; 10095eefbc40SYue Hin Lau cntl.hpd_sel = link->link_enc->hpd_source; 1010cf1835f0SCharlene Liu cntl.signal = SIGNAL_TYPE_EDP; 10115eefbc40SYue Hin Lau 10125eefbc40SYue Hin Lau /* For eDP, the following delays might need to be considered 10135eefbc40SYue Hin Lau * after link training completed: 10145eefbc40SYue Hin Lau * idle period - min. accounts for required BS-Idle pattern, 10155eefbc40SYue Hin Lau * max. allows for source frame synchronization); 10165eefbc40SYue Hin Lau * 50 msec max. delay from valid video data from source 10175eefbc40SYue Hin Lau * to video on dislpay or backlight enable. 10185eefbc40SYue Hin Lau * 10195eefbc40SYue Hin Lau * Disable the delay for now. 10205eefbc40SYue Hin Lau * Enable it in the future if necessary. 10215eefbc40SYue Hin Lau */ 10225eefbc40SYue Hin Lau /* dc_service_sleep_in_milliseconds(50); */ 10235180d4a4SCharlene Liu /*edp 1.2*/ 102406ddcee4SJake Wang panel_instance = link->panel_cntl->inst; 1025*a5148245SZhan Liu 1026*a5148245SZhan Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { 1027*a5148245SZhan Liu if (!link->dc->config.edp_no_power_sequencing) 1028*a5148245SZhan Liu /* 1029*a5148245SZhan Liu * Sometimes, DP receiver chip power-controlled externally by an 1030*a5148245SZhan Liu * Embedded Controller could be treated and used as eDP, 1031*a5148245SZhan Liu * if it drives mobile display. In this case, 1032*a5148245SZhan Liu * we shouldn't be doing power-sequencing, hence we can skip 1033*a5148245SZhan Liu * waiting for T7-ready. 1034*a5148245SZhan Liu */ 10355180d4a4SCharlene Liu edp_receiver_ready_T7(link); 1036*a5148245SZhan Liu else 1037*a5148245SZhan Liu DC_LOG_DC("edp_receiver_ready_T7 skipped\n"); 1038*a5148245SZhan Liu } 10398a0e210cSChris Park 10408a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 10418a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 10428a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 10438a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 104406ddcee4SJake Wang LVTMA_CONTROL_LCD_BLON, 104506ddcee4SJake Wang panel_instance); 10468a0e210cSChris Park else 10478a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 104806ddcee4SJake Wang LVTMA_CONTROL_LCD_BLOFF, 104906ddcee4SJake Wang panel_instance); 10508a0e210cSChris Park } 10518a0e210cSChris Park 1052069d418fSAndrew Jiang link_transmitter_control(ctx->dc_bios, &cntl); 105396577cf8SHersen Wu 105496577cf8SHersen Wu if (enable && link->dpcd_sink_ext_caps.bits.oled) 105596577cf8SHersen Wu msleep(OLED_POST_T7_DELAY); 105696577cf8SHersen Wu 105796577cf8SHersen Wu if (link->dpcd_sink_ext_caps.bits.oled || 105896577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 105996577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 106096577cf8SHersen Wu dc_link_backlight_enable_aux(link, enable); 106196577cf8SHersen Wu 106269b9723aSCharlene Liu /*edp 1.2*/ 1063*a5148245SZhan Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) { 1064*a5148245SZhan Liu if (!link->dc->config.edp_no_power_sequencing) 1065*a5148245SZhan Liu /* 1066*a5148245SZhan Liu * Sometimes, DP receiver chip power-controlled externally by an 1067*a5148245SZhan Liu * Embedded Controller could be treated and used as eDP, 1068*a5148245SZhan Liu * if it drives mobile display. In this case, 1069*a5148245SZhan Liu * we shouldn't be doing power-sequencing, hence we can skip 1070*a5148245SZhan Liu * waiting for T9-ready. 1071*a5148245SZhan Liu */ 10723a372bedSHugo Hu edp_add_delay_for_T9(link); 1073*a5148245SZhan Liu else 1074*a5148245SZhan Liu DC_LOG_DC("edp_receiver_ready_T9 skipped\n"); 1075*a5148245SZhan Liu } 107696577cf8SHersen Wu 107796577cf8SHersen Wu if (!enable && link->dpcd_sink_ext_caps.bits.oled) 107896577cf8SHersen Wu msleep(OLED_PRE_T11_DELAY); 10795eefbc40SYue Hin Lau } 10805eefbc40SYue Hin Lau 10811a05873fSAnthony Koo void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 10824562236bSHarry Wentland { 10831a05873fSAnthony Koo /* notify audio driver for audio modes of monitor */ 10842b77dcc5SAnthony Koo struct dc *dc; 10851d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 10861a05873fSAnthony Koo unsigned int i, num_audio = 1; 10871a05873fSAnthony Koo 10881d0610bcSAlvin Lee if (!pipe_ctx->stream) 10891d0610bcSAlvin Lee return; 10901d0610bcSAlvin Lee 10912b77dcc5SAnthony Koo dc = pipe_ctx->stream->ctx->dc; 10922b77dcc5SAnthony Koo clk_mgr = dc->clk_mgr; 10931d0610bcSAlvin Lee 10940a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 10950a32df9cSEryk Brol return; 10960a32df9cSEryk Brol 10971a05873fSAnthony Koo if (pipe_ctx->stream_res.audio) { 10981a05873fSAnthony Koo for (i = 0; i < MAX_PIPES; i++) { 10991a05873fSAnthony Koo /*current_state not updated yet*/ 11002b77dcc5SAnthony Koo if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 11011a05873fSAnthony Koo num_audio++; 11021a05873fSAnthony Koo } 11031a05873fSAnthony Koo 11041a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 11051a05873fSAnthony Koo 1106170a2398SSu Sung Chung if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 11071a05873fSAnthony Koo /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1108170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 11091a05873fSAnthony Koo /* un-mute audio */ 11101a05873fSAnthony Koo /* TODO: audio should be per stream rather than per link */ 11111a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 11121a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, false); 11130a32df9cSEryk Brol if (pipe_ctx->stream_res.audio) 11140a32df9cSEryk Brol pipe_ctx->stream_res.audio->enabled = true; 11151a05873fSAnthony Koo } 11161a05873fSAnthony Koo } 11171a05873fSAnthony Koo 111857430404SSu Sung Chung void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 11191a05873fSAnthony Koo { 11201d0610bcSAlvin Lee struct dc *dc; 11211d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 11221d0610bcSAlvin Lee 11231d0610bcSAlvin Lee if (!pipe_ctx || !pipe_ctx->stream) 11241d0610bcSAlvin Lee return; 11251d0610bcSAlvin Lee 11261d0610bcSAlvin Lee dc = pipe_ctx->stream->ctx->dc; 11271d0610bcSAlvin Lee clk_mgr = dc->clk_mgr; 11284562236bSHarry Wentland 11290a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 11300a32df9cSEryk Brol return; 11310a32df9cSEryk Brol 11322b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 11332b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc, true); 1134afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio) { 11353f52aa9fSNicholas Kazlauskas pipe_ctx->stream_res.audio->enabled = false; 11363f52aa9fSNicholas Kazlauskas 11374562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11388e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 11398e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 11404562236bSHarry Wentland else 11418e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 11428e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 114357430404SSu Sung Chung 1144170a2398SSu Sung Chung if (clk_mgr->funcs->enable_pme_wa) 1145070fe724SCharlene Liu /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1146170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 11474562236bSHarry Wentland 11484562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 11494562236bSHarry Wentland * add audio mode list change flag */ 11504562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 11514562236bSHarry Wentland * stream->stream_engine_id); 11524562236bSHarry Wentland */ 11534562236bSHarry Wentland } 11541a05873fSAnthony Koo } 11554562236bSHarry Wentland 115657430404SSu Sung Chung void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 11571a05873fSAnthony Koo { 11581a05873fSAnthony Koo struct dc_stream_state *stream = pipe_ctx->stream; 1159ceb3dbb4SJun Lei struct dc_link *link = stream->link; 11601a05873fSAnthony Koo struct dc *dc = pipe_ctx->stream->ctx->dc; 11611a05873fSAnthony Koo 1162ac42fd63SWenjing Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 11631a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 11641a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 1165ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1166ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc); 1167ac42fd63SWenjing Liu } 11681a05873fSAnthony Koo 11691a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11701a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 11711a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 11721a05873fSAnthony Koo 117357430404SSu Sung Chung dc->hwss.disable_audio_stream(pipe_ctx); 1174904623eeSYongqiang Sun 11754562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 11764562236bSHarry Wentland link->link_enc, 11778e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->id, 11784562236bSHarry Wentland false); 11794562236bSHarry Wentland 11804562236bSHarry Wentland } 11814562236bSHarry Wentland 11824562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 11834562236bSHarry Wentland struct dc_link_settings *link_settings) 11844562236bSHarry Wentland { 11854562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 118641b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1187ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1188f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 11894562236bSHarry Wentland 11904562236bSHarry Wentland /* only 3 items below are used by unblank */ 11917fe538a4SCharlene Liu params.timing = pipe_ctx->stream->timing; 11924562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 119341b49742SCharlene Liu 119441b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11958e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 119641b49742SCharlene Liu 119714d6f644SYongqiang Sun if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1198f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, true); 119914d6f644SYongqiang Sun } 120041b49742SCharlene Liu } 12012c850b7bSDmytro Laktyushkin 120241b49742SCharlene Liu void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 120341b49742SCharlene Liu { 120441b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1205ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1206f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 120741b49742SCharlene Liu 1208ab892598SRoman Li if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1209f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, false); 12103ba01817SYongqiang Sun link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1211ab892598SRoman Li } 121241b49742SCharlene Liu 1213eec3303dSAric Cyr if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 121441b49742SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 1215eec3303dSAric Cyr 12163a372bedSHugo Hu if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1217eec3303dSAric Cyr /* 1218eec3303dSAric Cyr * After output is idle pattern some sinks need time to recognize the stream 1219eec3303dSAric Cyr * has changed or they enter protection state and hang. 1220eec3303dSAric Cyr */ 1221eec3303dSAric Cyr msleep(60); 12223a372bedSHugo Hu } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) 12233a372bedSHugo Hu edp_receiver_ready_T9(link); 1224eec3303dSAric Cyr } 1225eec3303dSAric Cyr 12264562236bSHarry Wentland } 12274562236bSHarry Wentland 122815e17335SCharlene Liu 122915e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 123015e17335SCharlene Liu { 12318e9c4c8cSHarry Wentland if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 12328e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 123315e17335SCharlene Liu } 123415e17335SCharlene Liu 12354562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 12364562236bSHarry Wentland { 12374562236bSHarry Wentland switch (crtc_id) { 12384562236bSHarry Wentland case CONTROLLER_ID_D0: 12394562236bSHarry Wentland return DTO_SOURCE_ID0; 12404562236bSHarry Wentland case CONTROLLER_ID_D1: 12414562236bSHarry Wentland return DTO_SOURCE_ID1; 12424562236bSHarry Wentland case CONTROLLER_ID_D2: 12434562236bSHarry Wentland return DTO_SOURCE_ID2; 12444562236bSHarry Wentland case CONTROLLER_ID_D3: 12454562236bSHarry Wentland return DTO_SOURCE_ID3; 12464562236bSHarry Wentland case CONTROLLER_ID_D4: 12474562236bSHarry Wentland return DTO_SOURCE_ID4; 12484562236bSHarry Wentland case CONTROLLER_ID_D5: 12494562236bSHarry Wentland return DTO_SOURCE_ID5; 12504562236bSHarry Wentland default: 12514562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 12524562236bSHarry Wentland } 12534562236bSHarry Wentland } 12544562236bSHarry Wentland 12554562236bSHarry Wentland static void build_audio_output( 1256ab8db3e1SAndrey Grodzovsky struct dc_state *state, 12574562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 12584562236bSHarry Wentland struct audio_output *audio_output) 12594562236bSHarry Wentland { 12600971c40eSHarry Wentland const struct dc_stream_state *stream = pipe_ctx->stream; 12618e9c4c8cSHarry Wentland audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 12624562236bSHarry Wentland 12634562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 12644562236bSHarry Wentland 12654562236bSHarry Wentland /* audio_crtc_info */ 12664562236bSHarry Wentland 12674562236bSHarry Wentland audio_output->crtc_info.h_total = 12684fa086b9SLeo (Sunpeng) Li stream->timing.h_total; 12694562236bSHarry Wentland 12704562236bSHarry Wentland /* 12714562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 12724562236bSHarry Wentland * need to specify actual active signal portion 12734562236bSHarry Wentland */ 12744562236bSHarry Wentland audio_output->crtc_info.h_active = 12754fa086b9SLeo (Sunpeng) Li stream->timing.h_addressable 12764fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_left 12774fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_right; 12784562236bSHarry Wentland 12794562236bSHarry Wentland audio_output->crtc_info.v_active = 12804fa086b9SLeo (Sunpeng) Li stream->timing.v_addressable 12814fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_top 12824fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_bottom; 12834562236bSHarry Wentland 12844562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 12854562236bSHarry Wentland 12864562236bSHarry Wentland audio_output->crtc_info.interlaced = 12874fa086b9SLeo (Sunpeng) Li stream->timing.flags.INTERLACE; 12884562236bSHarry Wentland 12894562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 129040fd9090SNevenko Stupar (stream->timing.pix_clk_100hz*100)/ 12914fa086b9SLeo (Sunpeng) Li (stream->timing.h_total*stream->timing.v_total); 12924562236bSHarry Wentland 12934562236bSHarry Wentland audio_output->crtc_info.color_depth = 12944fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth; 12954562236bSHarry Wentland 129640fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 129740fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 12984562236bSHarry Wentland 129940fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 130040fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 13014562236bSHarry Wentland 130287b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 13032166d9fbSCharlene Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 130440fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz == 130540fd9090SNevenko Stupar (stream->timing.pix_clk_100hz)) { 130610688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 130740fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 130840fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz/2; 130940fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 131040fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 131187b58768SCharlene Liu 131287b58768SCharlene Liu } 131387b58768SCharlene Liu } 131487b58768SCharlene Liu 1315ed476602SAhzo if (state->clk_mgr && 1316ed476602SAhzo (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1317ed476602SAhzo pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 13184562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 13190de34efcSDmytro Laktyushkin state->clk_mgr->funcs->get_dp_ref_clk_frequency( 13200de34efcSDmytro Laktyushkin state->clk_mgr); 13214562236bSHarry Wentland } 13224562236bSHarry Wentland 13234562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 13244562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 13254562236bSHarry Wentland 13264562236bSHarry Wentland audio_output->pll_info.dto_source = 13274562236bSHarry Wentland translate_to_dto_source( 1328e07f541fSYongqiang Sun pipe_ctx->stream_res.tg->inst + 1); 13294562236bSHarry Wentland 13304562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 13314562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 13324562236bSHarry Wentland 13334562236bSHarry Wentland audio_output->pll_info.ss_percentage = 13344562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 13354562236bSHarry Wentland } 13364562236bSHarry Wentland 1337fb3466a4SBhawanpreet Lakha static void program_scaler(const struct dc *dc, 13384562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 13394562236bSHarry Wentland { 13404562236bSHarry Wentland struct tg_color color = {0}; 13414562236bSHarry Wentland 1342b86a1aa3SBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC_DCN) 1343ff5ef992SAlex Deucher /* TOFPGA */ 134486a66c4eSHarry Wentland if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1345ff5ef992SAlex Deucher return; 1346ff5ef992SAlex Deucher #endif 1347ff5ef992SAlex Deucher 1348bf53769dSGloria Li if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 13494562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 13504562236bSHarry Wentland else 13514562236bSHarry Wentland color_space_to_black_color(dc, 13524fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space, 13534562236bSHarry Wentland &color); 13544562236bSHarry Wentland 135586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 135686a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, 13576702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.depth, 13584562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 13594562236bSHarry Wentland 136012750d16SEric Yang if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 136112750d16SEric Yang /* 136212750d16SEric Yang * The way 420 is packed, 2 channels carry Y component, 1 channel 136312750d16SEric Yang * alternate between Cb and Cr, so both channels need the pixel 136412750d16SEric Yang * value for Y 136512750d16SEric Yang */ 136612750d16SEric Yang if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 136712750d16SEric Yang color.color_r_cr = color.color_g_y; 136812750d16SEric Yang 13696b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 13706b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 13714562236bSHarry Wentland &color); 137212750d16SEric Yang } 13734562236bSHarry Wentland 137486a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 13756702a9acSHarry Wentland &pipe_ctx->plane_res.scl_data); 13764562236bSHarry Wentland } 13774562236bSHarry Wentland 13783158223eSEric Bernstein static enum dc_status dce110_enable_stream_timing( 13794562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1380608ac7bbSJerry Zuo struct dc_state *context, 1381fb3466a4SBhawanpreet Lakha struct dc *dc) 13824562236bSHarry Wentland { 13830971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1384608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 13854562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 13864562236bSHarry Wentland struct tg_color black_color = {0}; 13874562236bSHarry Wentland 13884562236bSHarry Wentland if (!pipe_ctx_old->stream) { 13894562236bSHarry Wentland 13904562236bSHarry Wentland /* program blank color */ 13914562236bSHarry Wentland color_space_to_black_color(dc, 13924fa086b9SLeo (Sunpeng) Li stream->output_color_space, &black_color); 13936b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank_color( 13946b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 13954562236bSHarry Wentland &black_color); 13964b5e7d62SHersen Wu 13974562236bSHarry Wentland /* 13984562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 13994562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 14004562236bSHarry Wentland */ 14016b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 14024562236bSHarry Wentland 14034562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 14044562236bSHarry Wentland pipe_ctx->clock_source, 140510688217SHarry Wentland &pipe_ctx->stream_res.pix_clk_params, 14064562236bSHarry Wentland &pipe_ctx->pll_settings)) { 14074562236bSHarry Wentland BREAK_TO_DEBUGGER(); 14084562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 14094562236bSHarry Wentland } 14104562236bSHarry Wentland 14116b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->program_timing( 14126b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14134fa086b9SLeo (Sunpeng) Li &stream->timing, 1414e7e10c46SDmytro Laktyushkin 0, 1415e7e10c46SDmytro Laktyushkin 0, 1416e7e10c46SDmytro Laktyushkin 0, 1417e7e10c46SDmytro Laktyushkin 0, 1418e7e10c46SDmytro Laktyushkin pipe_ctx->stream->signal, 14194562236bSHarry Wentland true); 14204562236bSHarry Wentland } 14214562236bSHarry Wentland 14224562236bSHarry Wentland if (!pipe_ctx_old->stream) { 14236b670fa9SHarry Wentland if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 14246b670fa9SHarry Wentland pipe_ctx->stream_res.tg)) { 14254562236bSHarry Wentland BREAK_TO_DEBUGGER(); 14264562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 14274562236bSHarry Wentland } 14284562236bSHarry Wentland } 14294562236bSHarry Wentland 14304562236bSHarry Wentland return DC_OK; 14314562236bSHarry Wentland } 14324562236bSHarry Wentland 14334562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 14344562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1435608ac7bbSJerry Zuo struct dc_state *context, 1436fb3466a4SBhawanpreet Lakha struct dc *dc) 14374562236bSHarry Wentland { 14380971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 14399c0fb8d4SAnthony Koo struct drr_params params = {0}; 14409c0fb8d4SAnthony Koo unsigned int event_triggers = 0; 1441b1f6d01cSDmytro Laktyushkin struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1442f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 14434562236bSHarry Wentland 1444f42ea55bSAnthony Koo if (hws->funcs.disable_stream_gating) { 1445f42ea55bSAnthony Koo hws->funcs.disable_stream_gating(dc, pipe_ctx); 1446240d09d0SGary Kattan } 1447240d09d0SGary Kattan 14481a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 14491a05873fSAnthony Koo struct audio_output audio_output; 14501a05873fSAnthony Koo 14511a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 14521a05873fSAnthony Koo 14531a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 14541a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 14551a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 14561a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 14571a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 14581a05873fSAnthony Koo else 14591a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 14601a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 14611a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 14621a05873fSAnthony Koo &pipe_ctx->stream->audio_info, 14631a05873fSAnthony Koo &audio_output.crtc_info); 14641a05873fSAnthony Koo 14651a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_configure( 14661a05873fSAnthony Koo pipe_ctx->stream_res.audio, 14671a05873fSAnthony Koo pipe_ctx->stream->signal, 14681a05873fSAnthony Koo &audio_output.crtc_info, 14691a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 14701a05873fSAnthony Koo } 14711a05873fSAnthony Koo 14724562236bSHarry Wentland /* */ 1473d2d7885fSAnthony Koo /* Do not touch stream timing on seamless boot optimization. */ 1474d2d7885fSAnthony Koo if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1475f42ea55bSAnthony Koo hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 14764562236bSHarry Wentland 1477f42ea55bSAnthony Koo if (hws->funcs.setup_vupdate_interrupt) 1478f42ea55bSAnthony Koo hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1479a122b62dSAnthony Koo 14809c0fb8d4SAnthony Koo params.vertical_total_min = stream->adjust.v_total_min; 14819c0fb8d4SAnthony Koo params.vertical_total_max = stream->adjust.v_total_max; 14829c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_drr) 14839c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_drr( 14849c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg, ¶ms); 14859c0fb8d4SAnthony Koo 14869c0fb8d4SAnthony Koo // DRR should set trigger event to monitor surface update event 14879c0fb8d4SAnthony Koo if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 14889c0fb8d4SAnthony Koo event_triggers = 0x80; 14895b5abe95SAnthony Koo /* Event triggers and num frames initialized for DRR, but can be 14905b5abe95SAnthony Koo * later updated for PSR use. Note DRR trigger events are generated 14915b5abe95SAnthony Koo * regardless of whether num frames met. 14925b5abe95SAnthony Koo */ 14939c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 14949c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 14955b5abe95SAnthony Koo pipe_ctx->stream_res.tg, event_triggers, 2); 14969c0fb8d4SAnthony Koo 1497248cbed6SEric Bernstein if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1498d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1499d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc, 1500d2c460e7Shersen wu pipe_ctx->stream_res.tg->inst); 1501aa9c4abeSNikola Cornij 1502f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1503f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp, 1504f0c4d997SCorbin McElhanney COLOR_SPACE_YCBCR601, 1505f0c4d997SCorbin McElhanney stream->timing.display_color_depth, 1506661a8cd9SDmytro Laktyushkin stream->signal); 15074562236bSHarry Wentland 1508a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1509a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 1510181a888fSCharlene Liu &stream->bit_depth_params, 1511181a888fSCharlene Liu &stream->clamping); 1512b1f6d01cSDmytro Laktyushkin while (odm_pipe) { 15137ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 15147ed4e635SHarry Wentland odm_pipe->stream_res.opp, 15157ed4e635SHarry Wentland COLOR_SPACE_YCBCR601, 15167ed4e635SHarry Wentland stream->timing.display_color_depth, 15177ed4e635SHarry Wentland stream->signal); 15187ed4e635SHarry Wentland 15197ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_program_fmt( 15207ed4e635SHarry Wentland odm_pipe->stream_res.opp, 15217ed4e635SHarry Wentland &stream->bit_depth_params, 15227ed4e635SHarry Wentland &stream->clamping); 1523b1f6d01cSDmytro Laktyushkin odm_pipe = odm_pipe->next_odm_pipe; 15247ed4e635SHarry Wentland } 1525603767f9STony Cheng 15261e7e86c4SSamson Tam if (!stream->dpms_off) 1527ab8db3e1SAndrey Grodzovsky core_link_enable_stream(context, pipe_ctx); 15284562236bSHarry Wentland 15296702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 15304562236bSHarry Wentland 1531d1ebfdd8SWyatt Wood pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 153294267b3dSSylvia Tsai 15334562236bSHarry Wentland return DC_OK; 15344562236bSHarry Wentland } 15354562236bSHarry Wentland 15364562236bSHarry Wentland /******************************************************************************/ 15374562236bSHarry Wentland 1538fb3466a4SBhawanpreet Lakha static void power_down_encoders(struct dc *dc) 15394562236bSHarry Wentland { 15404562236bSHarry Wentland int i; 1541b9b171ffSHersen Wu 1542b9b171ffSHersen Wu /* do not know BIOS back-front mapping, simply blank all. It will not 1543b9b171ffSHersen Wu * hurt for non-DP 1544b9b171ffSHersen Wu */ 1545b9b171ffSHersen Wu for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1546b9b171ffSHersen Wu dc->res_pool->stream_enc[i]->funcs->dp_blank( 1547b9b171ffSHersen Wu dc->res_pool->stream_enc[i]); 1548b9b171ffSHersen Wu } 1549b9b171ffSHersen Wu 15504562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 1551d4c2a96fSLewis Huang enum signal_type signal = dc->links[i]->connector_signal; 1552a0c38ebaSCharlene Liu 1553d4c2a96fSLewis Huang if ((signal == SIGNAL_TYPE_EDP) || 1554d4c2a96fSLewis Huang (signal == SIGNAL_TYPE_DISPLAY_PORT)) 1555a0c38ebaSCharlene Liu if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) 1556a0c38ebaSCharlene Liu dp_receiver_power_ctrl(dc->links[i], false); 1557a0c38ebaSCharlene Liu 15584338ffa8SSung Lee if (signal != SIGNAL_TYPE_EDP) 15594338ffa8SSung Lee signal = SIGNAL_TYPE_NONE; 15604338ffa8SSung Lee 15614562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 1562069d418fSAndrew Jiang dc->links[i]->link_enc, signal); 1563b56e90eaSPaul Hsieh 1564b56e90eaSPaul Hsieh dc->links[i]->link_status.link_active = false; 156507920450SJoshua Aberback memset(&dc->links[i]->cur_link_settings, 0, 156607920450SJoshua Aberback sizeof(dc->links[i]->cur_link_settings)); 15674562236bSHarry Wentland } 15684562236bSHarry Wentland } 15694562236bSHarry Wentland 1570fb3466a4SBhawanpreet Lakha static void power_down_controllers(struct dc *dc) 15714562236bSHarry Wentland { 15724562236bSHarry Wentland int i; 15734562236bSHarry Wentland 15747f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 15754562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 15764562236bSHarry Wentland dc->res_pool->timing_generators[i]); 15774562236bSHarry Wentland } 15784562236bSHarry Wentland } 15794562236bSHarry Wentland 1580fb3466a4SBhawanpreet Lakha static void power_down_clock_sources(struct dc *dc) 15814562236bSHarry Wentland { 15824562236bSHarry Wentland int i; 15834562236bSHarry Wentland 15844562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 15854562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 15864562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 15874562236bSHarry Wentland 15884562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 15894562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 15904562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 15914562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 15924562236bSHarry Wentland } 15934562236bSHarry Wentland } 15944562236bSHarry Wentland 1595fb3466a4SBhawanpreet Lakha static void power_down_all_hw_blocks(struct dc *dc) 15964562236bSHarry Wentland { 15974562236bSHarry Wentland power_down_encoders(dc); 15984562236bSHarry Wentland 15994562236bSHarry Wentland power_down_controllers(dc); 16004562236bSHarry Wentland 16014562236bSHarry Wentland power_down_clock_sources(dc); 16021663ae1cSBhawanpreet Lakha 16032f3bfb27SRoman Li if (dc->fbc_compressor) 16041663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 16054562236bSHarry Wentland } 16064562236bSHarry Wentland 16074562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 1608fb3466a4SBhawanpreet Lakha struct dc *dc) 16094562236bSHarry Wentland { 16104562236bSHarry Wentland int i; 16114562236bSHarry Wentland struct timing_generator *tg; 16124562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 16134562236bSHarry Wentland 16147f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 16154562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 16164562236bSHarry Wentland 16170a87425aSTony Cheng if (tg->funcs->disable_vga) 16184562236bSHarry Wentland tg->funcs->disable_vga(tg); 16197f93c1deSCharlene Liu } 16207f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->pipe_count; i++) { 16214562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 16224562236bSHarry Wentland * powergating. */ 16234562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 16244562236bSHarry Wentland true); 16254562236bSHarry Wentland 1626e6c258cbSYongqiang Sun dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 16277f914a62SYongqiang Sun dc->hwss.disable_plane(dc, 1628e6c258cbSYongqiang Sun &dc->current_state->res_ctx.pipe_ctx[i]); 16294562236bSHarry Wentland } 16304562236bSHarry Wentland } 16314562236bSHarry Wentland 16323de5aa81SSivapiriyanKumarasamy 163345a1261bSJake Wang static void get_edp_streams(struct dc_state *context, 163445a1261bSJake Wang struct dc_stream_state **edp_streams, 163545a1261bSJake Wang int *edp_stream_num) 16363de5aa81SSivapiriyanKumarasamy { 16373de5aa81SSivapiriyanKumarasamy int i; 16383de5aa81SSivapiriyanKumarasamy 163945a1261bSJake Wang *edp_stream_num = 0; 16403de5aa81SSivapiriyanKumarasamy for (i = 0; i < context->stream_count; i++) { 164145a1261bSJake Wang if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 164245a1261bSJake Wang edp_streams[*edp_stream_num] = context->streams[i]; 164345a1261bSJake Wang if (++(*edp_stream_num) == MAX_NUM_EDP) 164445a1261bSJake Wang return; 16453de5aa81SSivapiriyanKumarasamy } 164645a1261bSJake Wang } 16473de5aa81SSivapiriyanKumarasamy } 16483de5aa81SSivapiriyanKumarasamy 164945a1261bSJake Wang static void get_edp_links_with_sink( 165025292028SYongqiang Sun struct dc *dc, 165145a1261bSJake Wang struct dc_link **edp_links_with_sink, 165245a1261bSJake Wang int *edp_with_sink_num) 165325292028SYongqiang Sun { 165425292028SYongqiang Sun int i; 165525292028SYongqiang Sun 165625292028SYongqiang Sun /* check if there is an eDP panel not in use */ 165745a1261bSJake Wang *edp_with_sink_num = 0; 165825292028SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 165925292028SYongqiang Sun if (dc->links[i]->local_sink && 166025292028SYongqiang Sun dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 166145a1261bSJake Wang edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; 166245a1261bSJake Wang if (++(*edp_with_sink_num) == MAX_NUM_EDP) 166345a1261bSJake Wang return; 166425292028SYongqiang Sun } 166525292028SYongqiang Sun } 166625292028SYongqiang Sun } 166725292028SYongqiang Sun 16681c17952eSLee Jones /* 16694562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 16704562236bSHarry Wentland * 1. Power down all DC HW blocks 16714562236bSHarry Wentland * 2. Disable VGA engine on all controllers 16724562236bSHarry Wentland * 3. Enable power gating for controller 16734562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 16744562236bSHarry Wentland */ 167525292028SYongqiang Sun void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 16764562236bSHarry Wentland { 167745a1261bSJake Wang struct dc_link *edp_links_with_sink[MAX_NUM_EDP]; 167845a1261bSJake Wang struct dc_link *edp_links[MAX_NUM_EDP]; 167945a1261bSJake Wang struct dc_stream_state *edp_streams[MAX_NUM_EDP]; 168045a1261bSJake Wang struct dc_link *edp_link_with_sink = NULL; 168145a1261bSJake Wang struct dc_link *edp_link = NULL; 16823de5aa81SSivapiriyanKumarasamy struct dc_stream_state *edp_stream = NULL; 168345a1261bSJake Wang struct dce_hwseq *hws = dc->hwseq; 168445a1261bSJake Wang int edp_with_sink_num; 168545a1261bSJake Wang int edp_num; 168645a1261bSJake Wang int edp_stream_num; 168745a1261bSJake Wang int i; 1688be4b289fSSivapiriyanKumarasamy bool can_apply_edp_fast_boot = false; 1689ce72741bSAnthony Koo bool can_apply_seamless_boot = false; 16903de5aa81SSivapiriyanKumarasamy bool keep_edp_vdd_on = false; 16910eda55caSMichael Strauss DC_LOGGER_INIT(); 16920eda55caSMichael Strauss 169345a1261bSJake Wang 169445a1261bSJake Wang get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); 169545a1261bSJake Wang get_edp_links(dc, edp_links, &edp_num); 1696ce72741bSAnthony Koo 1697f42ea55bSAnthony Koo if (hws->funcs.init_pipes) 1698f42ea55bSAnthony Koo hws->funcs.init_pipes(dc, context); 1699be4b289fSSivapiriyanKumarasamy 170045a1261bSJake Wang get_edp_streams(context, edp_streams, &edp_stream_num); 17013de5aa81SSivapiriyanKumarasamy 1702be4b289fSSivapiriyanKumarasamy // Check fastboot support, disable on DCE8 because of blank screens 170345a1261bSJake Wang if (edp_num && dc->ctx->dce_version != DCE_VERSION_8_0 && 1704be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_1 && 1705be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_3) { 170645a1261bSJake Wang for (i = 0; i < edp_num; i++) { 170745a1261bSJake Wang edp_link = edp_links[i]; 1708be4b289fSSivapiriyanKumarasamy // enable fastboot if backend is enabled on eDP 1709be4b289fSSivapiriyanKumarasamy if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) { 17103de5aa81SSivapiriyanKumarasamy /* Set optimization flag on eDP stream*/ 171145a1261bSJake Wang if (edp_stream_num && edp_link->link_status.link_active) { 171245a1261bSJake Wang edp_stream = edp_streams[0]; 1713f9fc6f39SMichael Strauss can_apply_edp_fast_boot = !is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing); 1714f9fc6f39SMichael Strauss edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot; 17150eda55caSMichael Strauss if (can_apply_edp_fast_boot) 17160eda55caSMichael Strauss DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n"); 1717f9fc6f39SMichael Strauss 171845a1261bSJake Wang break; 1719be4b289fSSivapiriyanKumarasamy } 1720be4b289fSSivapiriyanKumarasamy } 172145a1261bSJake Wang } 17223de5aa81SSivapiriyanKumarasamy // We are trying to enable eDP, don't power down VDD 172345a1261bSJake Wang if (edp_stream_num) 17243de5aa81SSivapiriyanKumarasamy keep_edp_vdd_on = true; 1725be4b289fSSivapiriyanKumarasamy } 1726be4b289fSSivapiriyanKumarasamy 1727be4b289fSSivapiriyanKumarasamy // Check seamless boot support 1728ce72741bSAnthony Koo for (i = 0; i < context->stream_count; i++) { 1729ce72741bSAnthony Koo if (context->streams[i]->apply_seamless_boot_optimization) { 1730ce72741bSAnthony Koo can_apply_seamless_boot = true; 1731ce72741bSAnthony Koo break; 1732ce72741bSAnthony Koo } 1733ce72741bSAnthony Koo } 17344cac1e6dSYongqiang Sun 1735be4b289fSSivapiriyanKumarasamy /* eDP should not have stream in resume from S4 and so even with VBios post 1736be4b289fSSivapiriyanKumarasamy * it should get turned off 17372c37e49aSYongqiang Sun */ 173845a1261bSJake Wang if (edp_with_sink_num) 173945a1261bSJake Wang edp_link_with_sink = edp_links_with_sink[0]; 174045a1261bSJake Wang 1741be4b289fSSivapiriyanKumarasamy if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 17423de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) { 17434cac1e6dSYongqiang Sun /*turn off backlight before DP_blank and encoder powered down*/ 1744f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1745c5fc7f59SCharlene Liu } 1746c5fc7f59SCharlene Liu /*resume from S3, no vbios posting, no need to power down again*/ 174725292028SYongqiang Sun power_down_all_hw_blocks(dc); 17484562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 17493de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) 1750be4b289fSSivapiriyanKumarasamy dc->hwss.edp_power_control(edp_link_with_sink, false); 1751c5fc7f59SCharlene Liu } 17521c5ea40cSYao Wang1 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); 17534562236bSHarry Wentland } 17544562236bSHarry Wentland 17554562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 17564562236bSHarry Wentland struct bw_fixed blackout_duration, 17570971c40eSHarry Wentland const struct dc_stream_state *stream) 17584562236bSHarry Wentland { 17594562236bSHarry Wentland uint32_t total_dest_line_time_ns; 17604562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 17614562236bSHarry Wentland 17624562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 17634562236bSHarry Wentland 17644562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 1765380604e2SKen Chalmers (stream->timing.h_total * 10) / 1766380604e2SKen Chalmers stream->timing.pix_clk_100hz + 17674562236bSHarry Wentland pstate_blackout_duration_ns; 17684562236bSHarry Wentland 17694562236bSHarry Wentland return total_dest_line_time_ns; 17704562236bSHarry Wentland } 17714562236bSHarry Wentland 1772f774b339SEric Yang static void dce110_set_displaymarks( 1773fb3466a4SBhawanpreet Lakha const struct dc *dc, 1774608ac7bbSJerry Zuo struct dc_state *context) 17754562236bSHarry Wentland { 17764562236bSHarry Wentland uint8_t i, num_pipes; 17774562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 17784562236bSHarry Wentland 17794562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 17804562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 17814562236bSHarry Wentland uint32_t total_dest_line_time_ns; 17824562236bSHarry Wentland 17834562236bSHarry Wentland if (pipe_ctx->stream == NULL) 17844562236bSHarry Wentland continue; 17854562236bSHarry Wentland 17864562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 178777a4ea53SBhawanpreet Lakha dc->bw_vbios->blackout_duration, pipe_ctx->stream); 178886a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 178986a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1790813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1791813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1792813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1793813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 17944562236bSHarry Wentland total_dest_line_time_ns); 17954562236bSHarry Wentland if (i == underlay_idx) { 17964562236bSHarry Wentland num_pipes++; 179786a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 179886a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1799813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1800813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1801813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 18024562236bSHarry Wentland total_dest_line_time_ns); 18034562236bSHarry Wentland } 18044562236bSHarry Wentland num_pipes++; 18054562236bSHarry Wentland } 18064562236bSHarry Wentland } 18074562236bSHarry Wentland 1808fab55d61SDmytro Laktyushkin void dce110_set_safe_displaymarks( 1809a2b8659dSTony Cheng struct resource_context *res_ctx, 1810a2b8659dSTony Cheng const struct resource_pool *pool) 18114562236bSHarry Wentland { 18124562236bSHarry Wentland int i; 1813a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 18149037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 18154562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 18169037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 18174562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 18183722c794SMikita Lipski struct dce_watermarks min_marks = { 0, 0, 0, 0}; 18194562236bSHarry Wentland 18204562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 18218feabd03SYue Hin Lau if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 18224562236bSHarry Wentland continue; 18234562236bSHarry Wentland 182486a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 182586a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 18264562236bSHarry Wentland nbp_marks, 18274562236bSHarry Wentland max_marks, 18283722c794SMikita Lipski min_marks, 18294562236bSHarry Wentland max_marks, 18304562236bSHarry Wentland MAX_WATERMARK); 18318feabd03SYue Hin Lau 18324562236bSHarry Wentland if (i == underlay_idx) 183386a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 183486a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 18354562236bSHarry Wentland nbp_marks, 18364562236bSHarry Wentland max_marks, 18374562236bSHarry Wentland max_marks, 18384562236bSHarry Wentland MAX_WATERMARK); 18398feabd03SYue Hin Lau 18404562236bSHarry Wentland } 18414562236bSHarry Wentland } 18424562236bSHarry Wentland 18434562236bSHarry Wentland /******************************************************************************* 18444562236bSHarry Wentland * Public functions 18454562236bSHarry Wentland ******************************************************************************/ 18464562236bSHarry Wentland 18474562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 184849c70eceSAlvin Lee int num_pipes, struct dc_crtc_timing_adjust adjust) 18494562236bSHarry Wentland { 18504562236bSHarry Wentland int i = 0; 18514562236bSHarry Wentland struct drr_params params = {0}; 185298e6436dSAnthony Koo // DRR should set trigger event to monitor surface update event 185398e6436dSAnthony Koo unsigned int event_triggers = 0x80; 18545b5abe95SAnthony Koo // Note DRR trigger events are generated regardless of whether num frames met. 18555b5abe95SAnthony Koo unsigned int num_frames = 2; 18564562236bSHarry Wentland 185749c70eceSAlvin Lee params.vertical_total_max = adjust.v_total_max; 185849c70eceSAlvin Lee params.vertical_total_min = adjust.v_total_min; 18594562236bSHarry Wentland 18604562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 186198e6436dSAnthony Koo * some GSL stuff. Static screen triggers may be programmed differently 186298e6436dSAnthony Koo * as well. 18634562236bSHarry Wentland */ 18644562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 186598e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_drr( 186698e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, ¶ms); 186798e6436dSAnthony Koo 186849c70eceSAlvin Lee if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 186998e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 187098e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, 18715b5abe95SAnthony Koo event_triggers, num_frames); 18724562236bSHarry Wentland } 18734562236bSHarry Wentland } 18744562236bSHarry Wentland 187572ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 187672ada5f7SEric Cook int num_pipes, 187772ada5f7SEric Cook struct crtc_position *position) 187872ada5f7SEric Cook { 187972ada5f7SEric Cook int i = 0; 188072ada5f7SEric Cook 188172ada5f7SEric Cook /* TODO: handle pipes > 1 188272ada5f7SEric Cook */ 188372ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 18846b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 188572ada5f7SEric Cook } 188672ada5f7SEric Cook 18874562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 18885b5abe95SAnthony Koo int num_pipes, const struct dc_static_screen_params *params) 18894562236bSHarry Wentland { 18904562236bSHarry Wentland unsigned int i; 18915b5abe95SAnthony Koo unsigned int triggers = 0; 189294267b3dSSylvia Tsai 18935b5abe95SAnthony Koo if (params->triggers.overlay_update) 18945b5abe95SAnthony Koo triggers |= 0x100; 18955b5abe95SAnthony Koo if (params->triggers.surface_update) 18965b5abe95SAnthony Koo triggers |= 0x80; 18975b5abe95SAnthony Koo if (params->triggers.cursor_update) 18985b5abe95SAnthony Koo triggers |= 0x2; 18995b5abe95SAnthony Koo if (params->triggers.force_trigger) 19005b5abe95SAnthony Koo triggers |= 0x1; 19014562236bSHarry Wentland 1902593f79a2SAlex Deucher if (num_pipes) { 1903593f79a2SAlex Deucher struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1904593f79a2SAlex Deucher 1905593f79a2SAlex Deucher if (dc->fbc_compressor) 19065b5abe95SAnthony Koo triggers |= 0x84; 1907593f79a2SAlex Deucher } 1908c3aa1d67SBhawanpreet Lakha 19094562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 19106b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs-> 19115b5abe95SAnthony Koo set_static_screen_control(pipe_ctx[i]->stream_res.tg, 19125b5abe95SAnthony Koo triggers, params->num_frames); 19134562236bSHarry Wentland } 19144562236bSHarry Wentland 1915f6baff4dSHarry Wentland /* 1916690b5e39SRoman Li * Check if FBC can be enabled 1917690b5e39SRoman Li */ 19189c6569deSHarry Wentland static bool should_enable_fbc(struct dc *dc, 19193bc4aaa9SRoman Li struct dc_state *context, 19203bc4aaa9SRoman Li uint32_t *pipe_idx) 1921690b5e39SRoman Li { 19223bc4aaa9SRoman Li uint32_t i; 19233bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = NULL; 19243bc4aaa9SRoman Li struct resource_context *res_ctx = &context->res_ctx; 192565d38262Shersen wu unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 19263bc4aaa9SRoman Li 1927690b5e39SRoman Li 1928690b5e39SRoman Li ASSERT(dc->fbc_compressor); 1929690b5e39SRoman Li 1930690b5e39SRoman Li /* FBC memory should be allocated */ 1931690b5e39SRoman Li if (!dc->ctx->fbc_gpu_addr) 19329c6569deSHarry Wentland return false; 1933690b5e39SRoman Li 1934690b5e39SRoman Li /* Only supports single display */ 1935690b5e39SRoman Li if (context->stream_count != 1) 19369c6569deSHarry Wentland return false; 1937690b5e39SRoman Li 19383bc4aaa9SRoman Li for (i = 0; i < dc->res_pool->pipe_count; i++) { 19393bc4aaa9SRoman Li if (res_ctx->pipe_ctx[i].stream) { 194065d38262Shersen wu 19413bc4aaa9SRoman Li pipe_ctx = &res_ctx->pipe_ctx[i]; 194265d38262Shersen wu 194365d38262Shersen wu if (!pipe_ctx) 194465d38262Shersen wu continue; 194565d38262Shersen wu 194665d38262Shersen wu /* fbc not applicable on underlay pipe */ 194765d38262Shersen wu if (pipe_ctx->pipe_idx != underlay_idx) { 19483bc4aaa9SRoman Li *pipe_idx = i; 19493bc4aaa9SRoman Li break; 19503bc4aaa9SRoman Li } 19513bc4aaa9SRoman Li } 195265d38262Shersen wu } 19533bc4aaa9SRoman Li 195465d38262Shersen wu if (i == dc->res_pool->pipe_count) 195565d38262Shersen wu return false; 195665d38262Shersen wu 1957ceb3dbb4SJun Lei if (!pipe_ctx->stream->link) 195865d38262Shersen wu return false; 19597a840773SRoman Li 1960690b5e39SRoman Li /* Only supports eDP */ 1961ceb3dbb4SJun Lei if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 19629c6569deSHarry Wentland return false; 1963690b5e39SRoman Li 1964690b5e39SRoman Li /* PSR should not be enabled */ 1965d1ebfdd8SWyatt Wood if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 19669c6569deSHarry Wentland return false; 1967690b5e39SRoman Li 196893984bbcSShirish S /* Nothing to compress */ 196993984bbcSShirish S if (!pipe_ctx->plane_state) 19709c6569deSHarry Wentland return false; 197193984bbcSShirish S 197205230fa9SRoman Li /* Only for non-linear tiling */ 197305230fa9SRoman Li if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 19749c6569deSHarry Wentland return false; 197505230fa9SRoman Li 19769c6569deSHarry Wentland return true; 1977690b5e39SRoman Li } 1978690b5e39SRoman Li 1979690b5e39SRoman Li /* 1980690b5e39SRoman Li * Enable FBC 1981690b5e39SRoman Li */ 198265d38262Shersen wu static void enable_fbc( 198365d38262Shersen wu struct dc *dc, 1984608ac7bbSJerry Zuo struct dc_state *context) 1985690b5e39SRoman Li { 19863bc4aaa9SRoman Li uint32_t pipe_idx = 0; 19873bc4aaa9SRoman Li 19883bc4aaa9SRoman Li if (should_enable_fbc(dc, context, &pipe_idx)) { 1989690b5e39SRoman Li /* Program GRPH COMPRESSED ADDRESS and PITCH */ 1990690b5e39SRoman Li struct compr_addr_and_pitch_params params = {0, 0, 0}; 1991690b5e39SRoman Li struct compressor *compr = dc->fbc_compressor; 19923bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 19933bc4aaa9SRoman Li 19949c6569deSHarry Wentland params.source_view_width = pipe_ctx->stream->timing.h_addressable; 19959c6569deSHarry Wentland params.source_view_height = pipe_ctx->stream->timing.v_addressable; 199665d38262Shersen wu params.inst = pipe_ctx->stream_res.tg->inst; 1997690b5e39SRoman Li compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 1998690b5e39SRoman Li 1999690b5e39SRoman Li compr->funcs->surface_address_and_pitch(compr, ¶ms); 2000690b5e39SRoman Li compr->funcs->set_fbc_invalidation_triggers(compr, 1); 2001690b5e39SRoman Li 2002690b5e39SRoman Li compr->funcs->enable_fbc(compr, ¶ms); 2003690b5e39SRoman Li } 2004690b5e39SRoman Li } 2005690b5e39SRoman Li 200654e8695eSDmytro Laktyushkin static void dce110_reset_hw_ctx_wrap( 2007fb3466a4SBhawanpreet Lakha struct dc *dc, 2008608ac7bbSJerry Zuo struct dc_state *context) 20094562236bSHarry Wentland { 20104562236bSHarry Wentland int i; 20114562236bSHarry Wentland 20124562236bSHarry Wentland /* Reset old context */ 20134562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 2014a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 20154562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2016608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 20174562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 20184562236bSHarry Wentland 20194562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 20204562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 20214562236bSHarry Wentland * PHY when not already disabled. 20224562236bSHarry Wentland */ 20234562236bSHarry Wentland 20244562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 20254562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 20264562236bSHarry Wentland continue; 20274562236bSHarry Wentland 20284562236bSHarry Wentland if (!pipe_ctx->stream || 202954e8695eSDmytro Laktyushkin pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 203021e67d4dSHarry Wentland struct clock_source *old_clk = pipe_ctx_old->clock_source; 203121e67d4dSHarry Wentland 2032827f11e9SLeo (Sunpeng) Li /* Disable if new stream is null. O/w, if stream is 2033827f11e9SLeo (Sunpeng) Li * disabled already, no need to disable again. 2034827f11e9SLeo (Sunpeng) Li */ 203557430404SSu Sung Chung if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 203657430404SSu Sung Chung core_link_disable_stream(pipe_ctx_old); 203757430404SSu Sung Chung 203857430404SSu Sung Chung /* free acquired resources*/ 203957430404SSu Sung Chung if (pipe_ctx_old->stream_res.audio) { 204057430404SSu Sung Chung /*disable az_endpoint*/ 204157430404SSu Sung Chung pipe_ctx_old->stream_res.audio->funcs-> 204257430404SSu Sung Chung az_disable(pipe_ctx_old->stream_res.audio); 204357430404SSu Sung Chung 204457430404SSu Sung Chung /*free audio*/ 204557430404SSu Sung Chung if (dc->caps.dynamic_audio == true) { 204657430404SSu Sung Chung /*we have to dynamic arbitrate the audio endpoints*/ 204757430404SSu Sung Chung /*we free the resource, need reset is_audio_acquired*/ 204857430404SSu Sung Chung update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 204957430404SSu Sung Chung pipe_ctx_old->stream_res.audio, false); 205057430404SSu Sung Chung pipe_ctx_old->stream_res.audio = NULL; 205157430404SSu Sung Chung } 205257430404SSu Sung Chung } 205357430404SSu Sung Chung } 2054d050f8edSHersen Wu 20556b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 20566b670fa9SHarry Wentland if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 205754e8695eSDmytro Laktyushkin dm_error("DC: failed to blank crtc!\n"); 205854e8695eSDmytro Laktyushkin BREAK_TO_DEBUGGER(); 205954e8695eSDmytro Laktyushkin } 20606b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 206186a66c4eSHarry Wentland pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2062608ac7bbSJerry Zuo pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 206354e8695eSDmytro Laktyushkin 2064ad8960a6SMikita Lipski if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2065ad8960a6SMikita Lipski dc->res_pool, 2066ad8960a6SMikita Lipski old_clk)) 206721e67d4dSHarry Wentland old_clk->funcs->cs_power_down(old_clk); 206821e67d4dSHarry Wentland 20697f914a62SYongqiang Sun dc->hwss.disable_plane(dc, pipe_ctx_old); 207054e8695eSDmytro Laktyushkin 207154e8695eSDmytro Laktyushkin pipe_ctx_old->stream = NULL; 207254e8695eSDmytro Laktyushkin } 20734562236bSHarry Wentland } 20744562236bSHarry Wentland } 20754562236bSHarry Wentland 20761a05873fSAnthony Koo static void dce110_setup_audio_dto( 20771a05873fSAnthony Koo struct dc *dc, 20781a05873fSAnthony Koo struct dc_state *context) 20791a05873fSAnthony Koo { 20801a05873fSAnthony Koo int i; 20811a05873fSAnthony Koo 20821a05873fSAnthony Koo /* program audio wall clock. use HDMI as clock source if HDMI 20831a05873fSAnthony Koo * audio active. Otherwise, use DP as clock source 20841a05873fSAnthony Koo * first, loop to find any HDMI audio, if not, loop find DP audio 20851a05873fSAnthony Koo */ 20861a05873fSAnthony Koo /* Setup audio rate clock source */ 20871a05873fSAnthony Koo /* Issue: 20881a05873fSAnthony Koo * Audio lag happened on DP monitor when unplug a HDMI monitor 20891a05873fSAnthony Koo * 20901a05873fSAnthony Koo * Cause: 20911a05873fSAnthony Koo * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 20921a05873fSAnthony Koo * is set to either dto0 or dto1, audio should work fine. 20931a05873fSAnthony Koo * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 20941a05873fSAnthony Koo * set to dto0 will cause audio lag. 20951a05873fSAnthony Koo * 20961a05873fSAnthony Koo * Solution: 20971a05873fSAnthony Koo * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 20981a05873fSAnthony Koo * find first available pipe with audio, setup audio wall DTO per topology 20991a05873fSAnthony Koo * instead of per pipe. 21001a05873fSAnthony Koo */ 21011a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 21021a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 21031a05873fSAnthony Koo 21041a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 21051a05873fSAnthony Koo continue; 21061a05873fSAnthony Koo 21071a05873fSAnthony Koo if (pipe_ctx->top_pipe) 21081a05873fSAnthony Koo continue; 21091a05873fSAnthony Koo if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 21101a05873fSAnthony Koo continue; 21111a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 21121a05873fSAnthony Koo struct audio_output audio_output; 21131a05873fSAnthony Koo 21141a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 21151a05873fSAnthony Koo 21168fe44c08SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 211764b1d0e8SNicholas Kazlauskas /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */ 211864b1d0e8SNicholas Kazlauskas if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 211964b1d0e8SNicholas Kazlauskas /* disable audio DTBCLK DTO */ 212064b1d0e8SNicholas Kazlauskas dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 212164b1d0e8SNicholas Kazlauskas dc->res_pool->dccg, 0); 212264b1d0e8SNicholas Kazlauskas 21231a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 21241a05873fSAnthony Koo pipe_ctx->stream_res.audio, 21251a05873fSAnthony Koo pipe_ctx->stream->signal, 21261a05873fSAnthony Koo &audio_output.crtc_info, 21271a05873fSAnthony Koo &audio_output.pll_info); 212864b1d0e8SNicholas Kazlauskas } else 212964b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 213064b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, 213164b1d0e8SNicholas Kazlauskas pipe_ctx->stream->signal, 213264b1d0e8SNicholas Kazlauskas &audio_output.crtc_info, 213364b1d0e8SNicholas Kazlauskas &audio_output.pll_info); 213464b1d0e8SNicholas Kazlauskas #else 213564b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 213664b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, 213764b1d0e8SNicholas Kazlauskas pipe_ctx->stream->signal, 213864b1d0e8SNicholas Kazlauskas &audio_output.crtc_info, 213964b1d0e8SNicholas Kazlauskas &audio_output.pll_info); 214064b1d0e8SNicholas Kazlauskas #endif 21411a05873fSAnthony Koo break; 21421a05873fSAnthony Koo } 21431a05873fSAnthony Koo } 21441a05873fSAnthony Koo 21451a05873fSAnthony Koo /* no HDMI audio is found, try DP audio */ 21461a05873fSAnthony Koo if (i == dc->res_pool->pipe_count) { 21471a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 21481a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 21491a05873fSAnthony Koo 21501a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 21511a05873fSAnthony Koo continue; 21521a05873fSAnthony Koo 21531a05873fSAnthony Koo if (pipe_ctx->top_pipe) 21541a05873fSAnthony Koo continue; 21551a05873fSAnthony Koo 21561a05873fSAnthony Koo if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 21571a05873fSAnthony Koo continue; 21581a05873fSAnthony Koo 21591a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 21601a05873fSAnthony Koo struct audio_output audio_output; 21611a05873fSAnthony Koo 21621a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 21631a05873fSAnthony Koo 21641a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 21651a05873fSAnthony Koo pipe_ctx->stream_res.audio, 21661a05873fSAnthony Koo pipe_ctx->stream->signal, 21671a05873fSAnthony Koo &audio_output.crtc_info, 21681a05873fSAnthony Koo &audio_output.pll_info); 21691a05873fSAnthony Koo break; 21701a05873fSAnthony Koo } 21711a05873fSAnthony Koo } 21721a05873fSAnthony Koo } 21731a05873fSAnthony Koo } 2174cf437593SDmytro Laktyushkin 21754562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 2176fb3466a4SBhawanpreet Lakha struct dc *dc, 2177608ac7bbSJerry Zuo struct dc_state *context) 21784562236bSHarry Wentland { 2179f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 21804562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 21814562236bSHarry Wentland enum dc_status status; 21824562236bSHarry Wentland int i; 21834562236bSHarry Wentland 21844562236bSHarry Wentland /* Reset old context */ 21854562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 2186f42ea55bSAnthony Koo hws->funcs.reset_hw_ctx_wrap(dc, context); 21874562236bSHarry Wentland 21884562236bSHarry Wentland /* Skip applying if no targets */ 2189ab2541b6SAric Cyr if (context->stream_count <= 0) 21904562236bSHarry Wentland return DC_OK; 21914562236bSHarry Wentland 21924562236bSHarry Wentland /* Apply new context */ 21934562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 21944562236bSHarry Wentland 21954562236bSHarry Wentland /* below is for real asic only */ 2196a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 21974562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2198608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 21994562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 22004562236bSHarry Wentland 22014562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 22024562236bSHarry Wentland continue; 22034562236bSHarry Wentland 22044562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 22054562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 22064562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 22074562236bSHarry Wentland pipe_ctx->clock_source, i); 22084562236bSHarry Wentland continue; 22094562236bSHarry Wentland } 22104562236bSHarry Wentland 2211f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 22124562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 22134562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 22144562236bSHarry Wentland } 22154562236bSHarry Wentland 22162f3bfb27SRoman Li if (dc->fbc_compressor) 22171663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 22185099114bSAlex Deucher 22191a05873fSAnthony Koo dce110_setup_audio_dto(dc, context); 2220ab8812a3SHersen Wu 2221a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2222ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 2223608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 2224ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2225ab8812a3SHersen Wu 2226ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2227ab8812a3SHersen Wu continue; 2228ab8812a3SHersen Wu 2229eed928dcSCharlene Liu if (pipe_ctx->stream == pipe_ctx_old->stream && 2230eed928dcSCharlene Liu pipe_ctx->stream->link->link_state_valid) { 2231ab8812a3SHersen Wu continue; 2232eed928dcSCharlene Liu } 2233ab8812a3SHersen Wu 22345b92d9d4SHarry Wentland if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2235313bf4ffSYongqiang Sun continue; 2236313bf4ffSYongqiang Sun 2237b1f6d01cSDmytro Laktyushkin if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2238ab8812a3SHersen Wu continue; 2239ab8812a3SHersen Wu 22404562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 22414562236bSHarry Wentland pipe_ctx, 22424562236bSHarry Wentland context, 22434562236bSHarry Wentland dc); 22444562236bSHarry Wentland 22454562236bSHarry Wentland if (DC_OK != status) 22464562236bSHarry Wentland return status; 22474562236bSHarry Wentland } 22484562236bSHarry Wentland 2249690b5e39SRoman Li if (dc->fbc_compressor) 225065d38262Shersen wu enable_fbc(dc, dc->current_state); 225165d38262Shersen wu 225265d38262Shersen wu dcb->funcs->set_scratch_critical_state(dcb, false); 2253690b5e39SRoman Li 22544562236bSHarry Wentland return DC_OK; 22554562236bSHarry Wentland } 22564562236bSHarry Wentland 22574562236bSHarry Wentland /******************************************************************************* 22584562236bSHarry Wentland * Front End programming 22594562236bSHarry Wentland ******************************************************************************/ 22604562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 22614562236bSHarry Wentland { 22624562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 22634562236bSHarry Wentland 22644562236bSHarry Wentland default_adjust.force_hw_default = false; 226534996173SHarry Wentland default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 226634996173SHarry Wentland default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 22674562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 22686702a9acSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 22694562236bSHarry Wentland 22704562236bSHarry Wentland /* display color depth */ 22714562236bSHarry Wentland default_adjust.color_depth = 22724fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.display_color_depth; 22734562236bSHarry Wentland 22744562236bSHarry Wentland /* Lb color depth */ 22756702a9acSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 22764562236bSHarry Wentland 227786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 227886a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, &default_adjust); 22794562236bSHarry Wentland } 22804562236bSHarry Wentland 2281b06b7680SLeon Elazar 2282b06b7680SLeon Elazar /******************************************************************************* 2283b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 2284b06b7680SLeon Elazar * Blender + CRTC 2285b06b7680SLeon Elazar * 2286b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 2287b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 2288b06b7680SLeon Elazar * 2289b06b7680SLeon Elazar * |----------------------------------------------- | 2290b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 2291b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 2292b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 2293b06b7680SLeon Elazar * |------------------------------------------------| 2294b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 2295b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 2296b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 2297b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 2298b06b7680SLeon Elazar * -------------------------------------------------| 2299b06b7680SLeon Elazar * 2300b06b7680SLeon Elazar ******************************************************************************/ 2301fb3466a4SBhawanpreet Lakha static void program_surface_visibility(const struct dc *dc, 23024562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 23034562236bSHarry Wentland { 23044562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2305b06b7680SLeon Elazar bool blank_target = false; 23064562236bSHarry Wentland 23074562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 2308b06b7680SLeon Elazar 2309b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 2310b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2311b06b7680SLeon Elazar 23123be5262eSHarry Wentland if (pipe_ctx->bottom_pipe->plane_state->visible) { 23133be5262eSHarry Wentland if (pipe_ctx->plane_state->visible) 23144562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 23154562236bSHarry Wentland else 23164562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 2317b06b7680SLeon Elazar 23183be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2319b06b7680SLeon Elazar blank_target = true; 2320b06b7680SLeon Elazar 23213be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2322b06b7680SLeon Elazar blank_target = true; 2323b06b7680SLeon Elazar 2324e07f541fSYongqiang Sun dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 23256b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2326b06b7680SLeon Elazar 23274562236bSHarry Wentland } 23284562236bSHarry Wentland 23291bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 23301bf56e62SZeyu Fan { 2331146a9f63SKrunoslav Kovac int i = 0; 23321bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 23331bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 23341bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 23351bf56e62SZeyu Fan 23361bf56e62SZeyu Fan 23374fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 23381bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2339146a9f63SKrunoslav Kovac 2340146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2341146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2342146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 23431bf56e62SZeyu Fan } 23441bf56e62SZeyu Fan 234586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 23461bf56e62SZeyu Fan } 2347fb3466a4SBhawanpreet Lakha static void update_plane_addr(const struct dc *dc, 23484562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 23494562236bSHarry Wentland { 23503be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 23514562236bSHarry Wentland 23523be5262eSHarry Wentland if (plane_state == NULL) 23534562236bSHarry Wentland return; 23544562236bSHarry Wentland 235586a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 235686a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 23573be5262eSHarry Wentland &plane_state->address, 23583be5262eSHarry Wentland plane_state->flip_immediate); 23594562236bSHarry Wentland 23603be5262eSHarry Wentland plane_state->status.requested_address = plane_state->address; 23614562236bSHarry Wentland } 23624562236bSHarry Wentland 2363f774b339SEric Yang static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 23644562236bSHarry Wentland { 23653be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 23664562236bSHarry Wentland 23673be5262eSHarry Wentland if (plane_state == NULL) 23684562236bSHarry Wentland return; 23694562236bSHarry Wentland 23703be5262eSHarry Wentland plane_state->status.is_flip_pending = 237186a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 237286a66c4eSHarry Wentland pipe_ctx->plane_res.mi); 23734562236bSHarry Wentland 23743be5262eSHarry Wentland if (plane_state->status.is_flip_pending && !plane_state->visible) 237586a66c4eSHarry Wentland pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 23764562236bSHarry Wentland 237786a66c4eSHarry Wentland plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 237886a66c4eSHarry Wentland if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 23796b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 23803be5262eSHarry Wentland plane_state->status.is_right_eye =\ 23816b670fa9SHarry Wentland !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 23827f5c22d1SVitaly Prosyak } 23834562236bSHarry Wentland } 23844562236bSHarry Wentland 2385fb3466a4SBhawanpreet Lakha void dce110_power_down(struct dc *dc) 23864562236bSHarry Wentland { 23874562236bSHarry Wentland power_down_all_hw_blocks(dc); 23884562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 23894562236bSHarry Wentland } 23904562236bSHarry Wentland 23914562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 23924562236bSHarry Wentland struct dc_context *dc_ctx, 23934562236bSHarry Wentland struct timing_generator *tg) 23944562236bSHarry Wentland { 23954562236bSHarry Wentland bool rc = false; 23964562236bSHarry Wentland 23974562236bSHarry Wentland /* To avoid endless loop we wait at most 23984562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 23994562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 24004562236bSHarry Wentland uint32_t i; 24014562236bSHarry Wentland 24024562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 24034562236bSHarry Wentland 24044562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 24054562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 24064562236bSHarry Wentland break; 24074562236bSHarry Wentland } 24084562236bSHarry Wentland 24094562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 24104562236bSHarry Wentland rc = true; 24114562236bSHarry Wentland /* usually occurs at i=1 */ 24124562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 24134562236bSHarry Wentland i); 24144562236bSHarry Wentland break; 24154562236bSHarry Wentland } 24164562236bSHarry Wentland 24174562236bSHarry Wentland /* Wait for one frame. */ 24184562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 24194562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 24204562236bSHarry Wentland } 24214562236bSHarry Wentland 24224562236bSHarry Wentland if (false == rc) 24234562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 24244562236bSHarry Wentland 24254562236bSHarry Wentland return rc; 24264562236bSHarry Wentland } 24274562236bSHarry Wentland 24284562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 24294562236bSHarry Wentland static void dce110_enable_timing_synchronization( 2430fb3466a4SBhawanpreet Lakha struct dc *dc, 24314562236bSHarry Wentland int group_index, 24324562236bSHarry Wentland int group_size, 24334562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 24344562236bSHarry Wentland { 24354562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 24364562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 24374562236bSHarry Wentland int i; 24384562236bSHarry Wentland 24394562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 24404562236bSHarry Wentland 24414562236bSHarry Wentland /* Designate a single TG in the group as a master. 24424562236bSHarry Wentland * Since HW doesn't care which one, we always assign 24434562236bSHarry Wentland * the 1st one in the group. */ 24444562236bSHarry Wentland gsl_params.gsl_group = 0; 24456b670fa9SHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 24464562236bSHarry Wentland 24474562236bSHarry Wentland for (i = 0; i < group_size; i++) 24486b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 24496b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg, &gsl_params); 24504562236bSHarry Wentland 24514562236bSHarry Wentland /* Reset slave controllers on master VSync */ 24524562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 24534562236bSHarry Wentland 24544562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 24556b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2456fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2457fa2123dbSMikita Lipski gsl_params.gsl_group); 24584562236bSHarry Wentland 24594562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 24604562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 24616b670fa9SHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2462fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2463fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg); 24644562236bSHarry Wentland } 24654562236bSHarry Wentland 24664562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 24674562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 24684562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 24694562236bSHarry Wentland for (i = 0; i < group_size; i++) 24706b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 24714562236bSHarry Wentland 24724562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 24734562236bSHarry Wentland } 24744562236bSHarry Wentland 2475fa2123dbSMikita Lipski static void dce110_enable_per_frame_crtc_position_reset( 2476fa2123dbSMikita Lipski struct dc *dc, 2477fa2123dbSMikita Lipski int group_size, 2478fa2123dbSMikita Lipski struct pipe_ctx *grouped_pipes[]) 2479fa2123dbSMikita Lipski { 2480fa2123dbSMikita Lipski struct dc_context *dc_ctx = dc->ctx; 2481fa2123dbSMikita Lipski struct dcp_gsl_params gsl_params = { 0 }; 2482fa2123dbSMikita Lipski int i; 2483fa2123dbSMikita Lipski 2484fa2123dbSMikita Lipski gsl_params.gsl_group = 0; 248537cd85ceSDavid Francis gsl_params.gsl_master = 0; 2486fa2123dbSMikita Lipski 2487fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2488fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2489fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, &gsl_params); 2490fa2123dbSMikita Lipski 2491fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2492fa2123dbSMikita Lipski 2493fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2494fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2495fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2496fa2123dbSMikita Lipski gsl_params.gsl_master, 2497fa2123dbSMikita Lipski &grouped_pipes[i]->stream->triggered_crtc_reset); 2498fa2123dbSMikita Lipski 2499fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2500fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2501fa2123dbSMikita Lipski wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2502fa2123dbSMikita Lipski 2503fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2504fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2505fa2123dbSMikita Lipski 2506fa2123dbSMikita Lipski } 2507fa2123dbSMikita Lipski 2508fb55546eSAnthony Koo static void init_pipes(struct dc *dc, struct dc_state *context) 2509fb55546eSAnthony Koo { 2510fb55546eSAnthony Koo // Do nothing 2511fb55546eSAnthony Koo } 2512fb55546eSAnthony Koo 2513fb3466a4SBhawanpreet Lakha static void init_hw(struct dc *dc) 25144562236bSHarry Wentland { 25154562236bSHarry Wentland int i; 25164562236bSHarry Wentland struct dc_bios *bp; 25174562236bSHarry Wentland struct transform *xfm; 25185e7773a2SAnthony Koo struct abm *abm; 251970d9e8cbSPaul Hsieh struct dmcu *dmcu; 2520f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 25213ba01817SYongqiang Sun uint32_t backlight = MAX_BACKLIGHT_LEVEL; 25224562236bSHarry Wentland 25234562236bSHarry Wentland bp = dc->ctx->dc_bios; 25244562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 25254562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 25264562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 25274562236bSHarry Wentland 2528f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 25294562236bSHarry Wentland dc, i, bp, 25304562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 2531f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 25324562236bSHarry Wentland dc, i, bp, 25334562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 2534f42ea55bSAnthony Koo hws->funcs.enable_display_pipe_clock_gating( 25354562236bSHarry Wentland dc->ctx, 25364562236bSHarry Wentland true); 25374562236bSHarry Wentland } 25384562236bSHarry Wentland 2539e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 25404562236bSHarry Wentland /***************************************/ 25414562236bSHarry Wentland 25424562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 25434562236bSHarry Wentland /****************************************/ 25444562236bSHarry Wentland /* Power up AND update implementation according to the 25454562236bSHarry Wentland * required signal (which may be different from the 25464562236bSHarry Wentland * default signal on connector). */ 2547d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 2548069d418fSAndrew Jiang 25494562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 25504562236bSHarry Wentland } 25514562236bSHarry Wentland 25524562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 25534562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 25544562236bSHarry Wentland 25554562236bSHarry Wentland tg->funcs->disable_vga(tg); 25564562236bSHarry Wentland 25574562236bSHarry Wentland /* Blank controller using driver code instead of 25584562236bSHarry Wentland * command table. */ 25594562236bSHarry Wentland tg->funcs->set_blank(tg, true); 25604b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 25614562236bSHarry Wentland } 25624562236bSHarry Wentland 25634562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 25644562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 25654562236bSHarry Wentland audio->funcs->hw_init(audio); 25664562236bSHarry Wentland } 25675e7773a2SAnthony Koo 25683ba01817SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 25693ba01817SYongqiang Sun struct dc_link *link = dc->links[i]; 25703ba01817SYongqiang Sun 25713ba01817SYongqiang Sun if (link->panel_cntl) 25723ba01817SYongqiang Sun backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 25734562236bSHarry Wentland } 25745099114bSAlex Deucher 25753ba01817SYongqiang Sun abm = dc->res_pool->abm; 25763ba01817SYongqiang Sun if (abm != NULL) 25773ba01817SYongqiang Sun abm->funcs->abm_init(abm, backlight); 25783ba01817SYongqiang Sun 257970d9e8cbSPaul Hsieh dmcu = dc->res_pool->dmcu; 258070d9e8cbSPaul Hsieh if (dmcu != NULL && abm != NULL) 258170d9e8cbSPaul Hsieh abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 258270d9e8cbSPaul Hsieh 25832f3bfb27SRoman Li if (dc->fbc_compressor) 25841663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2585690b5e39SRoman Li 25866728b30cSAnthony Koo } 25874562236bSHarry Wentland 25889566b675SDmytro Laktyushkin 25899566b675SDmytro Laktyushkin void dce110_prepare_bandwidth( 2590fb3466a4SBhawanpreet Lakha struct dc *dc, 25919566b675SDmytro Laktyushkin struct dc_state *context) 2592cf437593SDmytro Laktyushkin { 2593dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 2594fab55d61SDmytro Laktyushkin 2595fab55d61SDmytro Laktyushkin dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2596cf437593SDmytro Laktyushkin 25975a83c932SNicholas Kazlauskas dccg->funcs->update_clocks( 25985a83c932SNicholas Kazlauskas dccg, 259924f7dd7eSDmytro Laktyushkin context, 26009566b675SDmytro Laktyushkin false); 26019566b675SDmytro Laktyushkin } 26029566b675SDmytro Laktyushkin 26039566b675SDmytro Laktyushkin void dce110_optimize_bandwidth( 26049566b675SDmytro Laktyushkin struct dc *dc, 26059566b675SDmytro Laktyushkin struct dc_state *context) 26069566b675SDmytro Laktyushkin { 2607dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 26089566b675SDmytro Laktyushkin 26099566b675SDmytro Laktyushkin dce110_set_displaymarks(dc, context); 26109566b675SDmytro Laktyushkin 26119566b675SDmytro Laktyushkin dccg->funcs->update_clocks( 26129566b675SDmytro Laktyushkin dccg, 26139566b675SDmytro Laktyushkin context, 26149566b675SDmytro Laktyushkin true); 26154562236bSHarry Wentland } 26164562236bSHarry Wentland 26174562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 2618fb3466a4SBhawanpreet Lakha struct dc *dc, struct pipe_ctx *pipe_ctx) 26194562236bSHarry Wentland { 262086a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 26213be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 26224562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 26234562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 26244562236bSHarry Wentland unsigned int i; 2625f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2626f42ea55bSAnthony Koo 26275d4b05ddSBhawanpreet Lakha DC_LOGGER_INIT(); 26284562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 26294562236bSHarry Wentland 26304562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 26314562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 26324562236bSHarry Wentland 2633e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 26344562236bSHarry Wentland 26354562236bSHarry Wentland set_default_colors(pipe_ctx); 26364fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 26374562236bSHarry Wentland == true) { 26384562236bSHarry Wentland tbl_entry.color_space = 26394fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 26404562236bSHarry Wentland 26414562236bSHarry Wentland for (i = 0; i < 12; i++) 26424562236bSHarry Wentland tbl_entry.regval[i] = 26434fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 26444562236bSHarry Wentland 264586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 264686a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 26474562236bSHarry Wentland } 26484562236bSHarry Wentland 26494fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 26504562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2651146a9f63SKrunoslav Kovac 2652146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2653146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2654146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 26554562236bSHarry Wentland } 26564562236bSHarry Wentland 265786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 26584562236bSHarry Wentland 26596702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2660c1473558SAndrey Grodzovsky 26614562236bSHarry Wentland program_scaler(dc, pipe_ctx); 26624562236bSHarry Wentland 26634562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 26644562236bSHarry Wentland mi, 26653be5262eSHarry Wentland plane_state->format, 26663be5262eSHarry Wentland &plane_state->tiling_info, 26673be5262eSHarry Wentland &plane_state->plane_size, 26683be5262eSHarry Wentland plane_state->rotation, 2669624d7c47SYongqiang Sun NULL, 26704b28b76bSDmytro Laktyushkin false); 26714b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 26723be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 26734562236bSHarry Wentland 2674fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 26754562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 267686a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 26773be5262eSHarry Wentland plane_state->format, 26783be5262eSHarry Wentland &plane_state->tiling_info, 26793be5262eSHarry Wentland plane_state->rotation); 26804562236bSHarry Wentland 2681067c878aSYongqiang Sun /* Moved programming gamma from dc to hwss */ 2682405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update || 2683405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2684405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.gamma_change) 2685f42ea55bSAnthony Koo hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2686405c50a0SAndrew Jiang 2687405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update) 2688f42ea55bSAnthony Koo hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2689067c878aSYongqiang Sun 26901296423bSBhawanpreet Lakha DC_LOG_SURFACE( 26913032deb5SBhawanpreet Lakha "Pipe:%d %p: addr hi:0x%x, " 26924562236bSHarry Wentland "addr low:0x%x, " 26934562236bSHarry Wentland "src: %d, %d, %d," 26944562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 26954562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 26964562236bSHarry Wentland pipe_ctx->pipe_idx, 26973032deb5SBhawanpreet Lakha (void *) pipe_ctx->plane_state, 26983be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.high_part, 26993be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.low_part, 27003be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.x, 27013be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.y, 27023be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.width, 27033be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.height, 27043be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.x, 27053be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.y, 27063be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.width, 27073be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.height, 27083be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.x, 27093be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.y, 27103be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.width, 27113be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.height); 27124562236bSHarry Wentland 27131296423bSBhawanpreet Lakha DC_LOG_SURFACE( 27144562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 27154562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 27164562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 27174562236bSHarry Wentland pipe_ctx->pipe_idx, 27186702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.width, 27196702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.height, 27206702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.x, 27216702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.y, 27226702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.width, 27236702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.height, 27246702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.x, 27256702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.y); 27264562236bSHarry Wentland } 27274562236bSHarry Wentland 27284562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 2729fb3466a4SBhawanpreet Lakha struct dc *dc, 27303e9ad616SEric Yang const struct dc_stream_state *stream, 27313e9ad616SEric Yang int num_planes, 2732608ac7bbSJerry Zuo struct dc_state *context) 27334562236bSHarry Wentland { 27342194e3aeSRoman Li int i; 27354562236bSHarry Wentland 27363e9ad616SEric Yang if (num_planes == 0) 27374562236bSHarry Wentland return; 27384562236bSHarry Wentland 273965d38262Shersen wu if (dc->fbc_compressor) 274065d38262Shersen wu dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 274165d38262Shersen wu 27423e9ad616SEric Yang for (i = 0; i < dc->res_pool->pipe_count; i++) { 27433dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 27444562236bSHarry Wentland 2745a2607aefSHarry Wentland if (pipe_ctx->stream != stream) 27464562236bSHarry Wentland continue; 27474562236bSHarry Wentland 27483b21b6d2SJerry Zuo /* Need to allocate mem before program front end for Fiji */ 27493b21b6d2SJerry Zuo pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 27503b21b6d2SJerry Zuo pipe_ctx->plane_res.mi, 27513b21b6d2SJerry Zuo pipe_ctx->stream->timing.h_total, 27523b21b6d2SJerry Zuo pipe_ctx->stream->timing.v_total, 2753380604e2SKen Chalmers pipe_ctx->stream->timing.pix_clk_100hz / 10, 27543b21b6d2SJerry Zuo context->stream_count); 27553b21b6d2SJerry Zuo 27564562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 27574f804817SYongqiang Sun 27584f804817SYongqiang Sun dc->hwss.update_plane_addr(dc, pipe_ctx); 27594f804817SYongqiang Sun 2760b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 27614562236bSHarry Wentland 27624562236bSHarry Wentland } 27633dc780ecSYongqiang Sun 276465d38262Shersen wu if (dc->fbc_compressor) 276512a8bd88SShirish S enable_fbc(dc, context); 27664562236bSHarry Wentland } 27674562236bSHarry Wentland 2768bbf5f6c3SAnthony Koo static void dce110_post_unlock_program_front_end( 2769bbf5f6c3SAnthony Koo struct dc *dc, 2770bbf5f6c3SAnthony Koo struct dc_state *context) 2771bbf5f6c3SAnthony Koo { 2772bbf5f6c3SAnthony Koo } 2773009114f6SAnthony Koo 2774e6c258cbSYongqiang Sun static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 27754562236bSHarry Wentland { 2776f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2777bc373a89SRoman Li int fe_idx = pipe_ctx->plane_res.mi ? 2778bc373a89SRoman Li pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2779e6c258cbSYongqiang Sun 27807950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2781608ac7bbSJerry Zuo if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 27824562236bSHarry Wentland return; 27834562236bSHarry Wentland 2784f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 2785cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2786cfe4645eSDmytro Laktyushkin 2787cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2788cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 27894562236bSHarry Wentland } 27904562236bSHarry Wentland 27916be425f3SEric Yang static void dce110_wait_for_mpcc_disconnect( 2792fb3466a4SBhawanpreet Lakha struct dc *dc, 27936be425f3SEric Yang struct resource_pool *res_pool, 27946be425f3SEric Yang struct pipe_ctx *pipe_ctx) 2795b6762f0cSEric Yang { 2796b6762f0cSEric Yang /* do nothing*/ 2797b6762f0cSEric Yang } 2798b6762f0cSEric Yang 27994bd0dc68SJoshua Aberback static void program_output_csc(struct dc *dc, 28004bd0dc68SJoshua Aberback struct pipe_ctx *pipe_ctx, 28014bd0dc68SJoshua Aberback enum dc_color_space colorspace, 28024bd0dc68SJoshua Aberback uint16_t *matrix, 28034bd0dc68SJoshua Aberback int opp_id) 28044bd0dc68SJoshua Aberback { 28054bd0dc68SJoshua Aberback int i; 28064bd0dc68SJoshua Aberback struct out_csc_color_matrix tbl_entry; 28074bd0dc68SJoshua Aberback 28084bd0dc68SJoshua Aberback if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 28094bd0dc68SJoshua Aberback enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 28104bd0dc68SJoshua Aberback 28114bd0dc68SJoshua Aberback for (i = 0; i < 12; i++) 28124bd0dc68SJoshua Aberback tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 28134bd0dc68SJoshua Aberback 28144bd0dc68SJoshua Aberback tbl_entry.color_space = color_space; 28154bd0dc68SJoshua Aberback 28164bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 28174bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm, &tbl_entry); 28184bd0dc68SJoshua Aberback } 28194bd0dc68SJoshua Aberback } 28204bd0dc68SJoshua Aberback 2821faf0389fSJason Yan static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 282233fd17d9SEric Yang { 282333fd17d9SEric Yang struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 282433fd17d9SEric Yang struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 282533fd17d9SEric Yang struct mem_input *mi = pipe_ctx->plane_res.mi; 282633fd17d9SEric Yang struct dc_cursor_mi_param param = { 2827380604e2SKen Chalmers .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 282833d7598dSJun Lei .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 282939a9f4d8SDmytro Laktyushkin .viewport = pipe_ctx->plane_res.scl_data.viewport, 283039a9f4d8SDmytro Laktyushkin .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 283139a9f4d8SDmytro Laktyushkin .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 283208ed681cSDmytro Laktyushkin .rotation = pipe_ctx->plane_state->rotation, 283308ed681cSDmytro Laktyushkin .mirror = pipe_ctx->plane_state->horizontal_mirror 283433fd17d9SEric Yang }; 283533fd17d9SEric Yang 283603a4059bSNicholas Kazlauskas /** 283703a4059bSNicholas Kazlauskas * If the cursor's source viewport is clipped then we need to 283803a4059bSNicholas Kazlauskas * translate the cursor to appear in the correct position on 283903a4059bSNicholas Kazlauskas * the screen. 284003a4059bSNicholas Kazlauskas * 284103a4059bSNicholas Kazlauskas * This translation isn't affected by scaling so it needs to be 284203a4059bSNicholas Kazlauskas * done *after* we adjust the position for the scale factor. 2843033baeeeSNicholas Kazlauskas * 2844033baeeeSNicholas Kazlauskas * This is only done by opt-in for now since there are still 2845033baeeeSNicholas Kazlauskas * some usecases like tiled display that might enable the 2846033baeeeSNicholas Kazlauskas * cursor on both streams while expecting dc to clip it. 284703a4059bSNicholas Kazlauskas */ 2848033baeeeSNicholas Kazlauskas if (pos_cpy.translate_by_source) { 284903a4059bSNicholas Kazlauskas pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 285003a4059bSNicholas Kazlauskas pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2851033baeeeSNicholas Kazlauskas } 285203a4059bSNicholas Kazlauskas 285333fd17d9SEric Yang if (pipe_ctx->plane_state->address.type 285433fd17d9SEric Yang == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 285533fd17d9SEric Yang pos_cpy.enable = false; 285633fd17d9SEric Yang 285733fd17d9SEric Yang if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 285833fd17d9SEric Yang pos_cpy.enable = false; 285933fd17d9SEric Yang 2860dc75dd70SRoman Li if (ipp->funcs->ipp_cursor_set_position) 286133fd17d9SEric Yang ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2862dc75dd70SRoman Li if (mi->funcs->set_cursor_position) 286333fd17d9SEric Yang mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 286433fd17d9SEric Yang } 286533fd17d9SEric Yang 2866faf0389fSJason Yan static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 286733fd17d9SEric Yang { 286833fd17d9SEric Yang struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 286933fd17d9SEric Yang 2870d1aaad05SHarry Wentland if (pipe_ctx->plane_res.ipp && 2871d1aaad05SHarry Wentland pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 287233fd17d9SEric Yang pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 287333fd17d9SEric Yang pipe_ctx->plane_res.ipp, attributes); 287433fd17d9SEric Yang 2875d1aaad05SHarry Wentland if (pipe_ctx->plane_res.mi && 2876d1aaad05SHarry Wentland pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 287733fd17d9SEric Yang pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 287833fd17d9SEric Yang pipe_ctx->plane_res.mi, attributes); 287933fd17d9SEric Yang 2880d1aaad05SHarry Wentland if (pipe_ctx->plane_res.xfm && 2881d1aaad05SHarry Wentland pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 288233fd17d9SEric Yang pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 288333fd17d9SEric Yang pipe_ctx->plane_res.xfm, attributes); 288433fd17d9SEric Yang } 288533fd17d9SEric Yang 28864b0e95d1SYongqiang Sun bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 28874b0e95d1SYongqiang Sun uint32_t backlight_pwm_u16_16, 28884b0e95d1SYongqiang Sun uint32_t frame_ramp) 28894b0e95d1SYongqiang Sun { 28904b0e95d1SYongqiang Sun struct dc_link *link = pipe_ctx->stream->link; 28914b0e95d1SYongqiang Sun struct dc *dc = link->ctx->dc; 28924b0e95d1SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 28933ba01817SYongqiang Sun struct panel_cntl *panel_cntl = link->panel_cntl; 28944b0e95d1SYongqiang Sun struct dmcu *dmcu = dc->res_pool->dmcu; 28954b0e95d1SYongqiang Sun bool fw_set_brightness = true; 28964b0e95d1SYongqiang Sun /* DMCU -1 for all controller id values, 28974b0e95d1SYongqiang Sun * therefore +1 here 28984b0e95d1SYongqiang Sun */ 28994b0e95d1SYongqiang Sun uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 29004b0e95d1SYongqiang Sun 29013ba01817SYongqiang Sun if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 29024b0e95d1SYongqiang Sun return false; 29034b0e95d1SYongqiang Sun 29044b0e95d1SYongqiang Sun if (dmcu) 29054b0e95d1SYongqiang Sun fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 29064b0e95d1SYongqiang Sun 29073ba01817SYongqiang Sun if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 29083ba01817SYongqiang Sun panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 29093ba01817SYongqiang Sun else 29104b0e95d1SYongqiang Sun abm->funcs->set_backlight_level_pwm( 29114b0e95d1SYongqiang Sun abm, 29124b0e95d1SYongqiang Sun backlight_pwm_u16_16, 29134b0e95d1SYongqiang Sun frame_ramp, 29144b0e95d1SYongqiang Sun controller_id, 29153ba01817SYongqiang Sun link->panel_cntl->inst); 29164b0e95d1SYongqiang Sun 29174b0e95d1SYongqiang Sun return true; 29184b0e95d1SYongqiang Sun } 29194b0e95d1SYongqiang Sun 29203ba01817SYongqiang Sun void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 29213ba01817SYongqiang Sun { 29223ba01817SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 29233ba01817SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 29243ba01817SYongqiang Sun 29253ba01817SYongqiang Sun if (abm) 29263ba01817SYongqiang Sun abm->funcs->set_abm_immediate_disable(abm, 29273ba01817SYongqiang Sun pipe_ctx->stream->link->panel_cntl->inst); 29283ba01817SYongqiang Sun 29293ba01817SYongqiang Sun if (panel_cntl) 29303ba01817SYongqiang Sun panel_cntl->funcs->store_backlight_level(panel_cntl); 29313ba01817SYongqiang Sun } 29323ba01817SYongqiang Sun 2933474ac4a8SYongqiang Sun void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 2934474ac4a8SYongqiang Sun { 2935474ac4a8SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 2936474ac4a8SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 2937474ac4a8SYongqiang Sun uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 2938474ac4a8SYongqiang Sun 2939474ac4a8SYongqiang Sun if (abm && panel_cntl) 2940474ac4a8SYongqiang Sun abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 2941474ac4a8SYongqiang Sun } 2942474ac4a8SYongqiang Sun 29434562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 29441bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 29454bd0dc68SJoshua Aberback .program_output_csc = program_output_csc, 29464562236bSHarry Wentland .init_hw = init_hw, 29474562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 29484562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 2949bbf5f6c3SAnthony Koo .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 29504562236bSHarry Wentland .update_plane_addr = update_plane_addr, 29514562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 29524562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 29534562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 2954fa2123dbSMikita Lipski .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 29554562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 29564562236bSHarry Wentland .enable_stream = dce110_enable_stream, 29574562236bSHarry Wentland .disable_stream = dce110_disable_stream, 29584562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 295941b49742SCharlene Liu .blank_stream = dce110_blank_stream, 29601a05873fSAnthony Koo .enable_audio_stream = dce110_enable_audio_stream, 29611a05873fSAnthony Koo .disable_audio_stream = dce110_disable_audio_stream, 29627f914a62SYongqiang Sun .disable_plane = dce110_power_down_fe, 29634562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 2964009114f6SAnthony Koo .interdependent_update_lock = NULL, 29651e461c37SAric Cyr .cursor_lock = dce_pipe_control_lock, 29669566b675SDmytro Laktyushkin .prepare_bandwidth = dce110_prepare_bandwidth, 29679566b675SDmytro Laktyushkin .optimize_bandwidth = dce110_optimize_bandwidth, 29684562236bSHarry Wentland .set_drr = set_drr, 296972ada5f7SEric Cook .get_position = get_position, 29704562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 297115e17335SCharlene Liu .setup_stereo = NULL, 297215e17335SCharlene Liu .set_avmute = dce110_set_avmute, 297341f97c07SHersen Wu .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 2974099303e9SPeikang Zhang .edp_backlight_control = dce110_edp_backlight_control, 29758a31820bSMartin Leung .edp_power_control = dce110_edp_power_control, 29768a31820bSMartin Leung .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 297733fd17d9SEric Yang .set_cursor_position = dce110_set_cursor_position, 29784b0e95d1SYongqiang Sun .set_cursor_attribute = dce110_set_cursor_attribute, 29794b0e95d1SYongqiang Sun .set_backlight_level = dce110_set_backlight_level, 29803ba01817SYongqiang Sun .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 2981474ac4a8SYongqiang Sun .set_pipe = dce110_set_pipe, 29824562236bSHarry Wentland }; 29834562236bSHarry Wentland 2984f42ea55bSAnthony Koo static const struct hwseq_private_funcs dce110_private_funcs = { 2985f42ea55bSAnthony Koo .init_pipes = init_pipes, 2986f42ea55bSAnthony Koo .update_plane_addr = update_plane_addr, 2987f42ea55bSAnthony Koo .set_input_transfer_func = dce110_set_input_transfer_func, 2988f42ea55bSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 2989f42ea55bSAnthony Koo .power_down = dce110_power_down, 2990f42ea55bSAnthony Koo .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 2991f42ea55bSAnthony Koo .enable_display_power_gating = dce110_enable_display_power_gating, 2992f42ea55bSAnthony Koo .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 2993f42ea55bSAnthony Koo .enable_stream_timing = dce110_enable_stream_timing, 2994f42ea55bSAnthony Koo .disable_stream_gating = NULL, 2995f42ea55bSAnthony Koo .enable_stream_gating = NULL, 2996f42ea55bSAnthony Koo .edp_backlight_control = dce110_edp_backlight_control, 2997f42ea55bSAnthony Koo }; 2998f42ea55bSAnthony Koo 2999c13b408bSDave Airlie void dce110_hw_sequencer_construct(struct dc *dc) 30004562236bSHarry Wentland { 30014562236bSHarry Wentland dc->hwss = dce110_funcs; 3002f42ea55bSAnthony Koo dc->hwseq->funcs = dce110_private_funcs; 30034562236bSHarry Wentland } 30044562236bSHarry Wentland 3005