14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 25c366be54SSam Ravnborg 26c366be54SSam Ravnborg #include <linux/delay.h> 27c366be54SSam Ravnborg 284562236bSHarry Wentland #include "dm_services.h" 294562236bSHarry Wentland #include "dc.h" 304562236bSHarry Wentland #include "dc_bios_types.h" 314562236bSHarry Wentland #include "core_types.h" 324562236bSHarry Wentland #include "core_status.h" 334562236bSHarry Wentland #include "resource.h" 344562236bSHarry Wentland #include "dm_helpers.h" 354562236bSHarry Wentland #include "dce110_timing_generator.h" 3698489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 3787401969SAndrew Jiang #include "gpio_service_interface.h" 384562236bSHarry Wentland 391663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 401663ae1cSBhawanpreet Lakha 414562236bSHarry Wentland #include "bios/bios_parser_helper.h" 424562236bSHarry Wentland #include "timing_generator.h" 434562236bSHarry Wentland #include "mem_input.h" 444562236bSHarry Wentland #include "opp.h" 454562236bSHarry Wentland #include "ipp.h" 464562236bSHarry Wentland #include "transform.h" 474562236bSHarry Wentland #include "stream_encoder.h" 484562236bSHarry Wentland #include "link_encoder.h" 4964d283cbSJimmy Kizito #include "link_enc_cfg.h" 5087401969SAndrew Jiang #include "link_hwss.h" 51f9fc6f39SMichael Strauss #include "dc_link_dp.h" 5264b1d0e8SNicholas Kazlauskas #include "dccg.h" 534562236bSHarry Wentland #include "clock_source.h" 54dc88b4a6SEric Yang #include "clk_mgr.h" 555e7773a2SAnthony Koo #include "abm.h" 564562236bSHarry Wentland #include "audio.h" 5708b16886SZeyu Fan #include "reg_helper.h" 58d4caa72eSAnthony Koo #include "panel_cntl.h" 593550d622SLeo (Hanghong) Ma #include "inc/link_dpcd.h" 603550d622SLeo (Hanghong) Ma #include "dpcd_defs.h" 614562236bSHarry Wentland /* include DCE11 register header files */ 624562236bSHarry Wentland #include "dce/dce_11_0_d.h" 634562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 64e266fdf6SVitaly Prosyak #include "custom_float.h" 654562236bSHarry Wentland 664cac1e6dSYongqiang Sun #include "atomfirmware.h" 674cac1e6dSYongqiang Sun 68a76eb7d3SLee Jones #include "dcn10/dcn10_hw_sequencer.h" 696e4a14ccSLee Jones 7064cf26f0SIsabella Basso #include "dce110_hw_sequencer.h" 7164cf26f0SIsabella Basso 7278c77382SAnthony Koo #define GAMMA_HW_POINTS_NUM 256 7378c77382SAnthony Koo 7487401969SAndrew Jiang /* 7587401969SAndrew Jiang * All values are in milliseconds; 7687401969SAndrew Jiang * For eDP, after power-up/power/down, 7787401969SAndrew Jiang * 300/500 msec max. delay from LCDVCC to black video generation 7887401969SAndrew Jiang */ 7987401969SAndrew Jiang #define PANEL_POWER_UP_TIMEOUT 300 8087401969SAndrew Jiang #define PANEL_POWER_DOWN_TIMEOUT 500 8187401969SAndrew Jiang #define HPD_CHECK_INTERVAL 10 8296577cf8SHersen Wu #define OLED_POST_T7_DELAY 100 8396577cf8SHersen Wu #define OLED_PRE_T11_DELAY 150 8487401969SAndrew Jiang 855eefbc40SYue Hin Lau #define CTX \ 865eefbc40SYue Hin Lau hws->ctx 875d4b05ddSBhawanpreet Lakha 885d4b05ddSBhawanpreet Lakha #define DC_LOGGER_INIT() 895d4b05ddSBhawanpreet Lakha 905eefbc40SYue Hin Lau #define REG(reg)\ 915eefbc40SYue Hin Lau hws->regs->reg 925eefbc40SYue Hin Lau 935eefbc40SYue Hin Lau #undef FN 945eefbc40SYue Hin Lau #define FN(reg_name, field_name) \ 955eefbc40SYue Hin Lau hws->shifts->field_name, hws->masks->field_name 965eefbc40SYue Hin Lau 974562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 984562236bSHarry Wentland uint32_t crtc; 994562236bSHarry Wentland }; 1004562236bSHarry Wentland 1014562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 1024562236bSHarry Wentland { 1034562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1044562236bSHarry Wentland }, 1054562236bSHarry Wentland { 1064562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1074562236bSHarry Wentland }, 1084562236bSHarry Wentland { 1094562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1104562236bSHarry Wentland }, 1114562236bSHarry Wentland { 1124562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1134562236bSHarry Wentland } 1144562236bSHarry Wentland }; 1154562236bSHarry Wentland 1164562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 1174562236bSHarry Wentland (reg + reg_offsets[id].blnd) 1184562236bSHarry Wentland 1194562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 1204562236bSHarry Wentland (reg + reg_offsets[id].crtc) 1214562236bSHarry Wentland 1224562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 1234562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 1244562236bSHarry Wentland 1254562236bSHarry Wentland /******************************************************************************* 1264562236bSHarry Wentland * Private definitions 1274562236bSHarry Wentland ******************************************************************************/ 1284562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 1294562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 1304562236bSHarry Wentland { 1314562236bSHarry Wentland uint32_t addr; 1324562236bSHarry Wentland uint32_t value = 0; 1334562236bSHarry Wentland uint32_t chunk_int = 0; 1344562236bSHarry Wentland uint32_t chunk_mul = 0; 1354562236bSHarry Wentland 1364562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 1374562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1384562236bSHarry Wentland 1394562236bSHarry Wentland set_reg_field_value( 1404562236bSHarry Wentland value, 1414562236bSHarry Wentland 0, 1424562236bSHarry Wentland DVMM_PTE_CONTROL, 1434562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1444562236bSHarry Wentland 1454562236bSHarry Wentland set_reg_field_value( 1464562236bSHarry Wentland value, 1474562236bSHarry Wentland 1, 1484562236bSHarry Wentland DVMM_PTE_CONTROL, 1494562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1504562236bSHarry Wentland 1514562236bSHarry Wentland set_reg_field_value( 1524562236bSHarry Wentland value, 1534562236bSHarry Wentland 1, 1544562236bSHarry Wentland DVMM_PTE_CONTROL, 1554562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1564562236bSHarry Wentland 1574562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1584562236bSHarry Wentland 1594562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1604562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1614562236bSHarry Wentland 1624562236bSHarry Wentland chunk_int = get_reg_field_value( 1634562236bSHarry Wentland value, 1644562236bSHarry Wentland DVMM_PTE_REQ, 1654562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1664562236bSHarry Wentland 1674562236bSHarry Wentland chunk_mul = get_reg_field_value( 1684562236bSHarry Wentland value, 1694562236bSHarry Wentland DVMM_PTE_REQ, 1704562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1714562236bSHarry Wentland 1724562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1734562236bSHarry Wentland 1744562236bSHarry Wentland set_reg_field_value( 1754562236bSHarry Wentland value, 1764562236bSHarry Wentland 255, 1774562236bSHarry Wentland DVMM_PTE_REQ, 1784562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1794562236bSHarry Wentland 1804562236bSHarry Wentland set_reg_field_value( 1814562236bSHarry Wentland value, 1824562236bSHarry Wentland 4, 1834562236bSHarry Wentland DVMM_PTE_REQ, 1844562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1854562236bSHarry Wentland 1864562236bSHarry Wentland set_reg_field_value( 1874562236bSHarry Wentland value, 1884562236bSHarry Wentland 4, 1894562236bSHarry Wentland DVMM_PTE_REQ, 1904562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1914562236bSHarry Wentland 1924562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1934562236bSHarry Wentland } 1944562236bSHarry Wentland } 1954562236bSHarry Wentland /**************************************************************************/ 1964562236bSHarry Wentland 1974562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1984562236bSHarry Wentland struct dc_context *ctx, 1994562236bSHarry Wentland bool clock_gating) 2004562236bSHarry Wentland { 2014562236bSHarry Wentland /*TODO*/ 2024562236bSHarry Wentland } 2034562236bSHarry Wentland 2044562236bSHarry Wentland static bool dce110_enable_display_power_gating( 205fb3466a4SBhawanpreet Lakha struct dc *dc, 2064562236bSHarry Wentland uint8_t controller_id, 2074562236bSHarry Wentland struct dc_bios *dcb, 2084562236bSHarry Wentland enum pipe_gating_control power_gating) 2094562236bSHarry Wentland { 2104562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 2114562236bSHarry Wentland enum bp_pipe_control_action cntl; 2124562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 2134562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 2144562236bSHarry Wentland 2154562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 2164562236bSHarry Wentland return true; 2174562236bSHarry Wentland 2184562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 2194562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 2204562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 2214562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 2224562236bSHarry Wentland else 2234562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 2244562236bSHarry Wentland 2254562236bSHarry Wentland if (controller_id == underlay_idx) 2264562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 2274562236bSHarry Wentland 2284562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 2294562236bSHarry Wentland 2304562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 2314562236bSHarry Wentland dcb, controller_id + 1, cntl); 2324562236bSHarry Wentland 2334562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 2344562236bSHarry Wentland * by default when command table is called 2354562236bSHarry Wentland * 2364562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 2374562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2384562236bSHarry Wentland * than 3. 2394562236bSHarry Wentland */ 2404562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2414562236bSHarry Wentland dm_write_reg(ctx, 2424562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2434562236bSHarry Wentland 0); 2444562236bSHarry Wentland } 2454562236bSHarry Wentland 2464562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2474562236bSHarry Wentland dce110_init_pte(ctx); 2484562236bSHarry Wentland 2494562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2504562236bSHarry Wentland return true; 2514562236bSHarry Wentland else 2524562236bSHarry Wentland return false; 2534562236bSHarry Wentland } 2544562236bSHarry Wentland 2554562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2563be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2574562236bSHarry Wentland { 2584562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2594562236bSHarry Wentland 2603be5262eSHarry Wentland switch (plane_state->format) { 2611352c779SNicholas Kazlauskas case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2621352c779SNicholas Kazlauskas prescale_params->scale = 0x2082; 2631352c779SNicholas Kazlauskas break; 2644562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2658693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2664562236bSHarry Wentland prescale_params->scale = 0x2020; 2674562236bSHarry Wentland break; 2684562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2694562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2704562236bSHarry Wentland prescale_params->scale = 0x2008; 2714562236bSHarry Wentland break; 2724562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 273050cd3d6SMario Kleiner case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 2744562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2754562236bSHarry Wentland prescale_params->scale = 0x2000; 2764562236bSHarry Wentland break; 2774562236bSHarry Wentland default: 2784562236bSHarry Wentland ASSERT(false); 279d7194cf6SAric Cyr break; 2804562236bSHarry Wentland } 2814562236bSHarry Wentland } 2824562236bSHarry Wentland 283a6114e85SHarry Wentland static bool 28478c77382SAnthony Koo dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 2853be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2864562236bSHarry Wentland { 28786a66c4eSHarry Wentland struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2887b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 28990e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 29090e508baSAnthony Koo bool result = true; 29190e508baSAnthony Koo 29290e508baSAnthony Koo if (ipp == NULL) 29390e508baSAnthony Koo return false; 29490e508baSAnthony Koo 2953be5262eSHarry Wentland if (plane_state->in_transfer_func) 2963be5262eSHarry Wentland tf = plane_state->in_transfer_func; 29790e508baSAnthony Koo 2983be5262eSHarry Wentland build_prescale_params(&prescale_params, plane_state); 29990e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 30090e508baSAnthony Koo 30184ffa801SLeo (Sunpeng) Li if (plane_state->gamma_correction && 30284ffa801SLeo (Sunpeng) Li !plane_state->gamma_correction->is_identity && 30384ffa801SLeo (Sunpeng) Li dce_use_lut(plane_state->format)) 3043be5262eSHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 305d7194cf6SAric Cyr 30690e508baSAnthony Koo if (tf == NULL) { 30790e508baSAnthony Koo /* Default case if no input transfer function specified */ 308a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 3097b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 3107b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 31190e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 312a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 31390e508baSAnthony Koo break; 31490e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 315a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 31690e508baSAnthony Koo break; 31790e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 318a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 31990e508baSAnthony Koo break; 32090e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 32190e508baSAnthony Koo default: 32290e508baSAnthony Koo result = false; 323d7194cf6SAric Cyr break; 32490e508baSAnthony Koo } 3257b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 32670063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 32790e508baSAnthony Koo } else { 32890e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 32990e508baSAnthony Koo result = false; 33090e508baSAnthony Koo } 33190e508baSAnthony Koo 33290e508baSAnthony Koo return result; 33390e508baSAnthony Koo } 33490e508baSAnthony Koo 335bd1be8e8SHarry Wentland static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 336fcd2f4bfSAmy Zhang struct curve_points *arr_points, 337fcd2f4bfSAmy Zhang uint32_t hw_points_num) 338fcd2f4bfSAmy Zhang { 339fcd2f4bfSAmy Zhang struct custom_float_format fmt; 340fcd2f4bfSAmy Zhang 341fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 342fcd2f4bfSAmy Zhang 343fcd2f4bfSAmy Zhang uint32_t i = 0; 344fcd2f4bfSAmy Zhang 345fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 346fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 347fcd2f4bfSAmy Zhang fmt.sign = true; 348fcd2f4bfSAmy Zhang 349bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 350fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 351fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 352fcd2f4bfSAmy Zhang return false; 353fcd2f4bfSAmy Zhang } 354fcd2f4bfSAmy Zhang 355bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 356fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 357fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 358fcd2f4bfSAmy Zhang return false; 359fcd2f4bfSAmy Zhang } 360fcd2f4bfSAmy Zhang 361bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 362fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 363fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 364fcd2f4bfSAmy Zhang return false; 365fcd2f4bfSAmy Zhang } 366fcd2f4bfSAmy Zhang 367fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 368fcd2f4bfSAmy Zhang fmt.sign = false; 369fcd2f4bfSAmy Zhang 370bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 371fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 372fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 373fcd2f4bfSAmy Zhang return false; 374fcd2f4bfSAmy Zhang } 375fcd2f4bfSAmy Zhang 376bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 377fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 378fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 379fcd2f4bfSAmy Zhang return false; 380fcd2f4bfSAmy Zhang } 381fcd2f4bfSAmy Zhang 3824d06ccd0SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 3834d06ccd0SHarry Wentland &arr_points[1].custom_float_slope)) { 384fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 385fcd2f4bfSAmy Zhang return false; 386fcd2f4bfSAmy Zhang } 387fcd2f4bfSAmy Zhang 388fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 389fcd2f4bfSAmy Zhang fmt.sign = true; 390fcd2f4bfSAmy Zhang 391fcd2f4bfSAmy Zhang while (i != hw_points_num) { 392bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->red, &fmt, 393fcd2f4bfSAmy Zhang &rgb->red_reg)) { 394fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 395fcd2f4bfSAmy Zhang return false; 396fcd2f4bfSAmy Zhang } 397fcd2f4bfSAmy Zhang 398bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->green, &fmt, 399fcd2f4bfSAmy Zhang &rgb->green_reg)) { 400fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 401fcd2f4bfSAmy Zhang return false; 402fcd2f4bfSAmy Zhang } 403fcd2f4bfSAmy Zhang 404bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->blue, &fmt, 405fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 406fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 407fcd2f4bfSAmy Zhang return false; 408fcd2f4bfSAmy Zhang } 409fcd2f4bfSAmy Zhang 410bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 411fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 412fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 413fcd2f4bfSAmy Zhang return false; 414fcd2f4bfSAmy Zhang } 415fcd2f4bfSAmy Zhang 416bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 417fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 418fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 419fcd2f4bfSAmy Zhang return false; 420fcd2f4bfSAmy Zhang } 421fcd2f4bfSAmy Zhang 422bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 423fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 424fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 425fcd2f4bfSAmy Zhang return false; 426fcd2f4bfSAmy Zhang } 427fcd2f4bfSAmy Zhang 428fcd2f4bfSAmy Zhang ++rgb; 429fcd2f4bfSAmy Zhang ++i; 430fcd2f4bfSAmy Zhang } 431fcd2f4bfSAmy Zhang 432fcd2f4bfSAmy Zhang return true; 433fcd2f4bfSAmy Zhang } 434fcd2f4bfSAmy Zhang 43508616da5SLeo (Sunpeng) Li #define MAX_LOW_POINT 25 4368f8372c7SKrunoslav Kovac #define NUMBER_REGIONS 16 4378f8372c7SKrunoslav Kovac #define NUMBER_SW_SEGMENTS 16 4388f8372c7SKrunoslav Kovac 439b310b081SHarry Wentland static bool 440b310b081SHarry Wentland dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 441b310b081SHarry Wentland struct pwl_params *regamma_params) 442fcd2f4bfSAmy Zhang { 44323ae4f8eSAmy Zhang struct curve_points *arr_points; 44423ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 44523ae4f8eSAmy Zhang struct pwl_result_data *rgb; 44623ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 447fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 448fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 449fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 450fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 451fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 452fcd2f4bfSAmy Zhang 4538f8372c7SKrunoslav Kovac int32_t region_start, region_end; 4548f8372c7SKrunoslav Kovac uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 45523ae4f8eSAmy Zhang 456b310b081SHarry Wentland if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 45723ae4f8eSAmy Zhang return false; 45823ae4f8eSAmy Zhang 45923ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 46023ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 46123ae4f8eSAmy Zhang hw_points = 0; 462fcd2f4bfSAmy Zhang 463fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 464fcd2f4bfSAmy Zhang 465fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 466534db198SAmy Zhang /* 16 segments 467fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 468fcd2f4bfSAmy Zhang */ 46908616da5SLeo (Sunpeng) Li region_start = -11; 47008616da5SLeo (Sunpeng) Li region_end = region_start + NUMBER_REGIONS; 471fcd2f4bfSAmy Zhang 4728f8372c7SKrunoslav Kovac for (i = 0; i < NUMBER_REGIONS; i++) 4738f8372c7SKrunoslav Kovac seg_distr[i] = 4; 474534db198SAmy Zhang 475fcd2f4bfSAmy Zhang } else { 476534db198SAmy Zhang /* 10 segments 477fc6de1c5SLeo (Sunpeng) Li * segment is from 2^-10 to 2^1 478fc6de1c5SLeo (Sunpeng) Li * We include an extra segment for range [2^0, 2^1). This is to 479fc6de1c5SLeo (Sunpeng) Li * ensure that colors with normalized values of 1 don't miss the 480fc6de1c5SLeo (Sunpeng) Li * LUT. 481fcd2f4bfSAmy Zhang */ 4828f8372c7SKrunoslav Kovac region_start = -10; 483fc6de1c5SLeo (Sunpeng) Li region_end = 1; 484534db198SAmy Zhang 4858f8372c7SKrunoslav Kovac seg_distr[0] = 4; 486534db198SAmy Zhang seg_distr[1] = 4; 487534db198SAmy Zhang seg_distr[2] = 4; 488534db198SAmy Zhang seg_distr[3] = 4; 489534db198SAmy Zhang seg_distr[4] = 4; 490534db198SAmy Zhang seg_distr[5] = 4; 491534db198SAmy Zhang seg_distr[6] = 4; 492534db198SAmy Zhang seg_distr[7] = 4; 4938f8372c7SKrunoslav Kovac seg_distr[8] = 4; 4948f8372c7SKrunoslav Kovac seg_distr[9] = 4; 495fc6de1c5SLeo (Sunpeng) Li seg_distr[10] = 0; 496534db198SAmy Zhang seg_distr[11] = -1; 497534db198SAmy Zhang seg_distr[12] = -1; 498534db198SAmy Zhang seg_distr[13] = -1; 499534db198SAmy Zhang seg_distr[14] = -1; 500534db198SAmy Zhang seg_distr[15] = -1; 501fcd2f4bfSAmy Zhang } 502fcd2f4bfSAmy Zhang 503534db198SAmy Zhang for (k = 0; k < 16; k++) { 504534db198SAmy Zhang if (seg_distr[k] != -1) 505534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 506534db198SAmy Zhang } 507534db198SAmy Zhang 508fcd2f4bfSAmy Zhang j = 0; 5098f8372c7SKrunoslav Kovac for (k = 0; k < (region_end - region_start); k++) { 510ec47734aSLeo (Sunpeng) Li increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 5118f8372c7SKrunoslav Kovac start_index = (region_start + k + MAX_LOW_POINT) * 5128f8372c7SKrunoslav Kovac NUMBER_SW_SEGMENTS; 5138f8372c7SKrunoslav Kovac for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 5148f8372c7SKrunoslav Kovac i += increment) { 515534db198SAmy Zhang if (j == hw_points - 1) 516fcd2f4bfSAmy Zhang break; 517fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 518fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 519fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 520fcd2f4bfSAmy Zhang j++; 521fcd2f4bfSAmy Zhang } 522534db198SAmy Zhang } 523534db198SAmy Zhang 524534db198SAmy Zhang /* last point */ 5258f8372c7SKrunoslav Kovac start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 526b310b081SHarry Wentland rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 527b310b081SHarry Wentland rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 528b310b081SHarry Wentland rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 529fcd2f4bfSAmy Zhang 530eb0e5154SDmytro Laktyushkin arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 531eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_start)); 532eb0e5154SDmytro Laktyushkin arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 533eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_end)); 534fcd2f4bfSAmy Zhang 535fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 536fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 537fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 538fcd2f4bfSAmy Zhang 539eb0e5154SDmytro Laktyushkin y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 540fcd2f4bfSAmy Zhang 541fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 542eb0e5154SDmytro Laktyushkin arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 543fcd2f4bfSAmy Zhang arr_points[0].x); 544fcd2f4bfSAmy Zhang 545fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 546fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 547fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 548fcd2f4bfSAmy Zhang 549fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 550fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 551fcd2f4bfSAmy Zhang */ 552eb0e5154SDmytro Laktyushkin y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 553fcd2f4bfSAmy Zhang 554fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 555fcd2f4bfSAmy Zhang 556eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_zero; 557fcd2f4bfSAmy Zhang 558fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 559fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 560fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 561fcd2f4bfSAmy Zhang */ 562eb0e5154SDmytro Laktyushkin const struct fixed31_32 end_value = dc_fixpt_from_int(125); 563fcd2f4bfSAmy Zhang 564eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_div( 565eb0e5154SDmytro Laktyushkin dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 566eb0e5154SDmytro Laktyushkin dc_fixpt_sub(end_value, arr_points[1].x)); 567fcd2f4bfSAmy Zhang } 568fcd2f4bfSAmy Zhang 569fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 570fcd2f4bfSAmy Zhang 57169133b89SAric Cyr k = 0; 57269133b89SAric Cyr for (i = 1; i < 16; i++) { 573534db198SAmy Zhang if (seg_distr[k] != -1) { 574b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 575534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 576b310b081SHarry Wentland regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 577fcd2f4bfSAmy Zhang } 57869133b89SAric Cyr k++; 579534db198SAmy Zhang } 580534db198SAmy Zhang 581534db198SAmy Zhang if (seg_distr[k] != -1) 582b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 583fcd2f4bfSAmy Zhang 58423ae4f8eSAmy Zhang rgb = rgb_resulted; 58523ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 586fcd2f4bfSAmy Zhang 587fcd2f4bfSAmy Zhang i = 1; 588fcd2f4bfSAmy Zhang 589fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 590eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 591fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 592eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 593fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 594eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 595fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 596fcd2f4bfSAmy Zhang 597eb0e5154SDmytro Laktyushkin rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 598eb0e5154SDmytro Laktyushkin rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 599eb0e5154SDmytro Laktyushkin rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 600fcd2f4bfSAmy Zhang 601fcd2f4bfSAmy Zhang ++rgb_plus_1; 602fcd2f4bfSAmy Zhang ++rgb; 603fcd2f4bfSAmy Zhang ++i; 604fcd2f4bfSAmy Zhang } 605fcd2f4bfSAmy Zhang 606fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 607fcd2f4bfSAmy Zhang 608fcd2f4bfSAmy Zhang return true; 609fcd2f4bfSAmy Zhang } 610fcd2f4bfSAmy Zhang 611a6114e85SHarry Wentland static bool 61278c77382SAnthony Koo dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 6130971c40eSHarry Wentland const struct dc_stream_state *stream) 61490e508baSAnthony Koo { 61586a66c4eSHarry Wentland struct transform *xfm = pipe_ctx->plane_res.xfm; 6164562236bSHarry Wentland 6177a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, true); 6187a09f5beSYue Hin Lau xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 6194562236bSHarry Wentland 6204fa086b9SLeo (Sunpeng) Li if (stream->out_transfer_func && 621efd52204SHarry Wentland stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 622efd52204SHarry Wentland stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 6237a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 624efd52204SHarry Wentland } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 625efd52204SHarry Wentland &xfm->regamma_params)) { 6267a09f5beSYue Hin Lau xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 6277a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 6284562236bSHarry Wentland } else { 6297a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 6304562236bSHarry Wentland } 6314562236bSHarry Wentland 6327a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, false); 6334562236bSHarry Wentland 634cc0cb445SLeon Elazar return true; 6354562236bSHarry Wentland } 6364562236bSHarry Wentland 6374562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6384562236bSHarry Wentland { 63902553f57SEric Bernstein bool is_hdmi_tmds; 6406f0db2dcSKrunoslav Kovac bool is_dp; 6416f0db2dcSKrunoslav Kovac 64286e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 64386e2e1beSHersen Wu 6448e9c4c8cSHarry Wentland if (pipe_ctx->stream_res.stream_enc == NULL) 64586e2e1beSHersen Wu return; /* this is not root pipe */ 64686e2e1beSHersen Wu 64702553f57SEric Bernstein is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 6486f0db2dcSKrunoslav Kovac is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 6496f0db2dcSKrunoslav Kovac 65002553f57SEric Bernstein if (!is_hdmi_tmds && !is_dp) 6516f0db2dcSKrunoslav Kovac return; 6526f0db2dcSKrunoslav Kovac 65302553f57SEric Bernstein if (is_hdmi_tmds) 6548e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 6558e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 65696c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6576f0db2dcSKrunoslav Kovac else 6588e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 6598e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 66096c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6614562236bSHarry Wentland } 6624562236bSHarry Wentland 6634562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6644562236bSHarry Wentland { 6654562236bSHarry Wentland enum dc_lane_count lane_count = 666ceb3dbb4SJun Lei pipe_ctx->stream->link->cur_link_settings.lane_count; 6674fa086b9SLeo (Sunpeng) Li struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 668ceb3dbb4SJun Lei struct dc_link *link = pipe_ctx->stream->link; 669f42ea55bSAnthony Koo const struct dc *dc = link->dc; 6709d8033d6SWenjing Liu const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 6714562236bSHarry Wentland uint32_t active_total_with_borders; 6724562236bSHarry Wentland uint32_t early_control = 0; 6736b670fa9SHarry Wentland struct timing_generator *tg = pipe_ctx->stream_res.tg; 6744562236bSHarry Wentland 6759d8033d6SWenjing Liu link_hwss->setup_stream_encoder(pipe_ctx); 676f215a57dSEric Yang 677f42ea55bSAnthony Koo dc->hwss.update_info_frame(pipe_ctx); 678f215a57dSEric Yang 6794562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 6804562236bSHarry Wentland active_total_with_borders = 6814562236bSHarry Wentland timing->h_addressable 6824562236bSHarry Wentland + timing->h_border_left 6834562236bSHarry Wentland + timing->h_border_right; 6844562236bSHarry Wentland 6854562236bSHarry Wentland if (lane_count != 0) 6864562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 6874562236bSHarry Wentland 6884562236bSHarry Wentland if (early_control == 0) 6894562236bSHarry Wentland early_control = lane_count; 6904562236bSHarry Wentland 6914562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 6924562236bSHarry Wentland 6934562236bSHarry Wentland /* enable audio only within mode set */ 694afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 6954562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6968e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 6974562236bSHarry Wentland } 6984562236bSHarry Wentland 699f215a57dSEric Yang 700f215a57dSEric Yang 7014562236bSHarry Wentland 7024562236bSHarry Wentland } 7034562236bSHarry Wentland 7045eefbc40SYue Hin Lau static enum bp_result link_transmitter_control( 70587401969SAndrew Jiang struct dc_bios *bios, 7065eefbc40SYue Hin Lau struct bp_transmitter_control *cntl) 7075eefbc40SYue Hin Lau { 7085eefbc40SYue Hin Lau enum bp_result result; 7095eefbc40SYue Hin Lau 71087401969SAndrew Jiang result = bios->funcs->transmitter_control(bios, cntl); 7115eefbc40SYue Hin Lau 7125eefbc40SYue Hin Lau return result; 7135eefbc40SYue Hin Lau } 7145eefbc40SYue Hin Lau 71587401969SAndrew Jiang /* 71687401969SAndrew Jiang * @brief 71787401969SAndrew Jiang * eDP only. 71887401969SAndrew Jiang */ 7198a31820bSMartin Leung void dce110_edp_wait_for_hpd_ready( 720069d418fSAndrew Jiang struct dc_link *link, 72187401969SAndrew Jiang bool power_up) 72287401969SAndrew Jiang { 723069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 724069d418fSAndrew Jiang struct graphics_object_id connector = link->link_enc->connector; 72587401969SAndrew Jiang struct gpio *hpd; 7266798d042SLewis Huang struct dc_sink *sink = link->local_sink; 72787401969SAndrew Jiang bool edp_hpd_high = false; 72887401969SAndrew Jiang uint32_t time_elapsed = 0; 72987401969SAndrew Jiang uint32_t timeout = power_up ? 73087401969SAndrew Jiang PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 73187401969SAndrew Jiang 73287401969SAndrew Jiang if (dal_graphics_object_id_get_connector_id(connector) 73387401969SAndrew Jiang != CONNECTOR_ID_EDP) { 73487401969SAndrew Jiang BREAK_TO_DEBUGGER(); 73587401969SAndrew Jiang return; 73687401969SAndrew Jiang } 73787401969SAndrew Jiang 73887401969SAndrew Jiang if (!power_up) 73987401969SAndrew Jiang /* 74087401969SAndrew Jiang * From KV, we will not HPD low after turning off VCC - 74187401969SAndrew Jiang * instead, we will check the SW timer in power_up(). 74287401969SAndrew Jiang */ 74387401969SAndrew Jiang return; 74487401969SAndrew Jiang 74587401969SAndrew Jiang /* 74687401969SAndrew Jiang * When we power on/off the eDP panel, 74787401969SAndrew Jiang * we need to wait until SENSE bit is high/low. 74887401969SAndrew Jiang */ 74987401969SAndrew Jiang 75087401969SAndrew Jiang /* obtain HPD */ 75187401969SAndrew Jiang /* TODO what to do with this? */ 75287401969SAndrew Jiang hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 75387401969SAndrew Jiang 75487401969SAndrew Jiang if (!hpd) { 75587401969SAndrew Jiang BREAK_TO_DEBUGGER(); 75687401969SAndrew Jiang return; 75787401969SAndrew Jiang } 75887401969SAndrew Jiang 7596798d042SLewis Huang if (sink != NULL) { 7606798d042SLewis Huang if (sink->edid_caps.panel_patch.extra_t3_ms > 0) { 7616798d042SLewis Huang int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms; 7626798d042SLewis Huang 7636798d042SLewis Huang msleep(extra_t3_in_ms); 7646798d042SLewis Huang } 7656798d042SLewis Huang } 7666798d042SLewis Huang 76787401969SAndrew Jiang dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 76887401969SAndrew Jiang 76987401969SAndrew Jiang /* wait until timeout or panel detected */ 77087401969SAndrew Jiang 77187401969SAndrew Jiang do { 77287401969SAndrew Jiang uint32_t detected = 0; 77387401969SAndrew Jiang 77487401969SAndrew Jiang dal_gpio_get_value(hpd, &detected); 77587401969SAndrew Jiang 77687401969SAndrew Jiang if (!(detected ^ power_up)) { 77787401969SAndrew Jiang edp_hpd_high = true; 77887401969SAndrew Jiang break; 77987401969SAndrew Jiang } 78087401969SAndrew Jiang 78187401969SAndrew Jiang msleep(HPD_CHECK_INTERVAL); 78287401969SAndrew Jiang 78387401969SAndrew Jiang time_elapsed += HPD_CHECK_INTERVAL; 78487401969SAndrew Jiang } while (time_elapsed < timeout); 78587401969SAndrew Jiang 78687401969SAndrew Jiang dal_gpio_close(hpd); 78787401969SAndrew Jiang 78887401969SAndrew Jiang dal_gpio_destroy_irq(&hpd); 78987401969SAndrew Jiang 79087401969SAndrew Jiang if (false == edp_hpd_high) { 791e2d8ea43SVarone DC_LOG_WARNING( 79287401969SAndrew Jiang "%s: wait timed out!\n", __func__); 79387401969SAndrew Jiang } 79487401969SAndrew Jiang } 79587401969SAndrew Jiang 7968a31820bSMartin Leung void dce110_edp_power_control( 797069d418fSAndrew Jiang struct dc_link *link, 79887401969SAndrew Jiang bool power_up) 79987401969SAndrew Jiang { 800069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 80187401969SAndrew Jiang struct bp_transmitter_control cntl = { 0 }; 80287401969SAndrew Jiang enum bp_result bp_result; 80306ddcee4SJake Wang uint8_t panel_instance; 80487401969SAndrew Jiang 80587401969SAndrew Jiang 806069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 80787401969SAndrew Jiang != CONNECTOR_ID_EDP) { 80887401969SAndrew Jiang BREAK_TO_DEBUGGER(); 80987401969SAndrew Jiang return; 81087401969SAndrew Jiang } 81187401969SAndrew Jiang 812ffadb9d6SAnthony Koo if (!link->panel_cntl) 813904fb6e0SAnthony Koo return; 814d4caa72eSAnthony Koo if (power_up != 815d4caa72eSAnthony Koo link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 816172c9b77SAshley Thomas 81778d5d04dSCharlene Liu unsigned long long current_ts = dm_get_timestamp(ctx); 818172c9b77SAshley Thomas unsigned long long time_since_edp_poweroff_ms = 81993ed1814SHugo Hu div64_u64(dm_get_elapse_time_in_ns( 82078d5d04dSCharlene Liu ctx, 82178d5d04dSCharlene Liu current_ts, 82293ed1814SHugo Hu link->link_trace.time_stamp.edp_poweroff), 1000000); 823172c9b77SAshley Thomas unsigned long long time_since_edp_poweron_ms = 824172c9b77SAshley Thomas div64_u64(dm_get_elapse_time_in_ns( 825172c9b77SAshley Thomas ctx, 826172c9b77SAshley Thomas current_ts, 827172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron), 1000000); 828172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 829172c9b77SAshley Thomas "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 830172c9b77SAshley Thomas __func__, 831172c9b77SAshley Thomas power_up, 832172c9b77SAshley Thomas current_ts, 833172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 834172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron, 835172c9b77SAshley Thomas time_since_edp_poweroff_ms, 836172c9b77SAshley Thomas time_since_edp_poweron_ms); 83778d5d04dSCharlene Liu 838172c9b77SAshley Thomas /* Send VBIOS command to prompt eDP panel power */ 839172c9b77SAshley Thomas if (power_up) { 840172c9b77SAshley Thomas /* edp requires a min of 500ms from LCDVDD off to on */ 841172c9b77SAshley Thomas unsigned long long remaining_min_edp_poweroff_time_ms = 500; 842ff587987SHugo Hu 843172c9b77SAshley Thomas /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 8446c4fff06SYue Hin Lau if (link->local_sink != NULL) 845172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms += 846172c9b77SAshley Thomas link->local_sink->edid_caps.panel_patch.extra_t12_ms; 84778d5d04dSCharlene Liu 848172c9b77SAshley Thomas /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 849172c9b77SAshley Thomas if (link->link_trace.time_stamp.edp_poweroff != 0) { 850172c9b77SAshley Thomas if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 851172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 852172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 853172c9b77SAshley Thomas else 854172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 0; 85578d5d04dSCharlene Liu } 85678d5d04dSCharlene Liu 857172c9b77SAshley Thomas if (remaining_min_edp_poweroff_time_ms) { 858172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 859172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 860172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 861172c9b77SAshley Thomas msleep(remaining_min_edp_poweroff_time_ms); 862172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 863172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 864172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 865172c9b77SAshley Thomas dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 866172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 867172c9b77SAshley Thomas } else { 868172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 869172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 870172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 871172c9b77SAshley Thomas } 87278d5d04dSCharlene Liu } 87387401969SAndrew Jiang 8741296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 875172c9b77SAshley Thomas "%s: BEGIN: Panel Power action: %s\n", 87687401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 87787401969SAndrew Jiang 87887401969SAndrew Jiang cntl.action = power_up ? 87987401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_ON : 88087401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_OFF; 881069d418fSAndrew Jiang cntl.transmitter = link->link_enc->transmitter; 882069d418fSAndrew Jiang cntl.connector_obj_id = link->link_enc->connector; 88387401969SAndrew Jiang cntl.coherent = false; 88487401969SAndrew Jiang cntl.lanes_number = LANE_COUNT_FOUR; 885069d418fSAndrew Jiang cntl.hpd_sel = link->link_enc->hpd_source; 88606ddcee4SJake Wang panel_instance = link->panel_cntl->inst; 8878a0e210cSChris Park 8888a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 8898a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 8908a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) 8918a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 89206ddcee4SJake Wang LVTMA_CONTROL_POWER_ON, 89306ddcee4SJake Wang panel_instance); 8948a0e210cSChris Park else 8958a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 89606ddcee4SJake Wang LVTMA_CONTROL_POWER_OFF, 89706ddcee4SJake Wang panel_instance); 8988a0e210cSChris Park } 8998a0e210cSChris Park 90087401969SAndrew Jiang bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 90187401969SAndrew Jiang 902172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 903172c9b77SAshley Thomas "%s: END: Panel Power action: %s bp_result=%u\n", 904172c9b77SAshley Thomas __func__, (power_up ? "On":"Off"), 905172c9b77SAshley Thomas bp_result); 906172c9b77SAshley Thomas 90778d5d04dSCharlene Liu if (!power_up) 90878d5d04dSCharlene Liu /*save driver power off time stamp*/ 90978d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 91078d5d04dSCharlene Liu else 91178d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 91278d5d04dSCharlene Liu 913172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 914172c9b77SAshley Thomas "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 915172c9b77SAshley Thomas __func__, 916172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 917172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron); 918172c9b77SAshley Thomas 91987401969SAndrew Jiang if (bp_result != BP_RESULT_OK) 9201296423bSBhawanpreet Lakha DC_LOG_ERROR( 92187401969SAndrew Jiang "%s: Panel Power bp_result: %d\n", 92287401969SAndrew Jiang __func__, bp_result); 92387401969SAndrew Jiang } else { 9241296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 92587401969SAndrew Jiang "%s: Skipping Panel Power action: %s\n", 92687401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 92787401969SAndrew Jiang } 92887401969SAndrew Jiang } 9295eefbc40SYue Hin Lau 930cf3a2627SJun Lei void dce110_edp_wait_for_T12( 931cf3a2627SJun Lei struct dc_link *link) 932cf3a2627SJun Lei { 933cf3a2627SJun Lei struct dc_context *ctx = link->ctx; 934cf3a2627SJun Lei 935cf3a2627SJun Lei if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 936cf3a2627SJun Lei != CONNECTOR_ID_EDP) { 937cf3a2627SJun Lei BREAK_TO_DEBUGGER(); 938cf3a2627SJun Lei return; 939cf3a2627SJun Lei } 940cf3a2627SJun Lei 941cf3a2627SJun Lei if (!link->panel_cntl) 942cf3a2627SJun Lei return; 943cf3a2627SJun Lei 944cf3a2627SJun Lei if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 945cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff != 0) { 946cf3a2627SJun Lei unsigned int t12_duration = 500; // Default T12 as per spec 947cf3a2627SJun Lei unsigned long long current_ts = dm_get_timestamp(ctx); 948cf3a2627SJun Lei unsigned long long time_since_edp_poweroff_ms = 949cf3a2627SJun Lei div64_u64(dm_get_elapse_time_in_ns( 950cf3a2627SJun Lei ctx, 951cf3a2627SJun Lei current_ts, 952cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff), 1000000); 953cf3a2627SJun Lei 954cf3a2627SJun Lei t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12 955cf3a2627SJun Lei 956cf3a2627SJun Lei if (time_since_edp_poweroff_ms < t12_duration) 957cf3a2627SJun Lei msleep(t12_duration - time_since_edp_poweroff_ms); 958cf3a2627SJun Lei } 959cf3a2627SJun Lei } 960cf3a2627SJun Lei 9615eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 9625eefbc40SYue Hin Lau /* 9635eefbc40SYue Hin Lau * @brief 9645eefbc40SYue Hin Lau * eDP only. Control the backlight of the eDP panel 9655eefbc40SYue Hin Lau */ 9668a31820bSMartin Leung void dce110_edp_backlight_control( 9675eefbc40SYue Hin Lau struct dc_link *link, 9685eefbc40SYue Hin Lau bool enable) 9695eefbc40SYue Hin Lau { 970069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 9715eefbc40SYue Hin Lau struct bp_transmitter_control cntl = { 0 }; 97206ddcee4SJake Wang uint8_t panel_instance; 9735eefbc40SYue Hin Lau 974069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 9755eefbc40SYue Hin Lau != CONNECTOR_ID_EDP) { 9765eefbc40SYue Hin Lau BREAK_TO_DEBUGGER(); 9775eefbc40SYue Hin Lau return; 9785eefbc40SYue Hin Lau } 9795eefbc40SYue Hin Lau 980014427adSSherry if (link->panel_cntl) { 981014427adSSherry bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 982014427adSSherry 983014427adSSherry if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 9841296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 985014427adSSherry "%s: panel already powered up/off. Do nothing.\n", 9865eefbc40SYue Hin Lau __func__); 9875eefbc40SYue Hin Lau return; 9885eefbc40SYue Hin Lau } 989014427adSSherry } 9905eefbc40SYue Hin Lau 9915eefbc40SYue Hin Lau /* Send VBIOS command to control eDP panel backlight */ 9925eefbc40SYue Hin Lau 9931296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 9945eefbc40SYue Hin Lau "%s: backlight action: %s\n", 9955eefbc40SYue Hin Lau __func__, (enable ? "On":"Off")); 9965eefbc40SYue Hin Lau 9975eefbc40SYue Hin Lau cntl.action = enable ? 9985eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_ON : 9995eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_OFF; 100087401969SAndrew Jiang 10015eefbc40SYue Hin Lau /*cntl.engine_id = ctx->engine;*/ 10025eefbc40SYue Hin Lau cntl.transmitter = link->link_enc->transmitter; 10035eefbc40SYue Hin Lau cntl.connector_obj_id = link->link_enc->connector; 10045eefbc40SYue Hin Lau /*todo: unhardcode*/ 10055eefbc40SYue Hin Lau cntl.lanes_number = LANE_COUNT_FOUR; 10065eefbc40SYue Hin Lau cntl.hpd_sel = link->link_enc->hpd_source; 1007cf1835f0SCharlene Liu cntl.signal = SIGNAL_TYPE_EDP; 10085eefbc40SYue Hin Lau 10095eefbc40SYue Hin Lau /* For eDP, the following delays might need to be considered 10105eefbc40SYue Hin Lau * after link training completed: 10115eefbc40SYue Hin Lau * idle period - min. accounts for required BS-Idle pattern, 10125eefbc40SYue Hin Lau * max. allows for source frame synchronization); 10135eefbc40SYue Hin Lau * 50 msec max. delay from valid video data from source 10145eefbc40SYue Hin Lau * to video on dislpay or backlight enable. 10155eefbc40SYue Hin Lau * 10165eefbc40SYue Hin Lau * Disable the delay for now. 10175eefbc40SYue Hin Lau * Enable it in the future if necessary. 10185eefbc40SYue Hin Lau */ 10195eefbc40SYue Hin Lau /* dc_service_sleep_in_milliseconds(50); */ 10205180d4a4SCharlene Liu /*edp 1.2*/ 102106ddcee4SJake Wang panel_instance = link->panel_cntl->inst; 1022a5148245SZhan Liu 1023a5148245SZhan Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { 1024a5148245SZhan Liu if (!link->dc->config.edp_no_power_sequencing) 1025a5148245SZhan Liu /* 1026a5148245SZhan Liu * Sometimes, DP receiver chip power-controlled externally by an 1027a5148245SZhan Liu * Embedded Controller could be treated and used as eDP, 1028a5148245SZhan Liu * if it drives mobile display. In this case, 1029a5148245SZhan Liu * we shouldn't be doing power-sequencing, hence we can skip 1030a5148245SZhan Liu * waiting for T7-ready. 1031a5148245SZhan Liu */ 10325180d4a4SCharlene Liu edp_receiver_ready_T7(link); 1033a5148245SZhan Liu else 1034a5148245SZhan Liu DC_LOG_DC("edp_receiver_ready_T7 skipped\n"); 1035a5148245SZhan Liu } 10368a0e210cSChris Park 10378a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 10388a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 10398a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 10408a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 104106ddcee4SJake Wang LVTMA_CONTROL_LCD_BLON, 104206ddcee4SJake Wang panel_instance); 10438a0e210cSChris Park else 10448a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 104506ddcee4SJake Wang LVTMA_CONTROL_LCD_BLOFF, 104606ddcee4SJake Wang panel_instance); 10478a0e210cSChris Park } 10488a0e210cSChris Park 1049069d418fSAndrew Jiang link_transmitter_control(ctx->dc_bios, &cntl); 105096577cf8SHersen Wu 105196577cf8SHersen Wu if (enable && link->dpcd_sink_ext_caps.bits.oled) 105296577cf8SHersen Wu msleep(OLED_POST_T7_DELAY); 105396577cf8SHersen Wu 105496577cf8SHersen Wu if (link->dpcd_sink_ext_caps.bits.oled || 105596577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 105696577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 105796577cf8SHersen Wu dc_link_backlight_enable_aux(link, enable); 105896577cf8SHersen Wu 105969b9723aSCharlene Liu /*edp 1.2*/ 1060a5148245SZhan Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) { 1061a5148245SZhan Liu if (!link->dc->config.edp_no_power_sequencing) 1062a5148245SZhan Liu /* 1063a5148245SZhan Liu * Sometimes, DP receiver chip power-controlled externally by an 1064a5148245SZhan Liu * Embedded Controller could be treated and used as eDP, 1065a5148245SZhan Liu * if it drives mobile display. In this case, 1066a5148245SZhan Liu * we shouldn't be doing power-sequencing, hence we can skip 1067a5148245SZhan Liu * waiting for T9-ready. 1068a5148245SZhan Liu */ 10693a372bedSHugo Hu edp_add_delay_for_T9(link); 1070a5148245SZhan Liu else 1071a5148245SZhan Liu DC_LOG_DC("edp_receiver_ready_T9 skipped\n"); 1072a5148245SZhan Liu } 107396577cf8SHersen Wu 107496577cf8SHersen Wu if (!enable && link->dpcd_sink_ext_caps.bits.oled) 107596577cf8SHersen Wu msleep(OLED_PRE_T11_DELAY); 10765eefbc40SYue Hin Lau } 10775eefbc40SYue Hin Lau 10781a05873fSAnthony Koo void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 10794562236bSHarry Wentland { 10801a05873fSAnthony Koo /* notify audio driver for audio modes of monitor */ 10812b77dcc5SAnthony Koo struct dc *dc; 10821d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 10831a05873fSAnthony Koo unsigned int i, num_audio = 1; 10841a05873fSAnthony Koo 10851d0610bcSAlvin Lee if (!pipe_ctx->stream) 10861d0610bcSAlvin Lee return; 10871d0610bcSAlvin Lee 10882b77dcc5SAnthony Koo dc = pipe_ctx->stream->ctx->dc; 10892b77dcc5SAnthony Koo clk_mgr = dc->clk_mgr; 10901d0610bcSAlvin Lee 10910a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 10920a32df9cSEryk Brol return; 10930a32df9cSEryk Brol 10941a05873fSAnthony Koo if (pipe_ctx->stream_res.audio) { 10951a05873fSAnthony Koo for (i = 0; i < MAX_PIPES; i++) { 10961a05873fSAnthony Koo /*current_state not updated yet*/ 10972b77dcc5SAnthony Koo if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 10981a05873fSAnthony Koo num_audio++; 10991a05873fSAnthony Koo } 11001a05873fSAnthony Koo 11011a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 11021a05873fSAnthony Koo 1103170a2398SSu Sung Chung if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 11041a05873fSAnthony Koo /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1105170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 11061a05873fSAnthony Koo /* un-mute audio */ 11071a05873fSAnthony Koo /* TODO: audio should be per stream rather than per link */ 1108f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1109f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( 1110f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc, false); 1111f01ee019SFangzhi Zuo else 11121a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 11131a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, false); 11140a32df9cSEryk Brol if (pipe_ctx->stream_res.audio) 11150a32df9cSEryk Brol pipe_ctx->stream_res.audio->enabled = true; 11161a05873fSAnthony Koo } 11173550d622SLeo (Hanghong) Ma 11183550d622SLeo (Hanghong) Ma if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11193550d622SLeo (Hanghong) Ma dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM); 11201a05873fSAnthony Koo } 11211a05873fSAnthony Koo 112257430404SSu Sung Chung void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 11231a05873fSAnthony Koo { 11241d0610bcSAlvin Lee struct dc *dc; 11251d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 11261d0610bcSAlvin Lee 11271d0610bcSAlvin Lee if (!pipe_ctx || !pipe_ctx->stream) 11281d0610bcSAlvin Lee return; 11291d0610bcSAlvin Lee 11301d0610bcSAlvin Lee dc = pipe_ctx->stream->ctx->dc; 11311d0610bcSAlvin Lee clk_mgr = dc->clk_mgr; 11324562236bSHarry Wentland 11330a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 11340a32df9cSEryk Brol return; 11350a32df9cSEryk Brol 1136f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1137f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( 1138f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc, true); 1139f01ee019SFangzhi Zuo else 11402b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 11412b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc, true); 1142afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio) { 11433f52aa9fSNicholas Kazlauskas pipe_ctx->stream_res.audio->enabled = false; 11443f52aa9fSNicholas Kazlauskas 11454562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1146f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1147f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable( 1148f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1149f01ee019SFangzhi Zuo else 11508e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 11518e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 11524562236bSHarry Wentland else 11538e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 11548e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 115557430404SSu Sung Chung 1156170a2398SSu Sung Chung if (clk_mgr->funcs->enable_pme_wa) 1157070fe724SCharlene Liu /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1158170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 11594562236bSHarry Wentland 11604562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 11614562236bSHarry Wentland * add audio mode list change flag */ 11624562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 11634562236bSHarry Wentland * stream->stream_engine_id); 11644562236bSHarry Wentland */ 11654562236bSHarry Wentland } 11663550d622SLeo (Hanghong) Ma 11673550d622SLeo (Hanghong) Ma if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11683550d622SLeo (Hanghong) Ma dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM); 11691a05873fSAnthony Koo } 11704562236bSHarry Wentland 117157430404SSu Sung Chung void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 11721a05873fSAnthony Koo { 11731a05873fSAnthony Koo struct dc_stream_state *stream = pipe_ctx->stream; 1174ceb3dbb4SJun Lei struct dc_link *link = stream->link; 11751a05873fSAnthony Koo struct dc *dc = pipe_ctx->stream->ctx->dc; 11769d8033d6SWenjing Liu const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 11771a05873fSAnthony Koo 1178ac42fd63SWenjing Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 11791a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 11801a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 1181ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1182ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc); 1183ac42fd63SWenjing Liu } 11841a05873fSAnthony Koo 1185f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) { 1186f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets( 1187f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1188f01ee019SFangzhi Zuo } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11891a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 11901a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 11911a05873fSAnthony Koo 119257430404SSu Sung Chung dc->hwss.disable_audio_stream(pipe_ctx); 1193904623eeSYongqiang Sun 11949d8033d6SWenjing Liu link_hwss->reset_stream_encoder(pipe_ctx); 119564d283cbSJimmy Kizito 1196f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) { 11979d8033d6SWenjing Liu /* TODO: This looks like a bug to me as we are disabling HPO IO when 11989d8033d6SWenjing Liu * we are just disabling a single HPO stream. Shouldn't we disable HPO 11999d8033d6SWenjing Liu * HW control only when HPOs for all streams are disabled? 12009d8033d6SWenjing Liu */ 12019d8033d6SWenjing Liu if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control) 12029d8033d6SWenjing Liu pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control( 12039d8033d6SWenjing Liu pipe_ctx->stream->ctx->dc->hwseq, false); 1204f01ee019SFangzhi Zuo } 12054562236bSHarry Wentland } 12064562236bSHarry Wentland 12074562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 12084562236bSHarry Wentland struct dc_link_settings *link_settings) 12094562236bSHarry Wentland { 12104562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 121141b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1212ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1213f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 12144562236bSHarry Wentland 12154562236bSHarry Wentland /* only 3 items below are used by unblank */ 12167fe538a4SCharlene Liu params.timing = pipe_ctx->stream->timing; 12174562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 121841b49742SCharlene Liu 121941b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 12203550d622SLeo (Hanghong) Ma pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 122141b49742SCharlene Liu 122214d6f644SYongqiang Sun if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1223f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, true); 122414d6f644SYongqiang Sun } 122541b49742SCharlene Liu } 12262c850b7bSDmytro Laktyushkin 122741b49742SCharlene Liu void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 122841b49742SCharlene Liu { 122941b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1230ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1231f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 123241b49742SCharlene Liu 1233ab892598SRoman Li if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1234f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, false); 12353ba01817SYongqiang Sun link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1236ab892598SRoman Li } 123741b49742SCharlene Liu 1238f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) { 1239f01ee019SFangzhi Zuo /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1240f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank( 1241f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1242f01ee019SFangzhi Zuo } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 12433550d622SLeo (Hanghong) Ma pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc); 1244eec3303dSAric Cyr 12453a372bedSHugo Hu if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1246eec3303dSAric Cyr /* 1247eec3303dSAric Cyr * After output is idle pattern some sinks need time to recognize the stream 1248eec3303dSAric Cyr * has changed or they enter protection state and hang. 1249eec3303dSAric Cyr */ 1250eec3303dSAric Cyr msleep(60); 12513a372bedSHugo Hu } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) 12523a372bedSHugo Hu edp_receiver_ready_T9(link); 1253eec3303dSAric Cyr } 1254eec3303dSAric Cyr 12554562236bSHarry Wentland } 12564562236bSHarry Wentland 125715e17335SCharlene Liu 125815e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 125915e17335SCharlene Liu { 12608e9c4c8cSHarry Wentland if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 12618e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 126215e17335SCharlene Liu } 126315e17335SCharlene Liu 12644562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 12654562236bSHarry Wentland { 12664562236bSHarry Wentland switch (crtc_id) { 12674562236bSHarry Wentland case CONTROLLER_ID_D0: 12684562236bSHarry Wentland return DTO_SOURCE_ID0; 12694562236bSHarry Wentland case CONTROLLER_ID_D1: 12704562236bSHarry Wentland return DTO_SOURCE_ID1; 12714562236bSHarry Wentland case CONTROLLER_ID_D2: 12724562236bSHarry Wentland return DTO_SOURCE_ID2; 12734562236bSHarry Wentland case CONTROLLER_ID_D3: 12744562236bSHarry Wentland return DTO_SOURCE_ID3; 12754562236bSHarry Wentland case CONTROLLER_ID_D4: 12764562236bSHarry Wentland return DTO_SOURCE_ID4; 12774562236bSHarry Wentland case CONTROLLER_ID_D5: 12784562236bSHarry Wentland return DTO_SOURCE_ID5; 12794562236bSHarry Wentland default: 12804562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 12814562236bSHarry Wentland } 12824562236bSHarry Wentland } 12834562236bSHarry Wentland 12844562236bSHarry Wentland static void build_audio_output( 1285ab8db3e1SAndrey Grodzovsky struct dc_state *state, 12864562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 12874562236bSHarry Wentland struct audio_output *audio_output) 12884562236bSHarry Wentland { 12890971c40eSHarry Wentland const struct dc_stream_state *stream = pipe_ctx->stream; 12908e9c4c8cSHarry Wentland audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 12914562236bSHarry Wentland 12924562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 12934562236bSHarry Wentland 12944562236bSHarry Wentland /* audio_crtc_info */ 12954562236bSHarry Wentland 12964562236bSHarry Wentland audio_output->crtc_info.h_total = 12974fa086b9SLeo (Sunpeng) Li stream->timing.h_total; 12984562236bSHarry Wentland 12994562236bSHarry Wentland /* 13004562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 13014562236bSHarry Wentland * need to specify actual active signal portion 13024562236bSHarry Wentland */ 13034562236bSHarry Wentland audio_output->crtc_info.h_active = 13044fa086b9SLeo (Sunpeng) Li stream->timing.h_addressable 13054fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_left 13064fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_right; 13074562236bSHarry Wentland 13084562236bSHarry Wentland audio_output->crtc_info.v_active = 13094fa086b9SLeo (Sunpeng) Li stream->timing.v_addressable 13104fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_top 13114fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_bottom; 13124562236bSHarry Wentland 13134562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 13144562236bSHarry Wentland 13154562236bSHarry Wentland audio_output->crtc_info.interlaced = 13164fa086b9SLeo (Sunpeng) Li stream->timing.flags.INTERLACE; 13174562236bSHarry Wentland 13184562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 131940fd9090SNevenko Stupar (stream->timing.pix_clk_100hz*100)/ 13204fa086b9SLeo (Sunpeng) Li (stream->timing.h_total*stream->timing.v_total); 13214562236bSHarry Wentland 13224562236bSHarry Wentland audio_output->crtc_info.color_depth = 13234fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth; 13244562236bSHarry Wentland 132540fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 132640fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 13274562236bSHarry Wentland 132840fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 132940fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 13304562236bSHarry Wentland 133187b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 13322166d9fbSCharlene Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 133340fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz == 133440fd9090SNevenko Stupar (stream->timing.pix_clk_100hz)) { 133510688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 133640fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 133740fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz/2; 133840fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 133940fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 134087b58768SCharlene Liu 134187b58768SCharlene Liu } 134287b58768SCharlene Liu } 134387b58768SCharlene Liu 1344ed476602SAhzo if (state->clk_mgr && 1345ed476602SAhzo (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1346ed476602SAhzo pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 13474562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 13480de34efcSDmytro Laktyushkin state->clk_mgr->funcs->get_dp_ref_clk_frequency( 13490de34efcSDmytro Laktyushkin state->clk_mgr); 13504562236bSHarry Wentland } 13514562236bSHarry Wentland 13524562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 13534562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 13544562236bSHarry Wentland 13554562236bSHarry Wentland audio_output->pll_info.dto_source = 13564562236bSHarry Wentland translate_to_dto_source( 1357e07f541fSYongqiang Sun pipe_ctx->stream_res.tg->inst + 1); 13584562236bSHarry Wentland 13594562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 13604562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 13614562236bSHarry Wentland 13624562236bSHarry Wentland audio_output->pll_info.ss_percentage = 13634562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 13644562236bSHarry Wentland } 13654562236bSHarry Wentland 1366fb3466a4SBhawanpreet Lakha static void program_scaler(const struct dc *dc, 13674562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 13684562236bSHarry Wentland { 13694562236bSHarry Wentland struct tg_color color = {0}; 13704562236bSHarry Wentland 1371b86a1aa3SBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC_DCN) 1372ff5ef992SAlex Deucher /* TOFPGA */ 137386a66c4eSHarry Wentland if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1374ff5ef992SAlex Deucher return; 1375ff5ef992SAlex Deucher #endif 1376ff5ef992SAlex Deucher 1377bf53769dSGloria Li if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 13784562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 13794562236bSHarry Wentland else 13804562236bSHarry Wentland color_space_to_black_color(dc, 13814fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space, 13824562236bSHarry Wentland &color); 13834562236bSHarry Wentland 138486a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 138586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, 13866702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.depth, 13874562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 13884562236bSHarry Wentland 138912750d16SEric Yang if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 139012750d16SEric Yang /* 139112750d16SEric Yang * The way 420 is packed, 2 channels carry Y component, 1 channel 139212750d16SEric Yang * alternate between Cb and Cr, so both channels need the pixel 139312750d16SEric Yang * value for Y 139412750d16SEric Yang */ 139512750d16SEric Yang if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 139612750d16SEric Yang color.color_r_cr = color.color_g_y; 139712750d16SEric Yang 13986b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 13996b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14004562236bSHarry Wentland &color); 140112750d16SEric Yang } 14024562236bSHarry Wentland 140386a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 14046702a9acSHarry Wentland &pipe_ctx->plane_res.scl_data); 14054562236bSHarry Wentland } 14064562236bSHarry Wentland 14073158223eSEric Bernstein static enum dc_status dce110_enable_stream_timing( 14084562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1409608ac7bbSJerry Zuo struct dc_state *context, 1410fb3466a4SBhawanpreet Lakha struct dc *dc) 14114562236bSHarry Wentland { 14120971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1413608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 14144562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 14154562236bSHarry Wentland struct tg_color black_color = {0}; 14164562236bSHarry Wentland 14174562236bSHarry Wentland if (!pipe_ctx_old->stream) { 14184562236bSHarry Wentland 14194562236bSHarry Wentland /* program blank color */ 14204562236bSHarry Wentland color_space_to_black_color(dc, 14214fa086b9SLeo (Sunpeng) Li stream->output_color_space, &black_color); 14226b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank_color( 14236b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14244562236bSHarry Wentland &black_color); 14254b5e7d62SHersen Wu 14264562236bSHarry Wentland /* 14274562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 14284562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 14294562236bSHarry Wentland */ 14306b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 14314562236bSHarry Wentland 14324562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 14334562236bSHarry Wentland pipe_ctx->clock_source, 143410688217SHarry Wentland &pipe_ctx->stream_res.pix_clk_params, 14354562236bSHarry Wentland &pipe_ctx->pll_settings)) { 14364562236bSHarry Wentland BREAK_TO_DEBUGGER(); 14374562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 14384562236bSHarry Wentland } 14394562236bSHarry Wentland 14406b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->program_timing( 14416b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14424fa086b9SLeo (Sunpeng) Li &stream->timing, 1443e7e10c46SDmytro Laktyushkin 0, 1444e7e10c46SDmytro Laktyushkin 0, 1445e7e10c46SDmytro Laktyushkin 0, 1446e7e10c46SDmytro Laktyushkin 0, 1447e7e10c46SDmytro Laktyushkin pipe_ctx->stream->signal, 14484562236bSHarry Wentland true); 14494562236bSHarry Wentland } 14504562236bSHarry Wentland 14514562236bSHarry Wentland if (!pipe_ctx_old->stream) { 14526b670fa9SHarry Wentland if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 14536b670fa9SHarry Wentland pipe_ctx->stream_res.tg)) { 14544562236bSHarry Wentland BREAK_TO_DEBUGGER(); 14554562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 14564562236bSHarry Wentland } 14574562236bSHarry Wentland } 14584562236bSHarry Wentland 14594562236bSHarry Wentland return DC_OK; 14604562236bSHarry Wentland } 14614562236bSHarry Wentland 14624562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 14634562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1464608ac7bbSJerry Zuo struct dc_state *context, 1465fb3466a4SBhawanpreet Lakha struct dc *dc) 14664562236bSHarry Wentland { 14670971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 14683550d622SLeo (Hanghong) Ma struct dc_link *link = stream->link; 14699c0fb8d4SAnthony Koo struct drr_params params = {0}; 14709c0fb8d4SAnthony Koo unsigned int event_triggers = 0; 1471b1f6d01cSDmytro Laktyushkin struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1472f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 14734562236bSHarry Wentland 1474f42ea55bSAnthony Koo if (hws->funcs.disable_stream_gating) { 1475f42ea55bSAnthony Koo hws->funcs.disable_stream_gating(dc, pipe_ctx); 1476240d09d0SGary Kattan } 1477240d09d0SGary Kattan 14781a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 14791a05873fSAnthony Koo struct audio_output audio_output; 14801a05873fSAnthony Koo 14811a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 14821a05873fSAnthony Koo 14831a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1484f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1485f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( 1486f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc, 1487f01ee019SFangzhi Zuo pipe_ctx->stream_res.audio->inst, 1488f01ee019SFangzhi Zuo &pipe_ctx->stream->audio_info); 1489f01ee019SFangzhi Zuo else 14901a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 14911a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 14921a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 14931a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 14941a05873fSAnthony Koo else 14951a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 14961a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 14971a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 14981a05873fSAnthony Koo &pipe_ctx->stream->audio_info, 14991a05873fSAnthony Koo &audio_output.crtc_info); 15001a05873fSAnthony Koo 15011a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_configure( 15021a05873fSAnthony Koo pipe_ctx->stream_res.audio, 15031a05873fSAnthony Koo pipe_ctx->stream->signal, 15041a05873fSAnthony Koo &audio_output.crtc_info, 15051a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 15061a05873fSAnthony Koo } 15071a05873fSAnthony Koo 1508a896f870SMeenakshikumar Somasundaram /* make sure no pipes syncd to the pipe being enabled */ 1509a896f870SMeenakshikumar Somasundaram if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic) 1510a896f870SMeenakshikumar Somasundaram check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); 1511a896f870SMeenakshikumar Somasundaram 1512f01ee019SFangzhi Zuo /* DCN3.1 FPGA Workaround 1513f01ee019SFangzhi Zuo * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1514f01ee019SFangzhi Zuo * To do so, move calling function enable_stream_timing to only be done AFTER calling 1515f01ee019SFangzhi Zuo * function core_link_enable_stream 1516f01ee019SFangzhi Zuo */ 1517f01ee019SFangzhi Zuo if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx))) 15184562236bSHarry Wentland /* */ 1519d2d7885fSAnthony Koo /* Do not touch stream timing on seamless boot optimization. */ 1520d2d7885fSAnthony Koo if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1521f42ea55bSAnthony Koo hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 15224562236bSHarry Wentland 1523f42ea55bSAnthony Koo if (hws->funcs.setup_vupdate_interrupt) 1524f42ea55bSAnthony Koo hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1525a122b62dSAnthony Koo 15269c0fb8d4SAnthony Koo params.vertical_total_min = stream->adjust.v_total_min; 15279c0fb8d4SAnthony Koo params.vertical_total_max = stream->adjust.v_total_max; 15289c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_drr) 15299c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_drr( 15309c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg, ¶ms); 15319c0fb8d4SAnthony Koo 15329c0fb8d4SAnthony Koo // DRR should set trigger event to monitor surface update event 15339c0fb8d4SAnthony Koo if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 15349c0fb8d4SAnthony Koo event_triggers = 0x80; 15355b5abe95SAnthony Koo /* Event triggers and num frames initialized for DRR, but can be 15365b5abe95SAnthony Koo * later updated for PSR use. Note DRR trigger events are generated 15375b5abe95SAnthony Koo * regardless of whether num frames met. 15385b5abe95SAnthony Koo */ 15399c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 15409c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 15415b5abe95SAnthony Koo pipe_ctx->stream_res.tg, event_triggers, 2); 15429c0fb8d4SAnthony Koo 1543248cbed6SEric Bernstein if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1544d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1545d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc, 1546d2c460e7Shersen wu pipe_ctx->stream_res.tg->inst); 1547aa9c4abeSNikola Cornij 15483550d622SLeo (Hanghong) Ma if (dc_is_dp_signal(pipe_ctx->stream->signal)) 15493550d622SLeo (Hanghong) Ma dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG); 15503550d622SLeo (Hanghong) Ma 1551f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1552f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp, 1553f0c4d997SCorbin McElhanney COLOR_SPACE_YCBCR601, 1554f0c4d997SCorbin McElhanney stream->timing.display_color_depth, 1555661a8cd9SDmytro Laktyushkin stream->signal); 15564562236bSHarry Wentland 1557a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1558a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 1559181a888fSCharlene Liu &stream->bit_depth_params, 1560181a888fSCharlene Liu &stream->clamping); 1561b1f6d01cSDmytro Laktyushkin while (odm_pipe) { 15627ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 15637ed4e635SHarry Wentland odm_pipe->stream_res.opp, 15647ed4e635SHarry Wentland COLOR_SPACE_YCBCR601, 15657ed4e635SHarry Wentland stream->timing.display_color_depth, 15667ed4e635SHarry Wentland stream->signal); 15677ed4e635SHarry Wentland 15687ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_program_fmt( 15697ed4e635SHarry Wentland odm_pipe->stream_res.opp, 15707ed4e635SHarry Wentland &stream->bit_depth_params, 15717ed4e635SHarry Wentland &stream->clamping); 1572b1f6d01cSDmytro Laktyushkin odm_pipe = odm_pipe->next_odm_pipe; 15737ed4e635SHarry Wentland } 1574603767f9STony Cheng 15751e7e86c4SSamson Tam if (!stream->dpms_off) 1576ab8db3e1SAndrey Grodzovsky core_link_enable_stream(context, pipe_ctx); 15774562236bSHarry Wentland 1578f01ee019SFangzhi Zuo /* DCN3.1 FPGA Workaround 1579f01ee019SFangzhi Zuo * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1580f01ee019SFangzhi Zuo * To do so, move calling function enable_stream_timing to only be done AFTER calling 1581f01ee019SFangzhi Zuo * function core_link_enable_stream 1582f01ee019SFangzhi Zuo */ 1583f01ee019SFangzhi Zuo if (hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)) { 1584f01ee019SFangzhi Zuo if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1585f01ee019SFangzhi Zuo hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1586f01ee019SFangzhi Zuo } 1587f01ee019SFangzhi Zuo 15886702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 15894562236bSHarry Wentland 1590d1ebfdd8SWyatt Wood pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 159194267b3dSSylvia Tsai 15924562236bSHarry Wentland return DC_OK; 15934562236bSHarry Wentland } 15944562236bSHarry Wentland 15954562236bSHarry Wentland /******************************************************************************/ 15964562236bSHarry Wentland 1597fb3466a4SBhawanpreet Lakha static void power_down_encoders(struct dc *dc) 15984562236bSHarry Wentland { 1599ebd1e719SLeo (Hanghong) Ma int i; 1600b9b171ffSHersen Wu 16014562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 1602d4c2a96fSLewis Huang enum signal_type signal = dc->links[i]->connector_signal; 1603a0c38ebaSCharlene Liu 1604ebd1e719SLeo (Hanghong) Ma dc_link_blank_dp_stream(dc->links[i], false); 1605c494e579SAgustin Gutierrez 16064338ffa8SSung Lee if (signal != SIGNAL_TYPE_EDP) 16074338ffa8SSung Lee signal = SIGNAL_TYPE_NONE; 16084338ffa8SSung Lee 160964d283cbSJimmy Kizito if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY) 16104562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 1611069d418fSAndrew Jiang dc->links[i]->link_enc, signal); 1612b56e90eaSPaul Hsieh 1613b56e90eaSPaul Hsieh dc->links[i]->link_status.link_active = false; 161407920450SJoshua Aberback memset(&dc->links[i]->cur_link_settings, 0, 161507920450SJoshua Aberback sizeof(dc->links[i]->cur_link_settings)); 16164562236bSHarry Wentland } 16174562236bSHarry Wentland } 16184562236bSHarry Wentland 1619fb3466a4SBhawanpreet Lakha static void power_down_controllers(struct dc *dc) 16204562236bSHarry Wentland { 16214562236bSHarry Wentland int i; 16224562236bSHarry Wentland 16237f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 16244562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 16254562236bSHarry Wentland dc->res_pool->timing_generators[i]); 16264562236bSHarry Wentland } 16274562236bSHarry Wentland } 16284562236bSHarry Wentland 1629fb3466a4SBhawanpreet Lakha static void power_down_clock_sources(struct dc *dc) 16304562236bSHarry Wentland { 16314562236bSHarry Wentland int i; 16324562236bSHarry Wentland 16334562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 16344562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 16354562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 16364562236bSHarry Wentland 16374562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 16384562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 16394562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 16404562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 16414562236bSHarry Wentland } 16424562236bSHarry Wentland } 16434562236bSHarry Wentland 1644fb3466a4SBhawanpreet Lakha static void power_down_all_hw_blocks(struct dc *dc) 16454562236bSHarry Wentland { 16464562236bSHarry Wentland power_down_encoders(dc); 16474562236bSHarry Wentland 16484562236bSHarry Wentland power_down_controllers(dc); 16494562236bSHarry Wentland 16504562236bSHarry Wentland power_down_clock_sources(dc); 16511663ae1cSBhawanpreet Lakha 16522f3bfb27SRoman Li if (dc->fbc_compressor) 16531663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 16544562236bSHarry Wentland } 16554562236bSHarry Wentland 16564562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 1657fb3466a4SBhawanpreet Lakha struct dc *dc) 16584562236bSHarry Wentland { 16594562236bSHarry Wentland int i; 16604562236bSHarry Wentland struct timing_generator *tg; 16614562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 16624562236bSHarry Wentland 16637f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 16644562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 16654562236bSHarry Wentland 16660a87425aSTony Cheng if (tg->funcs->disable_vga) 16674562236bSHarry Wentland tg->funcs->disable_vga(tg); 16687f93c1deSCharlene Liu } 16697f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->pipe_count; i++) { 16704562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 16714562236bSHarry Wentland * powergating. */ 16724562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 16734562236bSHarry Wentland true); 16744562236bSHarry Wentland 1675e6c258cbSYongqiang Sun dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 16767f914a62SYongqiang Sun dc->hwss.disable_plane(dc, 1677e6c258cbSYongqiang Sun &dc->current_state->res_ctx.pipe_ctx[i]); 16784562236bSHarry Wentland } 16794562236bSHarry Wentland } 16804562236bSHarry Wentland 16813de5aa81SSivapiriyanKumarasamy 168245a1261bSJake Wang static void get_edp_streams(struct dc_state *context, 168345a1261bSJake Wang struct dc_stream_state **edp_streams, 168445a1261bSJake Wang int *edp_stream_num) 16853de5aa81SSivapiriyanKumarasamy { 16863de5aa81SSivapiriyanKumarasamy int i; 16873de5aa81SSivapiriyanKumarasamy 168845a1261bSJake Wang *edp_stream_num = 0; 16893de5aa81SSivapiriyanKumarasamy for (i = 0; i < context->stream_count; i++) { 169045a1261bSJake Wang if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 169145a1261bSJake Wang edp_streams[*edp_stream_num] = context->streams[i]; 169245a1261bSJake Wang if (++(*edp_stream_num) == MAX_NUM_EDP) 169345a1261bSJake Wang return; 16943de5aa81SSivapiriyanKumarasamy } 169545a1261bSJake Wang } 16963de5aa81SSivapiriyanKumarasamy } 16973de5aa81SSivapiriyanKumarasamy 169845a1261bSJake Wang static void get_edp_links_with_sink( 169925292028SYongqiang Sun struct dc *dc, 170045a1261bSJake Wang struct dc_link **edp_links_with_sink, 170145a1261bSJake Wang int *edp_with_sink_num) 170225292028SYongqiang Sun { 170325292028SYongqiang Sun int i; 170425292028SYongqiang Sun 170525292028SYongqiang Sun /* check if there is an eDP panel not in use */ 170645a1261bSJake Wang *edp_with_sink_num = 0; 170725292028SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 170825292028SYongqiang Sun if (dc->links[i]->local_sink && 170925292028SYongqiang Sun dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 171045a1261bSJake Wang edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; 171145a1261bSJake Wang if (++(*edp_with_sink_num) == MAX_NUM_EDP) 171245a1261bSJake Wang return; 171325292028SYongqiang Sun } 171425292028SYongqiang Sun } 171525292028SYongqiang Sun } 171625292028SYongqiang Sun 17171c17952eSLee Jones /* 17184562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 17194562236bSHarry Wentland * 1. Power down all DC HW blocks 17204562236bSHarry Wentland * 2. Disable VGA engine on all controllers 17214562236bSHarry Wentland * 3. Enable power gating for controller 17224562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 17234562236bSHarry Wentland */ 172425292028SYongqiang Sun void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 17254562236bSHarry Wentland { 172645a1261bSJake Wang struct dc_link *edp_links_with_sink[MAX_NUM_EDP]; 172745a1261bSJake Wang struct dc_link *edp_links[MAX_NUM_EDP]; 172845a1261bSJake Wang struct dc_stream_state *edp_streams[MAX_NUM_EDP]; 172945a1261bSJake Wang struct dc_link *edp_link_with_sink = NULL; 173045a1261bSJake Wang struct dc_link *edp_link = NULL; 173145a1261bSJake Wang struct dce_hwseq *hws = dc->hwseq; 173245a1261bSJake Wang int edp_with_sink_num; 173345a1261bSJake Wang int edp_num; 173445a1261bSJake Wang int edp_stream_num; 173545a1261bSJake Wang int i; 1736be4b289fSSivapiriyanKumarasamy bool can_apply_edp_fast_boot = false; 1737ce72741bSAnthony Koo bool can_apply_seamless_boot = false; 17383de5aa81SSivapiriyanKumarasamy bool keep_edp_vdd_on = false; 17390eda55caSMichael Strauss DC_LOGGER_INIT(); 17400eda55caSMichael Strauss 174145a1261bSJake Wang 174245a1261bSJake Wang get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); 174345a1261bSJake Wang get_edp_links(dc, edp_links, &edp_num); 1744ce72741bSAnthony Koo 1745f42ea55bSAnthony Koo if (hws->funcs.init_pipes) 1746f42ea55bSAnthony Koo hws->funcs.init_pipes(dc, context); 1747be4b289fSSivapiriyanKumarasamy 174845a1261bSJake Wang get_edp_streams(context, edp_streams, &edp_stream_num); 17493de5aa81SSivapiriyanKumarasamy 1750be4b289fSSivapiriyanKumarasamy // Check fastboot support, disable on DCE8 because of blank screens 1751b9957475SBrandon Syu if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 && 1752be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_1 && 1753be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_3) { 175445a1261bSJake Wang for (i = 0; i < edp_num; i++) { 175545a1261bSJake Wang edp_link = edp_links[i]; 1756b9957475SBrandon Syu if (edp_link != edp_streams[0]->link) 1757b9957475SBrandon Syu continue; 1758be4b289fSSivapiriyanKumarasamy // enable fastboot if backend is enabled on eDP 17594fe38194SMario Limonciello if (edp_link->link_enc->funcs->is_dig_enabled && 17604fe38194SMario Limonciello edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 17614fe38194SMario Limonciello edp_link->link_status.link_active) { 17622b36afc6SMario Limonciello struct dc_stream_state *edp_stream = edp_streams[0]; 17632b36afc6SMario Limonciello 1764*98ea24e6SPaul Hsieh can_apply_edp_fast_boot = dc_validate_boot_timing(dc, 1765*98ea24e6SPaul Hsieh edp_stream->sink, &edp_stream->timing); 1766f9fc6f39SMichael Strauss edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot; 17670eda55caSMichael Strauss if (can_apply_edp_fast_boot) 17680eda55caSMichael Strauss DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n"); 1769f9fc6f39SMichael Strauss 177045a1261bSJake Wang break; 1771be4b289fSSivapiriyanKumarasamy } 1772be4b289fSSivapiriyanKumarasamy } 17733de5aa81SSivapiriyanKumarasamy // We are trying to enable eDP, don't power down VDD 1774b9957475SBrandon Syu if (can_apply_edp_fast_boot) 17753de5aa81SSivapiriyanKumarasamy keep_edp_vdd_on = true; 1776be4b289fSSivapiriyanKumarasamy } 1777be4b289fSSivapiriyanKumarasamy 1778be4b289fSSivapiriyanKumarasamy // Check seamless boot support 1779ce72741bSAnthony Koo for (i = 0; i < context->stream_count; i++) { 1780ce72741bSAnthony Koo if (context->streams[i]->apply_seamless_boot_optimization) { 1781ce72741bSAnthony Koo can_apply_seamless_boot = true; 1782ce72741bSAnthony Koo break; 1783ce72741bSAnthony Koo } 1784ce72741bSAnthony Koo } 17854cac1e6dSYongqiang Sun 1786be4b289fSSivapiriyanKumarasamy /* eDP should not have stream in resume from S4 and so even with VBios post 1787be4b289fSSivapiriyanKumarasamy * it should get turned off 17882c37e49aSYongqiang Sun */ 178945a1261bSJake Wang if (edp_with_sink_num) 179045a1261bSJake Wang edp_link_with_sink = edp_links_with_sink[0]; 179145a1261bSJake Wang 1792be4b289fSSivapiriyanKumarasamy if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 17933de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) { 17944cac1e6dSYongqiang Sun /*turn off backlight before DP_blank and encoder powered down*/ 1795f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1796c5fc7f59SCharlene Liu } 1797c5fc7f59SCharlene Liu /*resume from S3, no vbios posting, no need to power down again*/ 179825292028SYongqiang Sun power_down_all_hw_blocks(dc); 17994562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 18003de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) 1801be4b289fSSivapiriyanKumarasamy dc->hwss.edp_power_control(edp_link_with_sink, false); 1802c5fc7f59SCharlene Liu } 18031c5ea40cSYao Wang1 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); 18044562236bSHarry Wentland } 18054562236bSHarry Wentland 18064562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 18074562236bSHarry Wentland struct bw_fixed blackout_duration, 18080971c40eSHarry Wentland const struct dc_stream_state *stream) 18094562236bSHarry Wentland { 18104562236bSHarry Wentland uint32_t total_dest_line_time_ns; 18114562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 18124562236bSHarry Wentland 18134562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 18144562236bSHarry Wentland 18154562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 1816380604e2SKen Chalmers (stream->timing.h_total * 10) / 1817380604e2SKen Chalmers stream->timing.pix_clk_100hz + 18184562236bSHarry Wentland pstate_blackout_duration_ns; 18194562236bSHarry Wentland 18204562236bSHarry Wentland return total_dest_line_time_ns; 18214562236bSHarry Wentland } 18224562236bSHarry Wentland 1823f774b339SEric Yang static void dce110_set_displaymarks( 1824fb3466a4SBhawanpreet Lakha const struct dc *dc, 1825608ac7bbSJerry Zuo struct dc_state *context) 18264562236bSHarry Wentland { 18274562236bSHarry Wentland uint8_t i, num_pipes; 18284562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 18294562236bSHarry Wentland 18304562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 18314562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 18324562236bSHarry Wentland uint32_t total_dest_line_time_ns; 18334562236bSHarry Wentland 18344562236bSHarry Wentland if (pipe_ctx->stream == NULL) 18354562236bSHarry Wentland continue; 18364562236bSHarry Wentland 18374562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 183877a4ea53SBhawanpreet Lakha dc->bw_vbios->blackout_duration, pipe_ctx->stream); 183986a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 184086a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1841813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1842813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1843813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1844813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 18454562236bSHarry Wentland total_dest_line_time_ns); 18464562236bSHarry Wentland if (i == underlay_idx) { 18474562236bSHarry Wentland num_pipes++; 184886a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 184986a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1850813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1851813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1852813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 18534562236bSHarry Wentland total_dest_line_time_ns); 18544562236bSHarry Wentland } 18554562236bSHarry Wentland num_pipes++; 18564562236bSHarry Wentland } 18574562236bSHarry Wentland } 18584562236bSHarry Wentland 1859fab55d61SDmytro Laktyushkin void dce110_set_safe_displaymarks( 1860a2b8659dSTony Cheng struct resource_context *res_ctx, 1861a2b8659dSTony Cheng const struct resource_pool *pool) 18624562236bSHarry Wentland { 18634562236bSHarry Wentland int i; 1864a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 18659037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 18664562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 18679037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 18684562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 18693722c794SMikita Lipski struct dce_watermarks min_marks = { 0, 0, 0, 0}; 18704562236bSHarry Wentland 18714562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 18728feabd03SYue Hin Lau if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 18734562236bSHarry Wentland continue; 18744562236bSHarry Wentland 187586a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 187686a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 18774562236bSHarry Wentland nbp_marks, 18784562236bSHarry Wentland max_marks, 18793722c794SMikita Lipski min_marks, 18804562236bSHarry Wentland max_marks, 18814562236bSHarry Wentland MAX_WATERMARK); 18828feabd03SYue Hin Lau 18834562236bSHarry Wentland if (i == underlay_idx) 188486a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 188586a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 18864562236bSHarry Wentland nbp_marks, 18874562236bSHarry Wentland max_marks, 18884562236bSHarry Wentland max_marks, 18894562236bSHarry Wentland MAX_WATERMARK); 18908feabd03SYue Hin Lau 18914562236bSHarry Wentland } 18924562236bSHarry Wentland } 18934562236bSHarry Wentland 18944562236bSHarry Wentland /******************************************************************************* 18954562236bSHarry Wentland * Public functions 18964562236bSHarry Wentland ******************************************************************************/ 18974562236bSHarry Wentland 18984562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 189949c70eceSAlvin Lee int num_pipes, struct dc_crtc_timing_adjust adjust) 19004562236bSHarry Wentland { 19014562236bSHarry Wentland int i = 0; 19024562236bSHarry Wentland struct drr_params params = {0}; 190398e6436dSAnthony Koo // DRR should set trigger event to monitor surface update event 190498e6436dSAnthony Koo unsigned int event_triggers = 0x80; 19055b5abe95SAnthony Koo // Note DRR trigger events are generated regardless of whether num frames met. 19065b5abe95SAnthony Koo unsigned int num_frames = 2; 19074562236bSHarry Wentland 190849c70eceSAlvin Lee params.vertical_total_max = adjust.v_total_max; 190949c70eceSAlvin Lee params.vertical_total_min = adjust.v_total_min; 19104562236bSHarry Wentland 19114562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 191298e6436dSAnthony Koo * some GSL stuff. Static screen triggers may be programmed differently 191398e6436dSAnthony Koo * as well. 19144562236bSHarry Wentland */ 19154562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 191698e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_drr( 191798e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, ¶ms); 191898e6436dSAnthony Koo 191949c70eceSAlvin Lee if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 192098e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 192198e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, 19225b5abe95SAnthony Koo event_triggers, num_frames); 19234562236bSHarry Wentland } 19244562236bSHarry Wentland } 19254562236bSHarry Wentland 192672ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 192772ada5f7SEric Cook int num_pipes, 192872ada5f7SEric Cook struct crtc_position *position) 192972ada5f7SEric Cook { 193072ada5f7SEric Cook int i = 0; 193172ada5f7SEric Cook 193272ada5f7SEric Cook /* TODO: handle pipes > 1 193372ada5f7SEric Cook */ 193472ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 19356b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 193672ada5f7SEric Cook } 193772ada5f7SEric Cook 19384562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 19395b5abe95SAnthony Koo int num_pipes, const struct dc_static_screen_params *params) 19404562236bSHarry Wentland { 19414562236bSHarry Wentland unsigned int i; 19425b5abe95SAnthony Koo unsigned int triggers = 0; 194394267b3dSSylvia Tsai 19445b5abe95SAnthony Koo if (params->triggers.overlay_update) 19455b5abe95SAnthony Koo triggers |= 0x100; 19465b5abe95SAnthony Koo if (params->triggers.surface_update) 19475b5abe95SAnthony Koo triggers |= 0x80; 19485b5abe95SAnthony Koo if (params->triggers.cursor_update) 19495b5abe95SAnthony Koo triggers |= 0x2; 19505b5abe95SAnthony Koo if (params->triggers.force_trigger) 19515b5abe95SAnthony Koo triggers |= 0x1; 19524562236bSHarry Wentland 1953593f79a2SAlex Deucher if (num_pipes) { 1954593f79a2SAlex Deucher struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1955593f79a2SAlex Deucher 1956593f79a2SAlex Deucher if (dc->fbc_compressor) 19575b5abe95SAnthony Koo triggers |= 0x84; 1958593f79a2SAlex Deucher } 1959c3aa1d67SBhawanpreet Lakha 19604562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 19616b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs-> 19625b5abe95SAnthony Koo set_static_screen_control(pipe_ctx[i]->stream_res.tg, 19635b5abe95SAnthony Koo triggers, params->num_frames); 19644562236bSHarry Wentland } 19654562236bSHarry Wentland 1966f6baff4dSHarry Wentland /* 1967690b5e39SRoman Li * Check if FBC can be enabled 1968690b5e39SRoman Li */ 19699c6569deSHarry Wentland static bool should_enable_fbc(struct dc *dc, 19703bc4aaa9SRoman Li struct dc_state *context, 19713bc4aaa9SRoman Li uint32_t *pipe_idx) 1972690b5e39SRoman Li { 19733bc4aaa9SRoman Li uint32_t i; 19743bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = NULL; 19753bc4aaa9SRoman Li struct resource_context *res_ctx = &context->res_ctx; 197665d38262Shersen wu unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 19773bc4aaa9SRoman Li 1978690b5e39SRoman Li 1979690b5e39SRoman Li ASSERT(dc->fbc_compressor); 1980690b5e39SRoman Li 1981690b5e39SRoman Li /* FBC memory should be allocated */ 1982690b5e39SRoman Li if (!dc->ctx->fbc_gpu_addr) 19839c6569deSHarry Wentland return false; 1984690b5e39SRoman Li 1985690b5e39SRoman Li /* Only supports single display */ 1986690b5e39SRoman Li if (context->stream_count != 1) 19879c6569deSHarry Wentland return false; 1988690b5e39SRoman Li 19893bc4aaa9SRoman Li for (i = 0; i < dc->res_pool->pipe_count; i++) { 19903bc4aaa9SRoman Li if (res_ctx->pipe_ctx[i].stream) { 199165d38262Shersen wu 19923bc4aaa9SRoman Li pipe_ctx = &res_ctx->pipe_ctx[i]; 199365d38262Shersen wu 199465d38262Shersen wu if (!pipe_ctx) 199565d38262Shersen wu continue; 199665d38262Shersen wu 199765d38262Shersen wu /* fbc not applicable on underlay pipe */ 199865d38262Shersen wu if (pipe_ctx->pipe_idx != underlay_idx) { 19993bc4aaa9SRoman Li *pipe_idx = i; 20003bc4aaa9SRoman Li break; 20013bc4aaa9SRoman Li } 20023bc4aaa9SRoman Li } 200365d38262Shersen wu } 20043bc4aaa9SRoman Li 200565d38262Shersen wu if (i == dc->res_pool->pipe_count) 200665d38262Shersen wu return false; 200765d38262Shersen wu 2008ceb3dbb4SJun Lei if (!pipe_ctx->stream->link) 200965d38262Shersen wu return false; 20107a840773SRoman Li 2011690b5e39SRoman Li /* Only supports eDP */ 2012ceb3dbb4SJun Lei if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 20139c6569deSHarry Wentland return false; 2014690b5e39SRoman Li 2015690b5e39SRoman Li /* PSR should not be enabled */ 2016d1ebfdd8SWyatt Wood if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 20179c6569deSHarry Wentland return false; 2018690b5e39SRoman Li 201993984bbcSShirish S /* Nothing to compress */ 202093984bbcSShirish S if (!pipe_ctx->plane_state) 20219c6569deSHarry Wentland return false; 202293984bbcSShirish S 202305230fa9SRoman Li /* Only for non-linear tiling */ 202405230fa9SRoman Li if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 20259c6569deSHarry Wentland return false; 202605230fa9SRoman Li 20279c6569deSHarry Wentland return true; 2028690b5e39SRoman Li } 2029690b5e39SRoman Li 2030690b5e39SRoman Li /* 2031690b5e39SRoman Li * Enable FBC 2032690b5e39SRoman Li */ 203365d38262Shersen wu static void enable_fbc( 203465d38262Shersen wu struct dc *dc, 2035608ac7bbSJerry Zuo struct dc_state *context) 2036690b5e39SRoman Li { 20373bc4aaa9SRoman Li uint32_t pipe_idx = 0; 20383bc4aaa9SRoman Li 20393bc4aaa9SRoman Li if (should_enable_fbc(dc, context, &pipe_idx)) { 2040690b5e39SRoman Li /* Program GRPH COMPRESSED ADDRESS and PITCH */ 2041690b5e39SRoman Li struct compr_addr_and_pitch_params params = {0, 0, 0}; 2042690b5e39SRoman Li struct compressor *compr = dc->fbc_compressor; 20433bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 20443bc4aaa9SRoman Li 20459c6569deSHarry Wentland params.source_view_width = pipe_ctx->stream->timing.h_addressable; 20469c6569deSHarry Wentland params.source_view_height = pipe_ctx->stream->timing.v_addressable; 204765d38262Shersen wu params.inst = pipe_ctx->stream_res.tg->inst; 2048690b5e39SRoman Li compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 2049690b5e39SRoman Li 2050690b5e39SRoman Li compr->funcs->surface_address_and_pitch(compr, ¶ms); 2051690b5e39SRoman Li compr->funcs->set_fbc_invalidation_triggers(compr, 1); 2052690b5e39SRoman Li 2053690b5e39SRoman Li compr->funcs->enable_fbc(compr, ¶ms); 2054690b5e39SRoman Li } 2055690b5e39SRoman Li } 2056690b5e39SRoman Li 205754e8695eSDmytro Laktyushkin static void dce110_reset_hw_ctx_wrap( 2058fb3466a4SBhawanpreet Lakha struct dc *dc, 2059608ac7bbSJerry Zuo struct dc_state *context) 20604562236bSHarry Wentland { 20614562236bSHarry Wentland int i; 20624562236bSHarry Wentland 20634562236bSHarry Wentland /* Reset old context */ 20644562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 2065a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 20664562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2067608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 20684562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 20694562236bSHarry Wentland 20704562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 20714562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 20724562236bSHarry Wentland * PHY when not already disabled. 20734562236bSHarry Wentland */ 20744562236bSHarry Wentland 20754562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 20764562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 20774562236bSHarry Wentland continue; 20784562236bSHarry Wentland 20794562236bSHarry Wentland if (!pipe_ctx->stream || 208054e8695eSDmytro Laktyushkin pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 208121e67d4dSHarry Wentland struct clock_source *old_clk = pipe_ctx_old->clock_source; 208221e67d4dSHarry Wentland 2083827f11e9SLeo (Sunpeng) Li /* Disable if new stream is null. O/w, if stream is 2084827f11e9SLeo (Sunpeng) Li * disabled already, no need to disable again. 2085827f11e9SLeo (Sunpeng) Li */ 208657430404SSu Sung Chung if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 208757430404SSu Sung Chung core_link_disable_stream(pipe_ctx_old); 208857430404SSu Sung Chung 208957430404SSu Sung Chung /* free acquired resources*/ 209057430404SSu Sung Chung if (pipe_ctx_old->stream_res.audio) { 209157430404SSu Sung Chung /*disable az_endpoint*/ 209257430404SSu Sung Chung pipe_ctx_old->stream_res.audio->funcs-> 209357430404SSu Sung Chung az_disable(pipe_ctx_old->stream_res.audio); 209457430404SSu Sung Chung 209557430404SSu Sung Chung /*free audio*/ 209657430404SSu Sung Chung if (dc->caps.dynamic_audio == true) { 209757430404SSu Sung Chung /*we have to dynamic arbitrate the audio endpoints*/ 209857430404SSu Sung Chung /*we free the resource, need reset is_audio_acquired*/ 209957430404SSu Sung Chung update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 210057430404SSu Sung Chung pipe_ctx_old->stream_res.audio, false); 210157430404SSu Sung Chung pipe_ctx_old->stream_res.audio = NULL; 210257430404SSu Sung Chung } 210357430404SSu Sung Chung } 210457430404SSu Sung Chung } 2105d050f8edSHersen Wu 21066b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 21076b670fa9SHarry Wentland if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 210854e8695eSDmytro Laktyushkin dm_error("DC: failed to blank crtc!\n"); 210954e8695eSDmytro Laktyushkin BREAK_TO_DEBUGGER(); 211054e8695eSDmytro Laktyushkin } 21116b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 211286a66c4eSHarry Wentland pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2113608ac7bbSJerry Zuo pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 211454e8695eSDmytro Laktyushkin 2115ad8960a6SMikita Lipski if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2116ad8960a6SMikita Lipski dc->res_pool, 2117ad8960a6SMikita Lipski old_clk)) 211821e67d4dSHarry Wentland old_clk->funcs->cs_power_down(old_clk); 211921e67d4dSHarry Wentland 21207f914a62SYongqiang Sun dc->hwss.disable_plane(dc, pipe_ctx_old); 212154e8695eSDmytro Laktyushkin 212254e8695eSDmytro Laktyushkin pipe_ctx_old->stream = NULL; 212354e8695eSDmytro Laktyushkin } 21244562236bSHarry Wentland } 21254562236bSHarry Wentland } 21264562236bSHarry Wentland 21271a05873fSAnthony Koo static void dce110_setup_audio_dto( 21281a05873fSAnthony Koo struct dc *dc, 21291a05873fSAnthony Koo struct dc_state *context) 21301a05873fSAnthony Koo { 21311a05873fSAnthony Koo int i; 21321a05873fSAnthony Koo 21331a05873fSAnthony Koo /* program audio wall clock. use HDMI as clock source if HDMI 21341a05873fSAnthony Koo * audio active. Otherwise, use DP as clock source 21351a05873fSAnthony Koo * first, loop to find any HDMI audio, if not, loop find DP audio 21361a05873fSAnthony Koo */ 21371a05873fSAnthony Koo /* Setup audio rate clock source */ 21381a05873fSAnthony Koo /* Issue: 21391a05873fSAnthony Koo * Audio lag happened on DP monitor when unplug a HDMI monitor 21401a05873fSAnthony Koo * 21411a05873fSAnthony Koo * Cause: 21421a05873fSAnthony Koo * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 21431a05873fSAnthony Koo * is set to either dto0 or dto1, audio should work fine. 21441a05873fSAnthony Koo * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 21451a05873fSAnthony Koo * set to dto0 will cause audio lag. 21461a05873fSAnthony Koo * 21471a05873fSAnthony Koo * Solution: 21481a05873fSAnthony Koo * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 21491a05873fSAnthony Koo * find first available pipe with audio, setup audio wall DTO per topology 21501a05873fSAnthony Koo * instead of per pipe. 21511a05873fSAnthony Koo */ 21521a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 21531a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 21541a05873fSAnthony Koo 21551a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 21561a05873fSAnthony Koo continue; 21571a05873fSAnthony Koo 21581a05873fSAnthony Koo if (pipe_ctx->top_pipe) 21591a05873fSAnthony Koo continue; 21601a05873fSAnthony Koo if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 21611a05873fSAnthony Koo continue; 21621a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 21631a05873fSAnthony Koo struct audio_output audio_output; 21641a05873fSAnthony Koo 21651a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 21661a05873fSAnthony Koo 216764b1d0e8SNicholas Kazlauskas if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 216864b1d0e8SNicholas Kazlauskas /* disable audio DTBCLK DTO */ 216964b1d0e8SNicholas Kazlauskas dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 217064b1d0e8SNicholas Kazlauskas dc->res_pool->dccg, 0); 217164b1d0e8SNicholas Kazlauskas 21721a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 21731a05873fSAnthony Koo pipe_ctx->stream_res.audio, 21741a05873fSAnthony Koo pipe_ctx->stream->signal, 21751a05873fSAnthony Koo &audio_output.crtc_info, 21761a05873fSAnthony Koo &audio_output.pll_info); 217764b1d0e8SNicholas Kazlauskas } else 217864b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 217964b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, 218064b1d0e8SNicholas Kazlauskas pipe_ctx->stream->signal, 218164b1d0e8SNicholas Kazlauskas &audio_output.crtc_info, 218264b1d0e8SNicholas Kazlauskas &audio_output.pll_info); 21831a05873fSAnthony Koo break; 21841a05873fSAnthony Koo } 21851a05873fSAnthony Koo } 21861a05873fSAnthony Koo 21871a05873fSAnthony Koo /* no HDMI audio is found, try DP audio */ 21881a05873fSAnthony Koo if (i == dc->res_pool->pipe_count) { 21891a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 21901a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 21911a05873fSAnthony Koo 21921a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 21931a05873fSAnthony Koo continue; 21941a05873fSAnthony Koo 21951a05873fSAnthony Koo if (pipe_ctx->top_pipe) 21961a05873fSAnthony Koo continue; 21971a05873fSAnthony Koo 21981a05873fSAnthony Koo if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 21991a05873fSAnthony Koo continue; 22001a05873fSAnthony Koo 22011a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 22021a05873fSAnthony Koo struct audio_output audio_output; 22031a05873fSAnthony Koo 22041a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 22051a05873fSAnthony Koo 22061a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 22071a05873fSAnthony Koo pipe_ctx->stream_res.audio, 22081a05873fSAnthony Koo pipe_ctx->stream->signal, 22091a05873fSAnthony Koo &audio_output.crtc_info, 22101a05873fSAnthony Koo &audio_output.pll_info); 22111a05873fSAnthony Koo break; 22121a05873fSAnthony Koo } 22131a05873fSAnthony Koo } 22141a05873fSAnthony Koo } 22151a05873fSAnthony Koo } 2216cf437593SDmytro Laktyushkin 22174562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 2218fb3466a4SBhawanpreet Lakha struct dc *dc, 2219608ac7bbSJerry Zuo struct dc_state *context) 22204562236bSHarry Wentland { 2221f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 22224562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 22234562236bSHarry Wentland enum dc_status status; 22244562236bSHarry Wentland int i; 22254562236bSHarry Wentland 2226a896f870SMeenakshikumar Somasundaram /* reset syncd pipes from disabled pipes */ 2227a896f870SMeenakshikumar Somasundaram if (dc->config.use_pipe_ctx_sync_logic) 2228a896f870SMeenakshikumar Somasundaram reset_syncd_pipes_from_disabled_pipes(dc, context); 2229a896f870SMeenakshikumar Somasundaram 22304562236bSHarry Wentland /* Reset old context */ 22314562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 2232f42ea55bSAnthony Koo hws->funcs.reset_hw_ctx_wrap(dc, context); 22334562236bSHarry Wentland 22344562236bSHarry Wentland /* Skip applying if no targets */ 2235ab2541b6SAric Cyr if (context->stream_count <= 0) 22364562236bSHarry Wentland return DC_OK; 22374562236bSHarry Wentland 22384562236bSHarry Wentland /* Apply new context */ 22394562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 22404562236bSHarry Wentland 22414562236bSHarry Wentland /* below is for real asic only */ 2242a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 22434562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2244608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 22454562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 22464562236bSHarry Wentland 22474562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 22484562236bSHarry Wentland continue; 22494562236bSHarry Wentland 22504562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 22514562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 22524562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 22534562236bSHarry Wentland pipe_ctx->clock_source, i); 22544562236bSHarry Wentland continue; 22554562236bSHarry Wentland } 22564562236bSHarry Wentland 2257f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 22584562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 22594562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 22604562236bSHarry Wentland } 22614562236bSHarry Wentland 22622f3bfb27SRoman Li if (dc->fbc_compressor) 22631663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 22645099114bSAlex Deucher 22651a05873fSAnthony Koo dce110_setup_audio_dto(dc, context); 2266ab8812a3SHersen Wu 2267a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2268ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 2269608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 2270ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2271ab8812a3SHersen Wu 2272ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2273ab8812a3SHersen Wu continue; 2274ab8812a3SHersen Wu 2275eed928dcSCharlene Liu if (pipe_ctx->stream == pipe_ctx_old->stream && 2276eed928dcSCharlene Liu pipe_ctx->stream->link->link_state_valid) { 2277ab8812a3SHersen Wu continue; 2278eed928dcSCharlene Liu } 2279ab8812a3SHersen Wu 22805b92d9d4SHarry Wentland if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2281313bf4ffSYongqiang Sun continue; 2282313bf4ffSYongqiang Sun 2283b1f6d01cSDmytro Laktyushkin if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2284ab8812a3SHersen Wu continue; 2285ab8812a3SHersen Wu 22864562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 22874562236bSHarry Wentland pipe_ctx, 22884562236bSHarry Wentland context, 22894562236bSHarry Wentland dc); 22904562236bSHarry Wentland 22914562236bSHarry Wentland if (DC_OK != status) 22924562236bSHarry Wentland return status; 22934562236bSHarry Wentland } 22944562236bSHarry Wentland 2295690b5e39SRoman Li if (dc->fbc_compressor) 229665d38262Shersen wu enable_fbc(dc, dc->current_state); 229765d38262Shersen wu 229865d38262Shersen wu dcb->funcs->set_scratch_critical_state(dcb, false); 2299690b5e39SRoman Li 23004562236bSHarry Wentland return DC_OK; 23014562236bSHarry Wentland } 23024562236bSHarry Wentland 23034562236bSHarry Wentland /******************************************************************************* 23044562236bSHarry Wentland * Front End programming 23054562236bSHarry Wentland ******************************************************************************/ 23064562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 23074562236bSHarry Wentland { 23084562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 23094562236bSHarry Wentland 23104562236bSHarry Wentland default_adjust.force_hw_default = false; 231134996173SHarry Wentland default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 231234996173SHarry Wentland default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 23134562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 23146702a9acSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 23154562236bSHarry Wentland 23164562236bSHarry Wentland /* display color depth */ 23174562236bSHarry Wentland default_adjust.color_depth = 23184fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.display_color_depth; 23194562236bSHarry Wentland 23204562236bSHarry Wentland /* Lb color depth */ 23216702a9acSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 23224562236bSHarry Wentland 232386a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 232486a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, &default_adjust); 23254562236bSHarry Wentland } 23264562236bSHarry Wentland 2327b06b7680SLeon Elazar 2328b06b7680SLeon Elazar /******************************************************************************* 2329b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 2330b06b7680SLeon Elazar * Blender + CRTC 2331b06b7680SLeon Elazar * 2332b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 2333b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 2334b06b7680SLeon Elazar * 2335b06b7680SLeon Elazar * |----------------------------------------------- | 2336b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 2337b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 2338b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 2339b06b7680SLeon Elazar * |------------------------------------------------| 2340b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 2341b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 2342b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 2343b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 2344b06b7680SLeon Elazar * -------------------------------------------------| 2345b06b7680SLeon Elazar * 2346b06b7680SLeon Elazar ******************************************************************************/ 2347fb3466a4SBhawanpreet Lakha static void program_surface_visibility(const struct dc *dc, 23484562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 23494562236bSHarry Wentland { 23504562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2351b06b7680SLeon Elazar bool blank_target = false; 23524562236bSHarry Wentland 23534562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 2354b06b7680SLeon Elazar 2355b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 2356b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2357b06b7680SLeon Elazar 23583be5262eSHarry Wentland if (pipe_ctx->bottom_pipe->plane_state->visible) { 23593be5262eSHarry Wentland if (pipe_ctx->plane_state->visible) 23604562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 23614562236bSHarry Wentland else 23624562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 2363b06b7680SLeon Elazar 23643be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2365b06b7680SLeon Elazar blank_target = true; 2366b06b7680SLeon Elazar 23673be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2368b06b7680SLeon Elazar blank_target = true; 2369b06b7680SLeon Elazar 2370e07f541fSYongqiang Sun dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 23716b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2372b06b7680SLeon Elazar 23734562236bSHarry Wentland } 23744562236bSHarry Wentland 23751bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 23761bf56e62SZeyu Fan { 2377146a9f63SKrunoslav Kovac int i = 0; 23781bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 23791bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 23801bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 23811bf56e62SZeyu Fan 23821bf56e62SZeyu Fan 23834fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 23841bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2385146a9f63SKrunoslav Kovac 2386146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2387146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2388146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 23891bf56e62SZeyu Fan } 23901bf56e62SZeyu Fan 239186a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 23921bf56e62SZeyu Fan } 2393fb3466a4SBhawanpreet Lakha static void update_plane_addr(const struct dc *dc, 23944562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 23954562236bSHarry Wentland { 23963be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 23974562236bSHarry Wentland 23983be5262eSHarry Wentland if (plane_state == NULL) 23994562236bSHarry Wentland return; 24004562236bSHarry Wentland 240186a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 240286a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 24033be5262eSHarry Wentland &plane_state->address, 24043be5262eSHarry Wentland plane_state->flip_immediate); 24054562236bSHarry Wentland 24063be5262eSHarry Wentland plane_state->status.requested_address = plane_state->address; 24074562236bSHarry Wentland } 24084562236bSHarry Wentland 2409f774b339SEric Yang static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 24104562236bSHarry Wentland { 24113be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 24124562236bSHarry Wentland 24133be5262eSHarry Wentland if (plane_state == NULL) 24144562236bSHarry Wentland return; 24154562236bSHarry Wentland 24163be5262eSHarry Wentland plane_state->status.is_flip_pending = 241786a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 241886a66c4eSHarry Wentland pipe_ctx->plane_res.mi); 24194562236bSHarry Wentland 24203be5262eSHarry Wentland if (plane_state->status.is_flip_pending && !plane_state->visible) 242186a66c4eSHarry Wentland pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 24224562236bSHarry Wentland 242386a66c4eSHarry Wentland plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 242486a66c4eSHarry Wentland if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 24256b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 24263be5262eSHarry Wentland plane_state->status.is_right_eye =\ 24276b670fa9SHarry Wentland !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 24287f5c22d1SVitaly Prosyak } 24294562236bSHarry Wentland } 24304562236bSHarry Wentland 2431fb3466a4SBhawanpreet Lakha void dce110_power_down(struct dc *dc) 24324562236bSHarry Wentland { 24334562236bSHarry Wentland power_down_all_hw_blocks(dc); 24344562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 24354562236bSHarry Wentland } 24364562236bSHarry Wentland 24374562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 24384562236bSHarry Wentland struct dc_context *dc_ctx, 24394562236bSHarry Wentland struct timing_generator *tg) 24404562236bSHarry Wentland { 24414562236bSHarry Wentland bool rc = false; 24424562236bSHarry Wentland 24434562236bSHarry Wentland /* To avoid endless loop we wait at most 24444562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 24454562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 24464562236bSHarry Wentland uint32_t i; 24474562236bSHarry Wentland 24484562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 24494562236bSHarry Wentland 24504562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 24514562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 24524562236bSHarry Wentland break; 24534562236bSHarry Wentland } 24544562236bSHarry Wentland 24554562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 24564562236bSHarry Wentland rc = true; 24574562236bSHarry Wentland /* usually occurs at i=1 */ 24584562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 24594562236bSHarry Wentland i); 24604562236bSHarry Wentland break; 24614562236bSHarry Wentland } 24624562236bSHarry Wentland 24634562236bSHarry Wentland /* Wait for one frame. */ 24644562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 24654562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 24664562236bSHarry Wentland } 24674562236bSHarry Wentland 24684562236bSHarry Wentland if (false == rc) 24694562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 24704562236bSHarry Wentland 24714562236bSHarry Wentland return rc; 24724562236bSHarry Wentland } 24734562236bSHarry Wentland 24744562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 24754562236bSHarry Wentland static void dce110_enable_timing_synchronization( 2476fb3466a4SBhawanpreet Lakha struct dc *dc, 24774562236bSHarry Wentland int group_index, 24784562236bSHarry Wentland int group_size, 24794562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 24804562236bSHarry Wentland { 24814562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 24824562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 24834562236bSHarry Wentland int i; 24844562236bSHarry Wentland 24854562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 24864562236bSHarry Wentland 24874562236bSHarry Wentland /* Designate a single TG in the group as a master. 24884562236bSHarry Wentland * Since HW doesn't care which one, we always assign 24894562236bSHarry Wentland * the 1st one in the group. */ 24904562236bSHarry Wentland gsl_params.gsl_group = 0; 24916b670fa9SHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 24924562236bSHarry Wentland 24934562236bSHarry Wentland for (i = 0; i < group_size; i++) 24946b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 24956b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg, &gsl_params); 24964562236bSHarry Wentland 24974562236bSHarry Wentland /* Reset slave controllers on master VSync */ 24984562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 24994562236bSHarry Wentland 25004562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 25016b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2502fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2503fa2123dbSMikita Lipski gsl_params.gsl_group); 25044562236bSHarry Wentland 25054562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 25064562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 25076b670fa9SHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2508fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2509fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg); 25104562236bSHarry Wentland } 25114562236bSHarry Wentland 25124562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 25134562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 25144562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 25154562236bSHarry Wentland for (i = 0; i < group_size; i++) 25166b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 25174562236bSHarry Wentland 25184562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 25194562236bSHarry Wentland } 25204562236bSHarry Wentland 2521fa2123dbSMikita Lipski static void dce110_enable_per_frame_crtc_position_reset( 2522fa2123dbSMikita Lipski struct dc *dc, 2523fa2123dbSMikita Lipski int group_size, 2524fa2123dbSMikita Lipski struct pipe_ctx *grouped_pipes[]) 2525fa2123dbSMikita Lipski { 2526fa2123dbSMikita Lipski struct dc_context *dc_ctx = dc->ctx; 2527fa2123dbSMikita Lipski struct dcp_gsl_params gsl_params = { 0 }; 2528fa2123dbSMikita Lipski int i; 2529fa2123dbSMikita Lipski 2530fa2123dbSMikita Lipski gsl_params.gsl_group = 0; 253137cd85ceSDavid Francis gsl_params.gsl_master = 0; 2532fa2123dbSMikita Lipski 2533fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2534fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2535fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, &gsl_params); 2536fa2123dbSMikita Lipski 2537fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2538fa2123dbSMikita Lipski 2539fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2540fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2541fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2542fa2123dbSMikita Lipski gsl_params.gsl_master, 2543fa2123dbSMikita Lipski &grouped_pipes[i]->stream->triggered_crtc_reset); 2544fa2123dbSMikita Lipski 2545fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2546fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2547fa2123dbSMikita Lipski wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2548fa2123dbSMikita Lipski 2549fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2550fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2551fa2123dbSMikita Lipski 2552fa2123dbSMikita Lipski } 2553fa2123dbSMikita Lipski 2554fb55546eSAnthony Koo static void init_pipes(struct dc *dc, struct dc_state *context) 2555fb55546eSAnthony Koo { 2556fb55546eSAnthony Koo // Do nothing 2557fb55546eSAnthony Koo } 2558fb55546eSAnthony Koo 2559fb3466a4SBhawanpreet Lakha static void init_hw(struct dc *dc) 25604562236bSHarry Wentland { 25614562236bSHarry Wentland int i; 25624562236bSHarry Wentland struct dc_bios *bp; 25634562236bSHarry Wentland struct transform *xfm; 25645e7773a2SAnthony Koo struct abm *abm; 256570d9e8cbSPaul Hsieh struct dmcu *dmcu; 2566f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 25673ba01817SYongqiang Sun uint32_t backlight = MAX_BACKLIGHT_LEVEL; 25684562236bSHarry Wentland 25694562236bSHarry Wentland bp = dc->ctx->dc_bios; 25704562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 25714562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 25724562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 25734562236bSHarry Wentland 2574f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 25754562236bSHarry Wentland dc, i, bp, 25764562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 2577f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 25784562236bSHarry Wentland dc, i, bp, 25794562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 2580f42ea55bSAnthony Koo hws->funcs.enable_display_pipe_clock_gating( 25814562236bSHarry Wentland dc->ctx, 25824562236bSHarry Wentland true); 25834562236bSHarry Wentland } 25844562236bSHarry Wentland 2585e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 25864562236bSHarry Wentland /***************************************/ 25874562236bSHarry Wentland 25884562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 25894562236bSHarry Wentland /****************************************/ 25904562236bSHarry Wentland /* Power up AND update implementation according to the 25914562236bSHarry Wentland * required signal (which may be different from the 25924562236bSHarry Wentland * default signal on connector). */ 2593d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 2594069d418fSAndrew Jiang 25954562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 25964562236bSHarry Wentland } 25974562236bSHarry Wentland 25984562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 25994562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 26004562236bSHarry Wentland 26014562236bSHarry Wentland tg->funcs->disable_vga(tg); 26024562236bSHarry Wentland 26034562236bSHarry Wentland /* Blank controller using driver code instead of 26044562236bSHarry Wentland * command table. */ 26054562236bSHarry Wentland tg->funcs->set_blank(tg, true); 26064b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 26074562236bSHarry Wentland } 26084562236bSHarry Wentland 26094562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 26104562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 26114562236bSHarry Wentland audio->funcs->hw_init(audio); 26124562236bSHarry Wentland } 26135e7773a2SAnthony Koo 26143ba01817SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 26153ba01817SYongqiang Sun struct dc_link *link = dc->links[i]; 26163ba01817SYongqiang Sun 26173ba01817SYongqiang Sun if (link->panel_cntl) 26183ba01817SYongqiang Sun backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 26194562236bSHarry Wentland } 26205099114bSAlex Deucher 26213ba01817SYongqiang Sun abm = dc->res_pool->abm; 26223ba01817SYongqiang Sun if (abm != NULL) 26233ba01817SYongqiang Sun abm->funcs->abm_init(abm, backlight); 26243ba01817SYongqiang Sun 262570d9e8cbSPaul Hsieh dmcu = dc->res_pool->dmcu; 262670d9e8cbSPaul Hsieh if (dmcu != NULL && abm != NULL) 262770d9e8cbSPaul Hsieh abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 262870d9e8cbSPaul Hsieh 26292f3bfb27SRoman Li if (dc->fbc_compressor) 26301663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2631690b5e39SRoman Li 26326728b30cSAnthony Koo } 26334562236bSHarry Wentland 26349566b675SDmytro Laktyushkin 26359566b675SDmytro Laktyushkin void dce110_prepare_bandwidth( 2636fb3466a4SBhawanpreet Lakha struct dc *dc, 26379566b675SDmytro Laktyushkin struct dc_state *context) 2638cf437593SDmytro Laktyushkin { 2639dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 2640fab55d61SDmytro Laktyushkin 2641fab55d61SDmytro Laktyushkin dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2642cf437593SDmytro Laktyushkin 26435a83c932SNicholas Kazlauskas dccg->funcs->update_clocks( 26445a83c932SNicholas Kazlauskas dccg, 264524f7dd7eSDmytro Laktyushkin context, 26469566b675SDmytro Laktyushkin false); 26479566b675SDmytro Laktyushkin } 26489566b675SDmytro Laktyushkin 26499566b675SDmytro Laktyushkin void dce110_optimize_bandwidth( 26509566b675SDmytro Laktyushkin struct dc *dc, 26519566b675SDmytro Laktyushkin struct dc_state *context) 26529566b675SDmytro Laktyushkin { 2653dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 26549566b675SDmytro Laktyushkin 26559566b675SDmytro Laktyushkin dce110_set_displaymarks(dc, context); 26569566b675SDmytro Laktyushkin 26579566b675SDmytro Laktyushkin dccg->funcs->update_clocks( 26589566b675SDmytro Laktyushkin dccg, 26599566b675SDmytro Laktyushkin context, 26609566b675SDmytro Laktyushkin true); 26614562236bSHarry Wentland } 26624562236bSHarry Wentland 26634562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 2664fb3466a4SBhawanpreet Lakha struct dc *dc, struct pipe_ctx *pipe_ctx) 26654562236bSHarry Wentland { 266686a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 26673be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 26684562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 26694562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 26704562236bSHarry Wentland unsigned int i; 2671f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2672f42ea55bSAnthony Koo 26735d4b05ddSBhawanpreet Lakha DC_LOGGER_INIT(); 26744562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 26754562236bSHarry Wentland 26764562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 26774562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 26784562236bSHarry Wentland 2679e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 26804562236bSHarry Wentland 26814562236bSHarry Wentland set_default_colors(pipe_ctx); 26824fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 26834562236bSHarry Wentland == true) { 26844562236bSHarry Wentland tbl_entry.color_space = 26854fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 26864562236bSHarry Wentland 26874562236bSHarry Wentland for (i = 0; i < 12; i++) 26884562236bSHarry Wentland tbl_entry.regval[i] = 26894fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 26904562236bSHarry Wentland 269186a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 269286a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 26934562236bSHarry Wentland } 26944562236bSHarry Wentland 26954fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 26964562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2697146a9f63SKrunoslav Kovac 2698146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2699146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2700146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 27014562236bSHarry Wentland } 27024562236bSHarry Wentland 270386a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 27044562236bSHarry Wentland 27056702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2706c1473558SAndrey Grodzovsky 27074562236bSHarry Wentland program_scaler(dc, pipe_ctx); 27084562236bSHarry Wentland 27094562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 27104562236bSHarry Wentland mi, 27113be5262eSHarry Wentland plane_state->format, 27123be5262eSHarry Wentland &plane_state->tiling_info, 27133be5262eSHarry Wentland &plane_state->plane_size, 27143be5262eSHarry Wentland plane_state->rotation, 2715624d7c47SYongqiang Sun NULL, 27164b28b76bSDmytro Laktyushkin false); 27174b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 27183be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 27194562236bSHarry Wentland 2720fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 27214562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 272286a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 27233be5262eSHarry Wentland plane_state->format, 27243be5262eSHarry Wentland &plane_state->tiling_info, 27253be5262eSHarry Wentland plane_state->rotation); 27264562236bSHarry Wentland 2727067c878aSYongqiang Sun /* Moved programming gamma from dc to hwss */ 2728405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update || 2729405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2730405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.gamma_change) 2731f42ea55bSAnthony Koo hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2732405c50a0SAndrew Jiang 2733405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update) 2734f42ea55bSAnthony Koo hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2735067c878aSYongqiang Sun 27361296423bSBhawanpreet Lakha DC_LOG_SURFACE( 27373032deb5SBhawanpreet Lakha "Pipe:%d %p: addr hi:0x%x, " 27384562236bSHarry Wentland "addr low:0x%x, " 27394562236bSHarry Wentland "src: %d, %d, %d," 27404562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 27414562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 27424562236bSHarry Wentland pipe_ctx->pipe_idx, 27433032deb5SBhawanpreet Lakha (void *) pipe_ctx->plane_state, 27443be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.high_part, 27453be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.low_part, 27463be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.x, 27473be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.y, 27483be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.width, 27493be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.height, 27503be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.x, 27513be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.y, 27523be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.width, 27533be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.height, 27543be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.x, 27553be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.y, 27563be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.width, 27573be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.height); 27584562236bSHarry Wentland 27591296423bSBhawanpreet Lakha DC_LOG_SURFACE( 27604562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 27614562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 27624562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 27634562236bSHarry Wentland pipe_ctx->pipe_idx, 27646702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.width, 27656702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.height, 27666702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.x, 27676702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.y, 27686702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.width, 27696702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.height, 27706702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.x, 27716702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.y); 27724562236bSHarry Wentland } 27734562236bSHarry Wentland 27744562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 2775fb3466a4SBhawanpreet Lakha struct dc *dc, 27763e9ad616SEric Yang const struct dc_stream_state *stream, 27773e9ad616SEric Yang int num_planes, 2778608ac7bbSJerry Zuo struct dc_state *context) 27794562236bSHarry Wentland { 27802194e3aeSRoman Li int i; 27814562236bSHarry Wentland 27823e9ad616SEric Yang if (num_planes == 0) 27834562236bSHarry Wentland return; 27844562236bSHarry Wentland 278565d38262Shersen wu if (dc->fbc_compressor) 278665d38262Shersen wu dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 278765d38262Shersen wu 27883e9ad616SEric Yang for (i = 0; i < dc->res_pool->pipe_count; i++) { 27893dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 27904562236bSHarry Wentland 2791a2607aefSHarry Wentland if (pipe_ctx->stream != stream) 27924562236bSHarry Wentland continue; 27934562236bSHarry Wentland 27943b21b6d2SJerry Zuo /* Need to allocate mem before program front end for Fiji */ 27953b21b6d2SJerry Zuo pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 27963b21b6d2SJerry Zuo pipe_ctx->plane_res.mi, 27973b21b6d2SJerry Zuo pipe_ctx->stream->timing.h_total, 27983b21b6d2SJerry Zuo pipe_ctx->stream->timing.v_total, 2799380604e2SKen Chalmers pipe_ctx->stream->timing.pix_clk_100hz / 10, 28003b21b6d2SJerry Zuo context->stream_count); 28013b21b6d2SJerry Zuo 28024562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 28034f804817SYongqiang Sun 28044f804817SYongqiang Sun dc->hwss.update_plane_addr(dc, pipe_ctx); 28054f804817SYongqiang Sun 2806b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 28074562236bSHarry Wentland 28084562236bSHarry Wentland } 28093dc780ecSYongqiang Sun 281065d38262Shersen wu if (dc->fbc_compressor) 281112a8bd88SShirish S enable_fbc(dc, context); 28124562236bSHarry Wentland } 28134562236bSHarry Wentland 2814bbf5f6c3SAnthony Koo static void dce110_post_unlock_program_front_end( 2815bbf5f6c3SAnthony Koo struct dc *dc, 2816bbf5f6c3SAnthony Koo struct dc_state *context) 2817bbf5f6c3SAnthony Koo { 2818bbf5f6c3SAnthony Koo } 2819009114f6SAnthony Koo 2820e6c258cbSYongqiang Sun static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 28214562236bSHarry Wentland { 2822f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2823bc373a89SRoman Li int fe_idx = pipe_ctx->plane_res.mi ? 2824bc373a89SRoman Li pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2825e6c258cbSYongqiang Sun 28267950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2827608ac7bbSJerry Zuo if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 28284562236bSHarry Wentland return; 28294562236bSHarry Wentland 2830f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 2831cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2832cfe4645eSDmytro Laktyushkin 2833cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2834cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 28354562236bSHarry Wentland } 28364562236bSHarry Wentland 28376be425f3SEric Yang static void dce110_wait_for_mpcc_disconnect( 2838fb3466a4SBhawanpreet Lakha struct dc *dc, 28396be425f3SEric Yang struct resource_pool *res_pool, 28406be425f3SEric Yang struct pipe_ctx *pipe_ctx) 2841b6762f0cSEric Yang { 2842b6762f0cSEric Yang /* do nothing*/ 2843b6762f0cSEric Yang } 2844b6762f0cSEric Yang 28454bd0dc68SJoshua Aberback static void program_output_csc(struct dc *dc, 28464bd0dc68SJoshua Aberback struct pipe_ctx *pipe_ctx, 28474bd0dc68SJoshua Aberback enum dc_color_space colorspace, 28484bd0dc68SJoshua Aberback uint16_t *matrix, 28494bd0dc68SJoshua Aberback int opp_id) 28504bd0dc68SJoshua Aberback { 28514bd0dc68SJoshua Aberback int i; 28524bd0dc68SJoshua Aberback struct out_csc_color_matrix tbl_entry; 28534bd0dc68SJoshua Aberback 28544bd0dc68SJoshua Aberback if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 28554bd0dc68SJoshua Aberback enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 28564bd0dc68SJoshua Aberback 28574bd0dc68SJoshua Aberback for (i = 0; i < 12; i++) 28584bd0dc68SJoshua Aberback tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 28594bd0dc68SJoshua Aberback 28604bd0dc68SJoshua Aberback tbl_entry.color_space = color_space; 28614bd0dc68SJoshua Aberback 28624bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 28634bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm, &tbl_entry); 28644bd0dc68SJoshua Aberback } 28654bd0dc68SJoshua Aberback } 28664bd0dc68SJoshua Aberback 2867faf0389fSJason Yan static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 286833fd17d9SEric Yang { 286933fd17d9SEric Yang struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 287033fd17d9SEric Yang struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 287133fd17d9SEric Yang struct mem_input *mi = pipe_ctx->plane_res.mi; 287233fd17d9SEric Yang struct dc_cursor_mi_param param = { 2873380604e2SKen Chalmers .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 287433d7598dSJun Lei .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 287539a9f4d8SDmytro Laktyushkin .viewport = pipe_ctx->plane_res.scl_data.viewport, 287639a9f4d8SDmytro Laktyushkin .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 287739a9f4d8SDmytro Laktyushkin .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 287808ed681cSDmytro Laktyushkin .rotation = pipe_ctx->plane_state->rotation, 287908ed681cSDmytro Laktyushkin .mirror = pipe_ctx->plane_state->horizontal_mirror 288033fd17d9SEric Yang }; 288133fd17d9SEric Yang 288203a4059bSNicholas Kazlauskas /** 288303a4059bSNicholas Kazlauskas * If the cursor's source viewport is clipped then we need to 288403a4059bSNicholas Kazlauskas * translate the cursor to appear in the correct position on 288503a4059bSNicholas Kazlauskas * the screen. 288603a4059bSNicholas Kazlauskas * 288703a4059bSNicholas Kazlauskas * This translation isn't affected by scaling so it needs to be 288803a4059bSNicholas Kazlauskas * done *after* we adjust the position for the scale factor. 2889033baeeeSNicholas Kazlauskas * 2890033baeeeSNicholas Kazlauskas * This is only done by opt-in for now since there are still 2891033baeeeSNicholas Kazlauskas * some usecases like tiled display that might enable the 2892033baeeeSNicholas Kazlauskas * cursor on both streams while expecting dc to clip it. 289303a4059bSNicholas Kazlauskas */ 2894033baeeeSNicholas Kazlauskas if (pos_cpy.translate_by_source) { 289503a4059bSNicholas Kazlauskas pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 289603a4059bSNicholas Kazlauskas pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2897033baeeeSNicholas Kazlauskas } 289803a4059bSNicholas Kazlauskas 289933fd17d9SEric Yang if (pipe_ctx->plane_state->address.type 290033fd17d9SEric Yang == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 290133fd17d9SEric Yang pos_cpy.enable = false; 290233fd17d9SEric Yang 290333fd17d9SEric Yang if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 290433fd17d9SEric Yang pos_cpy.enable = false; 290533fd17d9SEric Yang 2906dc75dd70SRoman Li if (ipp->funcs->ipp_cursor_set_position) 290733fd17d9SEric Yang ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2908dc75dd70SRoman Li if (mi->funcs->set_cursor_position) 290933fd17d9SEric Yang mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 291033fd17d9SEric Yang } 291133fd17d9SEric Yang 2912faf0389fSJason Yan static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 291333fd17d9SEric Yang { 291433fd17d9SEric Yang struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 291533fd17d9SEric Yang 2916d1aaad05SHarry Wentland if (pipe_ctx->plane_res.ipp && 2917d1aaad05SHarry Wentland pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 291833fd17d9SEric Yang pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 291933fd17d9SEric Yang pipe_ctx->plane_res.ipp, attributes); 292033fd17d9SEric Yang 2921d1aaad05SHarry Wentland if (pipe_ctx->plane_res.mi && 2922d1aaad05SHarry Wentland pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 292333fd17d9SEric Yang pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 292433fd17d9SEric Yang pipe_ctx->plane_res.mi, attributes); 292533fd17d9SEric Yang 2926d1aaad05SHarry Wentland if (pipe_ctx->plane_res.xfm && 2927d1aaad05SHarry Wentland pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 292833fd17d9SEric Yang pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 292933fd17d9SEric Yang pipe_ctx->plane_res.xfm, attributes); 293033fd17d9SEric Yang } 293133fd17d9SEric Yang 29324b0e95d1SYongqiang Sun bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 29334b0e95d1SYongqiang Sun uint32_t backlight_pwm_u16_16, 29344b0e95d1SYongqiang Sun uint32_t frame_ramp) 29354b0e95d1SYongqiang Sun { 29364b0e95d1SYongqiang Sun struct dc_link *link = pipe_ctx->stream->link; 29374b0e95d1SYongqiang Sun struct dc *dc = link->ctx->dc; 29384b0e95d1SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 29393ba01817SYongqiang Sun struct panel_cntl *panel_cntl = link->panel_cntl; 29404b0e95d1SYongqiang Sun struct dmcu *dmcu = dc->res_pool->dmcu; 29414b0e95d1SYongqiang Sun bool fw_set_brightness = true; 29424b0e95d1SYongqiang Sun /* DMCU -1 for all controller id values, 29434b0e95d1SYongqiang Sun * therefore +1 here 29444b0e95d1SYongqiang Sun */ 29454b0e95d1SYongqiang Sun uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 29464b0e95d1SYongqiang Sun 29473ba01817SYongqiang Sun if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 29484b0e95d1SYongqiang Sun return false; 29494b0e95d1SYongqiang Sun 29504b0e95d1SYongqiang Sun if (dmcu) 29514b0e95d1SYongqiang Sun fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 29524b0e95d1SYongqiang Sun 29533ba01817SYongqiang Sun if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 29543ba01817SYongqiang Sun panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 29553ba01817SYongqiang Sun else 29564b0e95d1SYongqiang Sun abm->funcs->set_backlight_level_pwm( 29574b0e95d1SYongqiang Sun abm, 29584b0e95d1SYongqiang Sun backlight_pwm_u16_16, 29594b0e95d1SYongqiang Sun frame_ramp, 29604b0e95d1SYongqiang Sun controller_id, 29613ba01817SYongqiang Sun link->panel_cntl->inst); 29624b0e95d1SYongqiang Sun 29634b0e95d1SYongqiang Sun return true; 29644b0e95d1SYongqiang Sun } 29654b0e95d1SYongqiang Sun 29663ba01817SYongqiang Sun void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 29673ba01817SYongqiang Sun { 29683ba01817SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 29693ba01817SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 29703ba01817SYongqiang Sun 29713ba01817SYongqiang Sun if (abm) 29723ba01817SYongqiang Sun abm->funcs->set_abm_immediate_disable(abm, 29733ba01817SYongqiang Sun pipe_ctx->stream->link->panel_cntl->inst); 29743ba01817SYongqiang Sun 29753ba01817SYongqiang Sun if (panel_cntl) 29763ba01817SYongqiang Sun panel_cntl->funcs->store_backlight_level(panel_cntl); 29773ba01817SYongqiang Sun } 29783ba01817SYongqiang Sun 2979474ac4a8SYongqiang Sun void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 2980474ac4a8SYongqiang Sun { 2981474ac4a8SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 2982474ac4a8SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 2983474ac4a8SYongqiang Sun uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 2984474ac4a8SYongqiang Sun 2985474ac4a8SYongqiang Sun if (abm && panel_cntl) 2986474ac4a8SYongqiang Sun abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 2987474ac4a8SYongqiang Sun } 2988474ac4a8SYongqiang Sun 29894562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 29901bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 29914bd0dc68SJoshua Aberback .program_output_csc = program_output_csc, 29924562236bSHarry Wentland .init_hw = init_hw, 29934562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 29944562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 2995bbf5f6c3SAnthony Koo .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 29964562236bSHarry Wentland .update_plane_addr = update_plane_addr, 29974562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 29984562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 29994562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 3000fa2123dbSMikita Lipski .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 30014562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 30024562236bSHarry Wentland .enable_stream = dce110_enable_stream, 30034562236bSHarry Wentland .disable_stream = dce110_disable_stream, 30044562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 300541b49742SCharlene Liu .blank_stream = dce110_blank_stream, 30061a05873fSAnthony Koo .enable_audio_stream = dce110_enable_audio_stream, 30071a05873fSAnthony Koo .disable_audio_stream = dce110_disable_audio_stream, 30087f914a62SYongqiang Sun .disable_plane = dce110_power_down_fe, 30094562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 3010009114f6SAnthony Koo .interdependent_update_lock = NULL, 30111e461c37SAric Cyr .cursor_lock = dce_pipe_control_lock, 30129566b675SDmytro Laktyushkin .prepare_bandwidth = dce110_prepare_bandwidth, 30139566b675SDmytro Laktyushkin .optimize_bandwidth = dce110_optimize_bandwidth, 30144562236bSHarry Wentland .set_drr = set_drr, 301572ada5f7SEric Cook .get_position = get_position, 30164562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 301715e17335SCharlene Liu .setup_stereo = NULL, 301815e17335SCharlene Liu .set_avmute = dce110_set_avmute, 301941f97c07SHersen Wu .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 3020099303e9SPeikang Zhang .edp_backlight_control = dce110_edp_backlight_control, 30218a31820bSMartin Leung .edp_power_control = dce110_edp_power_control, 30228a31820bSMartin Leung .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 302333fd17d9SEric Yang .set_cursor_position = dce110_set_cursor_position, 30244b0e95d1SYongqiang Sun .set_cursor_attribute = dce110_set_cursor_attribute, 30254b0e95d1SYongqiang Sun .set_backlight_level = dce110_set_backlight_level, 30263ba01817SYongqiang Sun .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 3027474ac4a8SYongqiang Sun .set_pipe = dce110_set_pipe, 30284562236bSHarry Wentland }; 30294562236bSHarry Wentland 3030f42ea55bSAnthony Koo static const struct hwseq_private_funcs dce110_private_funcs = { 3031f42ea55bSAnthony Koo .init_pipes = init_pipes, 3032f42ea55bSAnthony Koo .update_plane_addr = update_plane_addr, 3033f42ea55bSAnthony Koo .set_input_transfer_func = dce110_set_input_transfer_func, 3034f42ea55bSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 3035f42ea55bSAnthony Koo .power_down = dce110_power_down, 3036f42ea55bSAnthony Koo .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 3037f42ea55bSAnthony Koo .enable_display_power_gating = dce110_enable_display_power_gating, 3038f42ea55bSAnthony Koo .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 3039f42ea55bSAnthony Koo .enable_stream_timing = dce110_enable_stream_timing, 3040f42ea55bSAnthony Koo .disable_stream_gating = NULL, 3041f42ea55bSAnthony Koo .enable_stream_gating = NULL, 3042f42ea55bSAnthony Koo .edp_backlight_control = dce110_edp_backlight_control, 3043f42ea55bSAnthony Koo }; 3044f42ea55bSAnthony Koo 3045c13b408bSDave Airlie void dce110_hw_sequencer_construct(struct dc *dc) 30464562236bSHarry Wentland { 30474562236bSHarry Wentland dc->hwss = dce110_funcs; 3048f42ea55bSAnthony Koo dc->hwseq->funcs = dce110_private_funcs; 30494562236bSHarry Wentland } 30504562236bSHarry Wentland 3051