14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland #include "dm_services.h" 264562236bSHarry Wentland #include "dc.h" 274562236bSHarry Wentland #include "dc_bios_types.h" 284562236bSHarry Wentland #include "core_types.h" 294562236bSHarry Wentland #include "core_status.h" 304562236bSHarry Wentland #include "resource.h" 314562236bSHarry Wentland #include "hw_sequencer.h" 324562236bSHarry Wentland #include "dm_helpers.h" 334562236bSHarry Wentland #include "dce110_hw_sequencer.h" 344562236bSHarry Wentland #include "dce110_timing_generator.h" 354562236bSHarry Wentland 364562236bSHarry Wentland #include "bios/bios_parser_helper.h" 374562236bSHarry Wentland #include "timing_generator.h" 384562236bSHarry Wentland #include "mem_input.h" 394562236bSHarry Wentland #include "opp.h" 404562236bSHarry Wentland #include "ipp.h" 414562236bSHarry Wentland #include "transform.h" 424562236bSHarry Wentland #include "stream_encoder.h" 434562236bSHarry Wentland #include "link_encoder.h" 444562236bSHarry Wentland #include "clock_source.h" 455e7773a2SAnthony Koo #include "abm.h" 464562236bSHarry Wentland #include "audio.h" 474562236bSHarry Wentland #include "dce/dce_hwseq.h" 484562236bSHarry Wentland 494562236bSHarry Wentland /* include DCE11 register header files */ 504562236bSHarry Wentland #include "dce/dce_11_0_d.h" 514562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 52e266fdf6SVitaly Prosyak #include "custom_float.h" 534562236bSHarry Wentland 544562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 554562236bSHarry Wentland uint32_t crtc; 564562236bSHarry Wentland }; 574562236bSHarry Wentland 584562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 594562236bSHarry Wentland { 604562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 614562236bSHarry Wentland }, 624562236bSHarry Wentland { 634562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 644562236bSHarry Wentland }, 654562236bSHarry Wentland { 664562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 674562236bSHarry Wentland }, 684562236bSHarry Wentland { 694562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 704562236bSHarry Wentland } 714562236bSHarry Wentland }; 724562236bSHarry Wentland 734562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 744562236bSHarry Wentland (reg + reg_offsets[id].blnd) 754562236bSHarry Wentland 764562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 774562236bSHarry Wentland (reg + reg_offsets[id].crtc) 784562236bSHarry Wentland 794562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 804562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 814562236bSHarry Wentland 824562236bSHarry Wentland /******************************************************************************* 834562236bSHarry Wentland * Private definitions 844562236bSHarry Wentland ******************************************************************************/ 854562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 864562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 874562236bSHarry Wentland { 884562236bSHarry Wentland uint32_t addr; 894562236bSHarry Wentland uint32_t value = 0; 904562236bSHarry Wentland uint32_t chunk_int = 0; 914562236bSHarry Wentland uint32_t chunk_mul = 0; 924562236bSHarry Wentland 934562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 944562236bSHarry Wentland value = dm_read_reg(ctx, addr); 954562236bSHarry Wentland 964562236bSHarry Wentland set_reg_field_value( 974562236bSHarry Wentland value, 984562236bSHarry Wentland 0, 994562236bSHarry Wentland DVMM_PTE_CONTROL, 1004562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1014562236bSHarry Wentland 1024562236bSHarry Wentland set_reg_field_value( 1034562236bSHarry Wentland value, 1044562236bSHarry Wentland 1, 1054562236bSHarry Wentland DVMM_PTE_CONTROL, 1064562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1074562236bSHarry Wentland 1084562236bSHarry Wentland set_reg_field_value( 1094562236bSHarry Wentland value, 1104562236bSHarry Wentland 1, 1114562236bSHarry Wentland DVMM_PTE_CONTROL, 1124562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1134562236bSHarry Wentland 1144562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1154562236bSHarry Wentland 1164562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1174562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1184562236bSHarry Wentland 1194562236bSHarry Wentland chunk_int = get_reg_field_value( 1204562236bSHarry Wentland value, 1214562236bSHarry Wentland DVMM_PTE_REQ, 1224562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1234562236bSHarry Wentland 1244562236bSHarry Wentland chunk_mul = get_reg_field_value( 1254562236bSHarry Wentland value, 1264562236bSHarry Wentland DVMM_PTE_REQ, 1274562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1284562236bSHarry Wentland 1294562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1304562236bSHarry Wentland 1314562236bSHarry Wentland set_reg_field_value( 1324562236bSHarry Wentland value, 1334562236bSHarry Wentland 255, 1344562236bSHarry Wentland DVMM_PTE_REQ, 1354562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1364562236bSHarry Wentland 1374562236bSHarry Wentland set_reg_field_value( 1384562236bSHarry Wentland value, 1394562236bSHarry Wentland 4, 1404562236bSHarry Wentland DVMM_PTE_REQ, 1414562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1424562236bSHarry Wentland 1434562236bSHarry Wentland set_reg_field_value( 1444562236bSHarry Wentland value, 1454562236bSHarry Wentland 4, 1464562236bSHarry Wentland DVMM_PTE_REQ, 1474562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1484562236bSHarry Wentland 1494562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1504562236bSHarry Wentland } 1514562236bSHarry Wentland } 1524562236bSHarry Wentland /**************************************************************************/ 1534562236bSHarry Wentland 1544562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1554562236bSHarry Wentland struct dc_context *ctx, 1564562236bSHarry Wentland bool clock_gating) 1574562236bSHarry Wentland { 1584562236bSHarry Wentland /*TODO*/ 1594562236bSHarry Wentland } 1604562236bSHarry Wentland 1614562236bSHarry Wentland static bool dce110_enable_display_power_gating( 1624562236bSHarry Wentland struct core_dc *dc, 1634562236bSHarry Wentland uint8_t controller_id, 1644562236bSHarry Wentland struct dc_bios *dcb, 1654562236bSHarry Wentland enum pipe_gating_control power_gating) 1664562236bSHarry Wentland { 1674562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 1684562236bSHarry Wentland enum bp_pipe_control_action cntl; 1694562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 1704562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1714562236bSHarry Wentland 1724562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1734562236bSHarry Wentland return true; 1744562236bSHarry Wentland 1754562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 1764562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 1774562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 1784562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 1794562236bSHarry Wentland else 1804562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 1814562236bSHarry Wentland 1824562236bSHarry Wentland if (controller_id == underlay_idx) 1834562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 1844562236bSHarry Wentland 1854562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 1864562236bSHarry Wentland 1874562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 1884562236bSHarry Wentland dcb, controller_id + 1, cntl); 1894562236bSHarry Wentland 1904562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 1914562236bSHarry Wentland * by default when command table is called 1924562236bSHarry Wentland * 1934562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 1944562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 1954562236bSHarry Wentland * than 3. 1964562236bSHarry Wentland */ 1974562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 1984562236bSHarry Wentland dm_write_reg(ctx, 1994562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2004562236bSHarry Wentland 0); 2014562236bSHarry Wentland } 2024562236bSHarry Wentland 2034562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2044562236bSHarry Wentland dce110_init_pte(ctx); 2054562236bSHarry Wentland 2064562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2074562236bSHarry Wentland return true; 2084562236bSHarry Wentland else 2094562236bSHarry Wentland return false; 2104562236bSHarry Wentland } 2114562236bSHarry Wentland 2124562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2134562236bSHarry Wentland const struct core_surface *surface) 2144562236bSHarry Wentland { 2154562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2164562236bSHarry Wentland 2174562236bSHarry Wentland switch (surface->public.format) { 2184562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2198693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2204562236bSHarry Wentland prescale_params->scale = 0x2020; 2214562236bSHarry Wentland break; 2224562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2234562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2244562236bSHarry Wentland prescale_params->scale = 0x2008; 2254562236bSHarry Wentland break; 2264562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2274562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2284562236bSHarry Wentland prescale_params->scale = 0x2000; 2294562236bSHarry Wentland break; 2304562236bSHarry Wentland default: 2314562236bSHarry Wentland ASSERT(false); 232d7194cf6SAric Cyr break; 2334562236bSHarry Wentland } 2344562236bSHarry Wentland } 2354562236bSHarry Wentland 2365936223fSJordan Lazare 2375936223fSJordan Lazare /* Only use LUT for 8 bit formats */ 2385936223fSJordan Lazare static bool use_lut(const struct core_surface *surface) 2395936223fSJordan Lazare { 2405936223fSJordan Lazare switch (surface->public.format) { 2415936223fSJordan Lazare case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2425936223fSJordan Lazare case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2435936223fSJordan Lazare return true; 2445936223fSJordan Lazare default: 2455936223fSJordan Lazare return false; 2465936223fSJordan Lazare } 2475936223fSJordan Lazare } 2485936223fSJordan Lazare 249d7194cf6SAric Cyr static bool dce110_set_input_transfer_func( 250fb735a9fSAnthony Koo struct pipe_ctx *pipe_ctx, 2514562236bSHarry Wentland const struct core_surface *surface) 2524562236bSHarry Wentland { 253fb735a9fSAnthony Koo struct input_pixel_processor *ipp = pipe_ctx->ipp; 25490e508baSAnthony Koo const struct core_transfer_func *tf = NULL; 25590e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 25690e508baSAnthony Koo bool result = true; 25790e508baSAnthony Koo 25890e508baSAnthony Koo if (ipp == NULL) 25990e508baSAnthony Koo return false; 26090e508baSAnthony Koo 26190e508baSAnthony Koo if (surface->public.in_transfer_func) 26290e508baSAnthony Koo tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func); 26390e508baSAnthony Koo 26490e508baSAnthony Koo build_prescale_params(&prescale_params, surface); 26590e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 26690e508baSAnthony Koo 2675936223fSJordan Lazare if (surface->public.gamma_correction && use_lut(surface)) 268d7194cf6SAric Cyr ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); 269d7194cf6SAric Cyr 27090e508baSAnthony Koo if (tf == NULL) { 27190e508baSAnthony Koo /* Default case if no input transfer function specified */ 27290e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 273306dadf0SAmy Zhang IPP_DEGAMMA_MODE_HW_sRGB); 27490e508baSAnthony Koo } else if (tf->public.type == TF_TYPE_PREDEFINED) { 27590e508baSAnthony Koo switch (tf->public.tf) { 27690e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 27790e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 27890e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_sRGB); 27990e508baSAnthony Koo break; 28090e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 28190e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 28290e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_xvYCC); 28390e508baSAnthony Koo break; 28490e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 28590e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 28690e508baSAnthony Koo IPP_DEGAMMA_MODE_BYPASS); 28790e508baSAnthony Koo break; 28890e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 28990e508baSAnthony Koo result = false; 29090e508baSAnthony Koo break; 29190e508baSAnthony Koo default: 29290e508baSAnthony Koo result = false; 293d7194cf6SAric Cyr break; 29490e508baSAnthony Koo } 29570063a59SAmy Zhang } else if (tf->public.type == TF_TYPE_BYPASS) { 29670063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 29790e508baSAnthony Koo } else { 29890e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 29990e508baSAnthony Koo result = false; 30090e508baSAnthony Koo } 30190e508baSAnthony Koo 30290e508baSAnthony Koo return result; 30390e508baSAnthony Koo } 30490e508baSAnthony Koo 305fcd2f4bfSAmy Zhang static bool convert_to_custom_float( 306fcd2f4bfSAmy Zhang struct pwl_result_data *rgb_resulted, 307fcd2f4bfSAmy Zhang struct curve_points *arr_points, 308fcd2f4bfSAmy Zhang uint32_t hw_points_num) 309fcd2f4bfSAmy Zhang { 310fcd2f4bfSAmy Zhang struct custom_float_format fmt; 311fcd2f4bfSAmy Zhang 312fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 313fcd2f4bfSAmy Zhang 314fcd2f4bfSAmy Zhang uint32_t i = 0; 315fcd2f4bfSAmy Zhang 316fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 317fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 318fcd2f4bfSAmy Zhang fmt.sign = true; 319fcd2f4bfSAmy Zhang 320fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 321fcd2f4bfSAmy Zhang arr_points[0].x, 322fcd2f4bfSAmy Zhang &fmt, 323fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 324fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 325fcd2f4bfSAmy Zhang return false; 326fcd2f4bfSAmy Zhang } 327fcd2f4bfSAmy Zhang 328fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 329fcd2f4bfSAmy Zhang arr_points[0].offset, 330fcd2f4bfSAmy Zhang &fmt, 331fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 332fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 333fcd2f4bfSAmy Zhang return false; 334fcd2f4bfSAmy Zhang } 335fcd2f4bfSAmy Zhang 336fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 337fcd2f4bfSAmy Zhang arr_points[0].slope, 338fcd2f4bfSAmy Zhang &fmt, 339fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 340fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 341fcd2f4bfSAmy Zhang return false; 342fcd2f4bfSAmy Zhang } 343fcd2f4bfSAmy Zhang 344fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 345fcd2f4bfSAmy Zhang fmt.sign = false; 346fcd2f4bfSAmy Zhang 347fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 348fcd2f4bfSAmy Zhang arr_points[1].x, 349fcd2f4bfSAmy Zhang &fmt, 350fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 351fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 352fcd2f4bfSAmy Zhang return false; 353fcd2f4bfSAmy Zhang } 354fcd2f4bfSAmy Zhang 355fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 356fcd2f4bfSAmy Zhang arr_points[1].y, 357fcd2f4bfSAmy Zhang &fmt, 358fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 359fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 360fcd2f4bfSAmy Zhang return false; 361fcd2f4bfSAmy Zhang } 362fcd2f4bfSAmy Zhang 363fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 364fcd2f4bfSAmy Zhang arr_points[2].slope, 365fcd2f4bfSAmy Zhang &fmt, 366fcd2f4bfSAmy Zhang &arr_points[2].custom_float_slope)) { 367fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 368fcd2f4bfSAmy Zhang return false; 369fcd2f4bfSAmy Zhang } 370fcd2f4bfSAmy Zhang 371fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 372fcd2f4bfSAmy Zhang fmt.sign = true; 373fcd2f4bfSAmy Zhang 374fcd2f4bfSAmy Zhang while (i != hw_points_num) { 375fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 376fcd2f4bfSAmy Zhang rgb->red, 377fcd2f4bfSAmy Zhang &fmt, 378fcd2f4bfSAmy Zhang &rgb->red_reg)) { 379fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 380fcd2f4bfSAmy Zhang return false; 381fcd2f4bfSAmy Zhang } 382fcd2f4bfSAmy Zhang 383fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 384fcd2f4bfSAmy Zhang rgb->green, 385fcd2f4bfSAmy Zhang &fmt, 386fcd2f4bfSAmy Zhang &rgb->green_reg)) { 387fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 388fcd2f4bfSAmy Zhang return false; 389fcd2f4bfSAmy Zhang } 390fcd2f4bfSAmy Zhang 391fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 392fcd2f4bfSAmy Zhang rgb->blue, 393fcd2f4bfSAmy Zhang &fmt, 394fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 395fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 396fcd2f4bfSAmy Zhang return false; 397fcd2f4bfSAmy Zhang } 398fcd2f4bfSAmy Zhang 399fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 400fcd2f4bfSAmy Zhang rgb->delta_red, 401fcd2f4bfSAmy Zhang &fmt, 402fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 403fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 404fcd2f4bfSAmy Zhang return false; 405fcd2f4bfSAmy Zhang } 406fcd2f4bfSAmy Zhang 407fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 408fcd2f4bfSAmy Zhang rgb->delta_green, 409fcd2f4bfSAmy Zhang &fmt, 410fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 411fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 412fcd2f4bfSAmy Zhang return false; 413fcd2f4bfSAmy Zhang } 414fcd2f4bfSAmy Zhang 415fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 416fcd2f4bfSAmy Zhang rgb->delta_blue, 417fcd2f4bfSAmy Zhang &fmt, 418fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 419fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 420fcd2f4bfSAmy Zhang return false; 421fcd2f4bfSAmy Zhang } 422fcd2f4bfSAmy Zhang 423fcd2f4bfSAmy Zhang ++rgb; 424fcd2f4bfSAmy Zhang ++i; 425fcd2f4bfSAmy Zhang } 426fcd2f4bfSAmy Zhang 427fcd2f4bfSAmy Zhang return true; 428fcd2f4bfSAmy Zhang } 429fcd2f4bfSAmy Zhang 430e266fdf6SVitaly Prosyak static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func 431fcd2f4bfSAmy Zhang *output_tf, struct pwl_params *regamma_params) 432fcd2f4bfSAmy Zhang { 43323ae4f8eSAmy Zhang struct curve_points *arr_points; 43423ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 43523ae4f8eSAmy Zhang struct pwl_result_data *rgb; 43623ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 437fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 438fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 439fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 440fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 441fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 442fcd2f4bfSAmy Zhang 443fcd2f4bfSAmy Zhang int32_t segment_start, segment_end; 44423ae4f8eSAmy Zhang uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; 44523ae4f8eSAmy Zhang 44670063a59SAmy Zhang if (output_tf == NULL || regamma_params == NULL || 44770063a59SAmy Zhang output_tf->type == TF_TYPE_BYPASS) 44823ae4f8eSAmy Zhang return false; 44923ae4f8eSAmy Zhang 45023ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 45123ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 45223ae4f8eSAmy Zhang hw_points = 0; 453fcd2f4bfSAmy Zhang 454fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 455fcd2f4bfSAmy Zhang 456fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 457534db198SAmy Zhang /* 16 segments 458fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 459fcd2f4bfSAmy Zhang */ 460fcd2f4bfSAmy Zhang segment_start = -11; 461fcd2f4bfSAmy Zhang segment_end = 5; 462fcd2f4bfSAmy Zhang 463534db198SAmy Zhang seg_distr[0] = 2; 464534db198SAmy Zhang seg_distr[1] = 2; 465534db198SAmy Zhang seg_distr[2] = 2; 466534db198SAmy Zhang seg_distr[3] = 2; 467534db198SAmy Zhang seg_distr[4] = 2; 468534db198SAmy Zhang seg_distr[5] = 2; 469534db198SAmy Zhang seg_distr[6] = 3; 470534db198SAmy Zhang seg_distr[7] = 4; 471534db198SAmy Zhang seg_distr[8] = 4; 472534db198SAmy Zhang seg_distr[9] = 4; 473534db198SAmy Zhang seg_distr[10] = 4; 474534db198SAmy Zhang seg_distr[11] = 5; 475534db198SAmy Zhang seg_distr[12] = 5; 476534db198SAmy Zhang seg_distr[13] = 5; 477534db198SAmy Zhang seg_distr[14] = 5; 478534db198SAmy Zhang seg_distr[15] = 5; 479534db198SAmy Zhang 480fcd2f4bfSAmy Zhang } else { 481534db198SAmy Zhang /* 10 segments 482fcd2f4bfSAmy Zhang * segment is from 2^-10 to 2^0 483fcd2f4bfSAmy Zhang */ 484fcd2f4bfSAmy Zhang segment_start = -10; 485fcd2f4bfSAmy Zhang segment_end = 0; 486534db198SAmy Zhang 487534db198SAmy Zhang seg_distr[0] = 3; 488534db198SAmy Zhang seg_distr[1] = 4; 489534db198SAmy Zhang seg_distr[2] = 4; 490534db198SAmy Zhang seg_distr[3] = 4; 491534db198SAmy Zhang seg_distr[4] = 4; 492534db198SAmy Zhang seg_distr[5] = 4; 493534db198SAmy Zhang seg_distr[6] = 4; 494534db198SAmy Zhang seg_distr[7] = 4; 495534db198SAmy Zhang seg_distr[8] = 5; 496534db198SAmy Zhang seg_distr[9] = 5; 497534db198SAmy Zhang seg_distr[10] = -1; 498534db198SAmy Zhang seg_distr[11] = -1; 499534db198SAmy Zhang seg_distr[12] = -1; 500534db198SAmy Zhang seg_distr[13] = -1; 501534db198SAmy Zhang seg_distr[14] = -1; 502534db198SAmy Zhang seg_distr[15] = -1; 503fcd2f4bfSAmy Zhang } 504fcd2f4bfSAmy Zhang 505534db198SAmy Zhang for (k = 0; k < 16; k++) { 506534db198SAmy Zhang if (seg_distr[k] != -1) 507534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 508534db198SAmy Zhang } 509534db198SAmy Zhang 510fcd2f4bfSAmy Zhang j = 0; 511534db198SAmy Zhang for (k = 0; k < (segment_end - segment_start); k++) { 512534db198SAmy Zhang increment = 32 / (1 << seg_distr[k]); 513534db198SAmy Zhang start_index = (segment_start + k + 25) * 32; 514534db198SAmy Zhang for (i = start_index; i < start_index + 32; i += increment) { 515534db198SAmy Zhang if (j == hw_points - 1) 516fcd2f4bfSAmy Zhang break; 517fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 518fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 519fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 520fcd2f4bfSAmy Zhang j++; 521fcd2f4bfSAmy Zhang } 522534db198SAmy Zhang } 523534db198SAmy Zhang 524534db198SAmy Zhang /* last point */ 525534db198SAmy Zhang start_index = (segment_end + 25) * 32; 526534db198SAmy Zhang rgb_resulted[hw_points - 1].red = 527534db198SAmy Zhang output_tf->tf_pts.red[start_index]; 528534db198SAmy Zhang rgb_resulted[hw_points - 1].green = 529534db198SAmy Zhang output_tf->tf_pts.green[start_index]; 530534db198SAmy Zhang rgb_resulted[hw_points - 1].blue = 531534db198SAmy Zhang output_tf->tf_pts.blue[start_index]; 532fcd2f4bfSAmy Zhang 533fcd2f4bfSAmy Zhang arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 534fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_start)); 535fcd2f4bfSAmy Zhang arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 536fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 537fcd2f4bfSAmy Zhang arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 538fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 539fcd2f4bfSAmy Zhang 540fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 541fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 542fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 543fcd2f4bfSAmy Zhang 544fcd2f4bfSAmy Zhang y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); 545fcd2f4bfSAmy Zhang 546fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 547fcd2f4bfSAmy Zhang arr_points[0].slope = dal_fixed31_32_div( 548fcd2f4bfSAmy Zhang arr_points[0].y, 549fcd2f4bfSAmy Zhang arr_points[0].x); 550fcd2f4bfSAmy Zhang 551fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 552fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 553fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 554fcd2f4bfSAmy Zhang 555fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 556fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 557fcd2f4bfSAmy Zhang */ 558fcd2f4bfSAmy Zhang y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); 559fcd2f4bfSAmy Zhang 560fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 561fcd2f4bfSAmy Zhang arr_points[2].y = y3_max; 562fcd2f4bfSAmy Zhang 563fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_zero; 564fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_zero; 565fcd2f4bfSAmy Zhang 566fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 567fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 568fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 569fcd2f4bfSAmy Zhang */ 570fcd2f4bfSAmy Zhang const struct fixed31_32 end_value = 571fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(125); 572fcd2f4bfSAmy Zhang 573fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_div( 574fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 575fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 576fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_div( 577fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 578fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 579fcd2f4bfSAmy Zhang } 580fcd2f4bfSAmy Zhang 581fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 582fcd2f4bfSAmy Zhang 583534db198SAmy Zhang i = 1; 584534db198SAmy Zhang for (k = 0; k < 16 && i < 16; k++) { 585534db198SAmy Zhang if (seg_distr[k] != -1) { 586534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 587534db198SAmy Zhang seg_distr[k]; 588534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 589534db198SAmy Zhang regamma_params->arr_curve_points[k]. 590534db198SAmy Zhang offset + (1 << seg_distr[k]); 591fcd2f4bfSAmy Zhang } 592534db198SAmy Zhang i++; 593534db198SAmy Zhang } 594534db198SAmy Zhang 595534db198SAmy Zhang if (seg_distr[k] != -1) 596534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 597534db198SAmy Zhang seg_distr[k]; 598fcd2f4bfSAmy Zhang 59923ae4f8eSAmy Zhang rgb = rgb_resulted; 60023ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 601fcd2f4bfSAmy Zhang 602fcd2f4bfSAmy Zhang i = 1; 603fcd2f4bfSAmy Zhang 604fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 605fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) 606fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 607fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) 608fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 609fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) 610fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 611fcd2f4bfSAmy Zhang 612fcd2f4bfSAmy Zhang rgb->delta_red = dal_fixed31_32_sub( 613fcd2f4bfSAmy Zhang rgb_plus_1->red, 614fcd2f4bfSAmy Zhang rgb->red); 615fcd2f4bfSAmy Zhang rgb->delta_green = dal_fixed31_32_sub( 616fcd2f4bfSAmy Zhang rgb_plus_1->green, 617fcd2f4bfSAmy Zhang rgb->green); 618fcd2f4bfSAmy Zhang rgb->delta_blue = dal_fixed31_32_sub( 619fcd2f4bfSAmy Zhang rgb_plus_1->blue, 620fcd2f4bfSAmy Zhang rgb->blue); 621fcd2f4bfSAmy Zhang 622fcd2f4bfSAmy Zhang ++rgb_plus_1; 623fcd2f4bfSAmy Zhang ++rgb; 624fcd2f4bfSAmy Zhang ++i; 625fcd2f4bfSAmy Zhang } 626fcd2f4bfSAmy Zhang 627fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 628fcd2f4bfSAmy Zhang 629fcd2f4bfSAmy Zhang return true; 630fcd2f4bfSAmy Zhang } 631fcd2f4bfSAmy Zhang 63290e508baSAnthony Koo static bool dce110_set_output_transfer_func( 63390e508baSAnthony Koo struct pipe_ctx *pipe_ctx, 63490e508baSAnthony Koo const struct core_surface *surface, /* Surface - To be removed */ 63590e508baSAnthony Koo const struct core_stream *stream) 63690e508baSAnthony Koo { 637fb735a9fSAnthony Koo struct output_pixel_processor *opp = pipe_ctx->opp; 6384562236bSHarry Wentland 6394562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, true); 640974db151SDmytro Laktyushkin opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 6414562236bSHarry Wentland 642d7194cf6SAric Cyr if (stream->public.out_transfer_func && 643fcd2f4bfSAmy Zhang stream->public.out_transfer_func->type == 644fcd2f4bfSAmy Zhang TF_TYPE_PREDEFINED && 645fcd2f4bfSAmy Zhang stream->public.out_transfer_func->tf == 646fcd2f4bfSAmy Zhang TRANSFER_FUNCTION_SRGB) { 647d7194cf6SAric Cyr opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); 648fcd2f4bfSAmy Zhang } else if (dce110_translate_regamma_to_hw_format( 649974db151SDmytro Laktyushkin stream->public.out_transfer_func, &opp->regamma_params)) { 650974db151SDmytro Laktyushkin opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params); 6514562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); 6524562236bSHarry Wentland } else { 6534562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); 6544562236bSHarry Wentland } 6554562236bSHarry Wentland 6564562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, false); 6574562236bSHarry Wentland 658cc0cb445SLeon Elazar return true; 6594562236bSHarry Wentland } 6604562236bSHarry Wentland 6614562236bSHarry Wentland static enum dc_status bios_parser_crtc_source_select( 6624562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 6634562236bSHarry Wentland { 6644562236bSHarry Wentland struct dc_bios *dcb; 6654562236bSHarry Wentland /* call VBIOS table to set CRTC source for the HW 6664562236bSHarry Wentland * encoder block 6674562236bSHarry Wentland * note: video bios clears all FMT setting here. */ 6684562236bSHarry Wentland struct bp_crtc_source_select crtc_source_select = {0}; 6694562236bSHarry Wentland const struct core_sink *sink = pipe_ctx->stream->sink; 6704562236bSHarry Wentland 6714562236bSHarry Wentland crtc_source_select.engine_id = pipe_ctx->stream_enc->id; 6724562236bSHarry Wentland crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1; 6734562236bSHarry Wentland /*TODO: Need to un-hardcode color depth, dp_audio and account for 6744562236bSHarry Wentland * the case where signal and sink signal is different (translator 6754562236bSHarry Wentland * encoder)*/ 6764562236bSHarry Wentland crtc_source_select.signal = pipe_ctx->stream->signal; 6774562236bSHarry Wentland crtc_source_select.enable_dp_audio = false; 6784562236bSHarry Wentland crtc_source_select.sink_signal = pipe_ctx->stream->signal; 6794562236bSHarry Wentland crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6804562236bSHarry Wentland 6814562236bSHarry Wentland dcb = sink->ctx->dc_bios; 6824562236bSHarry Wentland 6834562236bSHarry Wentland if (BP_RESULT_OK != dcb->funcs->crtc_source_select( 6844562236bSHarry Wentland dcb, 6854562236bSHarry Wentland &crtc_source_select)) { 6864562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 6874562236bSHarry Wentland } 6884562236bSHarry Wentland 6894562236bSHarry Wentland return DC_OK; 6904562236bSHarry Wentland } 6914562236bSHarry Wentland 6924562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6934562236bSHarry Wentland { 69486e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 69586e2e1beSHersen Wu 69686e2e1beSHersen Wu if (pipe_ctx->stream_enc == NULL) 69786e2e1beSHersen Wu return; /* this is not root pipe */ 69886e2e1beSHersen Wu 6994562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 7004562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_hdmi_info_packets( 7014562236bSHarry Wentland pipe_ctx->stream_enc, 7024562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 7034562236bSHarry Wentland else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7044562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_dp_info_packets( 7054562236bSHarry Wentland pipe_ctx->stream_enc, 7064562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 7074562236bSHarry Wentland } 7084562236bSHarry Wentland 7094562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 7104562236bSHarry Wentland { 7114562236bSHarry Wentland enum dc_lane_count lane_count = 7124562236bSHarry Wentland pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count; 7134562236bSHarry Wentland 7144562236bSHarry Wentland struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; 7154562236bSHarry Wentland struct core_link *link = pipe_ctx->stream->sink->link; 7164562236bSHarry Wentland 7174562236bSHarry Wentland /* 1. update AVI info frame (HDMI, DP) 7184562236bSHarry Wentland * we always need to update info frame 7194562236bSHarry Wentland */ 7204562236bSHarry Wentland uint32_t active_total_with_borders; 7214562236bSHarry Wentland uint32_t early_control = 0; 7224562236bSHarry Wentland struct timing_generator *tg = pipe_ctx->tg; 7234562236bSHarry Wentland 7244562236bSHarry Wentland /* TODOFPGA may change to hwss.update_info_frame */ 7254562236bSHarry Wentland dce110_update_info_frame(pipe_ctx); 7264562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 7274562236bSHarry Wentland active_total_with_borders = 7284562236bSHarry Wentland timing->h_addressable 7294562236bSHarry Wentland + timing->h_border_left 7304562236bSHarry Wentland + timing->h_border_right; 7314562236bSHarry Wentland 7324562236bSHarry Wentland if (lane_count != 0) 7334562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 7344562236bSHarry Wentland 7354562236bSHarry Wentland if (early_control == 0) 7364562236bSHarry Wentland early_control = lane_count; 7374562236bSHarry Wentland 7384562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 7394562236bSHarry Wentland 7404562236bSHarry Wentland /* enable audio only within mode set */ 7414562236bSHarry Wentland if (pipe_ctx->audio != NULL) { 7424562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7434562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc); 7444562236bSHarry Wentland } 7454562236bSHarry Wentland 7464562236bSHarry Wentland /* For MST, there are multiply stream go to only one link. 7474562236bSHarry Wentland * connect DIG back_end to front_end while enable_stream and 7484562236bSHarry Wentland * disconnect them during disable_stream 7494562236bSHarry Wentland * BY this, it is logic clean to separate stream and link */ 7504562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 7514562236bSHarry Wentland pipe_ctx->stream_enc->id, true); 7524562236bSHarry Wentland 7534562236bSHarry Wentland } 7544562236bSHarry Wentland 7554562236bSHarry Wentland void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 7564562236bSHarry Wentland { 7574562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 7584562236bSHarry Wentland struct core_link *link = stream->sink->link; 7594562236bSHarry Wentland 7604562236bSHarry Wentland if (pipe_ctx->audio) { 7614562236bSHarry Wentland pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); 7624562236bSHarry Wentland 7634562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7644562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_disable( 7654562236bSHarry Wentland pipe_ctx->stream_enc); 7664562236bSHarry Wentland else 7674562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_disable( 7684562236bSHarry Wentland pipe_ctx->stream_enc); 7694562236bSHarry Wentland 7704562236bSHarry Wentland pipe_ctx->audio = NULL; 7714562236bSHarry Wentland 7724562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 7734562236bSHarry Wentland * add audio mode list change flag */ 7744562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 7754562236bSHarry Wentland * stream->stream_engine_id); 7764562236bSHarry Wentland */ 7774562236bSHarry Wentland } 7784562236bSHarry Wentland 7794562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 7804562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets( 7814562236bSHarry Wentland pipe_ctx->stream_enc); 7824562236bSHarry Wentland 7834562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7844562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_dp_info_packets( 7854562236bSHarry Wentland pipe_ctx->stream_enc); 7864562236bSHarry Wentland 7874562236bSHarry Wentland pipe_ctx->stream_enc->funcs->audio_mute_control( 7884562236bSHarry Wentland pipe_ctx->stream_enc, true); 7894562236bSHarry Wentland 7904562236bSHarry Wentland 7914562236bSHarry Wentland /* blank at encoder level */ 7924562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7934562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc); 7944562236bSHarry Wentland 7954562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 7964562236bSHarry Wentland link->link_enc, 7974562236bSHarry Wentland pipe_ctx->stream_enc->id, 7984562236bSHarry Wentland false); 7994562236bSHarry Wentland 8004562236bSHarry Wentland } 8014562236bSHarry Wentland 8024562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 8034562236bSHarry Wentland struct dc_link_settings *link_settings) 8044562236bSHarry Wentland { 8054562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 8064562236bSHarry Wentland 8074562236bSHarry Wentland /* only 3 items below are used by unblank */ 8086235b23cSTony Cheng params.pixel_clk_khz = 8094562236bSHarry Wentland pipe_ctx->stream->public.timing.pix_clk_khz; 8104562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 8114562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); 8124562236bSHarry Wentland } 8134562236bSHarry Wentland 8144562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 8154562236bSHarry Wentland { 8164562236bSHarry Wentland switch (crtc_id) { 8174562236bSHarry Wentland case CONTROLLER_ID_D0: 8184562236bSHarry Wentland return DTO_SOURCE_ID0; 8194562236bSHarry Wentland case CONTROLLER_ID_D1: 8204562236bSHarry Wentland return DTO_SOURCE_ID1; 8214562236bSHarry Wentland case CONTROLLER_ID_D2: 8224562236bSHarry Wentland return DTO_SOURCE_ID2; 8234562236bSHarry Wentland case CONTROLLER_ID_D3: 8244562236bSHarry Wentland return DTO_SOURCE_ID3; 8254562236bSHarry Wentland case CONTROLLER_ID_D4: 8264562236bSHarry Wentland return DTO_SOURCE_ID4; 8274562236bSHarry Wentland case CONTROLLER_ID_D5: 8284562236bSHarry Wentland return DTO_SOURCE_ID5; 8294562236bSHarry Wentland default: 8304562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 8314562236bSHarry Wentland } 8324562236bSHarry Wentland } 8334562236bSHarry Wentland 8344562236bSHarry Wentland static void build_audio_output( 8354562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 8364562236bSHarry Wentland struct audio_output *audio_output) 8374562236bSHarry Wentland { 8384562236bSHarry Wentland const struct core_stream *stream = pipe_ctx->stream; 8394562236bSHarry Wentland audio_output->engine_id = pipe_ctx->stream_enc->id; 8404562236bSHarry Wentland 8414562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 8424562236bSHarry Wentland 8434562236bSHarry Wentland /* audio_crtc_info */ 8444562236bSHarry Wentland 8454562236bSHarry Wentland audio_output->crtc_info.h_total = 8464562236bSHarry Wentland stream->public.timing.h_total; 8474562236bSHarry Wentland 8484562236bSHarry Wentland /* 8494562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 8504562236bSHarry Wentland * need to specify actual active signal portion 8514562236bSHarry Wentland */ 8524562236bSHarry Wentland audio_output->crtc_info.h_active = 8534562236bSHarry Wentland stream->public.timing.h_addressable 8544562236bSHarry Wentland + stream->public.timing.h_border_left 8554562236bSHarry Wentland + stream->public.timing.h_border_right; 8564562236bSHarry Wentland 8574562236bSHarry Wentland audio_output->crtc_info.v_active = 8584562236bSHarry Wentland stream->public.timing.v_addressable 8594562236bSHarry Wentland + stream->public.timing.v_border_top 8604562236bSHarry Wentland + stream->public.timing.v_border_bottom; 8614562236bSHarry Wentland 8624562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 8634562236bSHarry Wentland 8644562236bSHarry Wentland audio_output->crtc_info.interlaced = 8654562236bSHarry Wentland stream->public.timing.flags.INTERLACE; 8664562236bSHarry Wentland 8674562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 8684562236bSHarry Wentland (stream->public.timing.pix_clk_khz*1000)/ 8694562236bSHarry Wentland (stream->public.timing.h_total*stream->public.timing.v_total); 8704562236bSHarry Wentland 8714562236bSHarry Wentland audio_output->crtc_info.color_depth = 8724562236bSHarry Wentland stream->public.timing.display_color_depth; 8734562236bSHarry Wentland 8744562236bSHarry Wentland audio_output->crtc_info.requested_pixel_clock = 8754562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 8764562236bSHarry Wentland 8774562236bSHarry Wentland audio_output->crtc_info.calculated_pixel_clock = 8784562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 8794562236bSHarry Wentland 88087b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 88187b58768SCharlene Liu if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && 88287b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock == 88387b58768SCharlene Liu stream->public.timing.pix_clk_khz) { 88487b58768SCharlene Liu if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 88587b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock = 88687b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock/2; 88787b58768SCharlene Liu audio_output->crtc_info.calculated_pixel_clock = 88887b58768SCharlene Liu pipe_ctx->pix_clk_params.requested_pix_clk/2; 88987b58768SCharlene Liu 89087b58768SCharlene Liu } 89187b58768SCharlene Liu } 89287b58768SCharlene Liu 8934562236bSHarry Wentland if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 8944562236bSHarry Wentland pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 8954562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 8961a687574SDmytro Laktyushkin pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency( 8974562236bSHarry Wentland pipe_ctx->dis_clk); 8984562236bSHarry Wentland } 8994562236bSHarry Wentland 9004562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 9014562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 9024562236bSHarry Wentland 9034562236bSHarry Wentland audio_output->pll_info.dto_source = 9044562236bSHarry Wentland translate_to_dto_source( 9054562236bSHarry Wentland pipe_ctx->pipe_idx + 1); 9064562236bSHarry Wentland 9074562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 9084562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 9094562236bSHarry Wentland 9104562236bSHarry Wentland audio_output->pll_info.ss_percentage = 9114562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 9124562236bSHarry Wentland } 9134562236bSHarry Wentland 9144562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 9154562236bSHarry Wentland struct tg_color *color) 9164562236bSHarry Wentland { 9174562236bSHarry Wentland uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4; 9184562236bSHarry Wentland 9194562236bSHarry Wentland switch (pipe_ctx->scl_data.format) { 9204562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 9214562236bSHarry Wentland /* set boarder color to red */ 9224562236bSHarry Wentland color->color_r_cr = color_value; 9234562236bSHarry Wentland break; 9244562236bSHarry Wentland 9254562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 9264562236bSHarry Wentland /* set boarder color to blue */ 9274562236bSHarry Wentland color->color_b_cb = color_value; 9284562236bSHarry Wentland break; 9294562236bSHarry Wentland case PIXEL_FORMAT_420BPP12: 930b2d0a103SDmytro Laktyushkin case PIXEL_FORMAT_420BPP15: 9314562236bSHarry Wentland /* set boarder color to green */ 9324562236bSHarry Wentland color->color_g_y = color_value; 9334562236bSHarry Wentland break; 9344562236bSHarry Wentland case PIXEL_FORMAT_FP16: 9354562236bSHarry Wentland /* set boarder color to white */ 9364562236bSHarry Wentland color->color_r_cr = color_value; 9374562236bSHarry Wentland color->color_b_cb = color_value; 9384562236bSHarry Wentland color->color_g_y = color_value; 9394562236bSHarry Wentland break; 9404562236bSHarry Wentland default: 9414562236bSHarry Wentland break; 9424562236bSHarry Wentland } 9434562236bSHarry Wentland } 9444562236bSHarry Wentland 9454562236bSHarry Wentland static void program_scaler(const struct core_dc *dc, 9464562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 9474562236bSHarry Wentland { 9484562236bSHarry Wentland struct tg_color color = {0}; 9494562236bSHarry Wentland 9504562236bSHarry Wentland if (dc->public.debug.surface_visual_confirm) 9514562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 9524562236bSHarry Wentland else 9534562236bSHarry Wentland color_space_to_black_color(dc, 9544562236bSHarry Wentland pipe_ctx->stream->public.output_color_space, 9554562236bSHarry Wentland &color); 9564562236bSHarry Wentland 9574562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( 9584562236bSHarry Wentland pipe_ctx->xfm, 9594562236bSHarry Wentland pipe_ctx->scl_data.lb_params.depth, 9604562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 9614562236bSHarry Wentland 9624562236bSHarry Wentland if (pipe_ctx->tg->funcs->set_overscan_blank_color) 9634562236bSHarry Wentland pipe_ctx->tg->funcs->set_overscan_blank_color( 9644562236bSHarry Wentland pipe_ctx->tg, 9654562236bSHarry Wentland &color); 9664562236bSHarry Wentland 9674562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, 9684562236bSHarry Wentland &pipe_ctx->scl_data); 9694562236bSHarry Wentland } 9704562236bSHarry Wentland 9714b5e7d62SHersen Wu static enum dc_status dce110_prog_pixclk_crtc_otg( 9724562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 9734562236bSHarry Wentland struct validate_context *context, 9744562236bSHarry Wentland struct core_dc *dc) 9754562236bSHarry Wentland { 9764562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 9774562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 9784562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 9794562236bSHarry Wentland struct tg_color black_color = {0}; 9804562236bSHarry Wentland 9814562236bSHarry Wentland if (!pipe_ctx_old->stream) { 9824562236bSHarry Wentland 9834562236bSHarry Wentland /* program blank color */ 9844562236bSHarry Wentland color_space_to_black_color(dc, 9854562236bSHarry Wentland stream->public.output_color_space, &black_color); 9864562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank_color( 9874562236bSHarry Wentland pipe_ctx->tg, 9884562236bSHarry Wentland &black_color); 9894b5e7d62SHersen Wu 9904562236bSHarry Wentland /* 9914562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 9924562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 9934562236bSHarry Wentland */ 9944562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 9954562236bSHarry Wentland 9964562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 9974562236bSHarry Wentland pipe_ctx->clock_source, 9984562236bSHarry Wentland &pipe_ctx->pix_clk_params, 9994562236bSHarry Wentland &pipe_ctx->pll_settings)) { 10004562236bSHarry Wentland BREAK_TO_DEBUGGER(); 10014562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 10024562236bSHarry Wentland } 10034562236bSHarry Wentland 10044562236bSHarry Wentland pipe_ctx->tg->funcs->program_timing( 10054562236bSHarry Wentland pipe_ctx->tg, 10064562236bSHarry Wentland &stream->public.timing, 10074562236bSHarry Wentland true); 10084562236bSHarry Wentland } 10094562236bSHarry Wentland 10104562236bSHarry Wentland if (!pipe_ctx_old->stream) { 10114562236bSHarry Wentland if (false == pipe_ctx->tg->funcs->enable_crtc( 10124562236bSHarry Wentland pipe_ctx->tg)) { 10134562236bSHarry Wentland BREAK_TO_DEBUGGER(); 10144562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 10154562236bSHarry Wentland } 10164562236bSHarry Wentland } 10174562236bSHarry Wentland 10184562236bSHarry Wentland return DC_OK; 10194562236bSHarry Wentland } 10204562236bSHarry Wentland 10214562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 10224562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 10234562236bSHarry Wentland struct validate_context *context, 10244562236bSHarry Wentland struct core_dc *dc) 10254562236bSHarry Wentland { 10264562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 10274562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 10284562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 10294562236bSHarry Wentland 10304562236bSHarry Wentland /* */ 10314562236bSHarry Wentland dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); 10324562236bSHarry Wentland 10334562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_dyn_expansion( 10344562236bSHarry Wentland pipe_ctx->opp, 10354562236bSHarry Wentland COLOR_SPACE_YCBCR601, 10364562236bSHarry Wentland stream->public.timing.display_color_depth, 10374562236bSHarry Wentland pipe_ctx->stream->signal); 10384562236bSHarry Wentland 1039181a888fSCharlene Liu /* FPGA does not program backend */ 1040181a888fSCharlene Liu if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 10414562236bSHarry Wentland pipe_ctx->opp->funcs->opp_program_fmt( 10424562236bSHarry Wentland pipe_ctx->opp, 10434562236bSHarry Wentland &stream->bit_depth_params, 10444562236bSHarry Wentland &stream->clamping); 10454562236bSHarry Wentland return DC_OK; 1046181a888fSCharlene Liu } 10474562236bSHarry Wentland /* TODO: move to stream encoder */ 10484562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 10494562236bSHarry Wentland if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { 10504562236bSHarry Wentland BREAK_TO_DEBUGGER(); 10514562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 10524562236bSHarry Wentland } 10534562236bSHarry Wentland 10544562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 10554562236bSHarry Wentland stream->sink->link->link_enc->funcs->setup( 10564562236bSHarry Wentland stream->sink->link->link_enc, 10574562236bSHarry Wentland pipe_ctx->stream->signal); 10584562236bSHarry Wentland 1059ab3c1798SVitaly Prosyak if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 1060ab3c1798SVitaly Prosyak pipe_ctx->stream_enc->funcs->setup_stereo_sync( 1061ab3c1798SVitaly Prosyak pipe_ctx->stream_enc, 1062ab3c1798SVitaly Prosyak pipe_ctx->tg->inst, 1063ab3c1798SVitaly Prosyak stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE); 1064ab3c1798SVitaly Prosyak 1065ab3c1798SVitaly Prosyak 1066181a888fSCharlene Liu /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ 1067181a888fSCharlene Liu pipe_ctx->opp->funcs->opp_program_fmt( 1068181a888fSCharlene Liu pipe_ctx->opp, 1069181a888fSCharlene Liu &stream->bit_depth_params, 1070181a888fSCharlene Liu &stream->clamping); 1071181a888fSCharlene Liu 10724562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10734562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( 10744562236bSHarry Wentland pipe_ctx->stream_enc, 10754562236bSHarry Wentland &stream->public.timing, 10764562236bSHarry Wentland stream->public.output_color_space); 10774562236bSHarry Wentland 10784562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 10794562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( 10804562236bSHarry Wentland pipe_ctx->stream_enc, 10814562236bSHarry Wentland &stream->public.timing, 10824562236bSHarry Wentland stream->phy_pix_clk, 10834562236bSHarry Wentland pipe_ctx->audio != NULL); 10844562236bSHarry Wentland 10854562236bSHarry Wentland if (dc_is_dvi_signal(pipe_ctx->stream->signal)) 10864562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( 10874562236bSHarry Wentland pipe_ctx->stream_enc, 10884562236bSHarry Wentland &stream->public.timing, 10894562236bSHarry Wentland (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? 10904562236bSHarry Wentland true : false); 10914562236bSHarry Wentland 10924562236bSHarry Wentland if (!pipe_ctx_old->stream) { 10934562236bSHarry Wentland core_link_enable_stream(pipe_ctx); 10944562236bSHarry Wentland 1095b3c64dffSCharlene Liu resource_build_info_frame(pipe_ctx); 1096b3c64dffSCharlene Liu dce110_update_info_frame(pipe_ctx); 10974562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10984562236bSHarry Wentland dce110_unblank_stream(pipe_ctx, 10994562236bSHarry Wentland &stream->sink->link->public.cur_link_settings); 11004562236bSHarry Wentland } 11014562236bSHarry Wentland 11024562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 11034562236bSHarry Wentland /* program_scaler and allocate_mem_input are not new asic */ 11044562236bSHarry Wentland if (!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data, 11054562236bSHarry Wentland &pipe_ctx->scl_data, 11064562236bSHarry Wentland sizeof(struct scaler_data)) != 0) 11074562236bSHarry Wentland program_scaler(dc, pipe_ctx); 11084562236bSHarry Wentland 11094562236bSHarry Wentland /* mst support - use total stream count */ 11104562236bSHarry Wentland pipe_ctx->mi->funcs->allocate_mem_input( 11114562236bSHarry Wentland pipe_ctx->mi, 11124562236bSHarry Wentland stream->public.timing.h_total, 11134562236bSHarry Wentland stream->public.timing.v_total, 11144562236bSHarry Wentland stream->public.timing.pix_clk_khz, 1115ab2541b6SAric Cyr context->stream_count); 11164562236bSHarry Wentland 11174562236bSHarry Wentland return DC_OK; 11184562236bSHarry Wentland } 11194562236bSHarry Wentland 11204562236bSHarry Wentland /******************************************************************************/ 11214562236bSHarry Wentland 11224562236bSHarry Wentland static void power_down_encoders(struct core_dc *dc) 11234562236bSHarry Wentland { 11244562236bSHarry Wentland int i; 11254562236bSHarry Wentland 11264562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 11274562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 11284562236bSHarry Wentland dc->links[i]->link_enc, SIGNAL_TYPE_NONE); 11294562236bSHarry Wentland } 11304562236bSHarry Wentland } 11314562236bSHarry Wentland 11324562236bSHarry Wentland static void power_down_controllers(struct core_dc *dc) 11334562236bSHarry Wentland { 11344562236bSHarry Wentland int i; 11354562236bSHarry Wentland 11364562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 11374562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 11384562236bSHarry Wentland dc->res_pool->timing_generators[i]); 11394562236bSHarry Wentland } 11404562236bSHarry Wentland } 11414562236bSHarry Wentland 11424562236bSHarry Wentland static void power_down_clock_sources(struct core_dc *dc) 11434562236bSHarry Wentland { 11444562236bSHarry Wentland int i; 11454562236bSHarry Wentland 11464562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 11474562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 11484562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 11494562236bSHarry Wentland 11504562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 11514562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 11524562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 11534562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 11544562236bSHarry Wentland } 11554562236bSHarry Wentland } 11564562236bSHarry Wentland 11574562236bSHarry Wentland static void power_down_all_hw_blocks(struct core_dc *dc) 11584562236bSHarry Wentland { 11594562236bSHarry Wentland power_down_encoders(dc); 11604562236bSHarry Wentland 11614562236bSHarry Wentland power_down_controllers(dc); 11624562236bSHarry Wentland 11634562236bSHarry Wentland power_down_clock_sources(dc); 11644562236bSHarry Wentland } 11654562236bSHarry Wentland 11664562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 11674562236bSHarry Wentland struct core_dc *dc) 11684562236bSHarry Wentland { 11694562236bSHarry Wentland int i; 11704562236bSHarry Wentland struct timing_generator *tg; 11714562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 11724562236bSHarry Wentland 11734562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 11744562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 11754562236bSHarry Wentland 11764562236bSHarry Wentland tg->funcs->disable_vga(tg); 11774562236bSHarry Wentland 11784562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 11794562236bSHarry Wentland * powergating. */ 11804562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 11814562236bSHarry Wentland true); 11824562236bSHarry Wentland 11834562236bSHarry Wentland dc->hwss.power_down_front_end( 11844562236bSHarry Wentland dc, &dc->current_context->res_ctx.pipe_ctx[i]); 11854562236bSHarry Wentland } 11864562236bSHarry Wentland } 11874562236bSHarry Wentland 11884562236bSHarry Wentland /** 11894562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 11904562236bSHarry Wentland * 1. Power down all DC HW blocks 11914562236bSHarry Wentland * 2. Disable VGA engine on all controllers 11924562236bSHarry Wentland * 3. Enable power gating for controller 11934562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 11944562236bSHarry Wentland */ 11954562236bSHarry Wentland void dce110_enable_accelerated_mode(struct core_dc *dc) 11964562236bSHarry Wentland { 11974562236bSHarry Wentland power_down_all_hw_blocks(dc); 11984562236bSHarry Wentland 11994562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 12004562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 12014562236bSHarry Wentland } 12024562236bSHarry Wentland 12034562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 12044562236bSHarry Wentland struct bw_fixed blackout_duration, 12054562236bSHarry Wentland const struct core_stream *stream) 12064562236bSHarry Wentland { 12074562236bSHarry Wentland uint32_t total_dest_line_time_ns; 12084562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 12094562236bSHarry Wentland 12104562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 12114562236bSHarry Wentland 12124562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 12134562236bSHarry Wentland stream->public.timing.h_total / 12144562236bSHarry Wentland stream->public.timing.pix_clk_khz + 12154562236bSHarry Wentland pstate_blackout_duration_ns; 12164562236bSHarry Wentland 12174562236bSHarry Wentland return total_dest_line_time_ns; 12184562236bSHarry Wentland } 12194562236bSHarry Wentland 12204562236bSHarry Wentland void dce110_set_displaymarks( 12214562236bSHarry Wentland const struct core_dc *dc, 12224562236bSHarry Wentland struct validate_context *context) 12234562236bSHarry Wentland { 12244562236bSHarry Wentland uint8_t i, num_pipes; 12254562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 12264562236bSHarry Wentland 12274562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 12284562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 12294562236bSHarry Wentland uint32_t total_dest_line_time_ns; 12304562236bSHarry Wentland 12314562236bSHarry Wentland if (pipe_ctx->stream == NULL) 12324562236bSHarry Wentland continue; 12334562236bSHarry Wentland 12344562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 12354562236bSHarry Wentland dc->bw_vbios.blackout_duration, pipe_ctx->stream); 12364562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_display_marks( 12374562236bSHarry Wentland pipe_ctx->mi, 12384562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[num_pipes], 12394562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[num_pipes], 12404562236bSHarry Wentland context->bw_results.urgent_wm_ns[num_pipes], 12414562236bSHarry Wentland total_dest_line_time_ns); 12424562236bSHarry Wentland if (i == underlay_idx) { 12434562236bSHarry Wentland num_pipes++; 12444562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( 12454562236bSHarry Wentland pipe_ctx->mi, 12464562236bSHarry Wentland context->bw_results.nbp_state_change_wm_ns[num_pipes], 12474562236bSHarry Wentland context->bw_results.stutter_exit_wm_ns[num_pipes], 12484562236bSHarry Wentland context->bw_results.urgent_wm_ns[num_pipes], 12494562236bSHarry Wentland total_dest_line_time_ns); 12504562236bSHarry Wentland } 12514562236bSHarry Wentland num_pipes++; 12524562236bSHarry Wentland } 12534562236bSHarry Wentland } 12544562236bSHarry Wentland 12554562236bSHarry Wentland static void set_safe_displaymarks(struct resource_context *res_ctx) 12564562236bSHarry Wentland { 12574562236bSHarry Wentland int i; 12584562236bSHarry Wentland int underlay_idx = res_ctx->pool->underlay_pipe_index; 12594562236bSHarry Wentland struct bw_watermarks max_marks = { 12604562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 12614562236bSHarry Wentland struct bw_watermarks nbp_marks = { 12624562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 12634562236bSHarry Wentland 12644562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 12654562236bSHarry Wentland if (res_ctx->pipe_ctx[i].stream == NULL) 12664562236bSHarry Wentland continue; 12674562236bSHarry Wentland 12684562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks( 12694562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 12704562236bSHarry Wentland nbp_marks, 12714562236bSHarry Wentland max_marks, 12724562236bSHarry Wentland max_marks, 12734562236bSHarry Wentland MAX_WATERMARK); 12744562236bSHarry Wentland if (i == underlay_idx) 12754562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks( 12764562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 12774562236bSHarry Wentland nbp_marks, 12784562236bSHarry Wentland max_marks, 12794562236bSHarry Wentland max_marks, 12804562236bSHarry Wentland MAX_WATERMARK); 12814562236bSHarry Wentland } 12824562236bSHarry Wentland } 12834562236bSHarry Wentland 12844562236bSHarry Wentland static void switch_dp_clock_sources( 12854562236bSHarry Wentland const struct core_dc *dc, 12864562236bSHarry Wentland struct resource_context *res_ctx) 12874562236bSHarry Wentland { 12884562236bSHarry Wentland uint8_t i; 12894562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 12904562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 12914562236bSHarry Wentland 12924562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 12934562236bSHarry Wentland continue; 12944562236bSHarry Wentland 12954562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 12964562236bSHarry Wentland struct clock_source *clk_src = 12974562236bSHarry Wentland resource_find_used_clk_src_for_sharing( 12984562236bSHarry Wentland res_ctx, pipe_ctx); 12994562236bSHarry Wentland 13004562236bSHarry Wentland if (clk_src && 13014562236bSHarry Wentland clk_src != pipe_ctx->clock_source) { 13024562236bSHarry Wentland resource_unreference_clock_source( 13038c737fccSYongqiang Sun res_ctx, &pipe_ctx->clock_source); 13044562236bSHarry Wentland pipe_ctx->clock_source = clk_src; 13054562236bSHarry Wentland resource_reference_clock_source(res_ctx, clk_src); 13064562236bSHarry Wentland 13074562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i); 13084562236bSHarry Wentland } 13094562236bSHarry Wentland } 13104562236bSHarry Wentland } 13114562236bSHarry Wentland } 13124562236bSHarry Wentland 13134562236bSHarry Wentland /******************************************************************************* 13144562236bSHarry Wentland * Public functions 13154562236bSHarry Wentland ******************************************************************************/ 13164562236bSHarry Wentland 13174562236bSHarry Wentland static void reset_single_pipe_hw_ctx( 13184562236bSHarry Wentland const struct core_dc *dc, 13194562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 13204562236bSHarry Wentland struct validate_context *context) 13214562236bSHarry Wentland { 13224562236bSHarry Wentland core_link_disable_stream(pipe_ctx); 13234b5e7d62SHersen Wu pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 13244b5e7d62SHersen Wu if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) { 13254562236bSHarry Wentland dm_error("DC: failed to blank crtc!\n"); 13264562236bSHarry Wentland BREAK_TO_DEBUGGER(); 13274562236bSHarry Wentland } 13284562236bSHarry Wentland pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); 13294562236bSHarry Wentland pipe_ctx->mi->funcs->free_mem_input( 1330ab2541b6SAric Cyr pipe_ctx->mi, context->stream_count); 13314562236bSHarry Wentland resource_unreference_clock_source( 13328c737fccSYongqiang Sun &context->res_ctx, &pipe_ctx->clock_source); 13334562236bSHarry Wentland 13344562236bSHarry Wentland dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx); 13354562236bSHarry Wentland 13364562236bSHarry Wentland pipe_ctx->stream = NULL; 13374562236bSHarry Wentland } 13384562236bSHarry Wentland 13394562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 13404562236bSHarry Wentland int num_pipes, int vmin, int vmax) 13414562236bSHarry Wentland { 13424562236bSHarry Wentland int i = 0; 13434562236bSHarry Wentland struct drr_params params = {0}; 13444562236bSHarry Wentland 13454562236bSHarry Wentland params.vertical_total_max = vmax; 13464562236bSHarry Wentland params.vertical_total_min = vmin; 13474562236bSHarry Wentland 13484562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 13494562236bSHarry Wentland * some GSL stuff 13504562236bSHarry Wentland */ 13514562236bSHarry Wentland 13524562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 13534562236bSHarry Wentland pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, ¶ms); 13544562236bSHarry Wentland } 13554562236bSHarry Wentland } 13564562236bSHarry Wentland 13574562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 13584562236bSHarry Wentland int num_pipes, int value) 13594562236bSHarry Wentland { 13604562236bSHarry Wentland unsigned int i; 13614562236bSHarry Wentland 13624562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 13634562236bSHarry Wentland pipe_ctx[i]->tg->funcs-> 13644562236bSHarry Wentland set_static_screen_control(pipe_ctx[i]->tg, value); 13654562236bSHarry Wentland } 13664562236bSHarry Wentland 13674562236bSHarry Wentland /* unit: in_khz before mode set, get pixel clock from context. ASIC register 13684562236bSHarry Wentland * may not be programmed yet. 13694562236bSHarry Wentland * TODO: after mode set, pre_mode_set = false, 13704562236bSHarry Wentland * may read PLL register to get pixel clock 13714562236bSHarry Wentland */ 13724562236bSHarry Wentland static uint32_t get_max_pixel_clock_for_all_paths( 13734562236bSHarry Wentland struct core_dc *dc, 13744562236bSHarry Wentland struct validate_context *context, 13754562236bSHarry Wentland bool pre_mode_set) 13764562236bSHarry Wentland { 13774562236bSHarry Wentland uint32_t max_pix_clk = 0; 13784562236bSHarry Wentland int i; 13794562236bSHarry Wentland 13804562236bSHarry Wentland if (!pre_mode_set) { 13814562236bSHarry Wentland /* TODO: read ASIC register to get pixel clock */ 13824562236bSHarry Wentland ASSERT(0); 13834562236bSHarry Wentland } 13844562236bSHarry Wentland 13854562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 13864562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 13874562236bSHarry Wentland 13884562236bSHarry Wentland if (pipe_ctx->stream == NULL) 13894562236bSHarry Wentland continue; 13904562236bSHarry Wentland 13914562236bSHarry Wentland /* do not check under lay */ 13924562236bSHarry Wentland if (pipe_ctx->top_pipe) 13934562236bSHarry Wentland continue; 13944562236bSHarry Wentland 13954562236bSHarry Wentland if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk) 13964562236bSHarry Wentland max_pix_clk = 13974562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 13984562236bSHarry Wentland } 13994562236bSHarry Wentland 14004562236bSHarry Wentland if (max_pix_clk == 0) 14014562236bSHarry Wentland ASSERT(0); 14024562236bSHarry Wentland 14034562236bSHarry Wentland return max_pix_clk; 14044562236bSHarry Wentland } 14054562236bSHarry Wentland 14062c8ad2d5SAlex Deucher /* Find clock state based on clock requested. if clock value is 0, simply 14074562236bSHarry Wentland * set clock state as requested without finding clock state by clock value 14082c8ad2d5SAlex Deucher *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock. 14092c8ad2d5SAlex Deucher * 14102c8ad2d5SAlex Deucher * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value 14112c8ad2d5SAlex Deucher * etc support for dcn1.0 14124562236bSHarry Wentland */ 14134562236bSHarry Wentland static void apply_min_clocks( 14144562236bSHarry Wentland struct core_dc *dc, 14154562236bSHarry Wentland struct validate_context *context, 1416e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state *clocks_state, 14174562236bSHarry Wentland bool pre_mode_set) 14184562236bSHarry Wentland { 14194562236bSHarry Wentland struct state_dependent_clocks req_clocks = {0}; 14204562236bSHarry Wentland struct pipe_ctx *pipe_ctx; 14214562236bSHarry Wentland int i; 14224562236bSHarry Wentland 14234562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 14244562236bSHarry Wentland pipe_ctx = &context->res_ctx.pipe_ctx[i]; 14254562236bSHarry Wentland if (pipe_ctx->dis_clk != NULL) 14264562236bSHarry Wentland break; 14274562236bSHarry Wentland } 14284562236bSHarry Wentland 14294562236bSHarry Wentland if (!pre_mode_set) { 14304562236bSHarry Wentland /* set clock_state without verification */ 14315d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) { 14325d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 14335d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, *clocks_state); 14344562236bSHarry Wentland return; 14355d6d185fSDmytro Laktyushkin } 14364562236bSHarry Wentland 14372c8ad2d5SAlex Deucher /* TODO: This is incorrect. Figure out how to fix. */ 14382c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14392c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14402c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 14412c8ad2d5SAlex Deucher pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz, 14422c8ad2d5SAlex Deucher pre_mode_set, 14432c8ad2d5SAlex Deucher false); 14442c8ad2d5SAlex Deucher 14452c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14462c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14472c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 14482c8ad2d5SAlex Deucher pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz, 14492c8ad2d5SAlex Deucher pre_mode_set, 14502c8ad2d5SAlex Deucher false); 14512c8ad2d5SAlex Deucher 14522c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14532c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14542c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 14552c8ad2d5SAlex Deucher pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, 14562c8ad2d5SAlex Deucher pre_mode_set, 14572c8ad2d5SAlex Deucher false); 14582c8ad2d5SAlex Deucher return; 14594562236bSHarry Wentland } 14604562236bSHarry Wentland 14614562236bSHarry Wentland /* get the required state based on state dependent clocks: 14624562236bSHarry Wentland * display clock and pixel clock 14634562236bSHarry Wentland */ 1464a99240d5SDmytro Laktyushkin req_clocks.display_clk_khz = context->dispclk_khz; 14654562236bSHarry Wentland 14664562236bSHarry Wentland req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( 14674562236bSHarry Wentland dc, context, true); 14684562236bSHarry Wentland 14695d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) { 14705d6d185fSDmytro Laktyushkin *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state( 14715d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, &req_clocks); 14725d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 14734562236bSHarry Wentland pipe_ctx->dis_clk, *clocks_state); 14744562236bSHarry Wentland } else { 14752c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14762c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14772c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 14782c8ad2d5SAlex Deucher req_clocks.display_clk_khz, 14792c8ad2d5SAlex Deucher pre_mode_set, 14802c8ad2d5SAlex Deucher false); 14812c8ad2d5SAlex Deucher 14822c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14832c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14842c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 14852c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 14862c8ad2d5SAlex Deucher pre_mode_set, 14872c8ad2d5SAlex Deucher false); 14882c8ad2d5SAlex Deucher 14892c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14902c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14912c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 14922c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 14932c8ad2d5SAlex Deucher pre_mode_set, 14942c8ad2d5SAlex Deucher false); 14954562236bSHarry Wentland } 14964562236bSHarry Wentland } 14974562236bSHarry Wentland 14984562236bSHarry Wentland static enum dc_status apply_ctx_to_hw_fpga( 14994562236bSHarry Wentland struct core_dc *dc, 15004562236bSHarry Wentland struct validate_context *context) 15014562236bSHarry Wentland { 15024562236bSHarry Wentland enum dc_status status = DC_ERROR_UNEXPECTED; 15034562236bSHarry Wentland int i; 15044562236bSHarry Wentland 15054562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 15064562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15074562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15084562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15094562236bSHarry Wentland 15104562236bSHarry Wentland if (pipe_ctx->stream == NULL) 15114562236bSHarry Wentland continue; 15124562236bSHarry Wentland 15134562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) 15144562236bSHarry Wentland continue; 15154562236bSHarry Wentland 15164562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 15174562236bSHarry Wentland pipe_ctx, 15184562236bSHarry Wentland context, 15194562236bSHarry Wentland dc); 15204562236bSHarry Wentland 15214562236bSHarry Wentland if (status != DC_OK) 15224562236bSHarry Wentland return status; 15234562236bSHarry Wentland } 15244562236bSHarry Wentland 15254562236bSHarry Wentland return DC_OK; 15264562236bSHarry Wentland } 15274562236bSHarry Wentland 15284562236bSHarry Wentland static void reset_hw_ctx_wrap( 15294562236bSHarry Wentland struct core_dc *dc, 15304562236bSHarry Wentland struct validate_context *context) 15314562236bSHarry Wentland { 15324562236bSHarry Wentland int i; 15334562236bSHarry Wentland 15344562236bSHarry Wentland /* Reset old context */ 15354562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 15364562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 15374562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15384562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15394562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15404562236bSHarry Wentland 15414562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 15424562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 15434562236bSHarry Wentland * PHY when not already disabled. 15444562236bSHarry Wentland */ 15454562236bSHarry Wentland 15464562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 15474562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 15484562236bSHarry Wentland continue; 15494562236bSHarry Wentland 15504562236bSHarry Wentland if (!pipe_ctx->stream || 15514562236bSHarry Wentland pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 15524562236bSHarry Wentland reset_single_pipe_hw_ctx( 15534562236bSHarry Wentland dc, pipe_ctx_old, dc->current_context); 15544562236bSHarry Wentland } 15554562236bSHarry Wentland } 15564562236bSHarry Wentland 1557cf437593SDmytro Laktyushkin 15584562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 15594562236bSHarry Wentland struct core_dc *dc, 15604562236bSHarry Wentland struct validate_context *context) 15614562236bSHarry Wentland { 15624562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 15634562236bSHarry Wentland enum dc_status status; 15644562236bSHarry Wentland int i; 1565e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID; 15664562236bSHarry Wentland 15674562236bSHarry Wentland /* Reset old context */ 15684562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 15694562236bSHarry Wentland dc->hwss.reset_hw_ctx_wrap(dc, context); 15704562236bSHarry Wentland 15714562236bSHarry Wentland /* Skip applying if no targets */ 1572ab2541b6SAric Cyr if (context->stream_count <= 0) 15734562236bSHarry Wentland return DC_OK; 15744562236bSHarry Wentland 15754562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 15764562236bSHarry Wentland apply_ctx_to_hw_fpga(dc, context); 15774562236bSHarry Wentland return DC_OK; 15784562236bSHarry Wentland } 15794562236bSHarry Wentland 15804562236bSHarry Wentland /* Apply new context */ 15814562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 15824562236bSHarry Wentland 15834562236bSHarry Wentland /* below is for real asic only */ 15844562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 15854562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15864562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15874562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15884562236bSHarry Wentland 15894562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 15904562236bSHarry Wentland continue; 15914562236bSHarry Wentland 15924562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 15934562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 15944562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 15954562236bSHarry Wentland pipe_ctx->clock_source, i); 15964562236bSHarry Wentland continue; 15974562236bSHarry Wentland } 15984562236bSHarry Wentland 15994562236bSHarry Wentland dc->hwss.enable_display_power_gating( 16004562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 16014562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 16024562236bSHarry Wentland } 16034562236bSHarry Wentland 16044562236bSHarry Wentland set_safe_displaymarks(&context->res_ctx); 16054562236bSHarry Wentland /*TODO: when pplib works*/ 16064562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, true); 16074562236bSHarry Wentland 1608a99240d5SDmytro Laktyushkin if (context->dispclk_khz 16091ce71fcdSCharlene Liu > dc->current_context->dispclk_khz) { 16101a687574SDmytro Laktyushkin context->res_ctx.pool->display_clock->funcs->set_clock( 16111a687574SDmytro Laktyushkin context->res_ctx.pool->display_clock, 1612a99240d5SDmytro Laktyushkin context->dispclk_khz * 115 / 100); 16131ce71fcdSCharlene Liu } 1614ab8812a3SHersen Wu /* program audio wall clock. use HDMI as clock source if HDMI 1615ab8812a3SHersen Wu * audio active. Otherwise, use DP as clock source 1616ab8812a3SHersen Wu * first, loop to find any HDMI audio, if not, loop find DP audio 1617ab8812a3SHersen Wu */ 16184562236bSHarry Wentland /* Setup audio rate clock source */ 16194562236bSHarry Wentland /* Issue: 16204562236bSHarry Wentland * Audio lag happened on DP monitor when unplug a HDMI monitor 16214562236bSHarry Wentland * 16224562236bSHarry Wentland * Cause: 16234562236bSHarry Wentland * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 16244562236bSHarry Wentland * is set to either dto0 or dto1, audio should work fine. 16254562236bSHarry Wentland * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 16264562236bSHarry Wentland * set to dto0 will cause audio lag. 16274562236bSHarry Wentland * 16284562236bSHarry Wentland * Solution: 16294562236bSHarry Wentland * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 16304562236bSHarry Wentland * find first available pipe with audio, setup audio wall DTO per topology 16314562236bSHarry Wentland * instead of per pipe. 16324562236bSHarry Wentland */ 1633ab8812a3SHersen Wu for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 1634ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1635ab8812a3SHersen Wu 1636ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1637ab8812a3SHersen Wu continue; 1638ab8812a3SHersen Wu 1639ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1640ab8812a3SHersen Wu continue; 1641ab8812a3SHersen Wu 1642ab8812a3SHersen Wu if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 1643ab8812a3SHersen Wu continue; 1644ab8812a3SHersen Wu 1645ab8812a3SHersen Wu if (pipe_ctx->audio != NULL) { 1646ab8812a3SHersen Wu struct audio_output audio_output; 1647ab8812a3SHersen Wu 1648ab8812a3SHersen Wu build_audio_output(pipe_ctx, &audio_output); 1649ab8812a3SHersen Wu 1650ab8812a3SHersen Wu pipe_ctx->audio->funcs->wall_dto_setup( 1651ab8812a3SHersen Wu pipe_ctx->audio, 1652ab8812a3SHersen Wu pipe_ctx->stream->signal, 1653ab8812a3SHersen Wu &audio_output.crtc_info, 1654ab8812a3SHersen Wu &audio_output.pll_info); 1655ab8812a3SHersen Wu break; 1656ab8812a3SHersen Wu } 1657ab8812a3SHersen Wu } 1658ab8812a3SHersen Wu 1659ab8812a3SHersen Wu /* no HDMI audio is found, try DP audio */ 1660ab8812a3SHersen Wu if (i == context->res_ctx.pool->pipe_count) { 1661ab8812a3SHersen Wu for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 1662ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1663ab8812a3SHersen Wu 1664ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1665ab8812a3SHersen Wu continue; 1666ab8812a3SHersen Wu 1667ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1668ab8812a3SHersen Wu continue; 1669ab8812a3SHersen Wu 1670ab8812a3SHersen Wu if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 1671ab8812a3SHersen Wu continue; 1672ab8812a3SHersen Wu 1673ab8812a3SHersen Wu if (pipe_ctx->audio != NULL) { 1674ab8812a3SHersen Wu struct audio_output audio_output; 1675ab8812a3SHersen Wu 1676ab8812a3SHersen Wu build_audio_output(pipe_ctx, &audio_output); 1677ab8812a3SHersen Wu 1678ab8812a3SHersen Wu pipe_ctx->audio->funcs->wall_dto_setup( 1679ab8812a3SHersen Wu pipe_ctx->audio, 1680ab8812a3SHersen Wu pipe_ctx->stream->signal, 1681ab8812a3SHersen Wu &audio_output.crtc_info, 1682ab8812a3SHersen Wu &audio_output.pll_info); 1683ab8812a3SHersen Wu break; 1684ab8812a3SHersen Wu } 1685ab8812a3SHersen Wu } 1686ab8812a3SHersen Wu } 1687ab8812a3SHersen Wu 1688ab8812a3SHersen Wu for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 1689ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 1690ab8812a3SHersen Wu &dc->current_context->res_ctx.pipe_ctx[i]; 1691ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1692ab8812a3SHersen Wu 1693ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1694ab8812a3SHersen Wu continue; 1695ab8812a3SHersen Wu 1696ab8812a3SHersen Wu if (pipe_ctx->stream == pipe_ctx_old->stream) 1697ab8812a3SHersen Wu continue; 1698ab8812a3SHersen Wu 1699313bf4ffSYongqiang Sun if (pipe_ctx->stream && pipe_ctx_old->stream 1700313bf4ffSYongqiang Sun && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 1701313bf4ffSYongqiang Sun continue; 1702313bf4ffSYongqiang Sun 1703ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1704ab8812a3SHersen Wu continue; 1705ab8812a3SHersen Wu 1706ab8812a3SHersen Wu if (context->res_ctx.pipe_ctx[i].audio != NULL) { 1707ab8812a3SHersen Wu 17084562236bSHarry Wentland struct audio_output audio_output; 17094562236bSHarry Wentland 17104562236bSHarry Wentland build_audio_output(pipe_ctx, &audio_output); 17114562236bSHarry Wentland 17124562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 17134562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_setup( 17144562236bSHarry Wentland pipe_ctx->stream_enc, 17154562236bSHarry Wentland pipe_ctx->audio->inst, 17164562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 17174562236bSHarry Wentland else 17184562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_setup( 17194562236bSHarry Wentland pipe_ctx->stream_enc, 17204562236bSHarry Wentland pipe_ctx->audio->inst, 17214562236bSHarry Wentland &pipe_ctx->stream->public.audio_info, 17224562236bSHarry Wentland &audio_output.crtc_info); 17234562236bSHarry Wentland 17244562236bSHarry Wentland pipe_ctx->audio->funcs->az_configure( 17254562236bSHarry Wentland pipe_ctx->audio, 17264562236bSHarry Wentland pipe_ctx->stream->signal, 17274562236bSHarry Wentland &audio_output.crtc_info, 17284562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 17294562236bSHarry Wentland } 17304562236bSHarry Wentland 17314562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 17324562236bSHarry Wentland pipe_ctx, 17334562236bSHarry Wentland context, 17344562236bSHarry Wentland dc); 17354562236bSHarry Wentland 173618f7a1e4SYongqiang Sun if (dc->hwss.power_on_front_end) 173718f7a1e4SYongqiang Sun dc->hwss.power_on_front_end(dc, pipe_ctx, context); 173818f7a1e4SYongqiang Sun 17394562236bSHarry Wentland if (DC_OK != status) 17404562236bSHarry Wentland return status; 17414562236bSHarry Wentland } 17424562236bSHarry Wentland 1743cf437593SDmytro Laktyushkin dc->hwss.set_bandwidth(dc, context, true); 17444562236bSHarry Wentland 17454562236bSHarry Wentland /* to save power */ 17464562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, false); 17474562236bSHarry Wentland 17484562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, false); 17494562236bSHarry Wentland 17504562236bSHarry Wentland switch_dp_clock_sources(dc, &context->res_ctx); 17514562236bSHarry Wentland 1752cf437593SDmytro Laktyushkin 17534562236bSHarry Wentland return DC_OK; 17544562236bSHarry Wentland } 17554562236bSHarry Wentland 17564562236bSHarry Wentland /******************************************************************************* 17574562236bSHarry Wentland * Front End programming 17584562236bSHarry Wentland ******************************************************************************/ 17594562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 17604562236bSHarry Wentland { 17614562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 17624562236bSHarry Wentland 17634562236bSHarry Wentland default_adjust.force_hw_default = false; 17644562236bSHarry Wentland if (pipe_ctx->surface == NULL) 17654562236bSHarry Wentland default_adjust.in_color_space = COLOR_SPACE_SRGB; 17664562236bSHarry Wentland else 17674562236bSHarry Wentland default_adjust.in_color_space = 17684562236bSHarry Wentland pipe_ctx->surface->public.color_space; 17694562236bSHarry Wentland if (pipe_ctx->stream == NULL) 17704562236bSHarry Wentland default_adjust.out_color_space = COLOR_SPACE_SRGB; 17714562236bSHarry Wentland else 17724562236bSHarry Wentland default_adjust.out_color_space = 17734562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 17744562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 17754562236bSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; 17764562236bSHarry Wentland 17774562236bSHarry Wentland /* display color depth */ 17784562236bSHarry Wentland default_adjust.color_depth = 17794562236bSHarry Wentland pipe_ctx->stream->public.timing.display_color_depth; 17804562236bSHarry Wentland 17814562236bSHarry Wentland /* Lb color depth */ 17824562236bSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; 17834562236bSHarry Wentland 17844562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_default( 17854562236bSHarry Wentland pipe_ctx->opp, &default_adjust); 17864562236bSHarry Wentland } 17874562236bSHarry Wentland 1788b06b7680SLeon Elazar 1789b06b7680SLeon Elazar /******************************************************************************* 1790b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 1791b06b7680SLeon Elazar * Blender + CRTC 1792b06b7680SLeon Elazar * 1793b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 1794b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 1795b06b7680SLeon Elazar * 1796b06b7680SLeon Elazar * |----------------------------------------------- | 1797b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 1798b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 1799b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 1800b06b7680SLeon Elazar * |------------------------------------------------| 1801b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 1802b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 1803b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 1804b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 1805b06b7680SLeon Elazar * -------------------------------------------------| 1806b06b7680SLeon Elazar * 1807b06b7680SLeon Elazar ******************************************************************************/ 1808b06b7680SLeon Elazar static void program_surface_visibility(const struct core_dc *dc, 18094562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 18104562236bSHarry Wentland { 18114562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 1812b06b7680SLeon Elazar bool blank_target = false; 18134562236bSHarry Wentland 18144562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 1815b06b7680SLeon Elazar 1816b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 1817b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 1818b06b7680SLeon Elazar 18194562236bSHarry Wentland if (pipe_ctx->bottom_pipe->surface->public.visible) { 18204562236bSHarry Wentland if (pipe_ctx->surface->public.visible) 18214562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 18224562236bSHarry Wentland else 18234562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 1824b06b7680SLeon Elazar 1825b06b7680SLeon Elazar } else if (!pipe_ctx->surface->public.visible) 1826b06b7680SLeon Elazar blank_target = true; 1827b06b7680SLeon Elazar 1828b06b7680SLeon Elazar } else if (!pipe_ctx->surface->public.visible) 1829b06b7680SLeon Elazar blank_target = true; 1830b06b7680SLeon Elazar 18314562236bSHarry Wentland dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); 1832b06b7680SLeon Elazar pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target); 1833b06b7680SLeon Elazar 18344562236bSHarry Wentland } 18354562236bSHarry Wentland 18364562236bSHarry Wentland /** 18374562236bSHarry Wentland * TODO REMOVE, USE UPDATE INSTEAD 18384562236bSHarry Wentland */ 18394562236bSHarry Wentland static void set_plane_config( 18404562236bSHarry Wentland const struct core_dc *dc, 18414562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 18424562236bSHarry Wentland struct resource_context *res_ctx) 18434562236bSHarry Wentland { 18444562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 18454562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 18464562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 18474562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 18484562236bSHarry Wentland unsigned int i; 18494562236bSHarry Wentland 18504562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 18514562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 18524562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 18534562236bSHarry Wentland 18544562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 18554562236bSHarry Wentland 18564562236bSHarry Wentland set_default_colors(pipe_ctx); 18574562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 18584562236bSHarry Wentland == true) { 18594562236bSHarry Wentland tbl_entry.color_space = 18604562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 18614562236bSHarry Wentland 18624562236bSHarry Wentland for (i = 0; i < 12; i++) 18634562236bSHarry Wentland tbl_entry.regval[i] = 18644562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 18654562236bSHarry Wentland 18664562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 18674562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 18684562236bSHarry Wentland } 18694562236bSHarry Wentland 18704562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 18714562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 18724562236bSHarry Wentland adjust.temperature_matrix[0] = 18734562236bSHarry Wentland pipe_ctx->stream-> 18744562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 18754562236bSHarry Wentland adjust.temperature_matrix[1] = 18764562236bSHarry Wentland pipe_ctx->stream-> 18774562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 18784562236bSHarry Wentland adjust.temperature_matrix[2] = 18794562236bSHarry Wentland pipe_ctx->stream-> 18804562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 18814562236bSHarry Wentland adjust.temperature_matrix[3] = 18824562236bSHarry Wentland pipe_ctx->stream-> 18834562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 18844562236bSHarry Wentland adjust.temperature_matrix[4] = 18854562236bSHarry Wentland pipe_ctx->stream-> 18864562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 18874562236bSHarry Wentland adjust.temperature_matrix[5] = 18884562236bSHarry Wentland pipe_ctx->stream-> 18894562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 18904562236bSHarry Wentland adjust.temperature_matrix[6] = 18914562236bSHarry Wentland pipe_ctx->stream-> 18924562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 18934562236bSHarry Wentland adjust.temperature_matrix[7] = 18944562236bSHarry Wentland pipe_ctx->stream-> 18954562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 18964562236bSHarry Wentland adjust.temperature_matrix[8] = 18974562236bSHarry Wentland pipe_ctx->stream-> 18984562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 18994562236bSHarry Wentland } 19004562236bSHarry Wentland 19014562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 19024562236bSHarry Wentland 19034562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 19044562236bSHarry Wentland program_scaler(dc, pipe_ctx); 19054562236bSHarry Wentland 1906b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 19074562236bSHarry Wentland 19084562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 19094562236bSHarry Wentland mi, 19104562236bSHarry Wentland surface->public.format, 19114562236bSHarry Wentland &surface->public.tiling_info, 19124562236bSHarry Wentland &surface->public.plane_size, 19134562236bSHarry Wentland surface->public.rotation, 19144562236bSHarry Wentland NULL, 1915624d7c47SYongqiang Sun false, 1916624d7c47SYongqiang Sun pipe_ctx->surface->public.visible); 19174562236bSHarry Wentland 19184562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 19194562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 19204562236bSHarry Wentland pipe_ctx->mi, 19214562236bSHarry Wentland surface->public.format, 19224562236bSHarry Wentland &surface->public.tiling_info, 19234562236bSHarry Wentland surface->public.rotation); 19244562236bSHarry Wentland } 19254562236bSHarry Wentland 19264562236bSHarry Wentland static void update_plane_addr(const struct core_dc *dc, 19274562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 19284562236bSHarry Wentland { 19294562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 19304562236bSHarry Wentland 19314562236bSHarry Wentland if (surface == NULL) 19324562236bSHarry Wentland return; 19334562236bSHarry Wentland 19344562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( 19354562236bSHarry Wentland pipe_ctx->mi, 19364562236bSHarry Wentland &surface->public.address, 19374562236bSHarry Wentland surface->public.flip_immediate); 19384562236bSHarry Wentland 19394562236bSHarry Wentland surface->status.requested_address = surface->public.address; 19404562236bSHarry Wentland } 19414562236bSHarry Wentland 19424562236bSHarry Wentland void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 19434562236bSHarry Wentland { 19444562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 19454562236bSHarry Wentland 19464562236bSHarry Wentland if (surface == NULL) 19474562236bSHarry Wentland return; 19484562236bSHarry Wentland 19494562236bSHarry Wentland surface->status.is_flip_pending = 19504562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_is_flip_pending( 19514562236bSHarry Wentland pipe_ctx->mi); 19524562236bSHarry Wentland 19534562236bSHarry Wentland if (surface->status.is_flip_pending && !surface->public.visible) 19544562236bSHarry Wentland pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; 19554562236bSHarry Wentland 19564562236bSHarry Wentland surface->status.current_address = pipe_ctx->mi->current_address; 19574562236bSHarry Wentland } 19584562236bSHarry Wentland 19594562236bSHarry Wentland void dce110_power_down(struct core_dc *dc) 19604562236bSHarry Wentland { 19614562236bSHarry Wentland power_down_all_hw_blocks(dc); 19624562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 19634562236bSHarry Wentland } 19644562236bSHarry Wentland 19654562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 19664562236bSHarry Wentland struct dc_context *dc_ctx, 19674562236bSHarry Wentland struct timing_generator *tg) 19684562236bSHarry Wentland { 19694562236bSHarry Wentland bool rc = false; 19704562236bSHarry Wentland 19714562236bSHarry Wentland /* To avoid endless loop we wait at most 19724562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 19734562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 19744562236bSHarry Wentland uint32_t i; 19754562236bSHarry Wentland 19764562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 19774562236bSHarry Wentland 19784562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 19794562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 19804562236bSHarry Wentland break; 19814562236bSHarry Wentland } 19824562236bSHarry Wentland 19834562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 19844562236bSHarry Wentland rc = true; 19854562236bSHarry Wentland /* usually occurs at i=1 */ 19864562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 19874562236bSHarry Wentland i); 19884562236bSHarry Wentland break; 19894562236bSHarry Wentland } 19904562236bSHarry Wentland 19914562236bSHarry Wentland /* Wait for one frame. */ 19924562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 19934562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 19944562236bSHarry Wentland } 19954562236bSHarry Wentland 19964562236bSHarry Wentland if (false == rc) 19974562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 19984562236bSHarry Wentland 19994562236bSHarry Wentland return rc; 20004562236bSHarry Wentland } 20014562236bSHarry Wentland 20024562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 20034562236bSHarry Wentland static void dce110_enable_timing_synchronization( 20044562236bSHarry Wentland struct core_dc *dc, 20054562236bSHarry Wentland int group_index, 20064562236bSHarry Wentland int group_size, 20074562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 20084562236bSHarry Wentland { 20094562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 20104562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 20114562236bSHarry Wentland int i; 20124562236bSHarry Wentland 20134562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 20144562236bSHarry Wentland 20154562236bSHarry Wentland /* Designate a single TG in the group as a master. 20164562236bSHarry Wentland * Since HW doesn't care which one, we always assign 20174562236bSHarry Wentland * the 1st one in the group. */ 20184562236bSHarry Wentland gsl_params.gsl_group = 0; 20194562236bSHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->tg->inst; 20204562236bSHarry Wentland 20214562236bSHarry Wentland for (i = 0; i < group_size; i++) 20224562236bSHarry Wentland grouped_pipes[i]->tg->funcs->setup_global_swap_lock( 20234562236bSHarry Wentland grouped_pipes[i]->tg, &gsl_params); 20244562236bSHarry Wentland 20254562236bSHarry Wentland /* Reset slave controllers on master VSync */ 20264562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 20274562236bSHarry Wentland 20284562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 20294562236bSHarry Wentland grouped_pipes[i]->tg->funcs->enable_reset_trigger( 20304562236bSHarry Wentland grouped_pipes[i]->tg, gsl_params.gsl_group); 20314562236bSHarry Wentland 20324562236bSHarry Wentland 20334562236bSHarry Wentland 20344562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 20354562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 20364562236bSHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg); 20374562236bSHarry Wentland /* Regardless of success of the wait above, remove the reset or 20384562236bSHarry Wentland * the driver will start timing out on Display requests. */ 20394562236bSHarry Wentland DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); 20404562236bSHarry Wentland grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg); 20414562236bSHarry Wentland } 20424562236bSHarry Wentland 20434562236bSHarry Wentland 20444562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 20454562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 20464562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 20474562236bSHarry Wentland for (i = 0; i < group_size; i++) 20484562236bSHarry Wentland grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg); 20494562236bSHarry Wentland 20504562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 20514562236bSHarry Wentland } 20524562236bSHarry Wentland 20534562236bSHarry Wentland static void init_hw(struct core_dc *dc) 20544562236bSHarry Wentland { 20554562236bSHarry Wentland int i; 20564562236bSHarry Wentland struct dc_bios *bp; 20574562236bSHarry Wentland struct transform *xfm; 20585e7773a2SAnthony Koo struct abm *abm; 20594562236bSHarry Wentland 20604562236bSHarry Wentland bp = dc->ctx->dc_bios; 20614562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 20624562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 20634562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 20644562236bSHarry Wentland 20654562236bSHarry Wentland dc->hwss.enable_display_power_gating( 20664562236bSHarry Wentland dc, i, bp, 20674562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 20684562236bSHarry Wentland dc->hwss.enable_display_power_gating( 20694562236bSHarry Wentland dc, i, bp, 20704562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 20714562236bSHarry Wentland dc->hwss.enable_display_pipe_clock_gating( 20724562236bSHarry Wentland dc->ctx, 20734562236bSHarry Wentland true); 20744562236bSHarry Wentland } 20754562236bSHarry Wentland 2076e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 20774562236bSHarry Wentland /***************************************/ 20784562236bSHarry Wentland 20794562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 20804562236bSHarry Wentland /****************************************/ 20814562236bSHarry Wentland /* Power up AND update implementation according to the 20824562236bSHarry Wentland * required signal (which may be different from the 20834562236bSHarry Wentland * default signal on connector). */ 20844562236bSHarry Wentland struct core_link *link = dc->links[i]; 20854562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 20864562236bSHarry Wentland } 20874562236bSHarry Wentland 20884562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 20894562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 20904562236bSHarry Wentland 20914562236bSHarry Wentland tg->funcs->disable_vga(tg); 20924562236bSHarry Wentland 20934562236bSHarry Wentland /* Blank controller using driver code instead of 20944562236bSHarry Wentland * command table. */ 20954562236bSHarry Wentland tg->funcs->set_blank(tg, true); 20964b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 20974562236bSHarry Wentland } 20984562236bSHarry Wentland 20994562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 21004562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 21014562236bSHarry Wentland audio->funcs->hw_init(audio); 21024562236bSHarry Wentland } 21035e7773a2SAnthony Koo 21045e7773a2SAnthony Koo abm = dc->res_pool->abm; 21056728b30cSAnthony Koo if (abm != NULL) { 21066728b30cSAnthony Koo abm->funcs->init_backlight(abm); 21075e7773a2SAnthony Koo abm->funcs->abm_init(abm); 21084562236bSHarry Wentland } 21096728b30cSAnthony Koo } 21104562236bSHarry Wentland 211128f72454SJordan Lazare void dce110_fill_display_configs( 2112cf437593SDmytro Laktyushkin const struct validate_context *context, 2113cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg) 21144562236bSHarry Wentland { 2115cf437593SDmytro Laktyushkin int j; 2116cf437593SDmytro Laktyushkin int num_cfgs = 0; 2117cf437593SDmytro Laktyushkin 2118cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 2119cf437593SDmytro Laktyushkin int k; 2120cf437593SDmytro Laktyushkin 2121cf437593SDmytro Laktyushkin const struct core_stream *stream = context->streams[j]; 2122cf437593SDmytro Laktyushkin struct dm_pp_single_disp_config *cfg = 2123cf437593SDmytro Laktyushkin &pp_display_cfg->disp_configs[num_cfgs]; 2124cf437593SDmytro Laktyushkin const struct pipe_ctx *pipe_ctx = NULL; 2125cf437593SDmytro Laktyushkin 2126cf437593SDmytro Laktyushkin for (k = 0; k < MAX_PIPES; k++) 2127cf437593SDmytro Laktyushkin if (stream == context->res_ctx.pipe_ctx[k].stream) { 2128cf437593SDmytro Laktyushkin pipe_ctx = &context->res_ctx.pipe_ctx[k]; 2129cf437593SDmytro Laktyushkin break; 21304562236bSHarry Wentland } 21314562236bSHarry Wentland 2132cf437593SDmytro Laktyushkin ASSERT(pipe_ctx != NULL); 2133cf437593SDmytro Laktyushkin 2134cf437593SDmytro Laktyushkin num_cfgs++; 2135cf437593SDmytro Laktyushkin cfg->signal = pipe_ctx->stream->signal; 2136cf437593SDmytro Laktyushkin cfg->pipe_idx = pipe_ctx->pipe_idx; 2137cf437593SDmytro Laktyushkin cfg->src_height = stream->public.src.height; 2138cf437593SDmytro Laktyushkin cfg->src_width = stream->public.src.width; 2139cf437593SDmytro Laktyushkin cfg->ddi_channel_mapping = 2140cf437593SDmytro Laktyushkin stream->sink->link->ddi_channel_mapping.raw; 2141cf437593SDmytro Laktyushkin cfg->transmitter = 2142cf437593SDmytro Laktyushkin stream->sink->link->link_enc->transmitter; 2143cf437593SDmytro Laktyushkin cfg->link_settings.lane_count = 2144cf437593SDmytro Laktyushkin stream->sink->link->public.cur_link_settings.lane_count; 2145cf437593SDmytro Laktyushkin cfg->link_settings.link_rate = 2146cf437593SDmytro Laktyushkin stream->sink->link->public.cur_link_settings.link_rate; 2147cf437593SDmytro Laktyushkin cfg->link_settings.link_spread = 2148cf437593SDmytro Laktyushkin stream->sink->link->public.cur_link_settings.link_spread; 2149cf437593SDmytro Laktyushkin cfg->sym_clock = stream->phy_pix_clk; 2150cf437593SDmytro Laktyushkin /* Round v_refresh*/ 2151cf437593SDmytro Laktyushkin cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; 2152cf437593SDmytro Laktyushkin cfg->v_refresh /= stream->public.timing.h_total; 2153cf437593SDmytro Laktyushkin cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) 2154cf437593SDmytro Laktyushkin / stream->public.timing.v_total; 2155cf437593SDmytro Laktyushkin } 2156cf437593SDmytro Laktyushkin 2157cf437593SDmytro Laktyushkin pp_display_cfg->display_count = num_cfgs; 2158cf437593SDmytro Laktyushkin } 2159cf437593SDmytro Laktyushkin 216028f72454SJordan Lazare uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) 2161cf437593SDmytro Laktyushkin { 2162cf437593SDmytro Laktyushkin uint8_t j; 2163cf437593SDmytro Laktyushkin uint32_t min_vertical_blank_time = -1; 2164cf437593SDmytro Laktyushkin 2165cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 2166cf437593SDmytro Laktyushkin const struct dc_stream *stream = &context->streams[j]->public; 2167cf437593SDmytro Laktyushkin uint32_t vertical_blank_in_pixels = 0; 2168cf437593SDmytro Laktyushkin uint32_t vertical_blank_time = 0; 2169cf437593SDmytro Laktyushkin 2170cf437593SDmytro Laktyushkin vertical_blank_in_pixels = stream->timing.h_total * 2171cf437593SDmytro Laktyushkin (stream->timing.v_total 2172cf437593SDmytro Laktyushkin - stream->timing.v_addressable); 2173cf437593SDmytro Laktyushkin 2174cf437593SDmytro Laktyushkin vertical_blank_time = vertical_blank_in_pixels 2175cf437593SDmytro Laktyushkin * 1000 / stream->timing.pix_clk_khz; 2176cf437593SDmytro Laktyushkin 2177cf437593SDmytro Laktyushkin if (min_vertical_blank_time > vertical_blank_time) 2178cf437593SDmytro Laktyushkin min_vertical_blank_time = vertical_blank_time; 2179cf437593SDmytro Laktyushkin } 2180cf437593SDmytro Laktyushkin 2181cf437593SDmytro Laktyushkin return min_vertical_blank_time; 2182cf437593SDmytro Laktyushkin } 2183cf437593SDmytro Laktyushkin 2184cf437593SDmytro Laktyushkin static int determine_sclk_from_bounding_box( 2185cf437593SDmytro Laktyushkin const struct core_dc *dc, 2186cf437593SDmytro Laktyushkin int required_sclk) 21874562236bSHarry Wentland { 21884562236bSHarry Wentland int i; 21894562236bSHarry Wentland 2190cf437593SDmytro Laktyushkin /* 2191cf437593SDmytro Laktyushkin * Some asics do not give us sclk levels, so we just report the actual 2192cf437593SDmytro Laktyushkin * required sclk 2193cf437593SDmytro Laktyushkin */ 2194cf437593SDmytro Laktyushkin if (dc->sclk_lvls.num_levels == 0) 2195cf437593SDmytro Laktyushkin return required_sclk; 21964562236bSHarry Wentland 2197cf437593SDmytro Laktyushkin for (i = 0; i < dc->sclk_lvls.num_levels; i++) { 2198cf437593SDmytro Laktyushkin if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) 2199cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[i]; 2200cf437593SDmytro Laktyushkin } 2201cf437593SDmytro Laktyushkin /* 2202cf437593SDmytro Laktyushkin * even maximum level could not satisfy requirement, this 2203cf437593SDmytro Laktyushkin * is unexpected at this stage, should have been caught at 2204cf437593SDmytro Laktyushkin * validation time 2205cf437593SDmytro Laktyushkin */ 2206cf437593SDmytro Laktyushkin ASSERT(0); 2207cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; 22084562236bSHarry Wentland } 22094562236bSHarry Wentland 2210cf437593SDmytro Laktyushkin static void pplib_apply_display_requirements( 2211cf437593SDmytro Laktyushkin struct core_dc *dc, 2212cf437593SDmytro Laktyushkin struct validate_context *context) 2213cf437593SDmytro Laktyushkin { 2214cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 2215cf437593SDmytro Laktyushkin 2216cf437593SDmytro Laktyushkin pp_display_cfg->all_displays_in_sync = 2217cf437593SDmytro Laktyushkin context->bw_results.all_displays_in_sync; 2218cf437593SDmytro Laktyushkin pp_display_cfg->nb_pstate_switch_disable = 2219cf437593SDmytro Laktyushkin context->bw_results.nbp_state_change_enable == false; 2220cf437593SDmytro Laktyushkin pp_display_cfg->cpu_cc6_disable = 2221cf437593SDmytro Laktyushkin context->bw_results.cpuc_state_change_enable == false; 2222cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_disable = 2223cf437593SDmytro Laktyushkin context->bw_results.cpup_state_change_enable == false; 2224cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_separation_time = 2225cf437593SDmytro Laktyushkin context->bw_results.blackout_recovery_time_us; 2226cf437593SDmytro Laktyushkin 2227cf437593SDmytro Laktyushkin pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk 2228cf437593SDmytro Laktyushkin / MEMORY_TYPE_MULTIPLIER; 2229cf437593SDmytro Laktyushkin 2230cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( 2231cf437593SDmytro Laktyushkin dc, 2232cf437593SDmytro Laktyushkin context->bw_results.required_sclk); 2233cf437593SDmytro Laktyushkin 2234cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_deep_sleep_khz 2235cf437593SDmytro Laktyushkin = context->bw_results.required_sclk_deep_sleep; 2236cf437593SDmytro Laktyushkin 2237cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_us = 223828f72454SJordan Lazare dce110_get_min_vblank_time_us(context); 2239cf437593SDmytro Laktyushkin /* TODO: dce11.2*/ 2240cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; 2241cf437593SDmytro Laktyushkin 2242cf437593SDmytro Laktyushkin pp_display_cfg->disp_clk_khz = context->dispclk_khz; 2243cf437593SDmytro Laktyushkin 224428f72454SJordan Lazare dce110_fill_display_configs(context, pp_display_cfg); 2245cf437593SDmytro Laktyushkin 2246cf437593SDmytro Laktyushkin /* TODO: is this still applicable?*/ 2247cf437593SDmytro Laktyushkin if (pp_display_cfg->display_count == 1) { 2248cf437593SDmytro Laktyushkin const struct dc_crtc_timing *timing = 2249cf437593SDmytro Laktyushkin &context->streams[0]->public.timing; 2250cf437593SDmytro Laktyushkin 2251cf437593SDmytro Laktyushkin pp_display_cfg->crtc_index = 2252cf437593SDmytro Laktyushkin pp_display_cfg->disp_configs[0].pipe_idx; 2253cf437593SDmytro Laktyushkin pp_display_cfg->line_time_in_us = timing->h_total * 1000 2254cf437593SDmytro Laktyushkin / timing->pix_clk_khz; 2255cf437593SDmytro Laktyushkin } 2256cf437593SDmytro Laktyushkin 2257cf437593SDmytro Laktyushkin if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( 2258cf437593SDmytro Laktyushkin struct dm_pp_display_configuration)) != 0) 2259cf437593SDmytro Laktyushkin dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); 2260cf437593SDmytro Laktyushkin 2261cf437593SDmytro Laktyushkin dc->prev_display_config = *pp_display_cfg; 2262cf437593SDmytro Laktyushkin } 2263cf437593SDmytro Laktyushkin 2264cf437593SDmytro Laktyushkin static void dce110_set_bandwidth( 2265cf437593SDmytro Laktyushkin struct core_dc *dc, 2266cf437593SDmytro Laktyushkin struct validate_context *context, 2267cf437593SDmytro Laktyushkin bool decrease_allowed) 2268cf437593SDmytro Laktyushkin { 22692180e7ccSDmytro Laktyushkin dce110_set_displaymarks(dc, context); 2270cf437593SDmytro Laktyushkin 2271cf437593SDmytro Laktyushkin if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) { 2272cf437593SDmytro Laktyushkin context->res_ctx.pool->display_clock->funcs->set_clock( 2273cf437593SDmytro Laktyushkin context->res_ctx.pool->display_clock, 2274cf437593SDmytro Laktyushkin context->dispclk_khz * 115 / 100); 2275cf437593SDmytro Laktyushkin dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; 2276cf437593SDmytro Laktyushkin dc->current_context->dispclk_khz = context->dispclk_khz; 2277cf437593SDmytro Laktyushkin } 2278cf437593SDmytro Laktyushkin 2279cf437593SDmytro Laktyushkin pplib_apply_display_requirements(dc, context); 22804562236bSHarry Wentland } 22814562236bSHarry Wentland 22824562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 22834562236bSHarry Wentland struct core_dc *dc, struct pipe_ctx *pipe_ctx) 22844562236bSHarry Wentland { 22854562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 22864562236bSHarry Wentland struct pipe_ctx *old_pipe = NULL; 22874562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 22884562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 22894562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 22904562236bSHarry Wentland unsigned int i; 22914562236bSHarry Wentland 22924562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 22934562236bSHarry Wentland 22944562236bSHarry Wentland if (dc->current_context) 22954562236bSHarry Wentland old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 22964562236bSHarry Wentland 22974562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 22984562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 22994562236bSHarry Wentland 23004562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 23014562236bSHarry Wentland 23024562236bSHarry Wentland set_default_colors(pipe_ctx); 23034562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 23044562236bSHarry Wentland == true) { 23054562236bSHarry Wentland tbl_entry.color_space = 23064562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 23074562236bSHarry Wentland 23084562236bSHarry Wentland for (i = 0; i < 12; i++) 23094562236bSHarry Wentland tbl_entry.regval[i] = 23104562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 23114562236bSHarry Wentland 23124562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 23134562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 23144562236bSHarry Wentland } 23154562236bSHarry Wentland 23164562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 23174562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 23184562236bSHarry Wentland adjust.temperature_matrix[0] = 23194562236bSHarry Wentland pipe_ctx->stream-> 23204562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 23214562236bSHarry Wentland adjust.temperature_matrix[1] = 23224562236bSHarry Wentland pipe_ctx->stream-> 23234562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 23244562236bSHarry Wentland adjust.temperature_matrix[2] = 23254562236bSHarry Wentland pipe_ctx->stream-> 23264562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 23274562236bSHarry Wentland adjust.temperature_matrix[3] = 23284562236bSHarry Wentland pipe_ctx->stream-> 23294562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 23304562236bSHarry Wentland adjust.temperature_matrix[4] = 23314562236bSHarry Wentland pipe_ctx->stream-> 23324562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 23334562236bSHarry Wentland adjust.temperature_matrix[5] = 23344562236bSHarry Wentland pipe_ctx->stream-> 23354562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 23364562236bSHarry Wentland adjust.temperature_matrix[6] = 23374562236bSHarry Wentland pipe_ctx->stream-> 23384562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 23394562236bSHarry Wentland adjust.temperature_matrix[7] = 23404562236bSHarry Wentland pipe_ctx->stream-> 23414562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 23424562236bSHarry Wentland adjust.temperature_matrix[8] = 23434562236bSHarry Wentland pipe_ctx->stream-> 23444562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 23454562236bSHarry Wentland } 23464562236bSHarry Wentland 23474562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 23484562236bSHarry Wentland 23494562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 23504562236bSHarry Wentland if (old_pipe && memcmp(&old_pipe->scl_data, 23514562236bSHarry Wentland &pipe_ctx->scl_data, 23524562236bSHarry Wentland sizeof(struct scaler_data)) != 0) 23534562236bSHarry Wentland program_scaler(dc, pipe_ctx); 23544562236bSHarry Wentland 23554562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 23564562236bSHarry Wentland mi, 23574562236bSHarry Wentland surface->public.format, 23584562236bSHarry Wentland &surface->public.tiling_info, 23594562236bSHarry Wentland &surface->public.plane_size, 23604562236bSHarry Wentland surface->public.rotation, 2361624d7c47SYongqiang Sun NULL, 23624562236bSHarry Wentland false, 2363624d7c47SYongqiang Sun pipe_ctx->surface->public.visible); 23644562236bSHarry Wentland 23654562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 23664562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 23674562236bSHarry Wentland pipe_ctx->mi, 23684562236bSHarry Wentland surface->public.format, 23694562236bSHarry Wentland &surface->public.tiling_info, 23704562236bSHarry Wentland surface->public.rotation); 23714562236bSHarry Wentland 23724562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 23734562236bSHarry Wentland "Pipe:%d 0x%x: addr hi:0x%x, " 23744562236bSHarry Wentland "addr low:0x%x, " 23754562236bSHarry Wentland "src: %d, %d, %d," 23764562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 23774562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 23784562236bSHarry Wentland pipe_ctx->pipe_idx, 23794562236bSHarry Wentland pipe_ctx->surface, 23804562236bSHarry Wentland pipe_ctx->surface->public.address.grph.addr.high_part, 23814562236bSHarry Wentland pipe_ctx->surface->public.address.grph.addr.low_part, 23824562236bSHarry Wentland pipe_ctx->surface->public.src_rect.x, 23834562236bSHarry Wentland pipe_ctx->surface->public.src_rect.y, 23844562236bSHarry Wentland pipe_ctx->surface->public.src_rect.width, 23854562236bSHarry Wentland pipe_ctx->surface->public.src_rect.height, 23864562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.x, 23874562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.y, 23884562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.width, 23894562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.height, 23904562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.x, 23914562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.y, 23924562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.width, 23934562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.height); 23944562236bSHarry Wentland 23954562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 23964562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 23974562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 23984562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 23994562236bSHarry Wentland pipe_ctx->pipe_idx, 24004562236bSHarry Wentland pipe_ctx->scl_data.viewport.width, 24014562236bSHarry Wentland pipe_ctx->scl_data.viewport.height, 24024562236bSHarry Wentland pipe_ctx->scl_data.viewport.x, 24034562236bSHarry Wentland pipe_ctx->scl_data.viewport.y, 24044562236bSHarry Wentland pipe_ctx->scl_data.recout.width, 24054562236bSHarry Wentland pipe_ctx->scl_data.recout.height, 24064562236bSHarry Wentland pipe_ctx->scl_data.recout.x, 24074562236bSHarry Wentland pipe_ctx->scl_data.recout.y); 24084562236bSHarry Wentland } 24094562236bSHarry Wentland 24104562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 24114562236bSHarry Wentland struct core_dc *dc, 24124562236bSHarry Wentland struct core_surface *surface, 24134562236bSHarry Wentland struct validate_context *context) 24144562236bSHarry Wentland { 24154562236bSHarry Wentland int i; 24164562236bSHarry Wentland 24174562236bSHarry Wentland /* TODO remove when removing the surface reset workaroud*/ 24184562236bSHarry Wentland if (!surface) 24194562236bSHarry Wentland return; 24204562236bSHarry Wentland 24214562236bSHarry Wentland for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { 24224562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 24234562236bSHarry Wentland 24244562236bSHarry Wentland if (pipe_ctx->surface != surface) 24254562236bSHarry Wentland continue; 24264562236bSHarry Wentland 24274562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 2428b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 24294562236bSHarry Wentland 24304562236bSHarry Wentland } 24314562236bSHarry Wentland } 24324562236bSHarry Wentland 24334562236bSHarry Wentland static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) 24344562236bSHarry Wentland { 24354562236bSHarry Wentland int i; 24364562236bSHarry Wentland 24374562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) 24384562236bSHarry Wentland if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe) 24394562236bSHarry Wentland break; 24404562236bSHarry Wentland 24414562236bSHarry Wentland if (i == dc->res_pool->pipe_count) 24424562236bSHarry Wentland return; 24434562236bSHarry Wentland 24444562236bSHarry Wentland dc->hwss.enable_display_power_gating( 24454562236bSHarry Wentland dc, i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 24464562236bSHarry Wentland if (pipe->xfm) 24474562236bSHarry Wentland pipe->xfm->funcs->transform_reset(pipe->xfm); 24484562236bSHarry Wentland memset(&pipe->scl_data, 0, sizeof(struct scaler_data)); 24494562236bSHarry Wentland } 24504562236bSHarry Wentland 24514562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 24524562236bSHarry Wentland .init_hw = init_hw, 24534562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 24544562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 24554562236bSHarry Wentland .set_plane_config = set_plane_config, 24564562236bSHarry Wentland .update_plane_addr = update_plane_addr, 24574562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 2458d7194cf6SAric Cyr .set_input_transfer_func = dce110_set_input_transfer_func, 245990e508baSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 24604562236bSHarry Wentland .power_down = dce110_power_down, 24614562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 24624562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 24634562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 24644562236bSHarry Wentland .enable_stream = dce110_enable_stream, 24654562236bSHarry Wentland .disable_stream = dce110_disable_stream, 24664562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 24674562236bSHarry Wentland .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 24684562236bSHarry Wentland .enable_display_power_gating = dce110_enable_display_power_gating, 24694562236bSHarry Wentland .power_down_front_end = dce110_power_down_fe, 24704562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 24714562236bSHarry Wentland .set_bandwidth = dce110_set_bandwidth, 24724562236bSHarry Wentland .set_drr = set_drr, 24734562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 24744562236bSHarry Wentland .reset_hw_ctx_wrap = reset_hw_ctx_wrap, 24754b5e7d62SHersen Wu .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, 24764562236bSHarry Wentland }; 24774562236bSHarry Wentland 24784562236bSHarry Wentland bool dce110_hw_sequencer_construct(struct core_dc *dc) 24794562236bSHarry Wentland { 24804562236bSHarry Wentland dc->hwss = dce110_funcs; 24814562236bSHarry Wentland 24824562236bSHarry Wentland return true; 24834562236bSHarry Wentland } 24844562236bSHarry Wentland 2485