14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland #include "dm_services.h" 264562236bSHarry Wentland #include "dc.h" 274562236bSHarry Wentland #include "dc_bios_types.h" 284562236bSHarry Wentland #include "core_types.h" 294562236bSHarry Wentland #include "core_status.h" 304562236bSHarry Wentland #include "resource.h" 314562236bSHarry Wentland #include "dm_helpers.h" 324562236bSHarry Wentland #include "dce110_hw_sequencer.h" 334562236bSHarry Wentland #include "dce110_timing_generator.h" 3498489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 354562236bSHarry Wentland 364562236bSHarry Wentland #include "bios/bios_parser_helper.h" 374562236bSHarry Wentland #include "timing_generator.h" 384562236bSHarry Wentland #include "mem_input.h" 394562236bSHarry Wentland #include "opp.h" 404562236bSHarry Wentland #include "ipp.h" 414562236bSHarry Wentland #include "transform.h" 424562236bSHarry Wentland #include "stream_encoder.h" 434562236bSHarry Wentland #include "link_encoder.h" 444562236bSHarry Wentland #include "clock_source.h" 455e7773a2SAnthony Koo #include "abm.h" 464562236bSHarry Wentland #include "audio.h" 474562236bSHarry Wentland #include "dce/dce_hwseq.h" 484562236bSHarry Wentland 494562236bSHarry Wentland /* include DCE11 register header files */ 504562236bSHarry Wentland #include "dce/dce_11_0_d.h" 514562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 52e266fdf6SVitaly Prosyak #include "custom_float.h" 534562236bSHarry Wentland 544562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 554562236bSHarry Wentland uint32_t crtc; 564562236bSHarry Wentland }; 574562236bSHarry Wentland 584562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 594562236bSHarry Wentland { 604562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 614562236bSHarry Wentland }, 624562236bSHarry Wentland { 634562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 644562236bSHarry Wentland }, 654562236bSHarry Wentland { 664562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 674562236bSHarry Wentland }, 684562236bSHarry Wentland { 694562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 704562236bSHarry Wentland } 714562236bSHarry Wentland }; 724562236bSHarry Wentland 734562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 744562236bSHarry Wentland (reg + reg_offsets[id].blnd) 754562236bSHarry Wentland 764562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 774562236bSHarry Wentland (reg + reg_offsets[id].crtc) 784562236bSHarry Wentland 794562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 804562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 814562236bSHarry Wentland 824562236bSHarry Wentland /******************************************************************************* 834562236bSHarry Wentland * Private definitions 844562236bSHarry Wentland ******************************************************************************/ 854562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 864562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 874562236bSHarry Wentland { 884562236bSHarry Wentland uint32_t addr; 894562236bSHarry Wentland uint32_t value = 0; 904562236bSHarry Wentland uint32_t chunk_int = 0; 914562236bSHarry Wentland uint32_t chunk_mul = 0; 924562236bSHarry Wentland 934562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 944562236bSHarry Wentland value = dm_read_reg(ctx, addr); 954562236bSHarry Wentland 964562236bSHarry Wentland set_reg_field_value( 974562236bSHarry Wentland value, 984562236bSHarry Wentland 0, 994562236bSHarry Wentland DVMM_PTE_CONTROL, 1004562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1014562236bSHarry Wentland 1024562236bSHarry Wentland set_reg_field_value( 1034562236bSHarry Wentland value, 1044562236bSHarry Wentland 1, 1054562236bSHarry Wentland DVMM_PTE_CONTROL, 1064562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1074562236bSHarry Wentland 1084562236bSHarry Wentland set_reg_field_value( 1094562236bSHarry Wentland value, 1104562236bSHarry Wentland 1, 1114562236bSHarry Wentland DVMM_PTE_CONTROL, 1124562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1134562236bSHarry Wentland 1144562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1154562236bSHarry Wentland 1164562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1174562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1184562236bSHarry Wentland 1194562236bSHarry Wentland chunk_int = get_reg_field_value( 1204562236bSHarry Wentland value, 1214562236bSHarry Wentland DVMM_PTE_REQ, 1224562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1234562236bSHarry Wentland 1244562236bSHarry Wentland chunk_mul = get_reg_field_value( 1254562236bSHarry Wentland value, 1264562236bSHarry Wentland DVMM_PTE_REQ, 1274562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1284562236bSHarry Wentland 1294562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1304562236bSHarry Wentland 1314562236bSHarry Wentland set_reg_field_value( 1324562236bSHarry Wentland value, 1334562236bSHarry Wentland 255, 1344562236bSHarry Wentland DVMM_PTE_REQ, 1354562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1364562236bSHarry Wentland 1374562236bSHarry Wentland set_reg_field_value( 1384562236bSHarry Wentland value, 1394562236bSHarry Wentland 4, 1404562236bSHarry Wentland DVMM_PTE_REQ, 1414562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1424562236bSHarry Wentland 1434562236bSHarry Wentland set_reg_field_value( 1444562236bSHarry Wentland value, 1454562236bSHarry Wentland 4, 1464562236bSHarry Wentland DVMM_PTE_REQ, 1474562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1484562236bSHarry Wentland 1494562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1504562236bSHarry Wentland } 1514562236bSHarry Wentland } 1524562236bSHarry Wentland /**************************************************************************/ 1534562236bSHarry Wentland 1544562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1554562236bSHarry Wentland struct dc_context *ctx, 1564562236bSHarry Wentland bool clock_gating) 1574562236bSHarry Wentland { 1584562236bSHarry Wentland /*TODO*/ 1594562236bSHarry Wentland } 1604562236bSHarry Wentland 1614562236bSHarry Wentland static bool dce110_enable_display_power_gating( 1624562236bSHarry Wentland struct core_dc *dc, 1634562236bSHarry Wentland uint8_t controller_id, 1644562236bSHarry Wentland struct dc_bios *dcb, 1654562236bSHarry Wentland enum pipe_gating_control power_gating) 1664562236bSHarry Wentland { 1674562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 1684562236bSHarry Wentland enum bp_pipe_control_action cntl; 1694562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 1704562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1714562236bSHarry Wentland 1724562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1734562236bSHarry Wentland return true; 1744562236bSHarry Wentland 1754562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 1764562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 1774562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 1784562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 1794562236bSHarry Wentland else 1804562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 1814562236bSHarry Wentland 1824562236bSHarry Wentland if (controller_id == underlay_idx) 1834562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 1844562236bSHarry Wentland 1854562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 1864562236bSHarry Wentland 1874562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 1884562236bSHarry Wentland dcb, controller_id + 1, cntl); 1894562236bSHarry Wentland 1904562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 1914562236bSHarry Wentland * by default when command table is called 1924562236bSHarry Wentland * 1934562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 1944562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 1954562236bSHarry Wentland * than 3. 1964562236bSHarry Wentland */ 1974562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 1984562236bSHarry Wentland dm_write_reg(ctx, 1994562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2004562236bSHarry Wentland 0); 2014562236bSHarry Wentland } 2024562236bSHarry Wentland 2034562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2044562236bSHarry Wentland dce110_init_pte(ctx); 2054562236bSHarry Wentland 2064562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2074562236bSHarry Wentland return true; 2084562236bSHarry Wentland else 2094562236bSHarry Wentland return false; 2104562236bSHarry Wentland } 2114562236bSHarry Wentland 2124562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2134562236bSHarry Wentland const struct core_surface *surface) 2144562236bSHarry Wentland { 2154562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2164562236bSHarry Wentland 2174562236bSHarry Wentland switch (surface->public.format) { 2184562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2198693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2204562236bSHarry Wentland prescale_params->scale = 0x2020; 2214562236bSHarry Wentland break; 2224562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2234562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2244562236bSHarry Wentland prescale_params->scale = 0x2008; 2254562236bSHarry Wentland break; 2264562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2274562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2284562236bSHarry Wentland prescale_params->scale = 0x2000; 2294562236bSHarry Wentland break; 2304562236bSHarry Wentland default: 2314562236bSHarry Wentland ASSERT(false); 232d7194cf6SAric Cyr break; 2334562236bSHarry Wentland } 2344562236bSHarry Wentland } 2354562236bSHarry Wentland 236d7194cf6SAric Cyr static bool dce110_set_input_transfer_func( 237fb735a9fSAnthony Koo struct pipe_ctx *pipe_ctx, 2384562236bSHarry Wentland const struct core_surface *surface) 2394562236bSHarry Wentland { 240fb735a9fSAnthony Koo struct input_pixel_processor *ipp = pipe_ctx->ipp; 24190e508baSAnthony Koo const struct core_transfer_func *tf = NULL; 24290e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 24390e508baSAnthony Koo bool result = true; 24490e508baSAnthony Koo 24590e508baSAnthony Koo if (ipp == NULL) 24690e508baSAnthony Koo return false; 24790e508baSAnthony Koo 24890e508baSAnthony Koo if (surface->public.in_transfer_func) 24990e508baSAnthony Koo tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func); 25090e508baSAnthony Koo 25190e508baSAnthony Koo build_prescale_params(&prescale_params, surface); 25290e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 25390e508baSAnthony Koo 25498489c02SLeo (Sunpeng) Li if (surface->public.gamma_correction && dce_use_lut(surface)) 255d7194cf6SAric Cyr ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction); 256d7194cf6SAric Cyr 25790e508baSAnthony Koo if (tf == NULL) { 25890e508baSAnthony Koo /* Default case if no input transfer function specified */ 25990e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 260306dadf0SAmy Zhang IPP_DEGAMMA_MODE_HW_sRGB); 26190e508baSAnthony Koo } else if (tf->public.type == TF_TYPE_PREDEFINED) { 26290e508baSAnthony Koo switch (tf->public.tf) { 26390e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 26490e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 26590e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_sRGB); 26690e508baSAnthony Koo break; 26790e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 26890e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 26990e508baSAnthony Koo IPP_DEGAMMA_MODE_HW_xvYCC); 27090e508baSAnthony Koo break; 27190e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 27290e508baSAnthony Koo ipp->funcs->ipp_set_degamma(ipp, 27390e508baSAnthony Koo IPP_DEGAMMA_MODE_BYPASS); 27490e508baSAnthony Koo break; 27590e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 27690e508baSAnthony Koo result = false; 27790e508baSAnthony Koo break; 27890e508baSAnthony Koo default: 27990e508baSAnthony Koo result = false; 280d7194cf6SAric Cyr break; 28190e508baSAnthony Koo } 28270063a59SAmy Zhang } else if (tf->public.type == TF_TYPE_BYPASS) { 28370063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 28490e508baSAnthony Koo } else { 28590e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 28690e508baSAnthony Koo result = false; 28790e508baSAnthony Koo } 28890e508baSAnthony Koo 28990e508baSAnthony Koo return result; 29090e508baSAnthony Koo } 29190e508baSAnthony Koo 292fcd2f4bfSAmy Zhang static bool convert_to_custom_float( 293fcd2f4bfSAmy Zhang struct pwl_result_data *rgb_resulted, 294fcd2f4bfSAmy Zhang struct curve_points *arr_points, 295fcd2f4bfSAmy Zhang uint32_t hw_points_num) 296fcd2f4bfSAmy Zhang { 297fcd2f4bfSAmy Zhang struct custom_float_format fmt; 298fcd2f4bfSAmy Zhang 299fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 300fcd2f4bfSAmy Zhang 301fcd2f4bfSAmy Zhang uint32_t i = 0; 302fcd2f4bfSAmy Zhang 303fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 304fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 305fcd2f4bfSAmy Zhang fmt.sign = true; 306fcd2f4bfSAmy Zhang 307fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 308fcd2f4bfSAmy Zhang arr_points[0].x, 309fcd2f4bfSAmy Zhang &fmt, 310fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 311fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 312fcd2f4bfSAmy Zhang return false; 313fcd2f4bfSAmy Zhang } 314fcd2f4bfSAmy Zhang 315fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 316fcd2f4bfSAmy Zhang arr_points[0].offset, 317fcd2f4bfSAmy Zhang &fmt, 318fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 319fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 320fcd2f4bfSAmy Zhang return false; 321fcd2f4bfSAmy Zhang } 322fcd2f4bfSAmy Zhang 323fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 324fcd2f4bfSAmy Zhang arr_points[0].slope, 325fcd2f4bfSAmy Zhang &fmt, 326fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 327fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 328fcd2f4bfSAmy Zhang return false; 329fcd2f4bfSAmy Zhang } 330fcd2f4bfSAmy Zhang 331fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 332fcd2f4bfSAmy Zhang fmt.sign = false; 333fcd2f4bfSAmy Zhang 334fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 335fcd2f4bfSAmy Zhang arr_points[1].x, 336fcd2f4bfSAmy Zhang &fmt, 337fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 338fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 339fcd2f4bfSAmy Zhang return false; 340fcd2f4bfSAmy Zhang } 341fcd2f4bfSAmy Zhang 342fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 343fcd2f4bfSAmy Zhang arr_points[1].y, 344fcd2f4bfSAmy Zhang &fmt, 345fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 346fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 347fcd2f4bfSAmy Zhang return false; 348fcd2f4bfSAmy Zhang } 349fcd2f4bfSAmy Zhang 350fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 351fcd2f4bfSAmy Zhang arr_points[2].slope, 352fcd2f4bfSAmy Zhang &fmt, 353fcd2f4bfSAmy Zhang &arr_points[2].custom_float_slope)) { 354fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 355fcd2f4bfSAmy Zhang return false; 356fcd2f4bfSAmy Zhang } 357fcd2f4bfSAmy Zhang 358fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 359fcd2f4bfSAmy Zhang fmt.sign = true; 360fcd2f4bfSAmy Zhang 361fcd2f4bfSAmy Zhang while (i != hw_points_num) { 362fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 363fcd2f4bfSAmy Zhang rgb->red, 364fcd2f4bfSAmy Zhang &fmt, 365fcd2f4bfSAmy Zhang &rgb->red_reg)) { 366fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 367fcd2f4bfSAmy Zhang return false; 368fcd2f4bfSAmy Zhang } 369fcd2f4bfSAmy Zhang 370fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 371fcd2f4bfSAmy Zhang rgb->green, 372fcd2f4bfSAmy Zhang &fmt, 373fcd2f4bfSAmy Zhang &rgb->green_reg)) { 374fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 375fcd2f4bfSAmy Zhang return false; 376fcd2f4bfSAmy Zhang } 377fcd2f4bfSAmy Zhang 378fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 379fcd2f4bfSAmy Zhang rgb->blue, 380fcd2f4bfSAmy Zhang &fmt, 381fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 382fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 383fcd2f4bfSAmy Zhang return false; 384fcd2f4bfSAmy Zhang } 385fcd2f4bfSAmy Zhang 386fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 387fcd2f4bfSAmy Zhang rgb->delta_red, 388fcd2f4bfSAmy Zhang &fmt, 389fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 390fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 391fcd2f4bfSAmy Zhang return false; 392fcd2f4bfSAmy Zhang } 393fcd2f4bfSAmy Zhang 394fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 395fcd2f4bfSAmy Zhang rgb->delta_green, 396fcd2f4bfSAmy Zhang &fmt, 397fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 398fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 399fcd2f4bfSAmy Zhang return false; 400fcd2f4bfSAmy Zhang } 401fcd2f4bfSAmy Zhang 402fcd2f4bfSAmy Zhang if (!convert_to_custom_float_format( 403fcd2f4bfSAmy Zhang rgb->delta_blue, 404fcd2f4bfSAmy Zhang &fmt, 405fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 406fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 407fcd2f4bfSAmy Zhang return false; 408fcd2f4bfSAmy Zhang } 409fcd2f4bfSAmy Zhang 410fcd2f4bfSAmy Zhang ++rgb; 411fcd2f4bfSAmy Zhang ++i; 412fcd2f4bfSAmy Zhang } 413fcd2f4bfSAmy Zhang 414fcd2f4bfSAmy Zhang return true; 415fcd2f4bfSAmy Zhang } 416fcd2f4bfSAmy Zhang 417e266fdf6SVitaly Prosyak static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func 418fcd2f4bfSAmy Zhang *output_tf, struct pwl_params *regamma_params) 419fcd2f4bfSAmy Zhang { 42023ae4f8eSAmy Zhang struct curve_points *arr_points; 42123ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 42223ae4f8eSAmy Zhang struct pwl_result_data *rgb; 42323ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 424fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 425fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 426fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 427fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 428fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 429fcd2f4bfSAmy Zhang 430fcd2f4bfSAmy Zhang int32_t segment_start, segment_end; 43123ae4f8eSAmy Zhang uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; 43223ae4f8eSAmy Zhang 43370063a59SAmy Zhang if (output_tf == NULL || regamma_params == NULL || 43470063a59SAmy Zhang output_tf->type == TF_TYPE_BYPASS) 43523ae4f8eSAmy Zhang return false; 43623ae4f8eSAmy Zhang 43723ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 43823ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 43923ae4f8eSAmy Zhang hw_points = 0; 440fcd2f4bfSAmy Zhang 441fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 442fcd2f4bfSAmy Zhang 443fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 444534db198SAmy Zhang /* 16 segments 445fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 446fcd2f4bfSAmy Zhang */ 447fcd2f4bfSAmy Zhang segment_start = -11; 448fcd2f4bfSAmy Zhang segment_end = 5; 449fcd2f4bfSAmy Zhang 450534db198SAmy Zhang seg_distr[0] = 2; 451534db198SAmy Zhang seg_distr[1] = 2; 452534db198SAmy Zhang seg_distr[2] = 2; 453534db198SAmy Zhang seg_distr[3] = 2; 454534db198SAmy Zhang seg_distr[4] = 2; 455534db198SAmy Zhang seg_distr[5] = 2; 456534db198SAmy Zhang seg_distr[6] = 3; 457534db198SAmy Zhang seg_distr[7] = 4; 458534db198SAmy Zhang seg_distr[8] = 4; 459534db198SAmy Zhang seg_distr[9] = 4; 460534db198SAmy Zhang seg_distr[10] = 4; 461534db198SAmy Zhang seg_distr[11] = 5; 462534db198SAmy Zhang seg_distr[12] = 5; 463534db198SAmy Zhang seg_distr[13] = 5; 464534db198SAmy Zhang seg_distr[14] = 5; 465534db198SAmy Zhang seg_distr[15] = 5; 466534db198SAmy Zhang 467fcd2f4bfSAmy Zhang } else { 468534db198SAmy Zhang /* 10 segments 469fcd2f4bfSAmy Zhang * segment is from 2^-10 to 2^0 470fcd2f4bfSAmy Zhang */ 471fcd2f4bfSAmy Zhang segment_start = -10; 472fcd2f4bfSAmy Zhang segment_end = 0; 473534db198SAmy Zhang 474534db198SAmy Zhang seg_distr[0] = 3; 475534db198SAmy Zhang seg_distr[1] = 4; 476534db198SAmy Zhang seg_distr[2] = 4; 477534db198SAmy Zhang seg_distr[3] = 4; 478534db198SAmy Zhang seg_distr[4] = 4; 479534db198SAmy Zhang seg_distr[5] = 4; 480534db198SAmy Zhang seg_distr[6] = 4; 481534db198SAmy Zhang seg_distr[7] = 4; 482534db198SAmy Zhang seg_distr[8] = 5; 483534db198SAmy Zhang seg_distr[9] = 5; 484534db198SAmy Zhang seg_distr[10] = -1; 485534db198SAmy Zhang seg_distr[11] = -1; 486534db198SAmy Zhang seg_distr[12] = -1; 487534db198SAmy Zhang seg_distr[13] = -1; 488534db198SAmy Zhang seg_distr[14] = -1; 489534db198SAmy Zhang seg_distr[15] = -1; 490fcd2f4bfSAmy Zhang } 491fcd2f4bfSAmy Zhang 492534db198SAmy Zhang for (k = 0; k < 16; k++) { 493534db198SAmy Zhang if (seg_distr[k] != -1) 494534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 495534db198SAmy Zhang } 496534db198SAmy Zhang 497fcd2f4bfSAmy Zhang j = 0; 498534db198SAmy Zhang for (k = 0; k < (segment_end - segment_start); k++) { 499534db198SAmy Zhang increment = 32 / (1 << seg_distr[k]); 500534db198SAmy Zhang start_index = (segment_start + k + 25) * 32; 501534db198SAmy Zhang for (i = start_index; i < start_index + 32; i += increment) { 502534db198SAmy Zhang if (j == hw_points - 1) 503fcd2f4bfSAmy Zhang break; 504fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 505fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 506fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 507fcd2f4bfSAmy Zhang j++; 508fcd2f4bfSAmy Zhang } 509534db198SAmy Zhang } 510534db198SAmy Zhang 511534db198SAmy Zhang /* last point */ 512534db198SAmy Zhang start_index = (segment_end + 25) * 32; 513534db198SAmy Zhang rgb_resulted[hw_points - 1].red = 514534db198SAmy Zhang output_tf->tf_pts.red[start_index]; 515534db198SAmy Zhang rgb_resulted[hw_points - 1].green = 516534db198SAmy Zhang output_tf->tf_pts.green[start_index]; 517534db198SAmy Zhang rgb_resulted[hw_points - 1].blue = 518534db198SAmy Zhang output_tf->tf_pts.blue[start_index]; 519fcd2f4bfSAmy Zhang 520fcd2f4bfSAmy Zhang arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 521fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_start)); 522fcd2f4bfSAmy Zhang arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 523fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 524fcd2f4bfSAmy Zhang arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 525fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 526fcd2f4bfSAmy Zhang 527fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 528fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 529fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 530fcd2f4bfSAmy Zhang 531fcd2f4bfSAmy Zhang y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); 532fcd2f4bfSAmy Zhang 533fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 534fcd2f4bfSAmy Zhang arr_points[0].slope = dal_fixed31_32_div( 535fcd2f4bfSAmy Zhang arr_points[0].y, 536fcd2f4bfSAmy Zhang arr_points[0].x); 537fcd2f4bfSAmy Zhang 538fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 539fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 540fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 541fcd2f4bfSAmy Zhang 542fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 543fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 544fcd2f4bfSAmy Zhang */ 545fcd2f4bfSAmy Zhang y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); 546fcd2f4bfSAmy Zhang 547fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 548fcd2f4bfSAmy Zhang arr_points[2].y = y3_max; 549fcd2f4bfSAmy Zhang 550fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_zero; 551fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_zero; 552fcd2f4bfSAmy Zhang 553fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 554fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 555fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 556fcd2f4bfSAmy Zhang */ 557fcd2f4bfSAmy Zhang const struct fixed31_32 end_value = 558fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(125); 559fcd2f4bfSAmy Zhang 560fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_div( 561fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 562fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 563fcd2f4bfSAmy Zhang arr_points[2].slope = dal_fixed31_32_div( 564fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 565fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 566fcd2f4bfSAmy Zhang } 567fcd2f4bfSAmy Zhang 568fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 569fcd2f4bfSAmy Zhang 570534db198SAmy Zhang i = 1; 571534db198SAmy Zhang for (k = 0; k < 16 && i < 16; k++) { 572534db198SAmy Zhang if (seg_distr[k] != -1) { 573534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 574534db198SAmy Zhang seg_distr[k]; 575534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 576534db198SAmy Zhang regamma_params->arr_curve_points[k]. 577534db198SAmy Zhang offset + (1 << seg_distr[k]); 578fcd2f4bfSAmy Zhang } 579534db198SAmy Zhang i++; 580534db198SAmy Zhang } 581534db198SAmy Zhang 582534db198SAmy Zhang if (seg_distr[k] != -1) 583534db198SAmy Zhang regamma_params->arr_curve_points[k].segments_num = 584534db198SAmy Zhang seg_distr[k]; 585fcd2f4bfSAmy Zhang 58623ae4f8eSAmy Zhang rgb = rgb_resulted; 58723ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 588fcd2f4bfSAmy Zhang 589fcd2f4bfSAmy Zhang i = 1; 590fcd2f4bfSAmy Zhang 591fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 592fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) 593fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 594fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) 595fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 596fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) 597fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 598fcd2f4bfSAmy Zhang 599fcd2f4bfSAmy Zhang rgb->delta_red = dal_fixed31_32_sub( 600fcd2f4bfSAmy Zhang rgb_plus_1->red, 601fcd2f4bfSAmy Zhang rgb->red); 602fcd2f4bfSAmy Zhang rgb->delta_green = dal_fixed31_32_sub( 603fcd2f4bfSAmy Zhang rgb_plus_1->green, 604fcd2f4bfSAmy Zhang rgb->green); 605fcd2f4bfSAmy Zhang rgb->delta_blue = dal_fixed31_32_sub( 606fcd2f4bfSAmy Zhang rgb_plus_1->blue, 607fcd2f4bfSAmy Zhang rgb->blue); 608fcd2f4bfSAmy Zhang 609fcd2f4bfSAmy Zhang ++rgb_plus_1; 610fcd2f4bfSAmy Zhang ++rgb; 611fcd2f4bfSAmy Zhang ++i; 612fcd2f4bfSAmy Zhang } 613fcd2f4bfSAmy Zhang 614fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 615fcd2f4bfSAmy Zhang 616fcd2f4bfSAmy Zhang return true; 617fcd2f4bfSAmy Zhang } 618fcd2f4bfSAmy Zhang 61990e508baSAnthony Koo static bool dce110_set_output_transfer_func( 62090e508baSAnthony Koo struct pipe_ctx *pipe_ctx, 62190e508baSAnthony Koo const struct core_stream *stream) 62290e508baSAnthony Koo { 623fb735a9fSAnthony Koo struct output_pixel_processor *opp = pipe_ctx->opp; 6244562236bSHarry Wentland 6254562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, true); 626974db151SDmytro Laktyushkin opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 6274562236bSHarry Wentland 628d7194cf6SAric Cyr if (stream->public.out_transfer_func && 629fcd2f4bfSAmy Zhang stream->public.out_transfer_func->type == 630fcd2f4bfSAmy Zhang TF_TYPE_PREDEFINED && 631fcd2f4bfSAmy Zhang stream->public.out_transfer_func->tf == 632fcd2f4bfSAmy Zhang TRANSFER_FUNCTION_SRGB) { 633d7194cf6SAric Cyr opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); 634fcd2f4bfSAmy Zhang } else if (dce110_translate_regamma_to_hw_format( 635974db151SDmytro Laktyushkin stream->public.out_transfer_func, &opp->regamma_params)) { 636974db151SDmytro Laktyushkin opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params); 6374562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); 6384562236bSHarry Wentland } else { 6394562236bSHarry Wentland opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS); 6404562236bSHarry Wentland } 6414562236bSHarry Wentland 6424562236bSHarry Wentland opp->funcs->opp_power_on_regamma_lut(opp, false); 6434562236bSHarry Wentland 644cc0cb445SLeon Elazar return true; 6454562236bSHarry Wentland } 6464562236bSHarry Wentland 6474562236bSHarry Wentland static enum dc_status bios_parser_crtc_source_select( 6484562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 6494562236bSHarry Wentland { 6504562236bSHarry Wentland struct dc_bios *dcb; 6514562236bSHarry Wentland /* call VBIOS table to set CRTC source for the HW 6524562236bSHarry Wentland * encoder block 6534562236bSHarry Wentland * note: video bios clears all FMT setting here. */ 6544562236bSHarry Wentland struct bp_crtc_source_select crtc_source_select = {0}; 6554562236bSHarry Wentland const struct core_sink *sink = pipe_ctx->stream->sink; 6564562236bSHarry Wentland 6574562236bSHarry Wentland crtc_source_select.engine_id = pipe_ctx->stream_enc->id; 6584562236bSHarry Wentland crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1; 6594562236bSHarry Wentland /*TODO: Need to un-hardcode color depth, dp_audio and account for 6604562236bSHarry Wentland * the case where signal and sink signal is different (translator 6614562236bSHarry Wentland * encoder)*/ 6624562236bSHarry Wentland crtc_source_select.signal = pipe_ctx->stream->signal; 6634562236bSHarry Wentland crtc_source_select.enable_dp_audio = false; 6644562236bSHarry Wentland crtc_source_select.sink_signal = pipe_ctx->stream->signal; 6654562236bSHarry Wentland crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6664562236bSHarry Wentland 6674562236bSHarry Wentland dcb = sink->ctx->dc_bios; 6684562236bSHarry Wentland 6694562236bSHarry Wentland if (BP_RESULT_OK != dcb->funcs->crtc_source_select( 6704562236bSHarry Wentland dcb, 6714562236bSHarry Wentland &crtc_source_select)) { 6724562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 6734562236bSHarry Wentland } 6744562236bSHarry Wentland 6754562236bSHarry Wentland return DC_OK; 6764562236bSHarry Wentland } 6774562236bSHarry Wentland 6784562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6794562236bSHarry Wentland { 68086e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 68186e2e1beSHersen Wu 68286e2e1beSHersen Wu if (pipe_ctx->stream_enc == NULL) 68386e2e1beSHersen Wu return; /* this is not root pipe */ 68486e2e1beSHersen Wu 6854562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 6864562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_hdmi_info_packets( 6874562236bSHarry Wentland pipe_ctx->stream_enc, 6884562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 6894562236bSHarry Wentland else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6904562236bSHarry Wentland pipe_ctx->stream_enc->funcs->update_dp_info_packets( 6914562236bSHarry Wentland pipe_ctx->stream_enc, 6924562236bSHarry Wentland &pipe_ctx->encoder_info_frame); 6934562236bSHarry Wentland } 6944562236bSHarry Wentland 6954562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6964562236bSHarry Wentland { 6974562236bSHarry Wentland enum dc_lane_count lane_count = 6984562236bSHarry Wentland pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count; 6994562236bSHarry Wentland 7004562236bSHarry Wentland struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; 7014562236bSHarry Wentland struct core_link *link = pipe_ctx->stream->sink->link; 7024562236bSHarry Wentland 7034562236bSHarry Wentland /* 1. update AVI info frame (HDMI, DP) 7044562236bSHarry Wentland * we always need to update info frame 7054562236bSHarry Wentland */ 7064562236bSHarry Wentland uint32_t active_total_with_borders; 7074562236bSHarry Wentland uint32_t early_control = 0; 7084562236bSHarry Wentland struct timing_generator *tg = pipe_ctx->tg; 7094562236bSHarry Wentland 7104562236bSHarry Wentland /* TODOFPGA may change to hwss.update_info_frame */ 7114562236bSHarry Wentland dce110_update_info_frame(pipe_ctx); 7124562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 7134562236bSHarry Wentland active_total_with_borders = 7144562236bSHarry Wentland timing->h_addressable 7154562236bSHarry Wentland + timing->h_border_left 7164562236bSHarry Wentland + timing->h_border_right; 7174562236bSHarry Wentland 7184562236bSHarry Wentland if (lane_count != 0) 7194562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 7204562236bSHarry Wentland 7214562236bSHarry Wentland if (early_control == 0) 7224562236bSHarry Wentland early_control = lane_count; 7234562236bSHarry Wentland 7244562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 7254562236bSHarry Wentland 7264562236bSHarry Wentland /* enable audio only within mode set */ 7274562236bSHarry Wentland if (pipe_ctx->audio != NULL) { 7284562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7294562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_enc); 7304562236bSHarry Wentland } 7314562236bSHarry Wentland 7324562236bSHarry Wentland /* For MST, there are multiply stream go to only one link. 7334562236bSHarry Wentland * connect DIG back_end to front_end while enable_stream and 7344562236bSHarry Wentland * disconnect them during disable_stream 7354562236bSHarry Wentland * BY this, it is logic clean to separate stream and link */ 7364562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 7374562236bSHarry Wentland pipe_ctx->stream_enc->id, true); 7384562236bSHarry Wentland 7394562236bSHarry Wentland } 7404562236bSHarry Wentland 7414562236bSHarry Wentland void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 7424562236bSHarry Wentland { 7434562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 7444562236bSHarry Wentland struct core_link *link = stream->sink->link; 7454562236bSHarry Wentland 7464562236bSHarry Wentland if (pipe_ctx->audio) { 7474562236bSHarry Wentland pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); 7484562236bSHarry Wentland 7494562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7504562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_disable( 7514562236bSHarry Wentland pipe_ctx->stream_enc); 7524562236bSHarry Wentland else 7534562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_disable( 7544562236bSHarry Wentland pipe_ctx->stream_enc); 7554562236bSHarry Wentland 7564562236bSHarry Wentland pipe_ctx->audio = NULL; 7574562236bSHarry Wentland 7584562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 7594562236bSHarry Wentland * add audio mode list change flag */ 7604562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 7614562236bSHarry Wentland * stream->stream_engine_id); 7624562236bSHarry Wentland */ 7634562236bSHarry Wentland } 7644562236bSHarry Wentland 7654562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 7664562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets( 7674562236bSHarry Wentland pipe_ctx->stream_enc); 7684562236bSHarry Wentland 7694562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7704562236bSHarry Wentland pipe_ctx->stream_enc->funcs->stop_dp_info_packets( 7714562236bSHarry Wentland pipe_ctx->stream_enc); 7724562236bSHarry Wentland 7734562236bSHarry Wentland pipe_ctx->stream_enc->funcs->audio_mute_control( 7744562236bSHarry Wentland pipe_ctx->stream_enc, true); 7754562236bSHarry Wentland 7764562236bSHarry Wentland 7774562236bSHarry Wentland /* blank at encoder level */ 7784562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7794562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc); 7804562236bSHarry Wentland 7814562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 7824562236bSHarry Wentland link->link_enc, 7834562236bSHarry Wentland pipe_ctx->stream_enc->id, 7844562236bSHarry Wentland false); 7854562236bSHarry Wentland 7864562236bSHarry Wentland } 7874562236bSHarry Wentland 7884562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 7894562236bSHarry Wentland struct dc_link_settings *link_settings) 7904562236bSHarry Wentland { 7914562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 7924562236bSHarry Wentland 7934562236bSHarry Wentland /* only 3 items below are used by unblank */ 7946235b23cSTony Cheng params.pixel_clk_khz = 7954562236bSHarry Wentland pipe_ctx->stream->public.timing.pix_clk_khz; 7964562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 7974562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); 7984562236bSHarry Wentland } 7994562236bSHarry Wentland 8004562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 8014562236bSHarry Wentland { 8024562236bSHarry Wentland switch (crtc_id) { 8034562236bSHarry Wentland case CONTROLLER_ID_D0: 8044562236bSHarry Wentland return DTO_SOURCE_ID0; 8054562236bSHarry Wentland case CONTROLLER_ID_D1: 8064562236bSHarry Wentland return DTO_SOURCE_ID1; 8074562236bSHarry Wentland case CONTROLLER_ID_D2: 8084562236bSHarry Wentland return DTO_SOURCE_ID2; 8094562236bSHarry Wentland case CONTROLLER_ID_D3: 8104562236bSHarry Wentland return DTO_SOURCE_ID3; 8114562236bSHarry Wentland case CONTROLLER_ID_D4: 8124562236bSHarry Wentland return DTO_SOURCE_ID4; 8134562236bSHarry Wentland case CONTROLLER_ID_D5: 8144562236bSHarry Wentland return DTO_SOURCE_ID5; 8154562236bSHarry Wentland default: 8164562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 8174562236bSHarry Wentland } 8184562236bSHarry Wentland } 8194562236bSHarry Wentland 8204562236bSHarry Wentland static void build_audio_output( 8214562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 8224562236bSHarry Wentland struct audio_output *audio_output) 8234562236bSHarry Wentland { 8244562236bSHarry Wentland const struct core_stream *stream = pipe_ctx->stream; 8254562236bSHarry Wentland audio_output->engine_id = pipe_ctx->stream_enc->id; 8264562236bSHarry Wentland 8274562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 8284562236bSHarry Wentland 8294562236bSHarry Wentland /* audio_crtc_info */ 8304562236bSHarry Wentland 8314562236bSHarry Wentland audio_output->crtc_info.h_total = 8324562236bSHarry Wentland stream->public.timing.h_total; 8334562236bSHarry Wentland 8344562236bSHarry Wentland /* 8354562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 8364562236bSHarry Wentland * need to specify actual active signal portion 8374562236bSHarry Wentland */ 8384562236bSHarry Wentland audio_output->crtc_info.h_active = 8394562236bSHarry Wentland stream->public.timing.h_addressable 8404562236bSHarry Wentland + stream->public.timing.h_border_left 8414562236bSHarry Wentland + stream->public.timing.h_border_right; 8424562236bSHarry Wentland 8434562236bSHarry Wentland audio_output->crtc_info.v_active = 8444562236bSHarry Wentland stream->public.timing.v_addressable 8454562236bSHarry Wentland + stream->public.timing.v_border_top 8464562236bSHarry Wentland + stream->public.timing.v_border_bottom; 8474562236bSHarry Wentland 8484562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 8494562236bSHarry Wentland 8504562236bSHarry Wentland audio_output->crtc_info.interlaced = 8514562236bSHarry Wentland stream->public.timing.flags.INTERLACE; 8524562236bSHarry Wentland 8534562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 8544562236bSHarry Wentland (stream->public.timing.pix_clk_khz*1000)/ 8554562236bSHarry Wentland (stream->public.timing.h_total*stream->public.timing.v_total); 8564562236bSHarry Wentland 8574562236bSHarry Wentland audio_output->crtc_info.color_depth = 8584562236bSHarry Wentland stream->public.timing.display_color_depth; 8594562236bSHarry Wentland 8604562236bSHarry Wentland audio_output->crtc_info.requested_pixel_clock = 8614562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 8624562236bSHarry Wentland 8634562236bSHarry Wentland audio_output->crtc_info.calculated_pixel_clock = 8644562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 8654562236bSHarry Wentland 86687b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 86787b58768SCharlene Liu if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && 86887b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock == 86987b58768SCharlene Liu stream->public.timing.pix_clk_khz) { 87087b58768SCharlene Liu if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 87187b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock = 87287b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock/2; 87387b58768SCharlene Liu audio_output->crtc_info.calculated_pixel_clock = 87487b58768SCharlene Liu pipe_ctx->pix_clk_params.requested_pix_clk/2; 87587b58768SCharlene Liu 87687b58768SCharlene Liu } 87787b58768SCharlene Liu } 87887b58768SCharlene Liu 8794562236bSHarry Wentland if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 8804562236bSHarry Wentland pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 8814562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 8821a687574SDmytro Laktyushkin pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency( 8834562236bSHarry Wentland pipe_ctx->dis_clk); 8844562236bSHarry Wentland } 8854562236bSHarry Wentland 8864562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 8874562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 8884562236bSHarry Wentland 8894562236bSHarry Wentland audio_output->pll_info.dto_source = 8904562236bSHarry Wentland translate_to_dto_source( 8914562236bSHarry Wentland pipe_ctx->pipe_idx + 1); 8924562236bSHarry Wentland 8934562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 8944562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 8954562236bSHarry Wentland 8964562236bSHarry Wentland audio_output->pll_info.ss_percentage = 8974562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 8984562236bSHarry Wentland } 8994562236bSHarry Wentland 9004562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 9014562236bSHarry Wentland struct tg_color *color) 9024562236bSHarry Wentland { 9034562236bSHarry Wentland uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4; 9044562236bSHarry Wentland 9054562236bSHarry Wentland switch (pipe_ctx->scl_data.format) { 9064562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 9074562236bSHarry Wentland /* set boarder color to red */ 9084562236bSHarry Wentland color->color_r_cr = color_value; 9094562236bSHarry Wentland break; 9104562236bSHarry Wentland 9114562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 9124562236bSHarry Wentland /* set boarder color to blue */ 9134562236bSHarry Wentland color->color_b_cb = color_value; 9144562236bSHarry Wentland break; 9154562236bSHarry Wentland case PIXEL_FORMAT_420BPP12: 916b2d0a103SDmytro Laktyushkin case PIXEL_FORMAT_420BPP15: 9174562236bSHarry Wentland /* set boarder color to green */ 9184562236bSHarry Wentland color->color_g_y = color_value; 9194562236bSHarry Wentland break; 9204562236bSHarry Wentland case PIXEL_FORMAT_FP16: 9214562236bSHarry Wentland /* set boarder color to white */ 9224562236bSHarry Wentland color->color_r_cr = color_value; 9234562236bSHarry Wentland color->color_b_cb = color_value; 9244562236bSHarry Wentland color->color_g_y = color_value; 9254562236bSHarry Wentland break; 9264562236bSHarry Wentland default: 9274562236bSHarry Wentland break; 9284562236bSHarry Wentland } 9294562236bSHarry Wentland } 9304562236bSHarry Wentland 9314562236bSHarry Wentland static void program_scaler(const struct core_dc *dc, 9324562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 9334562236bSHarry Wentland { 9344562236bSHarry Wentland struct tg_color color = {0}; 9354562236bSHarry Wentland 936ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 937ff5ef992SAlex Deucher /* TOFPGA */ 938ff5ef992SAlex Deucher if (pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth == NULL) 939ff5ef992SAlex Deucher return; 940ff5ef992SAlex Deucher #endif 941ff5ef992SAlex Deucher 9424562236bSHarry Wentland if (dc->public.debug.surface_visual_confirm) 9434562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 9444562236bSHarry Wentland else 9454562236bSHarry Wentland color_space_to_black_color(dc, 9464562236bSHarry Wentland pipe_ctx->stream->public.output_color_space, 9474562236bSHarry Wentland &color); 9484562236bSHarry Wentland 9494562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( 9504562236bSHarry Wentland pipe_ctx->xfm, 9514562236bSHarry Wentland pipe_ctx->scl_data.lb_params.depth, 9524562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 9534562236bSHarry Wentland 9544562236bSHarry Wentland if (pipe_ctx->tg->funcs->set_overscan_blank_color) 9554562236bSHarry Wentland pipe_ctx->tg->funcs->set_overscan_blank_color( 9564562236bSHarry Wentland pipe_ctx->tg, 9574562236bSHarry Wentland &color); 9584562236bSHarry Wentland 9594562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, 9604562236bSHarry Wentland &pipe_ctx->scl_data); 9614562236bSHarry Wentland } 9624562236bSHarry Wentland 9634b5e7d62SHersen Wu static enum dc_status dce110_prog_pixclk_crtc_otg( 9644562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 9654562236bSHarry Wentland struct validate_context *context, 9664562236bSHarry Wentland struct core_dc *dc) 9674562236bSHarry Wentland { 9684562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 9694562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 9704562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 9714562236bSHarry Wentland struct tg_color black_color = {0}; 9724562236bSHarry Wentland 9734562236bSHarry Wentland if (!pipe_ctx_old->stream) { 9744562236bSHarry Wentland 9754562236bSHarry Wentland /* program blank color */ 9764562236bSHarry Wentland color_space_to_black_color(dc, 9774562236bSHarry Wentland stream->public.output_color_space, &black_color); 9784562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank_color( 9794562236bSHarry Wentland pipe_ctx->tg, 9804562236bSHarry Wentland &black_color); 9814b5e7d62SHersen Wu 9824562236bSHarry Wentland /* 9834562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 9844562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 9854562236bSHarry Wentland */ 9864562236bSHarry Wentland pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 9874562236bSHarry Wentland 9884562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 9894562236bSHarry Wentland pipe_ctx->clock_source, 9904562236bSHarry Wentland &pipe_ctx->pix_clk_params, 9914562236bSHarry Wentland &pipe_ctx->pll_settings)) { 9924562236bSHarry Wentland BREAK_TO_DEBUGGER(); 9934562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 9944562236bSHarry Wentland } 9954562236bSHarry Wentland 9964562236bSHarry Wentland pipe_ctx->tg->funcs->program_timing( 9974562236bSHarry Wentland pipe_ctx->tg, 9984562236bSHarry Wentland &stream->public.timing, 9994562236bSHarry Wentland true); 100094267b3dSSylvia Tsai 100194267b3dSSylvia Tsai pipe_ctx->tg->funcs->set_static_screen_control( 100294267b3dSSylvia Tsai pipe_ctx->tg, 100394267b3dSSylvia Tsai 0x182); 10044562236bSHarry Wentland } 10054562236bSHarry Wentland 10064562236bSHarry Wentland if (!pipe_ctx_old->stream) { 10074562236bSHarry Wentland if (false == pipe_ctx->tg->funcs->enable_crtc( 10084562236bSHarry Wentland pipe_ctx->tg)) { 10094562236bSHarry Wentland BREAK_TO_DEBUGGER(); 10104562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 10114562236bSHarry Wentland } 10124562236bSHarry Wentland } 10134562236bSHarry Wentland 101494267b3dSSylvia Tsai 101594267b3dSSylvia Tsai 10164562236bSHarry Wentland return DC_OK; 10174562236bSHarry Wentland } 10184562236bSHarry Wentland 10194562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 10204562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 10214562236bSHarry Wentland struct validate_context *context, 10224562236bSHarry Wentland struct core_dc *dc) 10234562236bSHarry Wentland { 10244562236bSHarry Wentland struct core_stream *stream = pipe_ctx->stream; 10254562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 10264562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 10274562236bSHarry Wentland 10284562236bSHarry Wentland /* */ 10294562236bSHarry Wentland dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); 10304562236bSHarry Wentland 10314562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_dyn_expansion( 10324562236bSHarry Wentland pipe_ctx->opp, 10334562236bSHarry Wentland COLOR_SPACE_YCBCR601, 10344562236bSHarry Wentland stream->public.timing.display_color_depth, 10354562236bSHarry Wentland pipe_ctx->stream->signal); 10364562236bSHarry Wentland 1037181a888fSCharlene Liu /* FPGA does not program backend */ 1038181a888fSCharlene Liu if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 10394562236bSHarry Wentland pipe_ctx->opp->funcs->opp_program_fmt( 10404562236bSHarry Wentland pipe_ctx->opp, 10414562236bSHarry Wentland &stream->bit_depth_params, 10424562236bSHarry Wentland &stream->clamping); 10434562236bSHarry Wentland return DC_OK; 1044181a888fSCharlene Liu } 10454562236bSHarry Wentland /* TODO: move to stream encoder */ 10464562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 10474562236bSHarry Wentland if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { 10484562236bSHarry Wentland BREAK_TO_DEBUGGER(); 10494562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 10504562236bSHarry Wentland } 10514562236bSHarry Wentland 10524562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 10534562236bSHarry Wentland stream->sink->link->link_enc->funcs->setup( 10544562236bSHarry Wentland stream->sink->link->link_enc, 10554562236bSHarry Wentland pipe_ctx->stream->signal); 10564562236bSHarry Wentland 1057ab3c1798SVitaly Prosyak if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 1058ab3c1798SVitaly Prosyak pipe_ctx->stream_enc->funcs->setup_stereo_sync( 1059ab3c1798SVitaly Prosyak pipe_ctx->stream_enc, 1060ab3c1798SVitaly Prosyak pipe_ctx->tg->inst, 1061ab3c1798SVitaly Prosyak stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE); 1062ab3c1798SVitaly Prosyak 1063ab3c1798SVitaly Prosyak 1064181a888fSCharlene Liu /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ 1065181a888fSCharlene Liu pipe_ctx->opp->funcs->opp_program_fmt( 1066181a888fSCharlene Liu pipe_ctx->opp, 1067181a888fSCharlene Liu &stream->bit_depth_params, 1068181a888fSCharlene Liu &stream->clamping); 1069181a888fSCharlene Liu 10704562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10714562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( 10724562236bSHarry Wentland pipe_ctx->stream_enc, 10734562236bSHarry Wentland &stream->public.timing, 10744562236bSHarry Wentland stream->public.output_color_space); 10754562236bSHarry Wentland 10764562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 10774562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( 10784562236bSHarry Wentland pipe_ctx->stream_enc, 10794562236bSHarry Wentland &stream->public.timing, 10804562236bSHarry Wentland stream->phy_pix_clk, 10814562236bSHarry Wentland pipe_ctx->audio != NULL); 10824562236bSHarry Wentland 10834562236bSHarry Wentland if (dc_is_dvi_signal(pipe_ctx->stream->signal)) 10844562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( 10854562236bSHarry Wentland pipe_ctx->stream_enc, 10864562236bSHarry Wentland &stream->public.timing, 10874562236bSHarry Wentland (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? 10884562236bSHarry Wentland true : false); 10894562236bSHarry Wentland 10904562236bSHarry Wentland if (!pipe_ctx_old->stream) { 10914562236bSHarry Wentland core_link_enable_stream(pipe_ctx); 10924562236bSHarry Wentland 1093b3c64dffSCharlene Liu resource_build_info_frame(pipe_ctx); 1094b3c64dffSCharlene Liu dce110_update_info_frame(pipe_ctx); 10954562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10964562236bSHarry Wentland dce110_unblank_stream(pipe_ctx, 10974562236bSHarry Wentland &stream->sink->link->public.cur_link_settings); 10984562236bSHarry Wentland } 10994562236bSHarry Wentland 11004562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 11014562236bSHarry Wentland /* program_scaler and allocate_mem_input are not new asic */ 1102866294f8SHarry Wentland if ((!pipe_ctx_old || 1103866294f8SHarry Wentland memcmp(&pipe_ctx_old->scl_data, &pipe_ctx->scl_data, 1104866294f8SHarry Wentland sizeof(struct scaler_data)) != 0) && 1105866294f8SHarry Wentland pipe_ctx->surface) { 11064562236bSHarry Wentland program_scaler(dc, pipe_ctx); 1107866294f8SHarry Wentland } 11084562236bSHarry Wentland 11094562236bSHarry Wentland /* mst support - use total stream count */ 1110ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1111ff5ef992SAlex Deucher if (pipe_ctx->mi->funcs->allocate_mem_input != NULL) 1112ff5ef992SAlex Deucher #endif 11134562236bSHarry Wentland pipe_ctx->mi->funcs->allocate_mem_input( 11144562236bSHarry Wentland pipe_ctx->mi, 11154562236bSHarry Wentland stream->public.timing.h_total, 11164562236bSHarry Wentland stream->public.timing.v_total, 11174562236bSHarry Wentland stream->public.timing.pix_clk_khz, 1118ab2541b6SAric Cyr context->stream_count); 11194562236bSHarry Wentland 112094267b3dSSylvia Tsai pipe_ctx->stream->sink->link->psr_enabled = false; 112194267b3dSSylvia Tsai 11224562236bSHarry Wentland return DC_OK; 11234562236bSHarry Wentland } 11244562236bSHarry Wentland 11254562236bSHarry Wentland /******************************************************************************/ 11264562236bSHarry Wentland 11274562236bSHarry Wentland static void power_down_encoders(struct core_dc *dc) 11284562236bSHarry Wentland { 11294562236bSHarry Wentland int i; 11304562236bSHarry Wentland 11314562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 11324562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 11334562236bSHarry Wentland dc->links[i]->link_enc, SIGNAL_TYPE_NONE); 11344562236bSHarry Wentland } 11354562236bSHarry Wentland } 11364562236bSHarry Wentland 11374562236bSHarry Wentland static void power_down_controllers(struct core_dc *dc) 11384562236bSHarry Wentland { 11394562236bSHarry Wentland int i; 11404562236bSHarry Wentland 11414562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 11424562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 11434562236bSHarry Wentland dc->res_pool->timing_generators[i]); 11444562236bSHarry Wentland } 11454562236bSHarry Wentland } 11464562236bSHarry Wentland 11474562236bSHarry Wentland static void power_down_clock_sources(struct core_dc *dc) 11484562236bSHarry Wentland { 11494562236bSHarry Wentland int i; 11504562236bSHarry Wentland 11514562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 11524562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 11534562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 11544562236bSHarry Wentland 11554562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 11564562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 11574562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 11584562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 11594562236bSHarry Wentland } 11604562236bSHarry Wentland } 11614562236bSHarry Wentland 11624562236bSHarry Wentland static void power_down_all_hw_blocks(struct core_dc *dc) 11634562236bSHarry Wentland { 11644562236bSHarry Wentland power_down_encoders(dc); 11654562236bSHarry Wentland 11664562236bSHarry Wentland power_down_controllers(dc); 11674562236bSHarry Wentland 11684562236bSHarry Wentland power_down_clock_sources(dc); 11694562236bSHarry Wentland } 11704562236bSHarry Wentland 11714562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 11724562236bSHarry Wentland struct core_dc *dc) 11734562236bSHarry Wentland { 11744562236bSHarry Wentland int i; 11754562236bSHarry Wentland struct timing_generator *tg; 11764562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 11774562236bSHarry Wentland 11784562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 11794562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 11804562236bSHarry Wentland 11814562236bSHarry Wentland tg->funcs->disable_vga(tg); 11824562236bSHarry Wentland 11834562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 11844562236bSHarry Wentland * powergating. */ 11854562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 11864562236bSHarry Wentland true); 11874562236bSHarry Wentland 11884562236bSHarry Wentland dc->hwss.power_down_front_end( 11894562236bSHarry Wentland dc, &dc->current_context->res_ctx.pipe_ctx[i]); 11904562236bSHarry Wentland } 11914562236bSHarry Wentland } 11924562236bSHarry Wentland 11934562236bSHarry Wentland /** 11944562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 11954562236bSHarry Wentland * 1. Power down all DC HW blocks 11964562236bSHarry Wentland * 2. Disable VGA engine on all controllers 11974562236bSHarry Wentland * 3. Enable power gating for controller 11984562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 11994562236bSHarry Wentland */ 12004562236bSHarry Wentland void dce110_enable_accelerated_mode(struct core_dc *dc) 12014562236bSHarry Wentland { 12024562236bSHarry Wentland power_down_all_hw_blocks(dc); 12034562236bSHarry Wentland 12044562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 12054562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 12064562236bSHarry Wentland } 12074562236bSHarry Wentland 12084562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 12094562236bSHarry Wentland struct bw_fixed blackout_duration, 12104562236bSHarry Wentland const struct core_stream *stream) 12114562236bSHarry Wentland { 12124562236bSHarry Wentland uint32_t total_dest_line_time_ns; 12134562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 12144562236bSHarry Wentland 12154562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 12164562236bSHarry Wentland 12174562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 12184562236bSHarry Wentland stream->public.timing.h_total / 12194562236bSHarry Wentland stream->public.timing.pix_clk_khz + 12204562236bSHarry Wentland pstate_blackout_duration_ns; 12214562236bSHarry Wentland 12224562236bSHarry Wentland return total_dest_line_time_ns; 12234562236bSHarry Wentland } 12244562236bSHarry Wentland 12254562236bSHarry Wentland void dce110_set_displaymarks( 12264562236bSHarry Wentland const struct core_dc *dc, 12274562236bSHarry Wentland struct validate_context *context) 12284562236bSHarry Wentland { 12294562236bSHarry Wentland uint8_t i, num_pipes; 12304562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 12314562236bSHarry Wentland 12324562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 12334562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 12344562236bSHarry Wentland uint32_t total_dest_line_time_ns; 12354562236bSHarry Wentland 12364562236bSHarry Wentland if (pipe_ctx->stream == NULL) 12374562236bSHarry Wentland continue; 12384562236bSHarry Wentland 12394562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 12404562236bSHarry Wentland dc->bw_vbios.blackout_duration, pipe_ctx->stream); 12414562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_display_marks( 12424562236bSHarry Wentland pipe_ctx->mi, 12439037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 12449037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 12459037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 12464562236bSHarry Wentland total_dest_line_time_ns); 12474562236bSHarry Wentland if (i == underlay_idx) { 12484562236bSHarry Wentland num_pipes++; 12494562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks( 12504562236bSHarry Wentland pipe_ctx->mi, 12519037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 12529037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 12539037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 12544562236bSHarry Wentland total_dest_line_time_ns); 12554562236bSHarry Wentland } 12564562236bSHarry Wentland num_pipes++; 12574562236bSHarry Wentland } 12584562236bSHarry Wentland } 12594562236bSHarry Wentland 1260a2b8659dSTony Cheng static void set_safe_displaymarks( 1261a2b8659dSTony Cheng struct resource_context *res_ctx, 1262a2b8659dSTony Cheng const struct resource_pool *pool) 12634562236bSHarry Wentland { 12644562236bSHarry Wentland int i; 1265a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 12669037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 12674562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 12689037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 12694562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 12704562236bSHarry Wentland 12714562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 12724562236bSHarry Wentland if (res_ctx->pipe_ctx[i].stream == NULL) 12734562236bSHarry Wentland continue; 12744562236bSHarry Wentland 12754562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks( 12764562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 12774562236bSHarry Wentland nbp_marks, 12784562236bSHarry Wentland max_marks, 12794562236bSHarry Wentland max_marks, 12804562236bSHarry Wentland MAX_WATERMARK); 12814562236bSHarry Wentland if (i == underlay_idx) 12824562236bSHarry Wentland res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_chroma_display_marks( 12834562236bSHarry Wentland res_ctx->pipe_ctx[i].mi, 12844562236bSHarry Wentland nbp_marks, 12854562236bSHarry Wentland max_marks, 12864562236bSHarry Wentland max_marks, 12874562236bSHarry Wentland MAX_WATERMARK); 12884562236bSHarry Wentland } 12894562236bSHarry Wentland } 12904562236bSHarry Wentland 12914562236bSHarry Wentland static void switch_dp_clock_sources( 12924562236bSHarry Wentland const struct core_dc *dc, 12934562236bSHarry Wentland struct resource_context *res_ctx) 12944562236bSHarry Wentland { 12954562236bSHarry Wentland uint8_t i; 12964562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 12974562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 12984562236bSHarry Wentland 12994562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 13004562236bSHarry Wentland continue; 13014562236bSHarry Wentland 13024562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 13034562236bSHarry Wentland struct clock_source *clk_src = 13044562236bSHarry Wentland resource_find_used_clk_src_for_sharing( 13054562236bSHarry Wentland res_ctx, pipe_ctx); 13064562236bSHarry Wentland 13074562236bSHarry Wentland if (clk_src && 13084562236bSHarry Wentland clk_src != pipe_ctx->clock_source) { 13094562236bSHarry Wentland resource_unreference_clock_source( 1310a2b8659dSTony Cheng res_ctx, dc->res_pool, 1311a2b8659dSTony Cheng &pipe_ctx->clock_source); 13124562236bSHarry Wentland pipe_ctx->clock_source = clk_src; 1313a2b8659dSTony Cheng resource_reference_clock_source( 1314a2b8659dSTony Cheng res_ctx, dc->res_pool, clk_src); 13154562236bSHarry Wentland 13164562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i); 13174562236bSHarry Wentland } 13184562236bSHarry Wentland } 13194562236bSHarry Wentland } 13204562236bSHarry Wentland } 13214562236bSHarry Wentland 13224562236bSHarry Wentland /******************************************************************************* 13234562236bSHarry Wentland * Public functions 13244562236bSHarry Wentland ******************************************************************************/ 13254562236bSHarry Wentland 13264562236bSHarry Wentland static void reset_single_pipe_hw_ctx( 13274562236bSHarry Wentland const struct core_dc *dc, 13284562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 13294562236bSHarry Wentland struct validate_context *context) 13304562236bSHarry Wentland { 13314562236bSHarry Wentland core_link_disable_stream(pipe_ctx); 13324b5e7d62SHersen Wu pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true); 13334b5e7d62SHersen Wu if (!hwss_wait_for_blank_complete(pipe_ctx->tg)) { 13344562236bSHarry Wentland dm_error("DC: failed to blank crtc!\n"); 13354562236bSHarry Wentland BREAK_TO_DEBUGGER(); 13364562236bSHarry Wentland } 13374562236bSHarry Wentland pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); 13384562236bSHarry Wentland pipe_ctx->mi->funcs->free_mem_input( 1339ab2541b6SAric Cyr pipe_ctx->mi, context->stream_count); 1340a2b8659dSTony Cheng resource_unreference_clock_source(&context->res_ctx, dc->res_pool, 1341a2b8659dSTony Cheng &pipe_ctx->clock_source); 13424562236bSHarry Wentland 13434562236bSHarry Wentland dc->hwss.power_down_front_end((struct core_dc *)dc, pipe_ctx); 13444562236bSHarry Wentland 13454562236bSHarry Wentland pipe_ctx->stream = NULL; 13464562236bSHarry Wentland } 13474562236bSHarry Wentland 13484562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 13494562236bSHarry Wentland int num_pipes, int vmin, int vmax) 13504562236bSHarry Wentland { 13514562236bSHarry Wentland int i = 0; 13524562236bSHarry Wentland struct drr_params params = {0}; 13534562236bSHarry Wentland 13544562236bSHarry Wentland params.vertical_total_max = vmax; 13554562236bSHarry Wentland params.vertical_total_min = vmin; 13564562236bSHarry Wentland 13574562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 13584562236bSHarry Wentland * some GSL stuff 13594562236bSHarry Wentland */ 13604562236bSHarry Wentland 13614562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 13624562236bSHarry Wentland pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, ¶ms); 13634562236bSHarry Wentland } 13644562236bSHarry Wentland } 13654562236bSHarry Wentland 136672ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 136772ada5f7SEric Cook int num_pipes, 136872ada5f7SEric Cook struct crtc_position *position) 136972ada5f7SEric Cook { 137072ada5f7SEric Cook int i = 0; 137172ada5f7SEric Cook 137272ada5f7SEric Cook /* TODO: handle pipes > 1 137372ada5f7SEric Cook */ 137472ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 137572ada5f7SEric Cook pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position); 137672ada5f7SEric Cook } 137772ada5f7SEric Cook 13784562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 137994267b3dSSylvia Tsai int num_pipes, const struct dc_static_screen_events *events) 13804562236bSHarry Wentland { 13814562236bSHarry Wentland unsigned int i; 138294267b3dSSylvia Tsai unsigned int value = 0; 138394267b3dSSylvia Tsai 138494267b3dSSylvia Tsai if (events->overlay_update) 138594267b3dSSylvia Tsai value |= 0x100; 138694267b3dSSylvia Tsai if (events->surface_update) 138794267b3dSSylvia Tsai value |= 0x80; 138894267b3dSSylvia Tsai if (events->cursor_update) 138994267b3dSSylvia Tsai value |= 0x2; 13904562236bSHarry Wentland 13914562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 13924562236bSHarry Wentland pipe_ctx[i]->tg->funcs-> 13934562236bSHarry Wentland set_static_screen_control(pipe_ctx[i]->tg, value); 13944562236bSHarry Wentland } 13954562236bSHarry Wentland 13964562236bSHarry Wentland /* unit: in_khz before mode set, get pixel clock from context. ASIC register 13974562236bSHarry Wentland * may not be programmed yet. 13984562236bSHarry Wentland * TODO: after mode set, pre_mode_set = false, 13994562236bSHarry Wentland * may read PLL register to get pixel clock 14004562236bSHarry Wentland */ 14014562236bSHarry Wentland static uint32_t get_max_pixel_clock_for_all_paths( 14024562236bSHarry Wentland struct core_dc *dc, 14034562236bSHarry Wentland struct validate_context *context, 14044562236bSHarry Wentland bool pre_mode_set) 14054562236bSHarry Wentland { 14064562236bSHarry Wentland uint32_t max_pix_clk = 0; 14074562236bSHarry Wentland int i; 14084562236bSHarry Wentland 14094562236bSHarry Wentland if (!pre_mode_set) { 14104562236bSHarry Wentland /* TODO: read ASIC register to get pixel clock */ 14114562236bSHarry Wentland ASSERT(0); 14124562236bSHarry Wentland } 14134562236bSHarry Wentland 14144562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 14154562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 14164562236bSHarry Wentland 14174562236bSHarry Wentland if (pipe_ctx->stream == NULL) 14184562236bSHarry Wentland continue; 14194562236bSHarry Wentland 14204562236bSHarry Wentland /* do not check under lay */ 14214562236bSHarry Wentland if (pipe_ctx->top_pipe) 14224562236bSHarry Wentland continue; 14234562236bSHarry Wentland 14244562236bSHarry Wentland if (pipe_ctx->pix_clk_params.requested_pix_clk > max_pix_clk) 14254562236bSHarry Wentland max_pix_clk = 14264562236bSHarry Wentland pipe_ctx->pix_clk_params.requested_pix_clk; 14274562236bSHarry Wentland } 14284562236bSHarry Wentland 14294562236bSHarry Wentland if (max_pix_clk == 0) 14304562236bSHarry Wentland ASSERT(0); 14314562236bSHarry Wentland 14324562236bSHarry Wentland return max_pix_clk; 14334562236bSHarry Wentland } 14344562236bSHarry Wentland 14352c8ad2d5SAlex Deucher /* Find clock state based on clock requested. if clock value is 0, simply 14364562236bSHarry Wentland * set clock state as requested without finding clock state by clock value 14372c8ad2d5SAlex Deucher *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock. 14382c8ad2d5SAlex Deucher * 14392c8ad2d5SAlex Deucher * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value 14402c8ad2d5SAlex Deucher * etc support for dcn1.0 14414562236bSHarry Wentland */ 14424562236bSHarry Wentland static void apply_min_clocks( 14434562236bSHarry Wentland struct core_dc *dc, 14444562236bSHarry Wentland struct validate_context *context, 1445e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state *clocks_state, 14464562236bSHarry Wentland bool pre_mode_set) 14474562236bSHarry Wentland { 14484562236bSHarry Wentland struct state_dependent_clocks req_clocks = {0}; 14494562236bSHarry Wentland struct pipe_ctx *pipe_ctx; 14504562236bSHarry Wentland int i; 14514562236bSHarry Wentland 14524562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 14534562236bSHarry Wentland pipe_ctx = &context->res_ctx.pipe_ctx[i]; 14544562236bSHarry Wentland if (pipe_ctx->dis_clk != NULL) 14554562236bSHarry Wentland break; 14564562236bSHarry Wentland } 14574562236bSHarry Wentland 14584562236bSHarry Wentland if (!pre_mode_set) { 14594562236bSHarry Wentland /* set clock_state without verification */ 14605d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) { 14615d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 14625d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, *clocks_state); 14634562236bSHarry Wentland return; 14645d6d185fSDmytro Laktyushkin } 14654562236bSHarry Wentland 14662c8ad2d5SAlex Deucher /* TODO: This is incorrect. Figure out how to fix. */ 14672c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14682c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14692c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 14702c8ad2d5SAlex Deucher pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz, 14712c8ad2d5SAlex Deucher pre_mode_set, 14722c8ad2d5SAlex Deucher false); 14732c8ad2d5SAlex Deucher 14742c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14752c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14762c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 14772c8ad2d5SAlex Deucher pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz, 14782c8ad2d5SAlex Deucher pre_mode_set, 14792c8ad2d5SAlex Deucher false); 14802c8ad2d5SAlex Deucher 14812c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 14822c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 14832c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 14842c8ad2d5SAlex Deucher pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, 14852c8ad2d5SAlex Deucher pre_mode_set, 14862c8ad2d5SAlex Deucher false); 14872c8ad2d5SAlex Deucher return; 14884562236bSHarry Wentland } 14894562236bSHarry Wentland 14904562236bSHarry Wentland /* get the required state based on state dependent clocks: 14914562236bSHarry Wentland * display clock and pixel clock 14924562236bSHarry Wentland */ 14939037d802SDmytro Laktyushkin req_clocks.display_clk_khz = context->bw.dce.dispclk_khz; 14944562236bSHarry Wentland 14954562236bSHarry Wentland req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( 14964562236bSHarry Wentland dc, context, true); 14974562236bSHarry Wentland 14985d6d185fSDmytro Laktyushkin if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) { 14995d6d185fSDmytro Laktyushkin *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state( 15005d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk, &req_clocks); 15015d6d185fSDmytro Laktyushkin pipe_ctx->dis_clk->funcs->set_min_clocks_state( 15024562236bSHarry Wentland pipe_ctx->dis_clk, *clocks_state); 15034562236bSHarry Wentland } else { 15042c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 15052c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 15062c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 15072c8ad2d5SAlex Deucher req_clocks.display_clk_khz, 15082c8ad2d5SAlex Deucher pre_mode_set, 15092c8ad2d5SAlex Deucher false); 15102c8ad2d5SAlex Deucher 15112c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 15122c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 15132c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 15142c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 15152c8ad2d5SAlex Deucher pre_mode_set, 15162c8ad2d5SAlex Deucher false); 15172c8ad2d5SAlex Deucher 15182c8ad2d5SAlex Deucher pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( 15192c8ad2d5SAlex Deucher pipe_ctx->dis_clk, 15202c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 15212c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 15222c8ad2d5SAlex Deucher pre_mode_set, 15232c8ad2d5SAlex Deucher false); 15244562236bSHarry Wentland } 15254562236bSHarry Wentland } 15264562236bSHarry Wentland 15274562236bSHarry Wentland static enum dc_status apply_ctx_to_hw_fpga( 15284562236bSHarry Wentland struct core_dc *dc, 15294562236bSHarry Wentland struct validate_context *context) 15304562236bSHarry Wentland { 15314562236bSHarry Wentland enum dc_status status = DC_ERROR_UNEXPECTED; 15324562236bSHarry Wentland int i; 15334562236bSHarry Wentland 1534a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 15354562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15364562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15374562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15384562236bSHarry Wentland 15394562236bSHarry Wentland if (pipe_ctx->stream == NULL) 15404562236bSHarry Wentland continue; 15414562236bSHarry Wentland 15424562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) 15434562236bSHarry Wentland continue; 15444562236bSHarry Wentland 15454562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 15464562236bSHarry Wentland pipe_ctx, 15474562236bSHarry Wentland context, 15484562236bSHarry Wentland dc); 15494562236bSHarry Wentland 15504562236bSHarry Wentland if (status != DC_OK) 15514562236bSHarry Wentland return status; 15524562236bSHarry Wentland } 15534562236bSHarry Wentland 15544562236bSHarry Wentland return DC_OK; 15554562236bSHarry Wentland } 15564562236bSHarry Wentland 15574562236bSHarry Wentland static void reset_hw_ctx_wrap( 15584562236bSHarry Wentland struct core_dc *dc, 15594562236bSHarry Wentland struct validate_context *context) 15604562236bSHarry Wentland { 15614562236bSHarry Wentland int i; 15624562236bSHarry Wentland 15634562236bSHarry Wentland /* Reset old context */ 15644562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 1565a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 15664562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 15674562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 15684562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15694562236bSHarry Wentland 15704562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 15714562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 15724562236bSHarry Wentland * PHY when not already disabled. 15734562236bSHarry Wentland */ 15744562236bSHarry Wentland 15754562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 15764562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 15774562236bSHarry Wentland continue; 15784562236bSHarry Wentland 15794562236bSHarry Wentland if (!pipe_ctx->stream || 15804562236bSHarry Wentland pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 15814562236bSHarry Wentland reset_single_pipe_hw_ctx( 15824562236bSHarry Wentland dc, pipe_ctx_old, dc->current_context); 15834562236bSHarry Wentland } 15844562236bSHarry Wentland } 15854562236bSHarry Wentland 1586cf437593SDmytro Laktyushkin 15874562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 15884562236bSHarry Wentland struct core_dc *dc, 15894562236bSHarry Wentland struct validate_context *context) 15904562236bSHarry Wentland { 15914562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 15924562236bSHarry Wentland enum dc_status status; 15934562236bSHarry Wentland int i; 1594e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID; 15954562236bSHarry Wentland 15964562236bSHarry Wentland /* Reset old context */ 15974562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 15984562236bSHarry Wentland dc->hwss.reset_hw_ctx_wrap(dc, context); 15994562236bSHarry Wentland 16004562236bSHarry Wentland /* Skip applying if no targets */ 1601ab2541b6SAric Cyr if (context->stream_count <= 0) 16024562236bSHarry Wentland return DC_OK; 16034562236bSHarry Wentland 16044562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 16054562236bSHarry Wentland apply_ctx_to_hw_fpga(dc, context); 16064562236bSHarry Wentland return DC_OK; 16074562236bSHarry Wentland } 16084562236bSHarry Wentland 16094562236bSHarry Wentland /* Apply new context */ 16104562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 16114562236bSHarry Wentland 16124562236bSHarry Wentland /* below is for real asic only */ 1613a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 16144562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 16154562236bSHarry Wentland &dc->current_context->res_ctx.pipe_ctx[i]; 16164562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 16174562236bSHarry Wentland 16184562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 16194562236bSHarry Wentland continue; 16204562236bSHarry Wentland 16214562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 16224562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 16234562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 16244562236bSHarry Wentland pipe_ctx->clock_source, i); 16254562236bSHarry Wentland continue; 16264562236bSHarry Wentland } 16274562236bSHarry Wentland 16284562236bSHarry Wentland dc->hwss.enable_display_power_gating( 16294562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 16304562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 16314562236bSHarry Wentland } 16324562236bSHarry Wentland 1633a2b8659dSTony Cheng set_safe_displaymarks(&context->res_ctx, dc->res_pool); 16344562236bSHarry Wentland /*TODO: when pplib works*/ 16354562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, true); 16364562236bSHarry Wentland 1637ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1638c8210d5aSHarry Wentland if (dc->ctx->dce_version == DCN_VERSION_1_0) { 16399037d802SDmytro Laktyushkin if (context->bw.dcn.calc_clk.fclk_khz 1640c66a54dcSDmytro Laktyushkin > dc->current_context->bw.dcn.cur_clk.fclk_khz) { 1641ff5ef992SAlex Deucher struct dm_pp_clock_for_voltage_req clock; 1642ff5ef992SAlex Deucher 1643ff5ef992SAlex Deucher clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; 16449037d802SDmytro Laktyushkin clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; 1645ff5ef992SAlex Deucher dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); 1646c66a54dcSDmytro Laktyushkin dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; 1647c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; 1648ff5ef992SAlex Deucher } 16499037d802SDmytro Laktyushkin if (context->bw.dcn.calc_clk.dcfclk_khz 1650c66a54dcSDmytro Laktyushkin > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { 1651ff5ef992SAlex Deucher struct dm_pp_clock_for_voltage_req clock; 1652ff5ef992SAlex Deucher 1653ff5ef992SAlex Deucher clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; 16549037d802SDmytro Laktyushkin clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; 1655ff5ef992SAlex Deucher dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); 1656c66a54dcSDmytro Laktyushkin dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; 1657c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; 1658ff5ef992SAlex Deucher } 1659c66a54dcSDmytro Laktyushkin if (context->bw.dcn.calc_clk.dispclk_khz 1660c66a54dcSDmytro Laktyushkin > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { 1661c66a54dcSDmytro Laktyushkin dc->res_pool->display_clock->funcs->set_clock( 1662c66a54dcSDmytro Laktyushkin dc->res_pool->display_clock, 1663c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz); 1664c66a54dcSDmytro Laktyushkin dc->current_context->bw.dcn.cur_clk.dispclk_khz = 1665c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz; 1666c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.dispclk_khz = 1667c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz; 1668c66a54dcSDmytro Laktyushkin } 1669c66a54dcSDmytro Laktyushkin } else 1670ff5ef992SAlex Deucher #endif 16719037d802SDmytro Laktyushkin if (context->bw.dce.dispclk_khz 16729037d802SDmytro Laktyushkin > dc->current_context->bw.dce.dispclk_khz) { 1673a2b8659dSTony Cheng dc->res_pool->display_clock->funcs->set_clock( 1674a2b8659dSTony Cheng dc->res_pool->display_clock, 16759037d802SDmytro Laktyushkin context->bw.dce.dispclk_khz * 115 / 100); 16761ce71fcdSCharlene Liu } 1677ab8812a3SHersen Wu /* program audio wall clock. use HDMI as clock source if HDMI 1678ab8812a3SHersen Wu * audio active. Otherwise, use DP as clock source 1679ab8812a3SHersen Wu * first, loop to find any HDMI audio, if not, loop find DP audio 1680ab8812a3SHersen Wu */ 16814562236bSHarry Wentland /* Setup audio rate clock source */ 16824562236bSHarry Wentland /* Issue: 16834562236bSHarry Wentland * Audio lag happened on DP monitor when unplug a HDMI monitor 16844562236bSHarry Wentland * 16854562236bSHarry Wentland * Cause: 16864562236bSHarry Wentland * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 16874562236bSHarry Wentland * is set to either dto0 or dto1, audio should work fine. 16884562236bSHarry Wentland * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 16894562236bSHarry Wentland * set to dto0 will cause audio lag. 16904562236bSHarry Wentland * 16914562236bSHarry Wentland * Solution: 16924562236bSHarry Wentland * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 16934562236bSHarry Wentland * find first available pipe with audio, setup audio wall DTO per topology 16944562236bSHarry Wentland * instead of per pipe. 16954562236bSHarry Wentland */ 1696a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 1697ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1698ab8812a3SHersen Wu 1699ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1700ab8812a3SHersen Wu continue; 1701ab8812a3SHersen Wu 1702ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1703ab8812a3SHersen Wu continue; 1704ab8812a3SHersen Wu 1705ab8812a3SHersen Wu if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 1706ab8812a3SHersen Wu continue; 1707ab8812a3SHersen Wu 1708ab8812a3SHersen Wu if (pipe_ctx->audio != NULL) { 1709ab8812a3SHersen Wu struct audio_output audio_output; 1710ab8812a3SHersen Wu 1711ab8812a3SHersen Wu build_audio_output(pipe_ctx, &audio_output); 1712ab8812a3SHersen Wu 1713ab8812a3SHersen Wu pipe_ctx->audio->funcs->wall_dto_setup( 1714ab8812a3SHersen Wu pipe_ctx->audio, 1715ab8812a3SHersen Wu pipe_ctx->stream->signal, 1716ab8812a3SHersen Wu &audio_output.crtc_info, 1717ab8812a3SHersen Wu &audio_output.pll_info); 1718ab8812a3SHersen Wu break; 1719ab8812a3SHersen Wu } 1720ab8812a3SHersen Wu } 1721ab8812a3SHersen Wu 1722ab8812a3SHersen Wu /* no HDMI audio is found, try DP audio */ 1723a2b8659dSTony Cheng if (i == dc->res_pool->pipe_count) { 1724a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 1725ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1726ab8812a3SHersen Wu 1727ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1728ab8812a3SHersen Wu continue; 1729ab8812a3SHersen Wu 1730ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1731ab8812a3SHersen Wu continue; 1732ab8812a3SHersen Wu 1733ab8812a3SHersen Wu if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 1734ab8812a3SHersen Wu continue; 1735ab8812a3SHersen Wu 1736ab8812a3SHersen Wu if (pipe_ctx->audio != NULL) { 1737ab8812a3SHersen Wu struct audio_output audio_output; 1738ab8812a3SHersen Wu 1739ab8812a3SHersen Wu build_audio_output(pipe_ctx, &audio_output); 1740ab8812a3SHersen Wu 1741ab8812a3SHersen Wu pipe_ctx->audio->funcs->wall_dto_setup( 1742ab8812a3SHersen Wu pipe_ctx->audio, 1743ab8812a3SHersen Wu pipe_ctx->stream->signal, 1744ab8812a3SHersen Wu &audio_output.crtc_info, 1745ab8812a3SHersen Wu &audio_output.pll_info); 1746ab8812a3SHersen Wu break; 1747ab8812a3SHersen Wu } 1748ab8812a3SHersen Wu } 1749ab8812a3SHersen Wu } 1750ab8812a3SHersen Wu 1751a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 1752ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 1753ab8812a3SHersen Wu &dc->current_context->res_ctx.pipe_ctx[i]; 1754ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1755ab8812a3SHersen Wu 1756ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 1757ab8812a3SHersen Wu continue; 1758ab8812a3SHersen Wu 1759ab8812a3SHersen Wu if (pipe_ctx->stream == pipe_ctx_old->stream) 1760ab8812a3SHersen Wu continue; 1761ab8812a3SHersen Wu 1762313bf4ffSYongqiang Sun if (pipe_ctx->stream && pipe_ctx_old->stream 1763313bf4ffSYongqiang Sun && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 1764313bf4ffSYongqiang Sun continue; 1765313bf4ffSYongqiang Sun 1766ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 1767ab8812a3SHersen Wu continue; 1768ab8812a3SHersen Wu 1769ab8812a3SHersen Wu if (context->res_ctx.pipe_ctx[i].audio != NULL) { 1770ab8812a3SHersen Wu 17714562236bSHarry Wentland struct audio_output audio_output; 17724562236bSHarry Wentland 17734562236bSHarry Wentland build_audio_output(pipe_ctx, &audio_output); 17744562236bSHarry Wentland 17754562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 17764562236bSHarry Wentland pipe_ctx->stream_enc->funcs->dp_audio_setup( 17774562236bSHarry Wentland pipe_ctx->stream_enc, 17784562236bSHarry Wentland pipe_ctx->audio->inst, 17794562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 17804562236bSHarry Wentland else 17814562236bSHarry Wentland pipe_ctx->stream_enc->funcs->hdmi_audio_setup( 17824562236bSHarry Wentland pipe_ctx->stream_enc, 17834562236bSHarry Wentland pipe_ctx->audio->inst, 17844562236bSHarry Wentland &pipe_ctx->stream->public.audio_info, 17854562236bSHarry Wentland &audio_output.crtc_info); 17864562236bSHarry Wentland 17874562236bSHarry Wentland pipe_ctx->audio->funcs->az_configure( 17884562236bSHarry Wentland pipe_ctx->audio, 17894562236bSHarry Wentland pipe_ctx->stream->signal, 17904562236bSHarry Wentland &audio_output.crtc_info, 17914562236bSHarry Wentland &pipe_ctx->stream->public.audio_info); 17924562236bSHarry Wentland } 17934562236bSHarry Wentland 17944562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 17954562236bSHarry Wentland pipe_ctx, 17964562236bSHarry Wentland context, 17974562236bSHarry Wentland dc); 17984562236bSHarry Wentland 179918f7a1e4SYongqiang Sun if (dc->hwss.power_on_front_end) 180018f7a1e4SYongqiang Sun dc->hwss.power_on_front_end(dc, pipe_ctx, context); 180118f7a1e4SYongqiang Sun 18024562236bSHarry Wentland if (DC_OK != status) 18034562236bSHarry Wentland return status; 18044562236bSHarry Wentland } 18054562236bSHarry Wentland 1806cf437593SDmytro Laktyushkin dc->hwss.set_bandwidth(dc, context, true); 18074562236bSHarry Wentland 18084562236bSHarry Wentland /* to save power */ 18094562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, false); 18104562236bSHarry Wentland 18114562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, false); 18124562236bSHarry Wentland 18134562236bSHarry Wentland switch_dp_clock_sources(dc, &context->res_ctx); 18144562236bSHarry Wentland 1815cf437593SDmytro Laktyushkin 18164562236bSHarry Wentland return DC_OK; 18174562236bSHarry Wentland } 18184562236bSHarry Wentland 18194562236bSHarry Wentland /******************************************************************************* 18204562236bSHarry Wentland * Front End programming 18214562236bSHarry Wentland ******************************************************************************/ 18224562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 18234562236bSHarry Wentland { 18244562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 18254562236bSHarry Wentland 18264562236bSHarry Wentland default_adjust.force_hw_default = false; 18274562236bSHarry Wentland if (pipe_ctx->surface == NULL) 18284562236bSHarry Wentland default_adjust.in_color_space = COLOR_SPACE_SRGB; 18294562236bSHarry Wentland else 18304562236bSHarry Wentland default_adjust.in_color_space = 18314562236bSHarry Wentland pipe_ctx->surface->public.color_space; 18324562236bSHarry Wentland if (pipe_ctx->stream == NULL) 18334562236bSHarry Wentland default_adjust.out_color_space = COLOR_SPACE_SRGB; 18344562236bSHarry Wentland else 18354562236bSHarry Wentland default_adjust.out_color_space = 18364562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 18374562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 18384562236bSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; 18394562236bSHarry Wentland 18404562236bSHarry Wentland /* display color depth */ 18414562236bSHarry Wentland default_adjust.color_depth = 18424562236bSHarry Wentland pipe_ctx->stream->public.timing.display_color_depth; 18434562236bSHarry Wentland 18444562236bSHarry Wentland /* Lb color depth */ 18454562236bSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; 18464562236bSHarry Wentland 18474562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_default( 18484562236bSHarry Wentland pipe_ctx->opp, &default_adjust); 18494562236bSHarry Wentland } 18504562236bSHarry Wentland 1851b06b7680SLeon Elazar 1852b06b7680SLeon Elazar /******************************************************************************* 1853b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 1854b06b7680SLeon Elazar * Blender + CRTC 1855b06b7680SLeon Elazar * 1856b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 1857b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 1858b06b7680SLeon Elazar * 1859b06b7680SLeon Elazar * |----------------------------------------------- | 1860b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 1861b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 1862b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 1863b06b7680SLeon Elazar * |------------------------------------------------| 1864b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 1865b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 1866b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 1867b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 1868b06b7680SLeon Elazar * -------------------------------------------------| 1869b06b7680SLeon Elazar * 1870b06b7680SLeon Elazar ******************************************************************************/ 1871b06b7680SLeon Elazar static void program_surface_visibility(const struct core_dc *dc, 18724562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 18734562236bSHarry Wentland { 18744562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 1875b06b7680SLeon Elazar bool blank_target = false; 18764562236bSHarry Wentland 18774562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 1878b06b7680SLeon Elazar 1879b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 1880b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 1881b06b7680SLeon Elazar 18824562236bSHarry Wentland if (pipe_ctx->bottom_pipe->surface->public.visible) { 18834562236bSHarry Wentland if (pipe_ctx->surface->public.visible) 18844562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 18854562236bSHarry Wentland else 18864562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 1887b06b7680SLeon Elazar 1888b06b7680SLeon Elazar } else if (!pipe_ctx->surface->public.visible) 1889b06b7680SLeon Elazar blank_target = true; 1890b06b7680SLeon Elazar 1891b06b7680SLeon Elazar } else if (!pipe_ctx->surface->public.visible) 1892b06b7680SLeon Elazar blank_target = true; 1893b06b7680SLeon Elazar 18944562236bSHarry Wentland dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); 1895b06b7680SLeon Elazar pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target); 1896b06b7680SLeon Elazar 18974562236bSHarry Wentland } 18984562236bSHarry Wentland 18991bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 19001bf56e62SZeyu Fan { 19011bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 19021bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 19031bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 19041bf56e62SZeyu Fan 19051bf56e62SZeyu Fan 19061bf56e62SZeyu Fan if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 19071bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 19081bf56e62SZeyu Fan adjust.temperature_matrix[0] = 19091bf56e62SZeyu Fan pipe_ctx->stream-> 19101bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[0]; 19111bf56e62SZeyu Fan adjust.temperature_matrix[1] = 19121bf56e62SZeyu Fan pipe_ctx->stream-> 19131bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[1]; 19141bf56e62SZeyu Fan adjust.temperature_matrix[2] = 19151bf56e62SZeyu Fan pipe_ctx->stream-> 19161bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[2]; 19171bf56e62SZeyu Fan adjust.temperature_matrix[3] = 19181bf56e62SZeyu Fan pipe_ctx->stream-> 19191bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[4]; 19201bf56e62SZeyu Fan adjust.temperature_matrix[4] = 19211bf56e62SZeyu Fan pipe_ctx->stream-> 19221bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[5]; 19231bf56e62SZeyu Fan adjust.temperature_matrix[5] = 19241bf56e62SZeyu Fan pipe_ctx->stream-> 19251bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[6]; 19261bf56e62SZeyu Fan adjust.temperature_matrix[6] = 19271bf56e62SZeyu Fan pipe_ctx->stream-> 19281bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[8]; 19291bf56e62SZeyu Fan adjust.temperature_matrix[7] = 19301bf56e62SZeyu Fan pipe_ctx->stream-> 19311bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[9]; 19321bf56e62SZeyu Fan adjust.temperature_matrix[8] = 19331bf56e62SZeyu Fan pipe_ctx->stream-> 19341bf56e62SZeyu Fan public.gamut_remap_matrix.matrix[10]; 19351bf56e62SZeyu Fan } 19361bf56e62SZeyu Fan 19371bf56e62SZeyu Fan pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 19381bf56e62SZeyu Fan } 19391bf56e62SZeyu Fan 19404562236bSHarry Wentland /** 19414562236bSHarry Wentland * TODO REMOVE, USE UPDATE INSTEAD 19424562236bSHarry Wentland */ 19434562236bSHarry Wentland static void set_plane_config( 19444562236bSHarry Wentland const struct core_dc *dc, 19454562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 19464562236bSHarry Wentland struct resource_context *res_ctx) 19474562236bSHarry Wentland { 19484562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 19494562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 19504562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 19514562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 19524562236bSHarry Wentland unsigned int i; 19534562236bSHarry Wentland 19544562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 19554562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 19564562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 19574562236bSHarry Wentland 19584562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 19594562236bSHarry Wentland 19604562236bSHarry Wentland set_default_colors(pipe_ctx); 19614562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 19624562236bSHarry Wentland == true) { 19634562236bSHarry Wentland tbl_entry.color_space = 19644562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 19654562236bSHarry Wentland 19664562236bSHarry Wentland for (i = 0; i < 12; i++) 19674562236bSHarry Wentland tbl_entry.regval[i] = 19684562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 19694562236bSHarry Wentland 19704562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 19714562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 19724562236bSHarry Wentland } 19734562236bSHarry Wentland 19744562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 19754562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 19764562236bSHarry Wentland adjust.temperature_matrix[0] = 19774562236bSHarry Wentland pipe_ctx->stream-> 19784562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 19794562236bSHarry Wentland adjust.temperature_matrix[1] = 19804562236bSHarry Wentland pipe_ctx->stream-> 19814562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 19824562236bSHarry Wentland adjust.temperature_matrix[2] = 19834562236bSHarry Wentland pipe_ctx->stream-> 19844562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 19854562236bSHarry Wentland adjust.temperature_matrix[3] = 19864562236bSHarry Wentland pipe_ctx->stream-> 19874562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 19884562236bSHarry Wentland adjust.temperature_matrix[4] = 19894562236bSHarry Wentland pipe_ctx->stream-> 19904562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 19914562236bSHarry Wentland adjust.temperature_matrix[5] = 19924562236bSHarry Wentland pipe_ctx->stream-> 19934562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 19944562236bSHarry Wentland adjust.temperature_matrix[6] = 19954562236bSHarry Wentland pipe_ctx->stream-> 19964562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 19974562236bSHarry Wentland adjust.temperature_matrix[7] = 19984562236bSHarry Wentland pipe_ctx->stream-> 19994562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 20004562236bSHarry Wentland adjust.temperature_matrix[8] = 20014562236bSHarry Wentland pipe_ctx->stream-> 20024562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 20034562236bSHarry Wentland } 20044562236bSHarry Wentland 20054562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 20064562236bSHarry Wentland 20074562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 20084562236bSHarry Wentland program_scaler(dc, pipe_ctx); 20094562236bSHarry Wentland 2010b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 20114562236bSHarry Wentland 20124562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 20134562236bSHarry Wentland mi, 20144562236bSHarry Wentland surface->public.format, 20154562236bSHarry Wentland &surface->public.tiling_info, 20164562236bSHarry Wentland &surface->public.plane_size, 20174562236bSHarry Wentland surface->public.rotation, 20184562236bSHarry Wentland NULL, 20194b28b76bSDmytro Laktyushkin false); 20204b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 20214b28b76bSDmytro Laktyushkin mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible); 20224562236bSHarry Wentland 20234562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 20244562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 20254562236bSHarry Wentland pipe_ctx->mi, 20264562236bSHarry Wentland surface->public.format, 20274562236bSHarry Wentland &surface->public.tiling_info, 20284562236bSHarry Wentland surface->public.rotation); 20294562236bSHarry Wentland } 20304562236bSHarry Wentland 20314562236bSHarry Wentland static void update_plane_addr(const struct core_dc *dc, 20324562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 20334562236bSHarry Wentland { 20344562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 20354562236bSHarry Wentland 20364562236bSHarry Wentland if (surface == NULL) 20374562236bSHarry Wentland return; 20384562236bSHarry Wentland 20394562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( 20404562236bSHarry Wentland pipe_ctx->mi, 20414562236bSHarry Wentland &surface->public.address, 20424562236bSHarry Wentland surface->public.flip_immediate); 20434562236bSHarry Wentland 20444562236bSHarry Wentland surface->status.requested_address = surface->public.address; 20454562236bSHarry Wentland } 20464562236bSHarry Wentland 20474562236bSHarry Wentland void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 20484562236bSHarry Wentland { 20494562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 20504562236bSHarry Wentland 20514562236bSHarry Wentland if (surface == NULL) 20524562236bSHarry Wentland return; 20534562236bSHarry Wentland 20544562236bSHarry Wentland surface->status.is_flip_pending = 20554562236bSHarry Wentland pipe_ctx->mi->funcs->mem_input_is_flip_pending( 20564562236bSHarry Wentland pipe_ctx->mi); 20574562236bSHarry Wentland 20584562236bSHarry Wentland if (surface->status.is_flip_pending && !surface->public.visible) 20594562236bSHarry Wentland pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; 20604562236bSHarry Wentland 20614562236bSHarry Wentland surface->status.current_address = pipe_ctx->mi->current_address; 20627f5c22d1SVitaly Prosyak if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 20637f5c22d1SVitaly Prosyak pipe_ctx->tg->funcs->is_stereo_left_eye) { 20647f5c22d1SVitaly Prosyak surface->status.is_right_eye =\ 20657f5c22d1SVitaly Prosyak !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg); 20667f5c22d1SVitaly Prosyak } 20674562236bSHarry Wentland } 20684562236bSHarry Wentland 20694562236bSHarry Wentland void dce110_power_down(struct core_dc *dc) 20704562236bSHarry Wentland { 20714562236bSHarry Wentland power_down_all_hw_blocks(dc); 20724562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 20734562236bSHarry Wentland } 20744562236bSHarry Wentland 20754562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 20764562236bSHarry Wentland struct dc_context *dc_ctx, 20774562236bSHarry Wentland struct timing_generator *tg) 20784562236bSHarry Wentland { 20794562236bSHarry Wentland bool rc = false; 20804562236bSHarry Wentland 20814562236bSHarry Wentland /* To avoid endless loop we wait at most 20824562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 20834562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 20844562236bSHarry Wentland uint32_t i; 20854562236bSHarry Wentland 20864562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 20874562236bSHarry Wentland 20884562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 20894562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 20904562236bSHarry Wentland break; 20914562236bSHarry Wentland } 20924562236bSHarry Wentland 20934562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 20944562236bSHarry Wentland rc = true; 20954562236bSHarry Wentland /* usually occurs at i=1 */ 20964562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 20974562236bSHarry Wentland i); 20984562236bSHarry Wentland break; 20994562236bSHarry Wentland } 21004562236bSHarry Wentland 21014562236bSHarry Wentland /* Wait for one frame. */ 21024562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 21034562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 21044562236bSHarry Wentland } 21054562236bSHarry Wentland 21064562236bSHarry Wentland if (false == rc) 21074562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 21084562236bSHarry Wentland 21094562236bSHarry Wentland return rc; 21104562236bSHarry Wentland } 21114562236bSHarry Wentland 21124562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 21134562236bSHarry Wentland static void dce110_enable_timing_synchronization( 21144562236bSHarry Wentland struct core_dc *dc, 21154562236bSHarry Wentland int group_index, 21164562236bSHarry Wentland int group_size, 21174562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 21184562236bSHarry Wentland { 21194562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 21204562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 21214562236bSHarry Wentland int i; 21224562236bSHarry Wentland 21234562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 21244562236bSHarry Wentland 21254562236bSHarry Wentland /* Designate a single TG in the group as a master. 21264562236bSHarry Wentland * Since HW doesn't care which one, we always assign 21274562236bSHarry Wentland * the 1st one in the group. */ 21284562236bSHarry Wentland gsl_params.gsl_group = 0; 21294562236bSHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->tg->inst; 21304562236bSHarry Wentland 21314562236bSHarry Wentland for (i = 0; i < group_size; i++) 21324562236bSHarry Wentland grouped_pipes[i]->tg->funcs->setup_global_swap_lock( 21334562236bSHarry Wentland grouped_pipes[i]->tg, &gsl_params); 21344562236bSHarry Wentland 21354562236bSHarry Wentland /* Reset slave controllers on master VSync */ 21364562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 21374562236bSHarry Wentland 21384562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 21394562236bSHarry Wentland grouped_pipes[i]->tg->funcs->enable_reset_trigger( 21404562236bSHarry Wentland grouped_pipes[i]->tg, gsl_params.gsl_group); 21414562236bSHarry Wentland 21424562236bSHarry Wentland 21434562236bSHarry Wentland 21444562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 21454562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 21464562236bSHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg); 21474562236bSHarry Wentland /* Regardless of success of the wait above, remove the reset or 21484562236bSHarry Wentland * the driver will start timing out on Display requests. */ 21494562236bSHarry Wentland DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); 21504562236bSHarry Wentland grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg); 21514562236bSHarry Wentland } 21524562236bSHarry Wentland 21534562236bSHarry Wentland 21544562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 21554562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 21564562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 21574562236bSHarry Wentland for (i = 0; i < group_size; i++) 21584562236bSHarry Wentland grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg); 21594562236bSHarry Wentland 21604562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 21614562236bSHarry Wentland } 21624562236bSHarry Wentland 21634562236bSHarry Wentland static void init_hw(struct core_dc *dc) 21644562236bSHarry Wentland { 21654562236bSHarry Wentland int i; 21664562236bSHarry Wentland struct dc_bios *bp; 21674562236bSHarry Wentland struct transform *xfm; 21685e7773a2SAnthony Koo struct abm *abm; 21694562236bSHarry Wentland 21704562236bSHarry Wentland bp = dc->ctx->dc_bios; 21714562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 21724562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 21734562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 21744562236bSHarry Wentland 21754562236bSHarry Wentland dc->hwss.enable_display_power_gating( 21764562236bSHarry Wentland dc, i, bp, 21774562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 21784562236bSHarry Wentland dc->hwss.enable_display_power_gating( 21794562236bSHarry Wentland dc, i, bp, 21804562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 21814562236bSHarry Wentland dc->hwss.enable_display_pipe_clock_gating( 21824562236bSHarry Wentland dc->ctx, 21834562236bSHarry Wentland true); 21844562236bSHarry Wentland } 21854562236bSHarry Wentland 2186e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 21874562236bSHarry Wentland /***************************************/ 21884562236bSHarry Wentland 21894562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 21904562236bSHarry Wentland /****************************************/ 21914562236bSHarry Wentland /* Power up AND update implementation according to the 21924562236bSHarry Wentland * required signal (which may be different from the 21934562236bSHarry Wentland * default signal on connector). */ 21944562236bSHarry Wentland struct core_link *link = dc->links[i]; 21954562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 21964562236bSHarry Wentland } 21974562236bSHarry Wentland 21984562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 21994562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 22004562236bSHarry Wentland 22014562236bSHarry Wentland tg->funcs->disable_vga(tg); 22024562236bSHarry Wentland 22034562236bSHarry Wentland /* Blank controller using driver code instead of 22044562236bSHarry Wentland * command table. */ 22054562236bSHarry Wentland tg->funcs->set_blank(tg, true); 22064b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 22074562236bSHarry Wentland } 22084562236bSHarry Wentland 22094562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 22104562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 22114562236bSHarry Wentland audio->funcs->hw_init(audio); 22124562236bSHarry Wentland } 22135e7773a2SAnthony Koo 22145e7773a2SAnthony Koo abm = dc->res_pool->abm; 22156728b30cSAnthony Koo if (abm != NULL) { 22166728b30cSAnthony Koo abm->funcs->init_backlight(abm); 22175e7773a2SAnthony Koo abm->funcs->abm_init(abm); 22184562236bSHarry Wentland } 22196728b30cSAnthony Koo } 22204562236bSHarry Wentland 222128f72454SJordan Lazare void dce110_fill_display_configs( 2222cf437593SDmytro Laktyushkin const struct validate_context *context, 2223cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg) 22244562236bSHarry Wentland { 2225cf437593SDmytro Laktyushkin int j; 2226cf437593SDmytro Laktyushkin int num_cfgs = 0; 2227cf437593SDmytro Laktyushkin 2228cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 2229cf437593SDmytro Laktyushkin int k; 2230cf437593SDmytro Laktyushkin 2231cf437593SDmytro Laktyushkin const struct core_stream *stream = context->streams[j]; 2232cf437593SDmytro Laktyushkin struct dm_pp_single_disp_config *cfg = 2233cf437593SDmytro Laktyushkin &pp_display_cfg->disp_configs[num_cfgs]; 2234cf437593SDmytro Laktyushkin const struct pipe_ctx *pipe_ctx = NULL; 2235cf437593SDmytro Laktyushkin 2236cf437593SDmytro Laktyushkin for (k = 0; k < MAX_PIPES; k++) 2237cf437593SDmytro Laktyushkin if (stream == context->res_ctx.pipe_ctx[k].stream) { 2238cf437593SDmytro Laktyushkin pipe_ctx = &context->res_ctx.pipe_ctx[k]; 2239cf437593SDmytro Laktyushkin break; 22404562236bSHarry Wentland } 22414562236bSHarry Wentland 2242cf437593SDmytro Laktyushkin ASSERT(pipe_ctx != NULL); 2243cf437593SDmytro Laktyushkin 2244cf437593SDmytro Laktyushkin num_cfgs++; 2245cf437593SDmytro Laktyushkin cfg->signal = pipe_ctx->stream->signal; 2246cf437593SDmytro Laktyushkin cfg->pipe_idx = pipe_ctx->pipe_idx; 2247cf437593SDmytro Laktyushkin cfg->src_height = stream->public.src.height; 2248cf437593SDmytro Laktyushkin cfg->src_width = stream->public.src.width; 2249cf437593SDmytro Laktyushkin cfg->ddi_channel_mapping = 2250cf437593SDmytro Laktyushkin stream->sink->link->ddi_channel_mapping.raw; 2251cf437593SDmytro Laktyushkin cfg->transmitter = 2252cf437593SDmytro Laktyushkin stream->sink->link->link_enc->transmitter; 2253cf437593SDmytro Laktyushkin cfg->link_settings.lane_count = 2254cf437593SDmytro Laktyushkin stream->sink->link->public.cur_link_settings.lane_count; 2255cf437593SDmytro Laktyushkin cfg->link_settings.link_rate = 2256cf437593SDmytro Laktyushkin stream->sink->link->public.cur_link_settings.link_rate; 2257cf437593SDmytro Laktyushkin cfg->link_settings.link_spread = 2258cf437593SDmytro Laktyushkin stream->sink->link->public.cur_link_settings.link_spread; 2259cf437593SDmytro Laktyushkin cfg->sym_clock = stream->phy_pix_clk; 2260cf437593SDmytro Laktyushkin /* Round v_refresh*/ 2261cf437593SDmytro Laktyushkin cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; 2262cf437593SDmytro Laktyushkin cfg->v_refresh /= stream->public.timing.h_total; 2263cf437593SDmytro Laktyushkin cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) 2264cf437593SDmytro Laktyushkin / stream->public.timing.v_total; 2265cf437593SDmytro Laktyushkin } 2266cf437593SDmytro Laktyushkin 2267cf437593SDmytro Laktyushkin pp_display_cfg->display_count = num_cfgs; 2268cf437593SDmytro Laktyushkin } 2269cf437593SDmytro Laktyushkin 227028f72454SJordan Lazare uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) 2271cf437593SDmytro Laktyushkin { 2272cf437593SDmytro Laktyushkin uint8_t j; 2273cf437593SDmytro Laktyushkin uint32_t min_vertical_blank_time = -1; 2274cf437593SDmytro Laktyushkin 2275cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 2276cf437593SDmytro Laktyushkin const struct dc_stream *stream = &context->streams[j]->public; 2277cf437593SDmytro Laktyushkin uint32_t vertical_blank_in_pixels = 0; 2278cf437593SDmytro Laktyushkin uint32_t vertical_blank_time = 0; 2279cf437593SDmytro Laktyushkin 2280cf437593SDmytro Laktyushkin vertical_blank_in_pixels = stream->timing.h_total * 2281cf437593SDmytro Laktyushkin (stream->timing.v_total 2282cf437593SDmytro Laktyushkin - stream->timing.v_addressable); 2283cf437593SDmytro Laktyushkin 2284cf437593SDmytro Laktyushkin vertical_blank_time = vertical_blank_in_pixels 2285cf437593SDmytro Laktyushkin * 1000 / stream->timing.pix_clk_khz; 2286cf437593SDmytro Laktyushkin 2287cf437593SDmytro Laktyushkin if (min_vertical_blank_time > vertical_blank_time) 2288cf437593SDmytro Laktyushkin min_vertical_blank_time = vertical_blank_time; 2289cf437593SDmytro Laktyushkin } 2290cf437593SDmytro Laktyushkin 2291cf437593SDmytro Laktyushkin return min_vertical_blank_time; 2292cf437593SDmytro Laktyushkin } 2293cf437593SDmytro Laktyushkin 2294cf437593SDmytro Laktyushkin static int determine_sclk_from_bounding_box( 2295cf437593SDmytro Laktyushkin const struct core_dc *dc, 2296cf437593SDmytro Laktyushkin int required_sclk) 22974562236bSHarry Wentland { 22984562236bSHarry Wentland int i; 22994562236bSHarry Wentland 2300cf437593SDmytro Laktyushkin /* 2301cf437593SDmytro Laktyushkin * Some asics do not give us sclk levels, so we just report the actual 2302cf437593SDmytro Laktyushkin * required sclk 2303cf437593SDmytro Laktyushkin */ 2304cf437593SDmytro Laktyushkin if (dc->sclk_lvls.num_levels == 0) 2305cf437593SDmytro Laktyushkin return required_sclk; 23064562236bSHarry Wentland 2307cf437593SDmytro Laktyushkin for (i = 0; i < dc->sclk_lvls.num_levels; i++) { 2308cf437593SDmytro Laktyushkin if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) 2309cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[i]; 2310cf437593SDmytro Laktyushkin } 2311cf437593SDmytro Laktyushkin /* 2312cf437593SDmytro Laktyushkin * even maximum level could not satisfy requirement, this 2313cf437593SDmytro Laktyushkin * is unexpected at this stage, should have been caught at 2314cf437593SDmytro Laktyushkin * validation time 2315cf437593SDmytro Laktyushkin */ 2316cf437593SDmytro Laktyushkin ASSERT(0); 2317cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; 23184562236bSHarry Wentland } 23194562236bSHarry Wentland 2320cf437593SDmytro Laktyushkin static void pplib_apply_display_requirements( 2321cf437593SDmytro Laktyushkin struct core_dc *dc, 2322cf437593SDmytro Laktyushkin struct validate_context *context) 2323cf437593SDmytro Laktyushkin { 2324cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 2325cf437593SDmytro Laktyushkin 2326cf437593SDmytro Laktyushkin pp_display_cfg->all_displays_in_sync = 23279037d802SDmytro Laktyushkin context->bw.dce.all_displays_in_sync; 2328cf437593SDmytro Laktyushkin pp_display_cfg->nb_pstate_switch_disable = 23299037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_enable == false; 2330cf437593SDmytro Laktyushkin pp_display_cfg->cpu_cc6_disable = 23319037d802SDmytro Laktyushkin context->bw.dce.cpuc_state_change_enable == false; 2332cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_disable = 23339037d802SDmytro Laktyushkin context->bw.dce.cpup_state_change_enable == false; 2334cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_separation_time = 23359037d802SDmytro Laktyushkin context->bw.dce.blackout_recovery_time_us; 2336cf437593SDmytro Laktyushkin 23379037d802SDmytro Laktyushkin pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz 2338cf437593SDmytro Laktyushkin / MEMORY_TYPE_MULTIPLIER; 2339cf437593SDmytro Laktyushkin 2340cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( 2341cf437593SDmytro Laktyushkin dc, 23429037d802SDmytro Laktyushkin context->bw.dce.sclk_khz); 2343cf437593SDmytro Laktyushkin 2344cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_deep_sleep_khz 23459037d802SDmytro Laktyushkin = context->bw.dce.sclk_deep_sleep_khz; 2346cf437593SDmytro Laktyushkin 2347cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_us = 234828f72454SJordan Lazare dce110_get_min_vblank_time_us(context); 2349cf437593SDmytro Laktyushkin /* TODO: dce11.2*/ 2350cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; 2351cf437593SDmytro Laktyushkin 23529037d802SDmytro Laktyushkin pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz; 2353cf437593SDmytro Laktyushkin 235428f72454SJordan Lazare dce110_fill_display_configs(context, pp_display_cfg); 2355cf437593SDmytro Laktyushkin 2356cf437593SDmytro Laktyushkin /* TODO: is this still applicable?*/ 2357cf437593SDmytro Laktyushkin if (pp_display_cfg->display_count == 1) { 2358cf437593SDmytro Laktyushkin const struct dc_crtc_timing *timing = 2359cf437593SDmytro Laktyushkin &context->streams[0]->public.timing; 2360cf437593SDmytro Laktyushkin 2361cf437593SDmytro Laktyushkin pp_display_cfg->crtc_index = 2362cf437593SDmytro Laktyushkin pp_display_cfg->disp_configs[0].pipe_idx; 2363cf437593SDmytro Laktyushkin pp_display_cfg->line_time_in_us = timing->h_total * 1000 2364cf437593SDmytro Laktyushkin / timing->pix_clk_khz; 2365cf437593SDmytro Laktyushkin } 2366cf437593SDmytro Laktyushkin 2367cf437593SDmytro Laktyushkin if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( 2368cf437593SDmytro Laktyushkin struct dm_pp_display_configuration)) != 0) 2369cf437593SDmytro Laktyushkin dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); 2370cf437593SDmytro Laktyushkin 2371cf437593SDmytro Laktyushkin dc->prev_display_config = *pp_display_cfg; 2372cf437593SDmytro Laktyushkin } 2373cf437593SDmytro Laktyushkin 2374cf437593SDmytro Laktyushkin static void dce110_set_bandwidth( 2375cf437593SDmytro Laktyushkin struct core_dc *dc, 2376cf437593SDmytro Laktyushkin struct validate_context *context, 2377cf437593SDmytro Laktyushkin bool decrease_allowed) 2378cf437593SDmytro Laktyushkin { 23792180e7ccSDmytro Laktyushkin dce110_set_displaymarks(dc, context); 2380cf437593SDmytro Laktyushkin 23819037d802SDmytro Laktyushkin if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { 2382a2b8659dSTony Cheng dc->res_pool->display_clock->funcs->set_clock( 2383a2b8659dSTony Cheng dc->res_pool->display_clock, 23849037d802SDmytro Laktyushkin context->bw.dce.dispclk_khz * 115 / 100); 23859037d802SDmytro Laktyushkin dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; 2386cf437593SDmytro Laktyushkin } 2387cf437593SDmytro Laktyushkin 2388cf437593SDmytro Laktyushkin pplib_apply_display_requirements(dc, context); 23894562236bSHarry Wentland } 23904562236bSHarry Wentland 23914562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 23924562236bSHarry Wentland struct core_dc *dc, struct pipe_ctx *pipe_ctx) 23934562236bSHarry Wentland { 23944562236bSHarry Wentland struct mem_input *mi = pipe_ctx->mi; 23954562236bSHarry Wentland struct pipe_ctx *old_pipe = NULL; 23964562236bSHarry Wentland struct core_surface *surface = pipe_ctx->surface; 23974562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 23984562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 23994562236bSHarry Wentland unsigned int i; 24004562236bSHarry Wentland 24014562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 24024562236bSHarry Wentland 24034562236bSHarry Wentland if (dc->current_context) 24044562236bSHarry Wentland old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 24054562236bSHarry Wentland 24064562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 24074562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 24084562236bSHarry Wentland 24094562236bSHarry Wentland dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); 24104562236bSHarry Wentland 24114562236bSHarry Wentland set_default_colors(pipe_ctx); 24124562236bSHarry Wentland if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment 24134562236bSHarry Wentland == true) { 24144562236bSHarry Wentland tbl_entry.color_space = 24154562236bSHarry Wentland pipe_ctx->stream->public.output_color_space; 24164562236bSHarry Wentland 24174562236bSHarry Wentland for (i = 0; i < 12; i++) 24184562236bSHarry Wentland tbl_entry.regval[i] = 24194562236bSHarry Wentland pipe_ctx->stream->public.csc_color_matrix.matrix[i]; 24204562236bSHarry Wentland 24214562236bSHarry Wentland pipe_ctx->opp->funcs->opp_set_csc_adjustment 24224562236bSHarry Wentland (pipe_ctx->opp, &tbl_entry); 24234562236bSHarry Wentland } 24244562236bSHarry Wentland 24254562236bSHarry Wentland if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { 24264562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 24274562236bSHarry Wentland adjust.temperature_matrix[0] = 24284562236bSHarry Wentland pipe_ctx->stream-> 24294562236bSHarry Wentland public.gamut_remap_matrix.matrix[0]; 24304562236bSHarry Wentland adjust.temperature_matrix[1] = 24314562236bSHarry Wentland pipe_ctx->stream-> 24324562236bSHarry Wentland public.gamut_remap_matrix.matrix[1]; 24334562236bSHarry Wentland adjust.temperature_matrix[2] = 24344562236bSHarry Wentland pipe_ctx->stream-> 24354562236bSHarry Wentland public.gamut_remap_matrix.matrix[2]; 24364562236bSHarry Wentland adjust.temperature_matrix[3] = 24374562236bSHarry Wentland pipe_ctx->stream-> 24384562236bSHarry Wentland public.gamut_remap_matrix.matrix[4]; 24394562236bSHarry Wentland adjust.temperature_matrix[4] = 24404562236bSHarry Wentland pipe_ctx->stream-> 24414562236bSHarry Wentland public.gamut_remap_matrix.matrix[5]; 24424562236bSHarry Wentland adjust.temperature_matrix[5] = 24434562236bSHarry Wentland pipe_ctx->stream-> 24444562236bSHarry Wentland public.gamut_remap_matrix.matrix[6]; 24454562236bSHarry Wentland adjust.temperature_matrix[6] = 24464562236bSHarry Wentland pipe_ctx->stream-> 24474562236bSHarry Wentland public.gamut_remap_matrix.matrix[8]; 24484562236bSHarry Wentland adjust.temperature_matrix[7] = 24494562236bSHarry Wentland pipe_ctx->stream-> 24504562236bSHarry Wentland public.gamut_remap_matrix.matrix[9]; 24514562236bSHarry Wentland adjust.temperature_matrix[8] = 24524562236bSHarry Wentland pipe_ctx->stream-> 24534562236bSHarry Wentland public.gamut_remap_matrix.matrix[10]; 24544562236bSHarry Wentland } 24554562236bSHarry Wentland 24564562236bSHarry Wentland pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); 24574562236bSHarry Wentland 24584562236bSHarry Wentland pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2459c1473558SAndrey Grodzovsky 24604562236bSHarry Wentland program_scaler(dc, pipe_ctx); 24614562236bSHarry Wentland 24624562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 24634562236bSHarry Wentland mi, 24644562236bSHarry Wentland surface->public.format, 24654562236bSHarry Wentland &surface->public.tiling_info, 24664562236bSHarry Wentland &surface->public.plane_size, 24674562236bSHarry Wentland surface->public.rotation, 2468624d7c47SYongqiang Sun NULL, 24694b28b76bSDmytro Laktyushkin false); 24704b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 24714b28b76bSDmytro Laktyushkin mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible); 24724562236bSHarry Wentland 24734562236bSHarry Wentland if (dc->public.config.gpu_vm_support) 24744562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 24754562236bSHarry Wentland pipe_ctx->mi, 24764562236bSHarry Wentland surface->public.format, 24774562236bSHarry Wentland &surface->public.tiling_info, 24784562236bSHarry Wentland surface->public.rotation); 24794562236bSHarry Wentland 24804562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 24814562236bSHarry Wentland "Pipe:%d 0x%x: addr hi:0x%x, " 24824562236bSHarry Wentland "addr low:0x%x, " 24834562236bSHarry Wentland "src: %d, %d, %d," 24844562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 24854562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 24864562236bSHarry Wentland pipe_ctx->pipe_idx, 24874562236bSHarry Wentland pipe_ctx->surface, 24884562236bSHarry Wentland pipe_ctx->surface->public.address.grph.addr.high_part, 24894562236bSHarry Wentland pipe_ctx->surface->public.address.grph.addr.low_part, 24904562236bSHarry Wentland pipe_ctx->surface->public.src_rect.x, 24914562236bSHarry Wentland pipe_ctx->surface->public.src_rect.y, 24924562236bSHarry Wentland pipe_ctx->surface->public.src_rect.width, 24934562236bSHarry Wentland pipe_ctx->surface->public.src_rect.height, 24944562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.x, 24954562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.y, 24964562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.width, 24974562236bSHarry Wentland pipe_ctx->surface->public.dst_rect.height, 24984562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.x, 24994562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.y, 25004562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.width, 25014562236bSHarry Wentland pipe_ctx->surface->public.clip_rect.height); 25024562236bSHarry Wentland 25034562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 25044562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 25054562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 25064562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 25074562236bSHarry Wentland pipe_ctx->pipe_idx, 25084562236bSHarry Wentland pipe_ctx->scl_data.viewport.width, 25094562236bSHarry Wentland pipe_ctx->scl_data.viewport.height, 25104562236bSHarry Wentland pipe_ctx->scl_data.viewport.x, 25114562236bSHarry Wentland pipe_ctx->scl_data.viewport.y, 25124562236bSHarry Wentland pipe_ctx->scl_data.recout.width, 25134562236bSHarry Wentland pipe_ctx->scl_data.recout.height, 25144562236bSHarry Wentland pipe_ctx->scl_data.recout.x, 25154562236bSHarry Wentland pipe_ctx->scl_data.recout.y); 25164562236bSHarry Wentland } 25174562236bSHarry Wentland 25184562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 25194562236bSHarry Wentland struct core_dc *dc, 25204562236bSHarry Wentland struct core_surface *surface, 25214562236bSHarry Wentland struct validate_context *context) 25224562236bSHarry Wentland { 25234562236bSHarry Wentland int i; 25244562236bSHarry Wentland 25254562236bSHarry Wentland /* TODO remove when removing the surface reset workaroud*/ 25264562236bSHarry Wentland if (!surface) 25274562236bSHarry Wentland return; 25284562236bSHarry Wentland 2529a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 25304562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 25314562236bSHarry Wentland 25324562236bSHarry Wentland if (pipe_ctx->surface != surface) 25334562236bSHarry Wentland continue; 25344562236bSHarry Wentland 25354562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 2536b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 25374562236bSHarry Wentland 25384562236bSHarry Wentland } 25394562236bSHarry Wentland } 25404562236bSHarry Wentland 25414562236bSHarry Wentland static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) 25424562236bSHarry Wentland { 25437950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 25447950f0f9SDmytro Laktyushkin if (pipe->stream) 25454562236bSHarry Wentland return; 25464562236bSHarry Wentland 25474562236bSHarry Wentland dc->hwss.enable_display_power_gating( 25487950f0f9SDmytro Laktyushkin dc, pipe->pipe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 25494562236bSHarry Wentland if (pipe->xfm) 25504562236bSHarry Wentland pipe->xfm->funcs->transform_reset(pipe->xfm); 25514562236bSHarry Wentland memset(&pipe->scl_data, 0, sizeof(struct scaler_data)); 25524562236bSHarry Wentland } 25534562236bSHarry Wentland 25544562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 25551bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 25564562236bSHarry Wentland .init_hw = init_hw, 25574562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 25584562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 25594562236bSHarry Wentland .set_plane_config = set_plane_config, 25604562236bSHarry Wentland .update_plane_addr = update_plane_addr, 25614562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 2562d7194cf6SAric Cyr .set_input_transfer_func = dce110_set_input_transfer_func, 256390e508baSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 25644562236bSHarry Wentland .power_down = dce110_power_down, 25654562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 25664562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 25674562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 25684562236bSHarry Wentland .enable_stream = dce110_enable_stream, 25694562236bSHarry Wentland .disable_stream = dce110_disable_stream, 25704562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 25714562236bSHarry Wentland .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 25724562236bSHarry Wentland .enable_display_power_gating = dce110_enable_display_power_gating, 25734562236bSHarry Wentland .power_down_front_end = dce110_power_down_fe, 25744562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 25754562236bSHarry Wentland .set_bandwidth = dce110_set_bandwidth, 25764562236bSHarry Wentland .set_drr = set_drr, 257772ada5f7SEric Cook .get_position = get_position, 25784562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 25794562236bSHarry Wentland .reset_hw_ctx_wrap = reset_hw_ctx_wrap, 25804b5e7d62SHersen Wu .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, 25817f5c22d1SVitaly Prosyak .setup_stereo = NULL 25824562236bSHarry Wentland }; 25834562236bSHarry Wentland 25844562236bSHarry Wentland bool dce110_hw_sequencer_construct(struct core_dc *dc) 25854562236bSHarry Wentland { 25864562236bSHarry Wentland dc->hwss = dce110_funcs; 25874562236bSHarry Wentland 25884562236bSHarry Wentland return true; 25894562236bSHarry Wentland } 25904562236bSHarry Wentland 2591