14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland #include "dm_services.h" 264562236bSHarry Wentland #include "dc.h" 274562236bSHarry Wentland #include "dc_bios_types.h" 284562236bSHarry Wentland #include "core_types.h" 294562236bSHarry Wentland #include "core_status.h" 304562236bSHarry Wentland #include "resource.h" 314562236bSHarry Wentland #include "dm_helpers.h" 324562236bSHarry Wentland #include "dce110_hw_sequencer.h" 334562236bSHarry Wentland #include "dce110_timing_generator.h" 3498489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 3587401969SAndrew Jiang #include "gpio_service_interface.h" 364562236bSHarry Wentland 371663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 381663ae1cSBhawanpreet Lakha 394562236bSHarry Wentland #include "bios/bios_parser_helper.h" 404562236bSHarry Wentland #include "timing_generator.h" 414562236bSHarry Wentland #include "mem_input.h" 424562236bSHarry Wentland #include "opp.h" 434562236bSHarry Wentland #include "ipp.h" 444562236bSHarry Wentland #include "transform.h" 454562236bSHarry Wentland #include "stream_encoder.h" 464562236bSHarry Wentland #include "link_encoder.h" 4787401969SAndrew Jiang #include "link_hwss.h" 484562236bSHarry Wentland #include "clock_source.h" 495e7773a2SAnthony Koo #include "abm.h" 504562236bSHarry Wentland #include "audio.h" 5108b16886SZeyu Fan #include "reg_helper.h" 524562236bSHarry Wentland 534562236bSHarry Wentland /* include DCE11 register header files */ 544562236bSHarry Wentland #include "dce/dce_11_0_d.h" 554562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 56e266fdf6SVitaly Prosyak #include "custom_float.h" 574562236bSHarry Wentland 584cac1e6dSYongqiang Sun #include "atomfirmware.h" 594cac1e6dSYongqiang Sun 6087401969SAndrew Jiang /* 6187401969SAndrew Jiang * All values are in milliseconds; 6287401969SAndrew Jiang * For eDP, after power-up/power/down, 6387401969SAndrew Jiang * 300/500 msec max. delay from LCDVCC to black video generation 6487401969SAndrew Jiang */ 6587401969SAndrew Jiang #define PANEL_POWER_UP_TIMEOUT 300 6687401969SAndrew Jiang #define PANEL_POWER_DOWN_TIMEOUT 500 6787401969SAndrew Jiang #define HPD_CHECK_INTERVAL 10 6887401969SAndrew Jiang 695eefbc40SYue Hin Lau #define CTX \ 705eefbc40SYue Hin Lau hws->ctx 715d4b05ddSBhawanpreet Lakha 725d4b05ddSBhawanpreet Lakha #define DC_LOGGER_INIT() 735d4b05ddSBhawanpreet Lakha 745eefbc40SYue Hin Lau #define REG(reg)\ 755eefbc40SYue Hin Lau hws->regs->reg 765eefbc40SYue Hin Lau 775eefbc40SYue Hin Lau #undef FN 785eefbc40SYue Hin Lau #define FN(reg_name, field_name) \ 795eefbc40SYue Hin Lau hws->shifts->field_name, hws->masks->field_name 805eefbc40SYue Hin Lau 814562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 824562236bSHarry Wentland uint32_t crtc; 834562236bSHarry Wentland }; 844562236bSHarry Wentland 854562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 864562236bSHarry Wentland { 874562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 884562236bSHarry Wentland }, 894562236bSHarry Wentland { 904562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 914562236bSHarry Wentland }, 924562236bSHarry Wentland { 934562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 944562236bSHarry Wentland }, 954562236bSHarry Wentland { 964562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 974562236bSHarry Wentland } 984562236bSHarry Wentland }; 994562236bSHarry Wentland 1004562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 1014562236bSHarry Wentland (reg + reg_offsets[id].blnd) 1024562236bSHarry Wentland 1034562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 1044562236bSHarry Wentland (reg + reg_offsets[id].crtc) 1054562236bSHarry Wentland 1064562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 1074562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 1084562236bSHarry Wentland 1094562236bSHarry Wentland /******************************************************************************* 1104562236bSHarry Wentland * Private definitions 1114562236bSHarry Wentland ******************************************************************************/ 1124562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 1134562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 1144562236bSHarry Wentland { 1154562236bSHarry Wentland uint32_t addr; 1164562236bSHarry Wentland uint32_t value = 0; 1174562236bSHarry Wentland uint32_t chunk_int = 0; 1184562236bSHarry Wentland uint32_t chunk_mul = 0; 1194562236bSHarry Wentland 1204562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 1214562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1224562236bSHarry Wentland 1234562236bSHarry Wentland set_reg_field_value( 1244562236bSHarry Wentland value, 1254562236bSHarry Wentland 0, 1264562236bSHarry Wentland DVMM_PTE_CONTROL, 1274562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1284562236bSHarry Wentland 1294562236bSHarry Wentland set_reg_field_value( 1304562236bSHarry Wentland value, 1314562236bSHarry Wentland 1, 1324562236bSHarry Wentland DVMM_PTE_CONTROL, 1334562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1344562236bSHarry Wentland 1354562236bSHarry Wentland set_reg_field_value( 1364562236bSHarry Wentland value, 1374562236bSHarry Wentland 1, 1384562236bSHarry Wentland DVMM_PTE_CONTROL, 1394562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1404562236bSHarry Wentland 1414562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1424562236bSHarry Wentland 1434562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1444562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1454562236bSHarry Wentland 1464562236bSHarry Wentland chunk_int = get_reg_field_value( 1474562236bSHarry Wentland value, 1484562236bSHarry Wentland DVMM_PTE_REQ, 1494562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1504562236bSHarry Wentland 1514562236bSHarry Wentland chunk_mul = get_reg_field_value( 1524562236bSHarry Wentland value, 1534562236bSHarry Wentland DVMM_PTE_REQ, 1544562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1554562236bSHarry Wentland 1564562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1574562236bSHarry Wentland 1584562236bSHarry Wentland set_reg_field_value( 1594562236bSHarry Wentland value, 1604562236bSHarry Wentland 255, 1614562236bSHarry Wentland DVMM_PTE_REQ, 1624562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1634562236bSHarry Wentland 1644562236bSHarry Wentland set_reg_field_value( 1654562236bSHarry Wentland value, 1664562236bSHarry Wentland 4, 1674562236bSHarry Wentland DVMM_PTE_REQ, 1684562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1694562236bSHarry Wentland 1704562236bSHarry Wentland set_reg_field_value( 1714562236bSHarry Wentland value, 1724562236bSHarry Wentland 4, 1734562236bSHarry Wentland DVMM_PTE_REQ, 1744562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1754562236bSHarry Wentland 1764562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1774562236bSHarry Wentland } 1784562236bSHarry Wentland } 1794562236bSHarry Wentland /**************************************************************************/ 1804562236bSHarry Wentland 1814562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1824562236bSHarry Wentland struct dc_context *ctx, 1834562236bSHarry Wentland bool clock_gating) 1844562236bSHarry Wentland { 1854562236bSHarry Wentland /*TODO*/ 1864562236bSHarry Wentland } 1874562236bSHarry Wentland 1884562236bSHarry Wentland static bool dce110_enable_display_power_gating( 189fb3466a4SBhawanpreet Lakha struct dc *dc, 1904562236bSHarry Wentland uint8_t controller_id, 1914562236bSHarry Wentland struct dc_bios *dcb, 1924562236bSHarry Wentland enum pipe_gating_control power_gating) 1934562236bSHarry Wentland { 1944562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 1954562236bSHarry Wentland enum bp_pipe_control_action cntl; 1964562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 1974562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1984562236bSHarry Wentland 1994562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 2004562236bSHarry Wentland return true; 2014562236bSHarry Wentland 2024562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 2034562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 2044562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 2054562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 2064562236bSHarry Wentland else 2074562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 2084562236bSHarry Wentland 2094562236bSHarry Wentland if (controller_id == underlay_idx) 2104562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 2114562236bSHarry Wentland 2124562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 2134562236bSHarry Wentland 2144562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 2154562236bSHarry Wentland dcb, controller_id + 1, cntl); 2164562236bSHarry Wentland 2174562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 2184562236bSHarry Wentland * by default when command table is called 2194562236bSHarry Wentland * 2204562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 2214562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2224562236bSHarry Wentland * than 3. 2234562236bSHarry Wentland */ 2244562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2254562236bSHarry Wentland dm_write_reg(ctx, 2264562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2274562236bSHarry Wentland 0); 2284562236bSHarry Wentland } 2294562236bSHarry Wentland 2304562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2314562236bSHarry Wentland dce110_init_pte(ctx); 2324562236bSHarry Wentland 2334562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2344562236bSHarry Wentland return true; 2354562236bSHarry Wentland else 2364562236bSHarry Wentland return false; 2374562236bSHarry Wentland } 2384562236bSHarry Wentland 2394562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2403be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2414562236bSHarry Wentland { 2424562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2434562236bSHarry Wentland 2443be5262eSHarry Wentland switch (plane_state->format) { 2454562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2468693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2474562236bSHarry Wentland prescale_params->scale = 0x2020; 2484562236bSHarry Wentland break; 2494562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2504562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2514562236bSHarry Wentland prescale_params->scale = 0x2008; 2524562236bSHarry Wentland break; 2534562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2544562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2554562236bSHarry Wentland prescale_params->scale = 0x2000; 2564562236bSHarry Wentland break; 2574562236bSHarry Wentland default: 2584562236bSHarry Wentland ASSERT(false); 259d7194cf6SAric Cyr break; 2604562236bSHarry Wentland } 2614562236bSHarry Wentland } 2624562236bSHarry Wentland 263a6114e85SHarry Wentland static bool 264a6114e85SHarry Wentland dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, 2653be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2664562236bSHarry Wentland { 26786a66c4eSHarry Wentland struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2687b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 26990e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 27090e508baSAnthony Koo bool result = true; 27190e508baSAnthony Koo 27290e508baSAnthony Koo if (ipp == NULL) 27390e508baSAnthony Koo return false; 27490e508baSAnthony Koo 2753be5262eSHarry Wentland if (plane_state->in_transfer_func) 2763be5262eSHarry Wentland tf = plane_state->in_transfer_func; 27790e508baSAnthony Koo 2783be5262eSHarry Wentland build_prescale_params(&prescale_params, plane_state); 27990e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 28090e508baSAnthony Koo 28184ffa801SLeo (Sunpeng) Li if (plane_state->gamma_correction && 28284ffa801SLeo (Sunpeng) Li !plane_state->gamma_correction->is_identity && 28384ffa801SLeo (Sunpeng) Li dce_use_lut(plane_state->format)) 2843be5262eSHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 285d7194cf6SAric Cyr 28690e508baSAnthony Koo if (tf == NULL) { 28790e508baSAnthony Koo /* Default case if no input transfer function specified */ 288a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 2897b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 2907b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 29190e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 292a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 29390e508baSAnthony Koo break; 29490e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 295a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 29690e508baSAnthony Koo break; 29790e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 298a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 29990e508baSAnthony Koo break; 30090e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 30190e508baSAnthony Koo default: 30290e508baSAnthony Koo result = false; 303d7194cf6SAric Cyr break; 30490e508baSAnthony Koo } 3057b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 30670063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 30790e508baSAnthony Koo } else { 30890e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 30990e508baSAnthony Koo result = false; 31090e508baSAnthony Koo } 31190e508baSAnthony Koo 31290e508baSAnthony Koo return result; 31390e508baSAnthony Koo } 31490e508baSAnthony Koo 315bd1be8e8SHarry Wentland static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 316fcd2f4bfSAmy Zhang struct curve_points *arr_points, 317fcd2f4bfSAmy Zhang uint32_t hw_points_num) 318fcd2f4bfSAmy Zhang { 319fcd2f4bfSAmy Zhang struct custom_float_format fmt; 320fcd2f4bfSAmy Zhang 321fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 322fcd2f4bfSAmy Zhang 323fcd2f4bfSAmy Zhang uint32_t i = 0; 324fcd2f4bfSAmy Zhang 325fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 326fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 327fcd2f4bfSAmy Zhang fmt.sign = true; 328fcd2f4bfSAmy Zhang 329bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 330fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 331fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 332fcd2f4bfSAmy Zhang return false; 333fcd2f4bfSAmy Zhang } 334fcd2f4bfSAmy Zhang 335bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 336fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 337fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 338fcd2f4bfSAmy Zhang return false; 339fcd2f4bfSAmy Zhang } 340fcd2f4bfSAmy Zhang 341bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 342fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 343fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 344fcd2f4bfSAmy Zhang return false; 345fcd2f4bfSAmy Zhang } 346fcd2f4bfSAmy Zhang 347fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 348fcd2f4bfSAmy Zhang fmt.sign = false; 349fcd2f4bfSAmy Zhang 350bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 351fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 352fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 353fcd2f4bfSAmy Zhang return false; 354fcd2f4bfSAmy Zhang } 355fcd2f4bfSAmy Zhang 356bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 357fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 358fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 359fcd2f4bfSAmy Zhang return false; 360fcd2f4bfSAmy Zhang } 361fcd2f4bfSAmy Zhang 3624d06ccd0SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 3634d06ccd0SHarry Wentland &arr_points[1].custom_float_slope)) { 364fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 365fcd2f4bfSAmy Zhang return false; 366fcd2f4bfSAmy Zhang } 367fcd2f4bfSAmy Zhang 368fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 369fcd2f4bfSAmy Zhang fmt.sign = true; 370fcd2f4bfSAmy Zhang 371fcd2f4bfSAmy Zhang while (i != hw_points_num) { 372bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->red, &fmt, 373fcd2f4bfSAmy Zhang &rgb->red_reg)) { 374fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 375fcd2f4bfSAmy Zhang return false; 376fcd2f4bfSAmy Zhang } 377fcd2f4bfSAmy Zhang 378bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->green, &fmt, 379fcd2f4bfSAmy Zhang &rgb->green_reg)) { 380fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 381fcd2f4bfSAmy Zhang return false; 382fcd2f4bfSAmy Zhang } 383fcd2f4bfSAmy Zhang 384bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->blue, &fmt, 385fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 386fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 387fcd2f4bfSAmy Zhang return false; 388fcd2f4bfSAmy Zhang } 389fcd2f4bfSAmy Zhang 390bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 391fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 392fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 393fcd2f4bfSAmy Zhang return false; 394fcd2f4bfSAmy Zhang } 395fcd2f4bfSAmy Zhang 396bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 397fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 398fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 399fcd2f4bfSAmy Zhang return false; 400fcd2f4bfSAmy Zhang } 401fcd2f4bfSAmy Zhang 402bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 403fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 404fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 405fcd2f4bfSAmy Zhang return false; 406fcd2f4bfSAmy Zhang } 407fcd2f4bfSAmy Zhang 408fcd2f4bfSAmy Zhang ++rgb; 409fcd2f4bfSAmy Zhang ++i; 410fcd2f4bfSAmy Zhang } 411fcd2f4bfSAmy Zhang 412fcd2f4bfSAmy Zhang return true; 413fcd2f4bfSAmy Zhang } 414fcd2f4bfSAmy Zhang 41508616da5SLeo (Sunpeng) Li #define MAX_LOW_POINT 25 4168f8372c7SKrunoslav Kovac #define NUMBER_REGIONS 16 4178f8372c7SKrunoslav Kovac #define NUMBER_SW_SEGMENTS 16 4188f8372c7SKrunoslav Kovac 419b310b081SHarry Wentland static bool 420b310b081SHarry Wentland dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 421b310b081SHarry Wentland struct pwl_params *regamma_params) 422fcd2f4bfSAmy Zhang { 42323ae4f8eSAmy Zhang struct curve_points *arr_points; 42423ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 42523ae4f8eSAmy Zhang struct pwl_result_data *rgb; 42623ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 427fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 428fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 429fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 430fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 431fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 432fcd2f4bfSAmy Zhang 4338f8372c7SKrunoslav Kovac int32_t region_start, region_end; 4348f8372c7SKrunoslav Kovac uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 43523ae4f8eSAmy Zhang 436b310b081SHarry Wentland if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 43723ae4f8eSAmy Zhang return false; 43823ae4f8eSAmy Zhang 43923ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 44023ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 44123ae4f8eSAmy Zhang hw_points = 0; 442fcd2f4bfSAmy Zhang 443fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 444fcd2f4bfSAmy Zhang 445fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 446534db198SAmy Zhang /* 16 segments 447fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 448fcd2f4bfSAmy Zhang */ 44908616da5SLeo (Sunpeng) Li region_start = -11; 45008616da5SLeo (Sunpeng) Li region_end = region_start + NUMBER_REGIONS; 451fcd2f4bfSAmy Zhang 4528f8372c7SKrunoslav Kovac for (i = 0; i < NUMBER_REGIONS; i++) 4538f8372c7SKrunoslav Kovac seg_distr[i] = 4; 454534db198SAmy Zhang 455fcd2f4bfSAmy Zhang } else { 456534db198SAmy Zhang /* 10 segments 457fc6de1c5SLeo (Sunpeng) Li * segment is from 2^-10 to 2^1 458fc6de1c5SLeo (Sunpeng) Li * We include an extra segment for range [2^0, 2^1). This is to 459fc6de1c5SLeo (Sunpeng) Li * ensure that colors with normalized values of 1 don't miss the 460fc6de1c5SLeo (Sunpeng) Li * LUT. 461fcd2f4bfSAmy Zhang */ 4628f8372c7SKrunoslav Kovac region_start = -10; 463fc6de1c5SLeo (Sunpeng) Li region_end = 1; 464534db198SAmy Zhang 4658f8372c7SKrunoslav Kovac seg_distr[0] = 4; 466534db198SAmy Zhang seg_distr[1] = 4; 467534db198SAmy Zhang seg_distr[2] = 4; 468534db198SAmy Zhang seg_distr[3] = 4; 469534db198SAmy Zhang seg_distr[4] = 4; 470534db198SAmy Zhang seg_distr[5] = 4; 471534db198SAmy Zhang seg_distr[6] = 4; 472534db198SAmy Zhang seg_distr[7] = 4; 4738f8372c7SKrunoslav Kovac seg_distr[8] = 4; 4748f8372c7SKrunoslav Kovac seg_distr[9] = 4; 475fc6de1c5SLeo (Sunpeng) Li seg_distr[10] = 0; 476534db198SAmy Zhang seg_distr[11] = -1; 477534db198SAmy Zhang seg_distr[12] = -1; 478534db198SAmy Zhang seg_distr[13] = -1; 479534db198SAmy Zhang seg_distr[14] = -1; 480534db198SAmy Zhang seg_distr[15] = -1; 481fcd2f4bfSAmy Zhang } 482fcd2f4bfSAmy Zhang 483534db198SAmy Zhang for (k = 0; k < 16; k++) { 484534db198SAmy Zhang if (seg_distr[k] != -1) 485534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 486534db198SAmy Zhang } 487534db198SAmy Zhang 488fcd2f4bfSAmy Zhang j = 0; 4898f8372c7SKrunoslav Kovac for (k = 0; k < (region_end - region_start); k++) { 490ec47734aSLeo (Sunpeng) Li increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 4918f8372c7SKrunoslav Kovac start_index = (region_start + k + MAX_LOW_POINT) * 4928f8372c7SKrunoslav Kovac NUMBER_SW_SEGMENTS; 4938f8372c7SKrunoslav Kovac for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 4948f8372c7SKrunoslav Kovac i += increment) { 495534db198SAmy Zhang if (j == hw_points - 1) 496fcd2f4bfSAmy Zhang break; 497fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 498fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 499fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 500fcd2f4bfSAmy Zhang j++; 501fcd2f4bfSAmy Zhang } 502534db198SAmy Zhang } 503534db198SAmy Zhang 504534db198SAmy Zhang /* last point */ 5058f8372c7SKrunoslav Kovac start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 506b310b081SHarry Wentland rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 507b310b081SHarry Wentland rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 508b310b081SHarry Wentland rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 509fcd2f4bfSAmy Zhang 510eb0e5154SDmytro Laktyushkin arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 511eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_start)); 512eb0e5154SDmytro Laktyushkin arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 513eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_end)); 514fcd2f4bfSAmy Zhang 515fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 516fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 517fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 518fcd2f4bfSAmy Zhang 519eb0e5154SDmytro Laktyushkin y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 520fcd2f4bfSAmy Zhang 521fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 522eb0e5154SDmytro Laktyushkin arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 523fcd2f4bfSAmy Zhang arr_points[0].x); 524fcd2f4bfSAmy Zhang 525fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 526fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 527fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 528fcd2f4bfSAmy Zhang 529fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 530fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 531fcd2f4bfSAmy Zhang */ 532eb0e5154SDmytro Laktyushkin y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 533fcd2f4bfSAmy Zhang 534fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 535fcd2f4bfSAmy Zhang 536eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_zero; 537fcd2f4bfSAmy Zhang 538fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 539fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 540fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 541fcd2f4bfSAmy Zhang */ 542eb0e5154SDmytro Laktyushkin const struct fixed31_32 end_value = dc_fixpt_from_int(125); 543fcd2f4bfSAmy Zhang 544eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_div( 545eb0e5154SDmytro Laktyushkin dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 546eb0e5154SDmytro Laktyushkin dc_fixpt_sub(end_value, arr_points[1].x)); 547fcd2f4bfSAmy Zhang } 548fcd2f4bfSAmy Zhang 549fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 550fcd2f4bfSAmy Zhang 55169133b89SAric Cyr k = 0; 55269133b89SAric Cyr for (i = 1; i < 16; i++) { 553534db198SAmy Zhang if (seg_distr[k] != -1) { 554b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 555534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 556b310b081SHarry Wentland regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 557fcd2f4bfSAmy Zhang } 55869133b89SAric Cyr k++; 559534db198SAmy Zhang } 560534db198SAmy Zhang 561534db198SAmy Zhang if (seg_distr[k] != -1) 562b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 563fcd2f4bfSAmy Zhang 56423ae4f8eSAmy Zhang rgb = rgb_resulted; 56523ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 566fcd2f4bfSAmy Zhang 567fcd2f4bfSAmy Zhang i = 1; 568fcd2f4bfSAmy Zhang 569fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 570eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 571fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 572eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 573fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 574eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 575fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 576fcd2f4bfSAmy Zhang 577eb0e5154SDmytro Laktyushkin rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 578eb0e5154SDmytro Laktyushkin rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 579eb0e5154SDmytro Laktyushkin rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 580fcd2f4bfSAmy Zhang 581fcd2f4bfSAmy Zhang ++rgb_plus_1; 582fcd2f4bfSAmy Zhang ++rgb; 583fcd2f4bfSAmy Zhang ++i; 584fcd2f4bfSAmy Zhang } 585fcd2f4bfSAmy Zhang 586fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 587fcd2f4bfSAmy Zhang 588fcd2f4bfSAmy Zhang return true; 589fcd2f4bfSAmy Zhang } 590fcd2f4bfSAmy Zhang 591a6114e85SHarry Wentland static bool 592a6114e85SHarry Wentland dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, 5930971c40eSHarry Wentland const struct dc_stream_state *stream) 59490e508baSAnthony Koo { 59586a66c4eSHarry Wentland struct transform *xfm = pipe_ctx->plane_res.xfm; 5964562236bSHarry Wentland 5977a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, true); 5987a09f5beSYue Hin Lau xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 5994562236bSHarry Wentland 6004fa086b9SLeo (Sunpeng) Li if (stream->out_transfer_func && 601efd52204SHarry Wentland stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 602efd52204SHarry Wentland stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 6037a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 604efd52204SHarry Wentland } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 605efd52204SHarry Wentland &xfm->regamma_params)) { 6067a09f5beSYue Hin Lau xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 6077a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 6084562236bSHarry Wentland } else { 6097a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 6104562236bSHarry Wentland } 6114562236bSHarry Wentland 6127a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, false); 6134562236bSHarry Wentland 614cc0cb445SLeon Elazar return true; 6154562236bSHarry Wentland } 6164562236bSHarry Wentland 6174562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6184562236bSHarry Wentland { 61902553f57SEric Bernstein bool is_hdmi_tmds; 6206f0db2dcSKrunoslav Kovac bool is_dp; 6216f0db2dcSKrunoslav Kovac 62286e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 62386e2e1beSHersen Wu 6248e9c4c8cSHarry Wentland if (pipe_ctx->stream_res.stream_enc == NULL) 62586e2e1beSHersen Wu return; /* this is not root pipe */ 62686e2e1beSHersen Wu 62702553f57SEric Bernstein is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 6286f0db2dcSKrunoslav Kovac is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 6296f0db2dcSKrunoslav Kovac 63002553f57SEric Bernstein if (!is_hdmi_tmds && !is_dp) 6316f0db2dcSKrunoslav Kovac return; 6326f0db2dcSKrunoslav Kovac 63302553f57SEric Bernstein if (is_hdmi_tmds) 6348e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 6358e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 63696c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6376f0db2dcSKrunoslav Kovac else 6388e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 6398e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 64096c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6414562236bSHarry Wentland } 6424562236bSHarry Wentland 6434562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6444562236bSHarry Wentland { 6454562236bSHarry Wentland enum dc_lane_count lane_count = 646ceb3dbb4SJun Lei pipe_ctx->stream->link->cur_link_settings.lane_count; 6474562236bSHarry Wentland 6484fa086b9SLeo (Sunpeng) Li struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 649ceb3dbb4SJun Lei struct dc_link *link = pipe_ctx->stream->link; 6504562236bSHarry Wentland 651f215a57dSEric Yang 6524562236bSHarry Wentland uint32_t active_total_with_borders; 6534562236bSHarry Wentland uint32_t early_control = 0; 6546b670fa9SHarry Wentland struct timing_generator *tg = pipe_ctx->stream_res.tg; 6554562236bSHarry Wentland 656f215a57dSEric Yang /* For MST, there are multiply stream go to only one link. 657f215a57dSEric Yang * connect DIG back_end to front_end while enable_stream and 658f215a57dSEric Yang * disconnect them during disable_stream 659f215a57dSEric Yang * BY this, it is logic clean to separate stream and link */ 660f215a57dSEric Yang link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 661f215a57dSEric Yang pipe_ctx->stream_res.stream_enc->id, true); 662f215a57dSEric Yang 663f215a57dSEric Yang /* update AVI info frame (HDMI, DP)*/ 664f215a57dSEric Yang /* TODO: FPGA may change to hwss.update_info_frame */ 6654562236bSHarry Wentland dce110_update_info_frame(pipe_ctx); 666f215a57dSEric Yang 6674562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 6684562236bSHarry Wentland active_total_with_borders = 6694562236bSHarry Wentland timing->h_addressable 6704562236bSHarry Wentland + timing->h_border_left 6714562236bSHarry Wentland + timing->h_border_right; 6724562236bSHarry Wentland 6734562236bSHarry Wentland if (lane_count != 0) 6744562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 6754562236bSHarry Wentland 6764562236bSHarry Wentland if (early_control == 0) 6774562236bSHarry Wentland early_control = lane_count; 6784562236bSHarry Wentland 6794562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 6804562236bSHarry Wentland 6814562236bSHarry Wentland /* enable audio only within mode set */ 682afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 6834562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6848e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 6854562236bSHarry Wentland } 6864562236bSHarry Wentland 687f215a57dSEric Yang 688f215a57dSEric Yang 6894562236bSHarry Wentland 6904562236bSHarry Wentland } 6914562236bSHarry Wentland 6925eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 6935eefbc40SYue Hin Lau static bool is_panel_backlight_on(struct dce_hwseq *hws) 6945eefbc40SYue Hin Lau { 6955eefbc40SYue Hin Lau uint32_t value; 6965eefbc40SYue Hin Lau 6975eefbc40SYue Hin Lau REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value); 6985eefbc40SYue Hin Lau 6995eefbc40SYue Hin Lau return value; 7005eefbc40SYue Hin Lau } 7015eefbc40SYue Hin Lau 70287401969SAndrew Jiang static bool is_panel_powered_on(struct dce_hwseq *hws) 70387401969SAndrew Jiang { 704d03f3f63SEric Yang uint32_t pwr_seq_state, dig_on, dig_on_ovrd; 70587401969SAndrew Jiang 706d03f3f63SEric Yang 707d03f3f63SEric Yang REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); 708d03f3f63SEric Yang 709d03f3f63SEric Yang REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd); 710d03f3f63SEric Yang 711d03f3f63SEric Yang return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1); 71287401969SAndrew Jiang } 71387401969SAndrew Jiang 7145eefbc40SYue Hin Lau static enum bp_result link_transmitter_control( 71587401969SAndrew Jiang struct dc_bios *bios, 7165eefbc40SYue Hin Lau struct bp_transmitter_control *cntl) 7175eefbc40SYue Hin Lau { 7185eefbc40SYue Hin Lau enum bp_result result; 7195eefbc40SYue Hin Lau 72087401969SAndrew Jiang result = bios->funcs->transmitter_control(bios, cntl); 7215eefbc40SYue Hin Lau 7225eefbc40SYue Hin Lau return result; 7235eefbc40SYue Hin Lau } 7245eefbc40SYue Hin Lau 72587401969SAndrew Jiang /* 72687401969SAndrew Jiang * @brief 72787401969SAndrew Jiang * eDP only. 72887401969SAndrew Jiang */ 72987401969SAndrew Jiang void hwss_edp_wait_for_hpd_ready( 730069d418fSAndrew Jiang struct dc_link *link, 73187401969SAndrew Jiang bool power_up) 73287401969SAndrew Jiang { 733069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 734069d418fSAndrew Jiang struct graphics_object_id connector = link->link_enc->connector; 73587401969SAndrew Jiang struct gpio *hpd; 73687401969SAndrew Jiang bool edp_hpd_high = false; 73787401969SAndrew Jiang uint32_t time_elapsed = 0; 73887401969SAndrew Jiang uint32_t timeout = power_up ? 73987401969SAndrew Jiang PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 74087401969SAndrew Jiang 74187401969SAndrew Jiang if (dal_graphics_object_id_get_connector_id(connector) 74287401969SAndrew Jiang != CONNECTOR_ID_EDP) { 74387401969SAndrew Jiang BREAK_TO_DEBUGGER(); 74487401969SAndrew Jiang return; 74587401969SAndrew Jiang } 74687401969SAndrew Jiang 74787401969SAndrew Jiang if (!power_up) 74887401969SAndrew Jiang /* 74987401969SAndrew Jiang * From KV, we will not HPD low after turning off VCC - 75087401969SAndrew Jiang * instead, we will check the SW timer in power_up(). 75187401969SAndrew Jiang */ 75287401969SAndrew Jiang return; 75387401969SAndrew Jiang 75487401969SAndrew Jiang /* 75587401969SAndrew Jiang * When we power on/off the eDP panel, 75687401969SAndrew Jiang * we need to wait until SENSE bit is high/low. 75787401969SAndrew Jiang */ 75887401969SAndrew Jiang 75987401969SAndrew Jiang /* obtain HPD */ 76087401969SAndrew Jiang /* TODO what to do with this? */ 76187401969SAndrew Jiang hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 76287401969SAndrew Jiang 76387401969SAndrew Jiang if (!hpd) { 76487401969SAndrew Jiang BREAK_TO_DEBUGGER(); 76587401969SAndrew Jiang return; 76687401969SAndrew Jiang } 76787401969SAndrew Jiang 76887401969SAndrew Jiang dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 76987401969SAndrew Jiang 77087401969SAndrew Jiang /* wait until timeout or panel detected */ 77187401969SAndrew Jiang 77287401969SAndrew Jiang do { 77387401969SAndrew Jiang uint32_t detected = 0; 77487401969SAndrew Jiang 77587401969SAndrew Jiang dal_gpio_get_value(hpd, &detected); 77687401969SAndrew Jiang 77787401969SAndrew Jiang if (!(detected ^ power_up)) { 77887401969SAndrew Jiang edp_hpd_high = true; 77987401969SAndrew Jiang break; 78087401969SAndrew Jiang } 78187401969SAndrew Jiang 78287401969SAndrew Jiang msleep(HPD_CHECK_INTERVAL); 78387401969SAndrew Jiang 78487401969SAndrew Jiang time_elapsed += HPD_CHECK_INTERVAL; 78587401969SAndrew Jiang } while (time_elapsed < timeout); 78687401969SAndrew Jiang 78787401969SAndrew Jiang dal_gpio_close(hpd); 78887401969SAndrew Jiang 78987401969SAndrew Jiang dal_gpio_destroy_irq(&hpd); 79087401969SAndrew Jiang 79187401969SAndrew Jiang if (false == edp_hpd_high) { 7921296423bSBhawanpreet Lakha DC_LOG_ERROR( 79387401969SAndrew Jiang "%s: wait timed out!\n", __func__); 79487401969SAndrew Jiang } 79587401969SAndrew Jiang } 79687401969SAndrew Jiang 79787401969SAndrew Jiang void hwss_edp_power_control( 798069d418fSAndrew Jiang struct dc_link *link, 79987401969SAndrew Jiang bool power_up) 80087401969SAndrew Jiang { 801069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 80287401969SAndrew Jiang struct dce_hwseq *hwseq = ctx->dc->hwseq; 80387401969SAndrew Jiang struct bp_transmitter_control cntl = { 0 }; 80487401969SAndrew Jiang enum bp_result bp_result; 80587401969SAndrew Jiang 80687401969SAndrew Jiang 807069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 80887401969SAndrew Jiang != CONNECTOR_ID_EDP) { 80987401969SAndrew Jiang BREAK_TO_DEBUGGER(); 81087401969SAndrew Jiang return; 81187401969SAndrew Jiang } 81287401969SAndrew Jiang 81387401969SAndrew Jiang if (power_up != is_panel_powered_on(hwseq)) { 81487401969SAndrew Jiang /* Send VBIOS command to prompt eDP panel power */ 81578d5d04dSCharlene Liu if (power_up) { 81678d5d04dSCharlene Liu unsigned long long current_ts = dm_get_timestamp(ctx); 81778d5d04dSCharlene Liu unsigned long long duration_in_ms = 81893ed1814SHugo Hu div64_u64(dm_get_elapse_time_in_ns( 81978d5d04dSCharlene Liu ctx, 82078d5d04dSCharlene Liu current_ts, 82193ed1814SHugo Hu link->link_trace.time_stamp.edp_poweroff), 1000000); 82278d5d04dSCharlene Liu unsigned long long wait_time_ms = 0; 82378d5d04dSCharlene Liu 82478d5d04dSCharlene Liu /* max 500ms from LCDVDD off to on */ 8256c4fff06SYue Hin Lau unsigned long long edp_poweroff_time_ms = 500; 826ff587987SHugo Hu 8276c4fff06SYue Hin Lau if (link->local_sink != NULL) 8286c4fff06SYue Hin Lau edp_poweroff_time_ms = 8296c4fff06SYue Hin Lau 500 + link->local_sink->edid_caps.panel_patch.extra_t12_ms; 83078d5d04dSCharlene Liu if (link->link_trace.time_stamp.edp_poweroff == 0) 831ff587987SHugo Hu wait_time_ms = edp_poweroff_time_ms; 832ff587987SHugo Hu else if (duration_in_ms < edp_poweroff_time_ms) 833ff587987SHugo Hu wait_time_ms = edp_poweroff_time_ms - duration_in_ms; 83478d5d04dSCharlene Liu 83578d5d04dSCharlene Liu if (wait_time_ms) { 83678d5d04dSCharlene Liu msleep(wait_time_ms); 83778d5d04dSCharlene Liu dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 83878d5d04dSCharlene Liu __func__, wait_time_ms); 83978d5d04dSCharlene Liu } 84078d5d04dSCharlene Liu 84178d5d04dSCharlene Liu } 84287401969SAndrew Jiang 8431296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 84487401969SAndrew Jiang "%s: Panel Power action: %s\n", 84587401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 84687401969SAndrew Jiang 84787401969SAndrew Jiang cntl.action = power_up ? 84887401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_ON : 84987401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_OFF; 850069d418fSAndrew Jiang cntl.transmitter = link->link_enc->transmitter; 851069d418fSAndrew Jiang cntl.connector_obj_id = link->link_enc->connector; 85287401969SAndrew Jiang cntl.coherent = false; 85387401969SAndrew Jiang cntl.lanes_number = LANE_COUNT_FOUR; 854069d418fSAndrew Jiang cntl.hpd_sel = link->link_enc->hpd_source; 85587401969SAndrew Jiang bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 85687401969SAndrew Jiang 85778d5d04dSCharlene Liu if (!power_up) 85878d5d04dSCharlene Liu /*save driver power off time stamp*/ 85978d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 86078d5d04dSCharlene Liu else 86178d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 86278d5d04dSCharlene Liu 86387401969SAndrew Jiang if (bp_result != BP_RESULT_OK) 8641296423bSBhawanpreet Lakha DC_LOG_ERROR( 86587401969SAndrew Jiang "%s: Panel Power bp_result: %d\n", 86687401969SAndrew Jiang __func__, bp_result); 86787401969SAndrew Jiang } else { 8681296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 86987401969SAndrew Jiang "%s: Skipping Panel Power action: %s\n", 87087401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 87187401969SAndrew Jiang } 87287401969SAndrew Jiang } 8735eefbc40SYue Hin Lau 8745eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 8755eefbc40SYue Hin Lau /* 8765eefbc40SYue Hin Lau * @brief 8775eefbc40SYue Hin Lau * eDP only. Control the backlight of the eDP panel 8785eefbc40SYue Hin Lau */ 87987401969SAndrew Jiang void hwss_edp_backlight_control( 8805eefbc40SYue Hin Lau struct dc_link *link, 8815eefbc40SYue Hin Lau bool enable) 8825eefbc40SYue Hin Lau { 883069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 884069d418fSAndrew Jiang struct dce_hwseq *hws = ctx->dc->hwseq; 8855eefbc40SYue Hin Lau struct bp_transmitter_control cntl = { 0 }; 8865eefbc40SYue Hin Lau 887069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 8885eefbc40SYue Hin Lau != CONNECTOR_ID_EDP) { 8895eefbc40SYue Hin Lau BREAK_TO_DEBUGGER(); 8905eefbc40SYue Hin Lau return; 8915eefbc40SYue Hin Lau } 8925eefbc40SYue Hin Lau 8935eefbc40SYue Hin Lau if (enable && is_panel_backlight_on(hws)) { 8941296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 8955eefbc40SYue Hin Lau "%s: panel already powered up. Do nothing.\n", 8965eefbc40SYue Hin Lau __func__); 8975eefbc40SYue Hin Lau return; 8985eefbc40SYue Hin Lau } 8995eefbc40SYue Hin Lau 9005eefbc40SYue Hin Lau /* Send VBIOS command to control eDP panel backlight */ 9015eefbc40SYue Hin Lau 9021296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 9035eefbc40SYue Hin Lau "%s: backlight action: %s\n", 9045eefbc40SYue Hin Lau __func__, (enable ? "On":"Off")); 9055eefbc40SYue Hin Lau 9065eefbc40SYue Hin Lau cntl.action = enable ? 9075eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_ON : 9085eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_OFF; 90987401969SAndrew Jiang 9105eefbc40SYue Hin Lau /*cntl.engine_id = ctx->engine;*/ 9115eefbc40SYue Hin Lau cntl.transmitter = link->link_enc->transmitter; 9125eefbc40SYue Hin Lau cntl.connector_obj_id = link->link_enc->connector; 9135eefbc40SYue Hin Lau /*todo: unhardcode*/ 9145eefbc40SYue Hin Lau cntl.lanes_number = LANE_COUNT_FOUR; 9155eefbc40SYue Hin Lau cntl.hpd_sel = link->link_enc->hpd_source; 916cf1835f0SCharlene Liu cntl.signal = SIGNAL_TYPE_EDP; 9175eefbc40SYue Hin Lau 9185eefbc40SYue Hin Lau /* For eDP, the following delays might need to be considered 9195eefbc40SYue Hin Lau * after link training completed: 9205eefbc40SYue Hin Lau * idle period - min. accounts for required BS-Idle pattern, 9215eefbc40SYue Hin Lau * max. allows for source frame synchronization); 9225eefbc40SYue Hin Lau * 50 msec max. delay from valid video data from source 9235eefbc40SYue Hin Lau * to video on dislpay or backlight enable. 9245eefbc40SYue Hin Lau * 9255eefbc40SYue Hin Lau * Disable the delay for now. 9265eefbc40SYue Hin Lau * Enable it in the future if necessary. 9275eefbc40SYue Hin Lau */ 9285eefbc40SYue Hin Lau /* dc_service_sleep_in_milliseconds(50); */ 9295180d4a4SCharlene Liu /*edp 1.2*/ 9305180d4a4SCharlene Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 9315180d4a4SCharlene Liu edp_receiver_ready_T7(link); 932069d418fSAndrew Jiang link_transmitter_control(ctx->dc_bios, &cntl); 93369b9723aSCharlene Liu /*edp 1.2*/ 9345180d4a4SCharlene Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) 93569b9723aSCharlene Liu edp_receiver_ready_T9(link); 9365eefbc40SYue Hin Lau } 9375eefbc40SYue Hin Lau 9380f1a6ad7SJun Lei // Static helper function which calls the correct function 9390f1a6ad7SJun Lei // based on pp_smu version 9400f1a6ad7SJun Lei static void set_pme_wa_enable_by_version(struct dc *dc) 9410f1a6ad7SJun Lei { 9420f1a6ad7SJun Lei struct pp_smu_funcs *pp_smu = NULL; 9430f1a6ad7SJun Lei 9440f1a6ad7SJun Lei if (dc->res_pool->pp_smu) 9450f1a6ad7SJun Lei pp_smu = dc->res_pool->pp_smu; 9460f1a6ad7SJun Lei 9470f1a6ad7SJun Lei if (pp_smu) { 9480f1a6ad7SJun Lei if (pp_smu->ctx.ver == PP_SMU_VER_RV && pp_smu->rv_funcs.set_pme_wa_enable) 9490f1a6ad7SJun Lei pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->ctx)); 9500f1a6ad7SJun Lei } 9510f1a6ad7SJun Lei } 9520f1a6ad7SJun Lei 9531a05873fSAnthony Koo void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 9544562236bSHarry Wentland { 9551a05873fSAnthony Koo /* notify audio driver for audio modes of monitor */ 9560f1a6ad7SJun Lei struct dc *core_dc = pipe_ctx->stream->ctx->dc; 9570f1a6ad7SJun Lei struct pp_smu_funcs *pp_smu = NULL; 9581a05873fSAnthony Koo unsigned int i, num_audio = 1; 9591a05873fSAnthony Koo 9600f1a6ad7SJun Lei if (core_dc->res_pool->pp_smu) 9610f1a6ad7SJun Lei pp_smu = core_dc->res_pool->pp_smu; 9620f1a6ad7SJun Lei 9631a05873fSAnthony Koo if (pipe_ctx->stream_res.audio) { 9641a05873fSAnthony Koo for (i = 0; i < MAX_PIPES; i++) { 9651a05873fSAnthony Koo /*current_state not updated yet*/ 9661a05873fSAnthony Koo if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 9671a05873fSAnthony Koo num_audio++; 9681a05873fSAnthony Koo } 9691a05873fSAnthony Koo 9701a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 9711a05873fSAnthony Koo 9720f1a6ad7SJun Lei if (num_audio >= 1 && pp_smu != NULL) 9731a05873fSAnthony Koo /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 9740f1a6ad7SJun Lei set_pme_wa_enable_by_version(core_dc); 9751a05873fSAnthony Koo /* un-mute audio */ 9761a05873fSAnthony Koo /* TODO: audio should be per stream rather than per link */ 9771a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 9781a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, false); 9791a05873fSAnthony Koo } 9801a05873fSAnthony Koo } 9811a05873fSAnthony Koo 9821a05873fSAnthony Koo void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) 9831a05873fSAnthony Koo { 9844176664bSCharlene Liu struct dc *dc = pipe_ctx->stream->ctx->dc; 9850f1a6ad7SJun Lei struct pp_smu_funcs *pp_smu = NULL; 9864562236bSHarry Wentland 9872b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 9882b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc, true); 989afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio) { 9900f1a6ad7SJun Lei if (dc->res_pool->pp_smu) 9910f1a6ad7SJun Lei pp_smu = dc->res_pool->pp_smu; 992070fe724SCharlene Liu 9937c357e61SCharlene Liu if (option != KEEP_ACQUIRED_RESOURCE || 9940f1a6ad7SJun Lei !dc->debug.az_endpoint_mute_only) 9957c357e61SCharlene Liu /*only disalbe az_endpoint if power down or free*/ 996afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 9974562236bSHarry Wentland 9984562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 9998e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 10008e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 10014562236bSHarry Wentland else 10028e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 10038e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 10044176664bSCharlene Liu /*don't free audio if it is from retrain or internal disable stream*/ 10054176664bSCharlene Liu if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) { 10064176664bSCharlene Liu /*we have to dynamic arbitrate the audio endpoints*/ 10074176664bSCharlene Liu /*we free the resource, need reset is_audio_acquired*/ 10084176664bSCharlene Liu update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false); 1009fb5fb63aSCharlene Liu pipe_ctx->stream_res.audio = NULL; 10104176664bSCharlene Liu } 10110f1a6ad7SJun Lei if (pp_smu != NULL) 1012070fe724SCharlene Liu /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 10130f1a6ad7SJun Lei set_pme_wa_enable_by_version(dc); 10144562236bSHarry Wentland 10154562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 10164562236bSHarry Wentland * add audio mode list change flag */ 10174562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 10184562236bSHarry Wentland * stream->stream_engine_id); 10194562236bSHarry Wentland */ 10204562236bSHarry Wentland } 10211a05873fSAnthony Koo } 10224562236bSHarry Wentland 10231a05873fSAnthony Koo void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) 10241a05873fSAnthony Koo { 10251a05873fSAnthony Koo struct dc_stream_state *stream = pipe_ctx->stream; 1026ceb3dbb4SJun Lei struct dc_link *link = stream->link; 10271a05873fSAnthony Koo struct dc *dc = pipe_ctx->stream->ctx->dc; 10281a05873fSAnthony Koo 102902553f57SEric Bernstein if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 10301a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 10311a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 10321a05873fSAnthony Koo 10331a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10341a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 10351a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 10361a05873fSAnthony Koo 10371a05873fSAnthony Koo dc->hwss.disable_audio_stream(pipe_ctx, option); 1038904623eeSYongqiang Sun 10394562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 10404562236bSHarry Wentland link->link_enc, 10418e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->id, 10424562236bSHarry Wentland false); 10434562236bSHarry Wentland 10444562236bSHarry Wentland } 10454562236bSHarry Wentland 10464562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 10474562236bSHarry Wentland struct dc_link_settings *link_settings) 10484562236bSHarry Wentland { 10494562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 105041b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1051ceb3dbb4SJun Lei struct dc_link *link = stream->link; 10524562236bSHarry Wentland 10534562236bSHarry Wentland /* only 3 items below are used by unblank */ 10547fe538a4SCharlene Liu params.timing = pipe_ctx->stream->timing; 10554562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 105641b49742SCharlene Liu 105741b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10588e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 105941b49742SCharlene Liu 106014d6f644SYongqiang Sun if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 106141b49742SCharlene Liu link->dc->hwss.edp_backlight_control(link, true); 106214d6f644SYongqiang Sun } 106341b49742SCharlene Liu } 10642c850b7bSDmytro Laktyushkin 106541b49742SCharlene Liu void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 106641b49742SCharlene Liu { 106741b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1068ceb3dbb4SJun Lei struct dc_link *link = stream->link; 106941b49742SCharlene Liu 1070ab892598SRoman Li if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 107141b49742SCharlene Liu link->dc->hwss.edp_backlight_control(link, false); 1072ab892598SRoman Li dc_link_set_abm_disable(link); 1073ab892598SRoman Li } 107441b49742SCharlene Liu 107541b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 107641b49742SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 10774562236bSHarry Wentland } 10784562236bSHarry Wentland 107915e17335SCharlene Liu 108015e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 108115e17335SCharlene Liu { 10828e9c4c8cSHarry Wentland if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 10838e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 108415e17335SCharlene Liu } 108515e17335SCharlene Liu 10864562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 10874562236bSHarry Wentland { 10884562236bSHarry Wentland switch (crtc_id) { 10894562236bSHarry Wentland case CONTROLLER_ID_D0: 10904562236bSHarry Wentland return DTO_SOURCE_ID0; 10914562236bSHarry Wentland case CONTROLLER_ID_D1: 10924562236bSHarry Wentland return DTO_SOURCE_ID1; 10934562236bSHarry Wentland case CONTROLLER_ID_D2: 10944562236bSHarry Wentland return DTO_SOURCE_ID2; 10954562236bSHarry Wentland case CONTROLLER_ID_D3: 10964562236bSHarry Wentland return DTO_SOURCE_ID3; 10974562236bSHarry Wentland case CONTROLLER_ID_D4: 10984562236bSHarry Wentland return DTO_SOURCE_ID4; 10994562236bSHarry Wentland case CONTROLLER_ID_D5: 11004562236bSHarry Wentland return DTO_SOURCE_ID5; 11014562236bSHarry Wentland default: 11024562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 11034562236bSHarry Wentland } 11044562236bSHarry Wentland } 11054562236bSHarry Wentland 11064562236bSHarry Wentland static void build_audio_output( 1107ab8db3e1SAndrey Grodzovsky struct dc_state *state, 11084562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 11094562236bSHarry Wentland struct audio_output *audio_output) 11104562236bSHarry Wentland { 11110971c40eSHarry Wentland const struct dc_stream_state *stream = pipe_ctx->stream; 11128e9c4c8cSHarry Wentland audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 11134562236bSHarry Wentland 11144562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 11154562236bSHarry Wentland 11164562236bSHarry Wentland /* audio_crtc_info */ 11174562236bSHarry Wentland 11184562236bSHarry Wentland audio_output->crtc_info.h_total = 11194fa086b9SLeo (Sunpeng) Li stream->timing.h_total; 11204562236bSHarry Wentland 11214562236bSHarry Wentland /* 11224562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 11234562236bSHarry Wentland * need to specify actual active signal portion 11244562236bSHarry Wentland */ 11254562236bSHarry Wentland audio_output->crtc_info.h_active = 11264fa086b9SLeo (Sunpeng) Li stream->timing.h_addressable 11274fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_left 11284fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_right; 11294562236bSHarry Wentland 11304562236bSHarry Wentland audio_output->crtc_info.v_active = 11314fa086b9SLeo (Sunpeng) Li stream->timing.v_addressable 11324fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_top 11334fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_bottom; 11344562236bSHarry Wentland 11354562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 11364562236bSHarry Wentland 11374562236bSHarry Wentland audio_output->crtc_info.interlaced = 11384fa086b9SLeo (Sunpeng) Li stream->timing.flags.INTERLACE; 11394562236bSHarry Wentland 11404562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 1141380604e2SKen Chalmers (stream->timing.pix_clk_100hz*10000)/ 11424fa086b9SLeo (Sunpeng) Li (stream->timing.h_total*stream->timing.v_total); 11434562236bSHarry Wentland 11444562236bSHarry Wentland audio_output->crtc_info.color_depth = 11454fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth; 11464562236bSHarry Wentland 11474562236bSHarry Wentland audio_output->crtc_info.requested_pixel_clock = 1148380604e2SKen Chalmers pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; 11494562236bSHarry Wentland 11504562236bSHarry Wentland audio_output->crtc_info.calculated_pixel_clock = 1151380604e2SKen Chalmers pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; 11524562236bSHarry Wentland 115387b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 115487b58768SCharlene Liu if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && 115587b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock == 1156380604e2SKen Chalmers (stream->timing.pix_clk_100hz / 10)) { 115710688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 115887b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock = 115987b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock/2; 116087b58768SCharlene Liu audio_output->crtc_info.calculated_pixel_clock = 1161380604e2SKen Chalmers pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/20; 116287b58768SCharlene Liu 116387b58768SCharlene Liu } 116487b58768SCharlene Liu } 116587b58768SCharlene Liu 11664562236bSHarry Wentland if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 11674562236bSHarry Wentland pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 11684562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 116924f7dd7eSDmytro Laktyushkin state->dccg->funcs->get_dp_ref_clk_frequency( 117024f7dd7eSDmytro Laktyushkin state->dccg); 11714562236bSHarry Wentland } 11724562236bSHarry Wentland 11734562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 11744562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 11754562236bSHarry Wentland 11764562236bSHarry Wentland audio_output->pll_info.dto_source = 11774562236bSHarry Wentland translate_to_dto_source( 1178e07f541fSYongqiang Sun pipe_ctx->stream_res.tg->inst + 1); 11794562236bSHarry Wentland 11804562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 11814562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 11824562236bSHarry Wentland 11834562236bSHarry Wentland audio_output->pll_info.ss_percentage = 11844562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 11854562236bSHarry Wentland } 11864562236bSHarry Wentland 11874562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 11884562236bSHarry Wentland struct tg_color *color) 11894562236bSHarry Wentland { 11902a54bd6eSJerry (Fangzhi) Zuo uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; 11914562236bSHarry Wentland 11926702a9acSHarry Wentland switch (pipe_ctx->plane_res.scl_data.format) { 11934562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 11944562236bSHarry Wentland /* set boarder color to red */ 11954562236bSHarry Wentland color->color_r_cr = color_value; 11964562236bSHarry Wentland break; 11974562236bSHarry Wentland 11984562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 11994562236bSHarry Wentland /* set boarder color to blue */ 12004562236bSHarry Wentland color->color_b_cb = color_value; 12014562236bSHarry Wentland break; 120287449a90SAnthony Koo case PIXEL_FORMAT_420BPP8: 12034562236bSHarry Wentland /* set boarder color to green */ 12044562236bSHarry Wentland color->color_g_y = color_value; 12054562236bSHarry Wentland break; 120687449a90SAnthony Koo case PIXEL_FORMAT_420BPP10: 120787449a90SAnthony Koo /* set boarder color to yellow */ 120887449a90SAnthony Koo color->color_g_y = color_value; 120987449a90SAnthony Koo color->color_r_cr = color_value; 121087449a90SAnthony Koo break; 12114562236bSHarry Wentland case PIXEL_FORMAT_FP16: 12124562236bSHarry Wentland /* set boarder color to white */ 12134562236bSHarry Wentland color->color_r_cr = color_value; 12144562236bSHarry Wentland color->color_b_cb = color_value; 12154562236bSHarry Wentland color->color_g_y = color_value; 12164562236bSHarry Wentland break; 12174562236bSHarry Wentland default: 12184562236bSHarry Wentland break; 12194562236bSHarry Wentland } 12204562236bSHarry Wentland } 12214562236bSHarry Wentland 1222fb3466a4SBhawanpreet Lakha static void program_scaler(const struct dc *dc, 12234562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 12244562236bSHarry Wentland { 12254562236bSHarry Wentland struct tg_color color = {0}; 12264562236bSHarry Wentland 1227dc37a9a0SLeo (Sunpeng) Li #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1228ff5ef992SAlex Deucher /* TOFPGA */ 122986a66c4eSHarry Wentland if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1230ff5ef992SAlex Deucher return; 1231ff5ef992SAlex Deucher #endif 1232ff5ef992SAlex Deucher 1233bf53769dSGloria Li if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 12344562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 12354562236bSHarry Wentland else 12364562236bSHarry Wentland color_space_to_black_color(dc, 12374fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space, 12384562236bSHarry Wentland &color); 12394562236bSHarry Wentland 124086a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 124186a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, 12426702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.depth, 12434562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 12444562236bSHarry Wentland 124512750d16SEric Yang if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 124612750d16SEric Yang /* 124712750d16SEric Yang * The way 420 is packed, 2 channels carry Y component, 1 channel 124812750d16SEric Yang * alternate between Cb and Cr, so both channels need the pixel 124912750d16SEric Yang * value for Y 125012750d16SEric Yang */ 125112750d16SEric Yang if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 125212750d16SEric Yang color.color_r_cr = color.color_g_y; 125312750d16SEric Yang 12546b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 12556b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12564562236bSHarry Wentland &color); 125712750d16SEric Yang } 12584562236bSHarry Wentland 125986a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 12606702a9acSHarry Wentland &pipe_ctx->plane_res.scl_data); 12614562236bSHarry Wentland } 12624562236bSHarry Wentland 12633158223eSEric Bernstein static enum dc_status dce110_enable_stream_timing( 12644562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1265608ac7bbSJerry Zuo struct dc_state *context, 1266fb3466a4SBhawanpreet Lakha struct dc *dc) 12674562236bSHarry Wentland { 12680971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1269608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 12704562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 12714562236bSHarry Wentland struct tg_color black_color = {0}; 12724562236bSHarry Wentland 12734562236bSHarry Wentland if (!pipe_ctx_old->stream) { 12744562236bSHarry Wentland 12754562236bSHarry Wentland /* program blank color */ 12764562236bSHarry Wentland color_space_to_black_color(dc, 12774fa086b9SLeo (Sunpeng) Li stream->output_color_space, &black_color); 12786b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank_color( 12796b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12804562236bSHarry Wentland &black_color); 12814b5e7d62SHersen Wu 12824562236bSHarry Wentland /* 12834562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 12844562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 12854562236bSHarry Wentland */ 12866b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 12874562236bSHarry Wentland 12884562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 12894562236bSHarry Wentland pipe_ctx->clock_source, 129010688217SHarry Wentland &pipe_ctx->stream_res.pix_clk_params, 12914562236bSHarry Wentland &pipe_ctx->pll_settings)) { 12924562236bSHarry Wentland BREAK_TO_DEBUGGER(); 12934562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 12944562236bSHarry Wentland } 12954562236bSHarry Wentland 12966b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->program_timing( 12976b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12984fa086b9SLeo (Sunpeng) Li &stream->timing, 12994562236bSHarry Wentland true); 13004562236bSHarry Wentland } 13014562236bSHarry Wentland 13024562236bSHarry Wentland if (!pipe_ctx_old->stream) { 13036b670fa9SHarry Wentland if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 13046b670fa9SHarry Wentland pipe_ctx->stream_res.tg)) { 13054562236bSHarry Wentland BREAK_TO_DEBUGGER(); 13064562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 13074562236bSHarry Wentland } 13084562236bSHarry Wentland } 13094562236bSHarry Wentland 13104562236bSHarry Wentland return DC_OK; 13114562236bSHarry Wentland } 13124562236bSHarry Wentland 13134562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 13144562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1315608ac7bbSJerry Zuo struct dc_state *context, 1316fb3466a4SBhawanpreet Lakha struct dc *dc) 13174562236bSHarry Wentland { 13180971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 13199c0fb8d4SAnthony Koo struct drr_params params = {0}; 13209c0fb8d4SAnthony Koo unsigned int event_triggers = 0; 13214562236bSHarry Wentland 1322240d09d0SGary Kattan if (dc->hwss.disable_stream_gating) { 1323240d09d0SGary Kattan dc->hwss.disable_stream_gating(dc, pipe_ctx); 1324240d09d0SGary Kattan } 1325240d09d0SGary Kattan 13261a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 13271a05873fSAnthony Koo struct audio_output audio_output; 13281a05873fSAnthony Koo 13291a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 13301a05873fSAnthony Koo 13311a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 13321a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 13331a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 13341a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 13351a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 13361a05873fSAnthony Koo else 13371a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 13381a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 13391a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 13401a05873fSAnthony Koo &pipe_ctx->stream->audio_info, 13411a05873fSAnthony Koo &audio_output.crtc_info); 13421a05873fSAnthony Koo 13431a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_configure( 13441a05873fSAnthony Koo pipe_ctx->stream_res.audio, 13451a05873fSAnthony Koo pipe_ctx->stream->signal, 13461a05873fSAnthony Koo &audio_output.crtc_info, 13471a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 13481a05873fSAnthony Koo } 13491a05873fSAnthony Koo 13504562236bSHarry Wentland /* */ 1351d2d7885fSAnthony Koo /* Do not touch stream timing on seamless boot optimization. */ 1352d2d7885fSAnthony Koo if (!pipe_ctx->stream->apply_seamless_boot_optimization) 13533158223eSEric Bernstein dc->hwss.enable_stream_timing(pipe_ctx, context, dc); 13544562236bSHarry Wentland 1355d6001aedSYongqiang Sun if (dc->hwss.setup_vupdate_interrupt) 1356d6001aedSYongqiang Sun dc->hwss.setup_vupdate_interrupt(pipe_ctx); 1357a122b62dSAnthony Koo 13589c0fb8d4SAnthony Koo params.vertical_total_min = stream->adjust.v_total_min; 13599c0fb8d4SAnthony Koo params.vertical_total_max = stream->adjust.v_total_max; 13609c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_drr) 13619c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_drr( 13629c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg, ¶ms); 13639c0fb8d4SAnthony Koo 13649c0fb8d4SAnthony Koo // DRR should set trigger event to monitor surface update event 13659c0fb8d4SAnthony Koo if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 13669c0fb8d4SAnthony Koo event_triggers = 0x80; 13679c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 13689c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 13699c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg, event_triggers); 13709c0fb8d4SAnthony Koo 13714562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 1372d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1373d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc, 1374d2c460e7Shersen wu pipe_ctx->stream_res.tg->inst); 1375aa9c4abeSNikola Cornij 1376f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1377f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp, 1378f0c4d997SCorbin McElhanney COLOR_SPACE_YCBCR601, 1379f0c4d997SCorbin McElhanney stream->timing.display_color_depth, 1380661a8cd9SDmytro Laktyushkin stream->signal); 13814562236bSHarry Wentland 1382a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1383a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 1384181a888fSCharlene Liu &stream->bit_depth_params, 1385181a888fSCharlene Liu &stream->clamping); 1386603767f9STony Cheng 13871e7e86c4SSamson Tam if (!stream->dpms_off) 1388ab8db3e1SAndrey Grodzovsky core_link_enable_stream(context, pipe_ctx); 13894562236bSHarry Wentland 13906702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 13914562236bSHarry Wentland 1392ceb3dbb4SJun Lei pipe_ctx->stream->link->psr_enabled = false; 139394267b3dSSylvia Tsai 13944562236bSHarry Wentland return DC_OK; 13954562236bSHarry Wentland } 13964562236bSHarry Wentland 13974562236bSHarry Wentland /******************************************************************************/ 13984562236bSHarry Wentland 1399fb3466a4SBhawanpreet Lakha static void power_down_encoders(struct dc *dc) 14004562236bSHarry Wentland { 14014562236bSHarry Wentland int i; 1402a0c38ebaSCharlene Liu enum connector_id connector_id; 140368d77dd8SAndrew Jiang enum signal_type signal = SIGNAL_TYPE_NONE; 1404b9b171ffSHersen Wu 1405b9b171ffSHersen Wu /* do not know BIOS back-front mapping, simply blank all. It will not 1406b9b171ffSHersen Wu * hurt for non-DP 1407b9b171ffSHersen Wu */ 1408b9b171ffSHersen Wu for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1409b9b171ffSHersen Wu dc->res_pool->stream_enc[i]->funcs->dp_blank( 1410b9b171ffSHersen Wu dc->res_pool->stream_enc[i]); 1411b9b171ffSHersen Wu } 1412b9b171ffSHersen Wu 14134562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 1414a0c38ebaSCharlene Liu connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id); 1415a0c38ebaSCharlene Liu if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || 1416a0c38ebaSCharlene Liu (connector_id == CONNECTOR_ID_EDP)) { 1417a0c38ebaSCharlene Liu 1418a0c38ebaSCharlene Liu if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) 1419a0c38ebaSCharlene Liu dp_receiver_power_ctrl(dc->links[i], false); 1420904623eeSYongqiang Sun if (connector_id == CONNECTOR_ID_EDP) 142168d77dd8SAndrew Jiang signal = SIGNAL_TYPE_EDP; 1422a0c38ebaSCharlene Liu } 1423a0c38ebaSCharlene Liu 14244562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 1425069d418fSAndrew Jiang dc->links[i]->link_enc, signal); 14264562236bSHarry Wentland } 14274562236bSHarry Wentland } 14284562236bSHarry Wentland 1429fb3466a4SBhawanpreet Lakha static void power_down_controllers(struct dc *dc) 14304562236bSHarry Wentland { 14314562236bSHarry Wentland int i; 14324562236bSHarry Wentland 14337f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 14344562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 14354562236bSHarry Wentland dc->res_pool->timing_generators[i]); 14364562236bSHarry Wentland } 14374562236bSHarry Wentland } 14384562236bSHarry Wentland 1439fb3466a4SBhawanpreet Lakha static void power_down_clock_sources(struct dc *dc) 14404562236bSHarry Wentland { 14414562236bSHarry Wentland int i; 14424562236bSHarry Wentland 14434562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 14444562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 14454562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 14464562236bSHarry Wentland 14474562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 14484562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 14494562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 14504562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 14514562236bSHarry Wentland } 14524562236bSHarry Wentland } 14534562236bSHarry Wentland 1454fb3466a4SBhawanpreet Lakha static void power_down_all_hw_blocks(struct dc *dc) 14554562236bSHarry Wentland { 14564562236bSHarry Wentland power_down_encoders(dc); 14574562236bSHarry Wentland 14584562236bSHarry Wentland power_down_controllers(dc); 14594562236bSHarry Wentland 14604562236bSHarry Wentland power_down_clock_sources(dc); 14611663ae1cSBhawanpreet Lakha 14622f3bfb27SRoman Li if (dc->fbc_compressor) 14631663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 14644562236bSHarry Wentland } 14654562236bSHarry Wentland 14664562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 1467fb3466a4SBhawanpreet Lakha struct dc *dc) 14684562236bSHarry Wentland { 14694562236bSHarry Wentland int i; 14704562236bSHarry Wentland struct timing_generator *tg; 14714562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 14724562236bSHarry Wentland 14737f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 14744562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 14754562236bSHarry Wentland 14760a87425aSTony Cheng if (tg->funcs->disable_vga) 14774562236bSHarry Wentland tg->funcs->disable_vga(tg); 14787f93c1deSCharlene Liu } 14797f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->pipe_count; i++) { 14804562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 14814562236bSHarry Wentland * powergating. */ 14824562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 14834562236bSHarry Wentland true); 14844562236bSHarry Wentland 1485e6c258cbSYongqiang Sun dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 14867f914a62SYongqiang Sun dc->hwss.disable_plane(dc, 1487e6c258cbSYongqiang Sun &dc->current_state->res_ctx.pipe_ctx[i]); 14884562236bSHarry Wentland } 14894562236bSHarry Wentland } 14904562236bSHarry Wentland 1491f0c0761bSYongqiang Sun static struct dc_link *get_link_for_edp(struct dc *dc) 1492339cc82aSYongqiang Sun { 1493339cc82aSYongqiang Sun int i; 1494339cc82aSYongqiang Sun 1495f0c0761bSYongqiang Sun for (i = 0; i < dc->link_count; i++) { 1496f0c0761bSYongqiang Sun if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) 1497f0c0761bSYongqiang Sun return dc->links[i]; 1498339cc82aSYongqiang Sun } 1499f0c0761bSYongqiang Sun return NULL; 1500339cc82aSYongqiang Sun } 1501339cc82aSYongqiang Sun 15020c522b65SEric Yang static struct dc_link *get_link_for_edp_to_turn_off( 150325292028SYongqiang Sun struct dc *dc, 150425292028SYongqiang Sun struct dc_state *context) 150525292028SYongqiang Sun { 150625292028SYongqiang Sun int i; 150725292028SYongqiang Sun struct dc_link *link = NULL; 150825292028SYongqiang Sun 150925292028SYongqiang Sun /* check if eDP panel is suppose to be set mode, if yes, no need to disable */ 151025292028SYongqiang Sun for (i = 0; i < context->stream_count; i++) { 15110c522b65SEric Yang if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 15120c522b65SEric Yang if (context->streams[i]->dpms_off == true) 15130c522b65SEric Yang return context->streams[i]->sink->link; 15140c522b65SEric Yang else 151525292028SYongqiang Sun return NULL; 151625292028SYongqiang Sun } 15170c522b65SEric Yang } 151825292028SYongqiang Sun 151925292028SYongqiang Sun /* check if there is an eDP panel not in use */ 152025292028SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 152125292028SYongqiang Sun if (dc->links[i]->local_sink && 152225292028SYongqiang Sun dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 152325292028SYongqiang Sun link = dc->links[i]; 152425292028SYongqiang Sun break; 152525292028SYongqiang Sun } 152625292028SYongqiang Sun } 152725292028SYongqiang Sun 152825292028SYongqiang Sun return link; 152925292028SYongqiang Sun } 153025292028SYongqiang Sun 15314562236bSHarry Wentland /** 15324562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 15334562236bSHarry Wentland * 1. Power down all DC HW blocks 15344562236bSHarry Wentland * 2. Disable VGA engine on all controllers 15354562236bSHarry Wentland * 3. Enable power gating for controller 15364562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 15374562236bSHarry Wentland */ 153825292028SYongqiang Sun void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 15394562236bSHarry Wentland { 1540d82f9942SAnthony Koo int i; 15414cac1e6dSYongqiang Sun struct dc_link *edp_link_to_turnoff = NULL; 1542f0c0761bSYongqiang Sun struct dc_link *edp_link = get_link_for_edp(dc); 1543d82f9942SAnthony Koo bool can_edp_fast_boot_optimize = false; 1544d82f9942SAnthony Koo bool apply_edp_fast_boot_optimization = false; 1545ce72741bSAnthony Koo bool can_apply_seamless_boot = false; 1546ce72741bSAnthony Koo 1547ce72741bSAnthony Koo for (i = 0; i < context->stream_count; i++) { 1548ce72741bSAnthony Koo if (context->streams[i]->apply_seamless_boot_optimization) { 1549ce72741bSAnthony Koo can_apply_seamless_boot = true; 1550ce72741bSAnthony Koo break; 1551ce72741bSAnthony Koo } 1552ce72741bSAnthony Koo } 15534cac1e6dSYongqiang Sun 1554522f82f3SAnthony Koo if (dc->hwss.init_pipes) 1555522f82f3SAnthony Koo dc->hwss.init_pipes(dc, context); 1556522f82f3SAnthony Koo 1557f0c0761bSYongqiang Sun if (edp_link) { 155895f05a3aSAlex Deucher /* this seems to cause blank screens on DCE8 */ 155995f05a3aSAlex Deucher if ((dc->ctx->dce_version == DCE_VERSION_8_0) || 156095f05a3aSAlex Deucher (dc->ctx->dce_version == DCE_VERSION_8_1) || 156195f05a3aSAlex Deucher (dc->ctx->dce_version == DCE_VERSION_8_3)) 1562d82f9942SAnthony Koo can_edp_fast_boot_optimize = false; 156395f05a3aSAlex Deucher else 1564d82f9942SAnthony Koo can_edp_fast_boot_optimize = 1565f0c0761bSYongqiang Sun edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc); 1566f0c0761bSYongqiang Sun } 1567f0c0761bSYongqiang Sun 1568d82f9942SAnthony Koo if (can_edp_fast_boot_optimize) 15690c522b65SEric Yang edp_link_to_turnoff = get_link_for_edp_to_turn_off(dc, context); 15704cac1e6dSYongqiang Sun 15712c37e49aSYongqiang Sun /* if OS doesn't light up eDP and eDP link is available, we want to disable 15722c37e49aSYongqiang Sun * If resume from S4/S5, should optimization. 15732c37e49aSYongqiang Sun */ 1574d82f9942SAnthony Koo if (can_edp_fast_boot_optimize && !edp_link_to_turnoff) { 1575d82f9942SAnthony Koo /* Find eDP stream and set optimization flag */ 1576d82f9942SAnthony Koo for (i = 0; i < context->stream_count; i++) { 1577d82f9942SAnthony Koo if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 1578d82f9942SAnthony Koo context->streams[i]->apply_edp_fast_boot_optimization = true; 1579d82f9942SAnthony Koo apply_edp_fast_boot_optimization = true; 1580d82f9942SAnthony Koo } 1581d82f9942SAnthony Koo } 15824cac1e6dSYongqiang Sun } 15834cac1e6dSYongqiang Sun 1584ce72741bSAnthony Koo if (!apply_edp_fast_boot_optimization && !can_apply_seamless_boot) { 15854cac1e6dSYongqiang Sun if (edp_link_to_turnoff) { 15864cac1e6dSYongqiang Sun /*turn off backlight before DP_blank and encoder powered down*/ 15874cac1e6dSYongqiang Sun dc->hwss.edp_backlight_control(edp_link_to_turnoff, false); 1588c5fc7f59SCharlene Liu } 1589c5fc7f59SCharlene Liu /*resume from S3, no vbios posting, no need to power down again*/ 159025292028SYongqiang Sun power_down_all_hw_blocks(dc); 15914562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 1592cf1835f0SCharlene Liu if (edp_link_to_turnoff) 1593cf1835f0SCharlene Liu dc->hwss.edp_power_control(edp_link_to_turnoff, false); 1594c5fc7f59SCharlene Liu } 15954562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 15964562236bSHarry Wentland } 15974562236bSHarry Wentland 15984562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 15994562236bSHarry Wentland struct bw_fixed blackout_duration, 16000971c40eSHarry Wentland const struct dc_stream_state *stream) 16014562236bSHarry Wentland { 16024562236bSHarry Wentland uint32_t total_dest_line_time_ns; 16034562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 16044562236bSHarry Wentland 16054562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 16064562236bSHarry Wentland 16074562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 1608380604e2SKen Chalmers (stream->timing.h_total * 10) / 1609380604e2SKen Chalmers stream->timing.pix_clk_100hz + 16104562236bSHarry Wentland pstate_blackout_duration_ns; 16114562236bSHarry Wentland 16124562236bSHarry Wentland return total_dest_line_time_ns; 16134562236bSHarry Wentland } 16144562236bSHarry Wentland 1615f774b339SEric Yang static void dce110_set_displaymarks( 1616fb3466a4SBhawanpreet Lakha const struct dc *dc, 1617608ac7bbSJerry Zuo struct dc_state *context) 16184562236bSHarry Wentland { 16194562236bSHarry Wentland uint8_t i, num_pipes; 16204562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 16214562236bSHarry Wentland 16224562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 16234562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 16244562236bSHarry Wentland uint32_t total_dest_line_time_ns; 16254562236bSHarry Wentland 16264562236bSHarry Wentland if (pipe_ctx->stream == NULL) 16274562236bSHarry Wentland continue; 16284562236bSHarry Wentland 16294562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 163077a4ea53SBhawanpreet Lakha dc->bw_vbios->blackout_duration, pipe_ctx->stream); 163186a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 163286a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 16339037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 16349037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 16353722c794SMikita Lipski context->bw.dce.stutter_entry_wm_ns[num_pipes], 16369037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 16374562236bSHarry Wentland total_dest_line_time_ns); 16384562236bSHarry Wentland if (i == underlay_idx) { 16394562236bSHarry Wentland num_pipes++; 164086a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 164186a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 16429037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 16439037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 16449037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 16454562236bSHarry Wentland total_dest_line_time_ns); 16464562236bSHarry Wentland } 16474562236bSHarry Wentland num_pipes++; 16484562236bSHarry Wentland } 16494562236bSHarry Wentland } 16504562236bSHarry Wentland 1651fab55d61SDmytro Laktyushkin void dce110_set_safe_displaymarks( 1652a2b8659dSTony Cheng struct resource_context *res_ctx, 1653a2b8659dSTony Cheng const struct resource_pool *pool) 16544562236bSHarry Wentland { 16554562236bSHarry Wentland int i; 1656a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 16579037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 16584562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 16599037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 16604562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 16613722c794SMikita Lipski struct dce_watermarks min_marks = { 0, 0, 0, 0}; 16624562236bSHarry Wentland 16634562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 16648feabd03SYue Hin Lau if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 16654562236bSHarry Wentland continue; 16664562236bSHarry Wentland 166786a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 166886a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 16694562236bSHarry Wentland nbp_marks, 16704562236bSHarry Wentland max_marks, 16713722c794SMikita Lipski min_marks, 16724562236bSHarry Wentland max_marks, 16734562236bSHarry Wentland MAX_WATERMARK); 16748feabd03SYue Hin Lau 16754562236bSHarry Wentland if (i == underlay_idx) 167686a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 167786a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 16784562236bSHarry Wentland nbp_marks, 16794562236bSHarry Wentland max_marks, 16804562236bSHarry Wentland max_marks, 16814562236bSHarry Wentland MAX_WATERMARK); 16828feabd03SYue Hin Lau 16834562236bSHarry Wentland } 16844562236bSHarry Wentland } 16854562236bSHarry Wentland 16864562236bSHarry Wentland /******************************************************************************* 16874562236bSHarry Wentland * Public functions 16884562236bSHarry Wentland ******************************************************************************/ 16894562236bSHarry Wentland 16904562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 16914562236bSHarry Wentland int num_pipes, int vmin, int vmax) 16924562236bSHarry Wentland { 16934562236bSHarry Wentland int i = 0; 16944562236bSHarry Wentland struct drr_params params = {0}; 169598e6436dSAnthony Koo // DRR should set trigger event to monitor surface update event 169698e6436dSAnthony Koo unsigned int event_triggers = 0x80; 16974562236bSHarry Wentland 16984562236bSHarry Wentland params.vertical_total_max = vmax; 16994562236bSHarry Wentland params.vertical_total_min = vmin; 17004562236bSHarry Wentland 17014562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 170298e6436dSAnthony Koo * some GSL stuff. Static screen triggers may be programmed differently 170398e6436dSAnthony Koo * as well. 17044562236bSHarry Wentland */ 17054562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 170698e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_drr( 170798e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, ¶ms); 170898e6436dSAnthony Koo 170998e6436dSAnthony Koo if (vmax != 0 && vmin != 0) 171098e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 171198e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, 171298e6436dSAnthony Koo event_triggers); 17134562236bSHarry Wentland } 17144562236bSHarry Wentland } 17154562236bSHarry Wentland 171672ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 171772ada5f7SEric Cook int num_pipes, 171872ada5f7SEric Cook struct crtc_position *position) 171972ada5f7SEric Cook { 172072ada5f7SEric Cook int i = 0; 172172ada5f7SEric Cook 172272ada5f7SEric Cook /* TODO: handle pipes > 1 172372ada5f7SEric Cook */ 172472ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 17256b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 172672ada5f7SEric Cook } 172772ada5f7SEric Cook 17284562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 172994267b3dSSylvia Tsai int num_pipes, const struct dc_static_screen_events *events) 17304562236bSHarry Wentland { 17314562236bSHarry Wentland unsigned int i; 173294267b3dSSylvia Tsai unsigned int value = 0; 173394267b3dSSylvia Tsai 173494267b3dSSylvia Tsai if (events->overlay_update) 173594267b3dSSylvia Tsai value |= 0x100; 173694267b3dSSylvia Tsai if (events->surface_update) 173794267b3dSSylvia Tsai value |= 0x80; 173894267b3dSSylvia Tsai if (events->cursor_update) 173994267b3dSSylvia Tsai value |= 0x2; 1740ed8462acSCharlene Liu if (events->force_trigger) 1741ed8462acSCharlene Liu value |= 0x1; 17424562236bSHarry Wentland 1743593f79a2SAlex Deucher if (num_pipes) { 1744593f79a2SAlex Deucher struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1745593f79a2SAlex Deucher 1746593f79a2SAlex Deucher if (dc->fbc_compressor) 1747c3aa1d67SBhawanpreet Lakha value |= 0x84; 1748593f79a2SAlex Deucher } 1749c3aa1d67SBhawanpreet Lakha 17504562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 17516b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs-> 17526b670fa9SHarry Wentland set_static_screen_control(pipe_ctx[i]->stream_res.tg, value); 17534562236bSHarry Wentland } 17544562236bSHarry Wentland 1755f6baff4dSHarry Wentland /* 1756690b5e39SRoman Li * Check if FBC can be enabled 1757690b5e39SRoman Li */ 17589c6569deSHarry Wentland static bool should_enable_fbc(struct dc *dc, 17593bc4aaa9SRoman Li struct dc_state *context, 17603bc4aaa9SRoman Li uint32_t *pipe_idx) 1761690b5e39SRoman Li { 17623bc4aaa9SRoman Li uint32_t i; 17633bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = NULL; 17643bc4aaa9SRoman Li struct resource_context *res_ctx = &context->res_ctx; 176565d38262Shersen wu unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 17663bc4aaa9SRoman Li 1767690b5e39SRoman Li 1768690b5e39SRoman Li ASSERT(dc->fbc_compressor); 1769690b5e39SRoman Li 1770690b5e39SRoman Li /* FBC memory should be allocated */ 1771690b5e39SRoman Li if (!dc->ctx->fbc_gpu_addr) 17729c6569deSHarry Wentland return false; 1773690b5e39SRoman Li 1774690b5e39SRoman Li /* Only supports single display */ 1775690b5e39SRoman Li if (context->stream_count != 1) 17769c6569deSHarry Wentland return false; 1777690b5e39SRoman Li 17783bc4aaa9SRoman Li for (i = 0; i < dc->res_pool->pipe_count; i++) { 17793bc4aaa9SRoman Li if (res_ctx->pipe_ctx[i].stream) { 178065d38262Shersen wu 17813bc4aaa9SRoman Li pipe_ctx = &res_ctx->pipe_ctx[i]; 178265d38262Shersen wu 178365d38262Shersen wu if (!pipe_ctx) 178465d38262Shersen wu continue; 178565d38262Shersen wu 178665d38262Shersen wu /* fbc not applicable on underlay pipe */ 178765d38262Shersen wu if (pipe_ctx->pipe_idx != underlay_idx) { 17883bc4aaa9SRoman Li *pipe_idx = i; 17893bc4aaa9SRoman Li break; 17903bc4aaa9SRoman Li } 17913bc4aaa9SRoman Li } 179265d38262Shersen wu } 17933bc4aaa9SRoman Li 179465d38262Shersen wu if (i == dc->res_pool->pipe_count) 179565d38262Shersen wu return false; 179665d38262Shersen wu 1797ceb3dbb4SJun Lei if (!pipe_ctx->stream->link) 179865d38262Shersen wu return false; 17997a840773SRoman Li 1800690b5e39SRoman Li /* Only supports eDP */ 1801ceb3dbb4SJun Lei if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 18029c6569deSHarry Wentland return false; 1803690b5e39SRoman Li 1804690b5e39SRoman Li /* PSR should not be enabled */ 1805ceb3dbb4SJun Lei if (pipe_ctx->stream->link->psr_enabled) 18069c6569deSHarry Wentland return false; 1807690b5e39SRoman Li 180893984bbcSShirish S /* Nothing to compress */ 180993984bbcSShirish S if (!pipe_ctx->plane_state) 18109c6569deSHarry Wentland return false; 181193984bbcSShirish S 181205230fa9SRoman Li /* Only for non-linear tiling */ 181305230fa9SRoman Li if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 18149c6569deSHarry Wentland return false; 181505230fa9SRoman Li 18169c6569deSHarry Wentland return true; 1817690b5e39SRoman Li } 1818690b5e39SRoman Li 1819690b5e39SRoman Li /* 1820690b5e39SRoman Li * Enable FBC 1821690b5e39SRoman Li */ 182265d38262Shersen wu static void enable_fbc( 182365d38262Shersen wu struct dc *dc, 1824608ac7bbSJerry Zuo struct dc_state *context) 1825690b5e39SRoman Li { 18263bc4aaa9SRoman Li uint32_t pipe_idx = 0; 18273bc4aaa9SRoman Li 18283bc4aaa9SRoman Li if (should_enable_fbc(dc, context, &pipe_idx)) { 1829690b5e39SRoman Li /* Program GRPH COMPRESSED ADDRESS and PITCH */ 1830690b5e39SRoman Li struct compr_addr_and_pitch_params params = {0, 0, 0}; 1831690b5e39SRoman Li struct compressor *compr = dc->fbc_compressor; 18323bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 18333bc4aaa9SRoman Li 18349c6569deSHarry Wentland params.source_view_width = pipe_ctx->stream->timing.h_addressable; 18359c6569deSHarry Wentland params.source_view_height = pipe_ctx->stream->timing.v_addressable; 183665d38262Shersen wu params.inst = pipe_ctx->stream_res.tg->inst; 1837690b5e39SRoman Li compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 1838690b5e39SRoman Li 1839690b5e39SRoman Li compr->funcs->surface_address_and_pitch(compr, ¶ms); 1840690b5e39SRoman Li compr->funcs->set_fbc_invalidation_triggers(compr, 1); 1841690b5e39SRoman Li 1842690b5e39SRoman Li compr->funcs->enable_fbc(compr, ¶ms); 1843690b5e39SRoman Li } 1844690b5e39SRoman Li } 1845690b5e39SRoman Li 184654e8695eSDmytro Laktyushkin static void dce110_reset_hw_ctx_wrap( 1847fb3466a4SBhawanpreet Lakha struct dc *dc, 1848608ac7bbSJerry Zuo struct dc_state *context) 18494562236bSHarry Wentland { 18504562236bSHarry Wentland int i; 18514562236bSHarry Wentland 18524562236bSHarry Wentland /* Reset old context */ 18534562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 1854a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 18554562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 1856608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 18574562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 18584562236bSHarry Wentland 18594562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 18604562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 18614562236bSHarry Wentland * PHY when not already disabled. 18624562236bSHarry Wentland */ 18634562236bSHarry Wentland 18644562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 18654562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 18664562236bSHarry Wentland continue; 18674562236bSHarry Wentland 18684562236bSHarry Wentland if (!pipe_ctx->stream || 186954e8695eSDmytro Laktyushkin pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 187021e67d4dSHarry Wentland struct clock_source *old_clk = pipe_ctx_old->clock_source; 187121e67d4dSHarry Wentland 1872827f11e9SLeo (Sunpeng) Li /* Disable if new stream is null. O/w, if stream is 1873827f11e9SLeo (Sunpeng) Li * disabled already, no need to disable again. 1874827f11e9SLeo (Sunpeng) Li */ 1875827f11e9SLeo (Sunpeng) Li if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) 18764176664bSCharlene Liu core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); 1877d050f8edSHersen Wu 18786b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 18796b670fa9SHarry Wentland if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 188054e8695eSDmytro Laktyushkin dm_error("DC: failed to blank crtc!\n"); 188154e8695eSDmytro Laktyushkin BREAK_TO_DEBUGGER(); 188254e8695eSDmytro Laktyushkin } 18836b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 188486a66c4eSHarry Wentland pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 1885608ac7bbSJerry Zuo pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 188654e8695eSDmytro Laktyushkin 1887ad8960a6SMikita Lipski if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 1888ad8960a6SMikita Lipski dc->res_pool, 1889ad8960a6SMikita Lipski old_clk)) 189021e67d4dSHarry Wentland old_clk->funcs->cs_power_down(old_clk); 189121e67d4dSHarry Wentland 18927f914a62SYongqiang Sun dc->hwss.disable_plane(dc, pipe_ctx_old); 189354e8695eSDmytro Laktyushkin 189454e8695eSDmytro Laktyushkin pipe_ctx_old->stream = NULL; 189554e8695eSDmytro Laktyushkin } 18964562236bSHarry Wentland } 18974562236bSHarry Wentland } 18984562236bSHarry Wentland 18991a05873fSAnthony Koo static void dce110_setup_audio_dto( 19001a05873fSAnthony Koo struct dc *dc, 19011a05873fSAnthony Koo struct dc_state *context) 19021a05873fSAnthony Koo { 19031a05873fSAnthony Koo int i; 19041a05873fSAnthony Koo 19051a05873fSAnthony Koo /* program audio wall clock. use HDMI as clock source if HDMI 19061a05873fSAnthony Koo * audio active. Otherwise, use DP as clock source 19071a05873fSAnthony Koo * first, loop to find any HDMI audio, if not, loop find DP audio 19081a05873fSAnthony Koo */ 19091a05873fSAnthony Koo /* Setup audio rate clock source */ 19101a05873fSAnthony Koo /* Issue: 19111a05873fSAnthony Koo * Audio lag happened on DP monitor when unplug a HDMI monitor 19121a05873fSAnthony Koo * 19131a05873fSAnthony Koo * Cause: 19141a05873fSAnthony Koo * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 19151a05873fSAnthony Koo * is set to either dto0 or dto1, audio should work fine. 19161a05873fSAnthony Koo * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 19171a05873fSAnthony Koo * set to dto0 will cause audio lag. 19181a05873fSAnthony Koo * 19191a05873fSAnthony Koo * Solution: 19201a05873fSAnthony Koo * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 19211a05873fSAnthony Koo * find first available pipe with audio, setup audio wall DTO per topology 19221a05873fSAnthony Koo * instead of per pipe. 19231a05873fSAnthony Koo */ 19241a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 19251a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 19261a05873fSAnthony Koo 19271a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 19281a05873fSAnthony Koo continue; 19291a05873fSAnthony Koo 19301a05873fSAnthony Koo if (pipe_ctx->top_pipe) 19311a05873fSAnthony Koo continue; 19321a05873fSAnthony Koo 19331a05873fSAnthony Koo if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 19341a05873fSAnthony Koo continue; 19351a05873fSAnthony Koo 19361a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 19371a05873fSAnthony Koo struct audio_output audio_output; 19381a05873fSAnthony Koo 19391a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 19401a05873fSAnthony Koo 19411a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 19421a05873fSAnthony Koo pipe_ctx->stream_res.audio, 19431a05873fSAnthony Koo pipe_ctx->stream->signal, 19441a05873fSAnthony Koo &audio_output.crtc_info, 19451a05873fSAnthony Koo &audio_output.pll_info); 19461a05873fSAnthony Koo break; 19471a05873fSAnthony Koo } 19481a05873fSAnthony Koo } 19491a05873fSAnthony Koo 19501a05873fSAnthony Koo /* no HDMI audio is found, try DP audio */ 19511a05873fSAnthony Koo if (i == dc->res_pool->pipe_count) { 19521a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 19531a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 19541a05873fSAnthony Koo 19551a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 19561a05873fSAnthony Koo continue; 19571a05873fSAnthony Koo 19581a05873fSAnthony Koo if (pipe_ctx->top_pipe) 19591a05873fSAnthony Koo continue; 19601a05873fSAnthony Koo 19611a05873fSAnthony Koo if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 19621a05873fSAnthony Koo continue; 19631a05873fSAnthony Koo 19641a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 19651a05873fSAnthony Koo struct audio_output audio_output; 19661a05873fSAnthony Koo 19671a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 19681a05873fSAnthony Koo 19691a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 19701a05873fSAnthony Koo pipe_ctx->stream_res.audio, 19711a05873fSAnthony Koo pipe_ctx->stream->signal, 19721a05873fSAnthony Koo &audio_output.crtc_info, 19731a05873fSAnthony Koo &audio_output.pll_info); 19741a05873fSAnthony Koo break; 19751a05873fSAnthony Koo } 19761a05873fSAnthony Koo } 19771a05873fSAnthony Koo } 19781a05873fSAnthony Koo } 1979cf437593SDmytro Laktyushkin 19804562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 1981fb3466a4SBhawanpreet Lakha struct dc *dc, 1982608ac7bbSJerry Zuo struct dc_state *context) 19834562236bSHarry Wentland { 19844562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 19854562236bSHarry Wentland enum dc_status status; 19864562236bSHarry Wentland int i; 19874562236bSHarry Wentland 19884562236bSHarry Wentland /* Reset old context */ 19894562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 19904562236bSHarry Wentland dc->hwss.reset_hw_ctx_wrap(dc, context); 19914562236bSHarry Wentland 19924562236bSHarry Wentland /* Skip applying if no targets */ 1993ab2541b6SAric Cyr if (context->stream_count <= 0) 19944562236bSHarry Wentland return DC_OK; 19954562236bSHarry Wentland 19964562236bSHarry Wentland /* Apply new context */ 19974562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 19984562236bSHarry Wentland 19994562236bSHarry Wentland /* below is for real asic only */ 2000a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 20014562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2002608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 20034562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 20044562236bSHarry Wentland 20054562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 20064562236bSHarry Wentland continue; 20074562236bSHarry Wentland 20084562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 20094562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 20104562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 20114562236bSHarry Wentland pipe_ctx->clock_source, i); 20124562236bSHarry Wentland continue; 20134562236bSHarry Wentland } 20144562236bSHarry Wentland 20154562236bSHarry Wentland dc->hwss.enable_display_power_gating( 20164562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 20174562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 20184562236bSHarry Wentland } 20194562236bSHarry Wentland 20202f3bfb27SRoman Li if (dc->fbc_compressor) 20211663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 20225099114bSAlex Deucher 20231a05873fSAnthony Koo dce110_setup_audio_dto(dc, context); 2024ab8812a3SHersen Wu 2025a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2026ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 2027608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 2028ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2029ab8812a3SHersen Wu 2030ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2031ab8812a3SHersen Wu continue; 2032ab8812a3SHersen Wu 2033ab8812a3SHersen Wu if (pipe_ctx->stream == pipe_ctx_old->stream) 2034ab8812a3SHersen Wu continue; 2035ab8812a3SHersen Wu 20365b92d9d4SHarry Wentland if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2037313bf4ffSYongqiang Sun continue; 2038313bf4ffSYongqiang Sun 2039ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 2040ab8812a3SHersen Wu continue; 2041ab8812a3SHersen Wu 20424562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 20434562236bSHarry Wentland pipe_ctx, 20444562236bSHarry Wentland context, 20454562236bSHarry Wentland dc); 20464562236bSHarry Wentland 20474562236bSHarry Wentland if (DC_OK != status) 20484562236bSHarry Wentland return status; 20494562236bSHarry Wentland } 20504562236bSHarry Wentland 2051690b5e39SRoman Li if (dc->fbc_compressor) 205265d38262Shersen wu enable_fbc(dc, dc->current_state); 205365d38262Shersen wu 205465d38262Shersen wu dcb->funcs->set_scratch_critical_state(dcb, false); 2055690b5e39SRoman Li 20564562236bSHarry Wentland return DC_OK; 20574562236bSHarry Wentland } 20584562236bSHarry Wentland 20594562236bSHarry Wentland /******************************************************************************* 20604562236bSHarry Wentland * Front End programming 20614562236bSHarry Wentland ******************************************************************************/ 20624562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 20634562236bSHarry Wentland { 20644562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 20654562236bSHarry Wentland 20664562236bSHarry Wentland default_adjust.force_hw_default = false; 206734996173SHarry Wentland default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 206834996173SHarry Wentland default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 20694562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 20706702a9acSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 20714562236bSHarry Wentland 20724562236bSHarry Wentland /* display color depth */ 20734562236bSHarry Wentland default_adjust.color_depth = 20744fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.display_color_depth; 20754562236bSHarry Wentland 20764562236bSHarry Wentland /* Lb color depth */ 20776702a9acSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 20784562236bSHarry Wentland 207986a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 208086a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, &default_adjust); 20814562236bSHarry Wentland } 20824562236bSHarry Wentland 2083b06b7680SLeon Elazar 2084b06b7680SLeon Elazar /******************************************************************************* 2085b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 2086b06b7680SLeon Elazar * Blender + CRTC 2087b06b7680SLeon Elazar * 2088b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 2089b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 2090b06b7680SLeon Elazar * 2091b06b7680SLeon Elazar * |----------------------------------------------- | 2092b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 2093b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 2094b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 2095b06b7680SLeon Elazar * |------------------------------------------------| 2096b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 2097b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 2098b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 2099b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 2100b06b7680SLeon Elazar * -------------------------------------------------| 2101b06b7680SLeon Elazar * 2102b06b7680SLeon Elazar ******************************************************************************/ 2103fb3466a4SBhawanpreet Lakha static void program_surface_visibility(const struct dc *dc, 21044562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 21054562236bSHarry Wentland { 21064562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2107b06b7680SLeon Elazar bool blank_target = false; 21084562236bSHarry Wentland 21094562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 2110b06b7680SLeon Elazar 2111b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 2112b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2113b06b7680SLeon Elazar 21143be5262eSHarry Wentland if (pipe_ctx->bottom_pipe->plane_state->visible) { 21153be5262eSHarry Wentland if (pipe_ctx->plane_state->visible) 21164562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 21174562236bSHarry Wentland else 21184562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 2119b06b7680SLeon Elazar 21203be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2121b06b7680SLeon Elazar blank_target = true; 2122b06b7680SLeon Elazar 21233be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2124b06b7680SLeon Elazar blank_target = true; 2125b06b7680SLeon Elazar 2126e07f541fSYongqiang Sun dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 21276b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2128b06b7680SLeon Elazar 21294562236bSHarry Wentland } 21304562236bSHarry Wentland 21311bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 21321bf56e62SZeyu Fan { 2133146a9f63SKrunoslav Kovac int i = 0; 21341bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 21351bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 21361bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 21371bf56e62SZeyu Fan 21381bf56e62SZeyu Fan 21394fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 21401bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2141146a9f63SKrunoslav Kovac 2142146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2143146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2144146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 21451bf56e62SZeyu Fan } 21461bf56e62SZeyu Fan 214786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 21481bf56e62SZeyu Fan } 2149fb3466a4SBhawanpreet Lakha static void update_plane_addr(const struct dc *dc, 21504562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 21514562236bSHarry Wentland { 21523be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 21534562236bSHarry Wentland 21543be5262eSHarry Wentland if (plane_state == NULL) 21554562236bSHarry Wentland return; 21564562236bSHarry Wentland 215786a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 215886a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 21593be5262eSHarry Wentland &plane_state->address, 21603be5262eSHarry Wentland plane_state->flip_immediate); 21614562236bSHarry Wentland 21623be5262eSHarry Wentland plane_state->status.requested_address = plane_state->address; 21634562236bSHarry Wentland } 21644562236bSHarry Wentland 2165f774b339SEric Yang static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 21664562236bSHarry Wentland { 21673be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 21684562236bSHarry Wentland 21693be5262eSHarry Wentland if (plane_state == NULL) 21704562236bSHarry Wentland return; 21714562236bSHarry Wentland 21723be5262eSHarry Wentland plane_state->status.is_flip_pending = 217386a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 217486a66c4eSHarry Wentland pipe_ctx->plane_res.mi); 21754562236bSHarry Wentland 21763be5262eSHarry Wentland if (plane_state->status.is_flip_pending && !plane_state->visible) 217786a66c4eSHarry Wentland pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 21784562236bSHarry Wentland 217986a66c4eSHarry Wentland plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 218086a66c4eSHarry Wentland if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 21816b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 21823be5262eSHarry Wentland plane_state->status.is_right_eye =\ 21836b670fa9SHarry Wentland !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 21847f5c22d1SVitaly Prosyak } 21854562236bSHarry Wentland } 21864562236bSHarry Wentland 2187fb3466a4SBhawanpreet Lakha void dce110_power_down(struct dc *dc) 21884562236bSHarry Wentland { 21894562236bSHarry Wentland power_down_all_hw_blocks(dc); 21904562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 21914562236bSHarry Wentland } 21924562236bSHarry Wentland 21934562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 21944562236bSHarry Wentland struct dc_context *dc_ctx, 21954562236bSHarry Wentland struct timing_generator *tg) 21964562236bSHarry Wentland { 21974562236bSHarry Wentland bool rc = false; 21984562236bSHarry Wentland 21994562236bSHarry Wentland /* To avoid endless loop we wait at most 22004562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 22014562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 22024562236bSHarry Wentland uint32_t i; 22034562236bSHarry Wentland 22044562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 22054562236bSHarry Wentland 22064562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 22074562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 22084562236bSHarry Wentland break; 22094562236bSHarry Wentland } 22104562236bSHarry Wentland 22114562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 22124562236bSHarry Wentland rc = true; 22134562236bSHarry Wentland /* usually occurs at i=1 */ 22144562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 22154562236bSHarry Wentland i); 22164562236bSHarry Wentland break; 22174562236bSHarry Wentland } 22184562236bSHarry Wentland 22194562236bSHarry Wentland /* Wait for one frame. */ 22204562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 22214562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 22224562236bSHarry Wentland } 22234562236bSHarry Wentland 22244562236bSHarry Wentland if (false == rc) 22254562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 22264562236bSHarry Wentland 22274562236bSHarry Wentland return rc; 22284562236bSHarry Wentland } 22294562236bSHarry Wentland 22304562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 22314562236bSHarry Wentland static void dce110_enable_timing_synchronization( 2232fb3466a4SBhawanpreet Lakha struct dc *dc, 22334562236bSHarry Wentland int group_index, 22344562236bSHarry Wentland int group_size, 22354562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 22364562236bSHarry Wentland { 22374562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 22384562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 22394562236bSHarry Wentland int i; 22404562236bSHarry Wentland 22414562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 22424562236bSHarry Wentland 22434562236bSHarry Wentland /* Designate a single TG in the group as a master. 22444562236bSHarry Wentland * Since HW doesn't care which one, we always assign 22454562236bSHarry Wentland * the 1st one in the group. */ 22464562236bSHarry Wentland gsl_params.gsl_group = 0; 22476b670fa9SHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 22484562236bSHarry Wentland 22494562236bSHarry Wentland for (i = 0; i < group_size; i++) 22506b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 22516b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg, &gsl_params); 22524562236bSHarry Wentland 22534562236bSHarry Wentland /* Reset slave controllers on master VSync */ 22544562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 22554562236bSHarry Wentland 22564562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 22576b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2258fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2259fa2123dbSMikita Lipski gsl_params.gsl_group); 22604562236bSHarry Wentland 22614562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 22624562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 22636b670fa9SHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2264fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2265fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg); 22664562236bSHarry Wentland } 22674562236bSHarry Wentland 22684562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 22694562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 22704562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 22714562236bSHarry Wentland for (i = 0; i < group_size; i++) 22726b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 22734562236bSHarry Wentland 22744562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 22754562236bSHarry Wentland } 22764562236bSHarry Wentland 2277fa2123dbSMikita Lipski static void dce110_enable_per_frame_crtc_position_reset( 2278fa2123dbSMikita Lipski struct dc *dc, 2279fa2123dbSMikita Lipski int group_size, 2280fa2123dbSMikita Lipski struct pipe_ctx *grouped_pipes[]) 2281fa2123dbSMikita Lipski { 2282fa2123dbSMikita Lipski struct dc_context *dc_ctx = dc->ctx; 2283fa2123dbSMikita Lipski struct dcp_gsl_params gsl_params = { 0 }; 2284fa2123dbSMikita Lipski int i; 2285fa2123dbSMikita Lipski 2286fa2123dbSMikita Lipski gsl_params.gsl_group = 0; 228737cd85ceSDavid Francis gsl_params.gsl_master = 0; 2288fa2123dbSMikita Lipski 2289fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2290fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2291fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, &gsl_params); 2292fa2123dbSMikita Lipski 2293fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2294fa2123dbSMikita Lipski 2295fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2296fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2297fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2298fa2123dbSMikita Lipski gsl_params.gsl_master, 2299fa2123dbSMikita Lipski &grouped_pipes[i]->stream->triggered_crtc_reset); 2300fa2123dbSMikita Lipski 2301fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2302fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2303fa2123dbSMikita Lipski wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2304fa2123dbSMikita Lipski 2305fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2306fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2307fa2123dbSMikita Lipski 2308fa2123dbSMikita Lipski } 2309fa2123dbSMikita Lipski 2310fb55546eSAnthony Koo static void init_pipes(struct dc *dc, struct dc_state *context) 2311fb55546eSAnthony Koo { 2312fb55546eSAnthony Koo // Do nothing 2313fb55546eSAnthony Koo } 2314fb55546eSAnthony Koo 2315fb3466a4SBhawanpreet Lakha static void init_hw(struct dc *dc) 23164562236bSHarry Wentland { 23174562236bSHarry Wentland int i; 23184562236bSHarry Wentland struct dc_bios *bp; 23194562236bSHarry Wentland struct transform *xfm; 23205e7773a2SAnthony Koo struct abm *abm; 23214562236bSHarry Wentland 23224562236bSHarry Wentland bp = dc->ctx->dc_bios; 23234562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 23244562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 23254562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 23264562236bSHarry Wentland 23274562236bSHarry Wentland dc->hwss.enable_display_power_gating( 23284562236bSHarry Wentland dc, i, bp, 23294562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 23304562236bSHarry Wentland dc->hwss.enable_display_power_gating( 23314562236bSHarry Wentland dc, i, bp, 23324562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 23334562236bSHarry Wentland dc->hwss.enable_display_pipe_clock_gating( 23344562236bSHarry Wentland dc->ctx, 23354562236bSHarry Wentland true); 23364562236bSHarry Wentland } 23374562236bSHarry Wentland 2338e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 23394562236bSHarry Wentland /***************************************/ 23404562236bSHarry Wentland 23414562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 23424562236bSHarry Wentland /****************************************/ 23434562236bSHarry Wentland /* Power up AND update implementation according to the 23444562236bSHarry Wentland * required signal (which may be different from the 23454562236bSHarry Wentland * default signal on connector). */ 2346d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 2347069d418fSAndrew Jiang 2348069d418fSAndrew Jiang if (link->link_enc->connector.id == CONNECTOR_ID_EDP) 2349069d418fSAndrew Jiang dc->hwss.edp_power_control(link, true); 2350069d418fSAndrew Jiang 23514562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 23524562236bSHarry Wentland } 23534562236bSHarry Wentland 23544562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 23554562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 23564562236bSHarry Wentland 23574562236bSHarry Wentland tg->funcs->disable_vga(tg); 23584562236bSHarry Wentland 23594562236bSHarry Wentland /* Blank controller using driver code instead of 23604562236bSHarry Wentland * command table. */ 23614562236bSHarry Wentland tg->funcs->set_blank(tg, true); 23624b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 23634562236bSHarry Wentland } 23644562236bSHarry Wentland 23654562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 23664562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 23674562236bSHarry Wentland audio->funcs->hw_init(audio); 23684562236bSHarry Wentland } 23695e7773a2SAnthony Koo 23705e7773a2SAnthony Koo abm = dc->res_pool->abm; 23716728b30cSAnthony Koo if (abm != NULL) { 23726728b30cSAnthony Koo abm->funcs->init_backlight(abm); 23735e7773a2SAnthony Koo abm->funcs->abm_init(abm); 23744562236bSHarry Wentland } 23755099114bSAlex Deucher 23762f3bfb27SRoman Li if (dc->fbc_compressor) 23771663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2378690b5e39SRoman Li 23796728b30cSAnthony Koo } 23804562236bSHarry Wentland 23819566b675SDmytro Laktyushkin 23829566b675SDmytro Laktyushkin void dce110_prepare_bandwidth( 2383fb3466a4SBhawanpreet Lakha struct dc *dc, 23849566b675SDmytro Laktyushkin struct dc_state *context) 2385cf437593SDmytro Laktyushkin { 238684e7fc05SDmytro Laktyushkin struct clk_mgr *dccg = dc->res_pool->clk_mgr; 2387fab55d61SDmytro Laktyushkin 2388fab55d61SDmytro Laktyushkin dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2389cf437593SDmytro Laktyushkin 23905a83c932SNicholas Kazlauskas dccg->funcs->update_clocks( 23915a83c932SNicholas Kazlauskas dccg, 239224f7dd7eSDmytro Laktyushkin context, 23939566b675SDmytro Laktyushkin false); 23949566b675SDmytro Laktyushkin } 23959566b675SDmytro Laktyushkin 23969566b675SDmytro Laktyushkin void dce110_optimize_bandwidth( 23979566b675SDmytro Laktyushkin struct dc *dc, 23989566b675SDmytro Laktyushkin struct dc_state *context) 23999566b675SDmytro Laktyushkin { 240084e7fc05SDmytro Laktyushkin struct clk_mgr *dccg = dc->res_pool->clk_mgr; 24019566b675SDmytro Laktyushkin 24029566b675SDmytro Laktyushkin dce110_set_displaymarks(dc, context); 24039566b675SDmytro Laktyushkin 24049566b675SDmytro Laktyushkin dccg->funcs->update_clocks( 24059566b675SDmytro Laktyushkin dccg, 24069566b675SDmytro Laktyushkin context, 24079566b675SDmytro Laktyushkin true); 24084562236bSHarry Wentland } 24094562236bSHarry Wentland 24104562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 2411fb3466a4SBhawanpreet Lakha struct dc *dc, struct pipe_ctx *pipe_ctx) 24124562236bSHarry Wentland { 241386a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 24144562236bSHarry Wentland struct pipe_ctx *old_pipe = NULL; 24153be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 24164562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 24174562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 24184562236bSHarry Wentland unsigned int i; 24195d4b05ddSBhawanpreet Lakha DC_LOGGER_INIT(); 24204562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 24214562236bSHarry Wentland 2422608ac7bbSJerry Zuo if (dc->current_state) 2423608ac7bbSJerry Zuo old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 24244562236bSHarry Wentland 24254562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 24264562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 24274562236bSHarry Wentland 2428e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 24294562236bSHarry Wentland 24304562236bSHarry Wentland set_default_colors(pipe_ctx); 24314fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 24324562236bSHarry Wentland == true) { 24334562236bSHarry Wentland tbl_entry.color_space = 24344fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 24354562236bSHarry Wentland 24364562236bSHarry Wentland for (i = 0; i < 12; i++) 24374562236bSHarry Wentland tbl_entry.regval[i] = 24384fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 24394562236bSHarry Wentland 244086a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 244186a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 24424562236bSHarry Wentland } 24434562236bSHarry Wentland 24444fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 24454562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2446146a9f63SKrunoslav Kovac 2447146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2448146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2449146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 24504562236bSHarry Wentland } 24514562236bSHarry Wentland 245286a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 24534562236bSHarry Wentland 24546702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2455c1473558SAndrey Grodzovsky 24564562236bSHarry Wentland program_scaler(dc, pipe_ctx); 24574562236bSHarry Wentland 24584562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 24594562236bSHarry Wentland mi, 24603be5262eSHarry Wentland plane_state->format, 24613be5262eSHarry Wentland &plane_state->tiling_info, 24623be5262eSHarry Wentland &plane_state->plane_size, 24633be5262eSHarry Wentland plane_state->rotation, 2464624d7c47SYongqiang Sun NULL, 24654b28b76bSDmytro Laktyushkin false); 24664b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 24673be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 24684562236bSHarry Wentland 2469fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 24704562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 247186a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 24723be5262eSHarry Wentland plane_state->format, 24733be5262eSHarry Wentland &plane_state->tiling_info, 24743be5262eSHarry Wentland plane_state->rotation); 24754562236bSHarry Wentland 2476067c878aSYongqiang Sun /* Moved programming gamma from dc to hwss */ 2477405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update || 2478405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2479405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.gamma_change) 2480a6114e85SHarry Wentland dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); 2481405c50a0SAndrew Jiang 2482405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update) 2483a6114e85SHarry Wentland dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); 2484067c878aSYongqiang Sun 24851296423bSBhawanpreet Lakha DC_LOG_SURFACE( 24863032deb5SBhawanpreet Lakha "Pipe:%d %p: addr hi:0x%x, " 24874562236bSHarry Wentland "addr low:0x%x, " 24884562236bSHarry Wentland "src: %d, %d, %d," 24894562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 24904562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 24914562236bSHarry Wentland pipe_ctx->pipe_idx, 24923032deb5SBhawanpreet Lakha (void *) pipe_ctx->plane_state, 24933be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.high_part, 24943be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.low_part, 24953be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.x, 24963be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.y, 24973be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.width, 24983be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.height, 24993be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.x, 25003be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.y, 25013be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.width, 25023be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.height, 25033be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.x, 25043be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.y, 25053be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.width, 25063be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.height); 25074562236bSHarry Wentland 25081296423bSBhawanpreet Lakha DC_LOG_SURFACE( 25094562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 25104562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 25114562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 25124562236bSHarry Wentland pipe_ctx->pipe_idx, 25136702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.width, 25146702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.height, 25156702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.x, 25166702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.y, 25176702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.width, 25186702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.height, 25196702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.x, 25206702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.y); 25214562236bSHarry Wentland } 25224562236bSHarry Wentland 25234562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 2524fb3466a4SBhawanpreet Lakha struct dc *dc, 25253e9ad616SEric Yang const struct dc_stream_state *stream, 25263e9ad616SEric Yang int num_planes, 2527608ac7bbSJerry Zuo struct dc_state *context) 25284562236bSHarry Wentland { 25292194e3aeSRoman Li int i; 25304562236bSHarry Wentland 25313e9ad616SEric Yang if (num_planes == 0) 25324562236bSHarry Wentland return; 25334562236bSHarry Wentland 253465d38262Shersen wu if (dc->fbc_compressor) 253565d38262Shersen wu dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 253665d38262Shersen wu 25373e9ad616SEric Yang for (i = 0; i < dc->res_pool->pipe_count; i++) { 25383dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 25393dc780ecSYongqiang Sun struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 25403dc780ecSYongqiang Sun 25412194e3aeSRoman Li if (stream == pipe_ctx->stream) { 25423dc780ecSYongqiang Sun if (!pipe_ctx->top_pipe && 25433dc780ecSYongqiang Sun (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) 25443dc780ecSYongqiang Sun dc->hwss.pipe_control_lock(dc, pipe_ctx, true); 25453e9ad616SEric Yang } 25463e9ad616SEric Yang } 25473e9ad616SEric Yang 2548a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 25494562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 25504562236bSHarry Wentland 2551a2607aefSHarry Wentland if (pipe_ctx->stream != stream) 25524562236bSHarry Wentland continue; 25534562236bSHarry Wentland 25543b21b6d2SJerry Zuo /* Need to allocate mem before program front end for Fiji */ 25553b21b6d2SJerry Zuo pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 25563b21b6d2SJerry Zuo pipe_ctx->plane_res.mi, 25573b21b6d2SJerry Zuo pipe_ctx->stream->timing.h_total, 25583b21b6d2SJerry Zuo pipe_ctx->stream->timing.v_total, 2559380604e2SKen Chalmers pipe_ctx->stream->timing.pix_clk_100hz / 10, 25603b21b6d2SJerry Zuo context->stream_count); 25613b21b6d2SJerry Zuo 25624562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 25634f804817SYongqiang Sun 25644f804817SYongqiang Sun dc->hwss.update_plane_addr(dc, pipe_ctx); 25654f804817SYongqiang Sun 2566b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 25674562236bSHarry Wentland 25684562236bSHarry Wentland } 25693dc780ecSYongqiang Sun 25703dc780ecSYongqiang Sun for (i = 0; i < dc->res_pool->pipe_count; i++) { 25713dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 25723dc780ecSYongqiang Sun struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 25733dc780ecSYongqiang Sun 25743dc780ecSYongqiang Sun if ((stream == pipe_ctx->stream) && 25753dc780ecSYongqiang Sun (!pipe_ctx->top_pipe) && 25763dc780ecSYongqiang Sun (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) 25773dc780ecSYongqiang Sun dc->hwss.pipe_control_lock(dc, pipe_ctx, false); 25783dc780ecSYongqiang Sun } 257965d38262Shersen wu 258065d38262Shersen wu if (dc->fbc_compressor) 258112a8bd88SShirish S enable_fbc(dc, context); 25824562236bSHarry Wentland } 25834562236bSHarry Wentland 2584e6c258cbSYongqiang Sun static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 25854562236bSHarry Wentland { 2586bc373a89SRoman Li int fe_idx = pipe_ctx->plane_res.mi ? 2587bc373a89SRoman Li pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2588e6c258cbSYongqiang Sun 25897950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2590608ac7bbSJerry Zuo if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 25914562236bSHarry Wentland return; 25924562236bSHarry Wentland 25934562236bSHarry Wentland dc->hwss.enable_display_power_gating( 2594cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2595cfe4645eSDmytro Laktyushkin 2596cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2597cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 25984562236bSHarry Wentland } 25994562236bSHarry Wentland 26006be425f3SEric Yang static void dce110_wait_for_mpcc_disconnect( 2601fb3466a4SBhawanpreet Lakha struct dc *dc, 26026be425f3SEric Yang struct resource_pool *res_pool, 26036be425f3SEric Yang struct pipe_ctx *pipe_ctx) 2604b6762f0cSEric Yang { 2605b6762f0cSEric Yang /* do nothing*/ 2606b6762f0cSEric Yang } 2607b6762f0cSEric Yang 26084bd0dc68SJoshua Aberback static void program_output_csc(struct dc *dc, 26094bd0dc68SJoshua Aberback struct pipe_ctx *pipe_ctx, 26104bd0dc68SJoshua Aberback enum dc_color_space colorspace, 26114bd0dc68SJoshua Aberback uint16_t *matrix, 26124bd0dc68SJoshua Aberback int opp_id) 26134bd0dc68SJoshua Aberback { 26144bd0dc68SJoshua Aberback int i; 26154bd0dc68SJoshua Aberback struct out_csc_color_matrix tbl_entry; 26164bd0dc68SJoshua Aberback 26174bd0dc68SJoshua Aberback if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 26184bd0dc68SJoshua Aberback enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 26194bd0dc68SJoshua Aberback 26204bd0dc68SJoshua Aberback for (i = 0; i < 12; i++) 26214bd0dc68SJoshua Aberback tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 26224bd0dc68SJoshua Aberback 26234bd0dc68SJoshua Aberback tbl_entry.color_space = color_space; 26244bd0dc68SJoshua Aberback 26254bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 26264bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm, &tbl_entry); 26274bd0dc68SJoshua Aberback } 26284bd0dc68SJoshua Aberback } 26294bd0dc68SJoshua Aberback 263033fd17d9SEric Yang void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 263133fd17d9SEric Yang { 263233fd17d9SEric Yang struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 263333fd17d9SEric Yang struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 263433fd17d9SEric Yang struct mem_input *mi = pipe_ctx->plane_res.mi; 263533fd17d9SEric Yang struct dc_cursor_mi_param param = { 2636380604e2SKen Chalmers .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 263733d7598dSJun Lei .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 263839a9f4d8SDmytro Laktyushkin .viewport = pipe_ctx->plane_res.scl_data.viewport, 263939a9f4d8SDmytro Laktyushkin .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 264039a9f4d8SDmytro Laktyushkin .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 264108ed681cSDmytro Laktyushkin .rotation = pipe_ctx->plane_state->rotation, 264208ed681cSDmytro Laktyushkin .mirror = pipe_ctx->plane_state->horizontal_mirror 264333fd17d9SEric Yang }; 264433fd17d9SEric Yang 264533fd17d9SEric Yang if (pipe_ctx->plane_state->address.type 264633fd17d9SEric Yang == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 264733fd17d9SEric Yang pos_cpy.enable = false; 264833fd17d9SEric Yang 264933fd17d9SEric Yang if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 265033fd17d9SEric Yang pos_cpy.enable = false; 265133fd17d9SEric Yang 2652dc75dd70SRoman Li if (ipp->funcs->ipp_cursor_set_position) 265333fd17d9SEric Yang ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2654dc75dd70SRoman Li if (mi->funcs->set_cursor_position) 265533fd17d9SEric Yang mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 265633fd17d9SEric Yang } 265733fd17d9SEric Yang 265833fd17d9SEric Yang void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 265933fd17d9SEric Yang { 266033fd17d9SEric Yang struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 266133fd17d9SEric Yang 2662d1aaad05SHarry Wentland if (pipe_ctx->plane_res.ipp && 2663d1aaad05SHarry Wentland pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 266433fd17d9SEric Yang pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 266533fd17d9SEric Yang pipe_ctx->plane_res.ipp, attributes); 266633fd17d9SEric Yang 2667d1aaad05SHarry Wentland if (pipe_ctx->plane_res.mi && 2668d1aaad05SHarry Wentland pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 266933fd17d9SEric Yang pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 267033fd17d9SEric Yang pipe_ctx->plane_res.mi, attributes); 267133fd17d9SEric Yang 2672d1aaad05SHarry Wentland if (pipe_ctx->plane_res.xfm && 2673d1aaad05SHarry Wentland pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 267433fd17d9SEric Yang pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 267533fd17d9SEric Yang pipe_ctx->plane_res.xfm, attributes); 267633fd17d9SEric Yang } 267733fd17d9SEric Yang 26784562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 26791bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 26804bd0dc68SJoshua Aberback .program_output_csc = program_output_csc, 26814562236bSHarry Wentland .init_hw = init_hw, 2682fb55546eSAnthony Koo .init_pipes = init_pipes, 26834562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 26844562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 26854562236bSHarry Wentland .update_plane_addr = update_plane_addr, 26864562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 2687d7194cf6SAric Cyr .set_input_transfer_func = dce110_set_input_transfer_func, 268890e508baSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 26894562236bSHarry Wentland .power_down = dce110_power_down, 26904562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 26914562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 2692fa2123dbSMikita Lipski .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 26934562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 26944562236bSHarry Wentland .enable_stream = dce110_enable_stream, 26954562236bSHarry Wentland .disable_stream = dce110_disable_stream, 26964562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 269741b49742SCharlene Liu .blank_stream = dce110_blank_stream, 26981a05873fSAnthony Koo .enable_audio_stream = dce110_enable_audio_stream, 26991a05873fSAnthony Koo .disable_audio_stream = dce110_disable_audio_stream, 27004562236bSHarry Wentland .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 27014562236bSHarry Wentland .enable_display_power_gating = dce110_enable_display_power_gating, 27027f914a62SYongqiang Sun .disable_plane = dce110_power_down_fe, 27034562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 27049566b675SDmytro Laktyushkin .prepare_bandwidth = dce110_prepare_bandwidth, 27059566b675SDmytro Laktyushkin .optimize_bandwidth = dce110_optimize_bandwidth, 27064562236bSHarry Wentland .set_drr = set_drr, 270772ada5f7SEric Cook .get_position = get_position, 27084562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 270954e8695eSDmytro Laktyushkin .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 27103158223eSEric Bernstein .enable_stream_timing = dce110_enable_stream_timing, 2711240d09d0SGary Kattan .disable_stream_gating = NULL, 2712240d09d0SGary Kattan .enable_stream_gating = NULL, 271315e17335SCharlene Liu .setup_stereo = NULL, 271415e17335SCharlene Liu .set_avmute = dce110_set_avmute, 271541f97c07SHersen Wu .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 271687401969SAndrew Jiang .edp_backlight_control = hwss_edp_backlight_control, 271787401969SAndrew Jiang .edp_power_control = hwss_edp_power_control, 2718904623eeSYongqiang Sun .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, 271933fd17d9SEric Yang .set_cursor_position = dce110_set_cursor_position, 272033fd17d9SEric Yang .set_cursor_attribute = dce110_set_cursor_attribute 27214562236bSHarry Wentland }; 27224562236bSHarry Wentland 2723c13b408bSDave Airlie void dce110_hw_sequencer_construct(struct dc *dc) 27244562236bSHarry Wentland { 27254562236bSHarry Wentland dc->hwss = dce110_funcs; 27264562236bSHarry Wentland } 27274562236bSHarry Wentland 2728