14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland #include "dm_services.h" 264562236bSHarry Wentland #include "dc.h" 274562236bSHarry Wentland #include "dc_bios_types.h" 284562236bSHarry Wentland #include "core_types.h" 294562236bSHarry Wentland #include "core_status.h" 304562236bSHarry Wentland #include "resource.h" 314562236bSHarry Wentland #include "dm_helpers.h" 324562236bSHarry Wentland #include "dce110_hw_sequencer.h" 334562236bSHarry Wentland #include "dce110_timing_generator.h" 3498489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 3587401969SAndrew Jiang #include "gpio_service_interface.h" 364562236bSHarry Wentland 373eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 381663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 391663ae1cSBhawanpreet Lakha #endif 401663ae1cSBhawanpreet Lakha 414562236bSHarry Wentland #include "bios/bios_parser_helper.h" 424562236bSHarry Wentland #include "timing_generator.h" 434562236bSHarry Wentland #include "mem_input.h" 444562236bSHarry Wentland #include "opp.h" 454562236bSHarry Wentland #include "ipp.h" 464562236bSHarry Wentland #include "transform.h" 474562236bSHarry Wentland #include "stream_encoder.h" 484562236bSHarry Wentland #include "link_encoder.h" 4987401969SAndrew Jiang #include "link_hwss.h" 504562236bSHarry Wentland #include "clock_source.h" 515e7773a2SAnthony Koo #include "abm.h" 524562236bSHarry Wentland #include "audio.h" 5308b16886SZeyu Fan #include "reg_helper.h" 544562236bSHarry Wentland 554562236bSHarry Wentland /* include DCE11 register header files */ 564562236bSHarry Wentland #include "dce/dce_11_0_d.h" 574562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 58e266fdf6SVitaly Prosyak #include "custom_float.h" 594562236bSHarry Wentland 604cac1e6dSYongqiang Sun #include "atomfirmware.h" 614cac1e6dSYongqiang Sun 6287401969SAndrew Jiang /* 6387401969SAndrew Jiang * All values are in milliseconds; 6487401969SAndrew Jiang * For eDP, after power-up/power/down, 6587401969SAndrew Jiang * 300/500 msec max. delay from LCDVCC to black video generation 6687401969SAndrew Jiang */ 6787401969SAndrew Jiang #define PANEL_POWER_UP_TIMEOUT 300 6887401969SAndrew Jiang #define PANEL_POWER_DOWN_TIMEOUT 500 6987401969SAndrew Jiang #define HPD_CHECK_INTERVAL 10 7087401969SAndrew Jiang 715eefbc40SYue Hin Lau #define CTX \ 725eefbc40SYue Hin Lau hws->ctx 735d4b05ddSBhawanpreet Lakha 745d4b05ddSBhawanpreet Lakha #define DC_LOGGER_INIT() 755d4b05ddSBhawanpreet Lakha 765eefbc40SYue Hin Lau #define REG(reg)\ 775eefbc40SYue Hin Lau hws->regs->reg 785eefbc40SYue Hin Lau 795eefbc40SYue Hin Lau #undef FN 805eefbc40SYue Hin Lau #define FN(reg_name, field_name) \ 815eefbc40SYue Hin Lau hws->shifts->field_name, hws->masks->field_name 825eefbc40SYue Hin Lau 834562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 844562236bSHarry Wentland uint32_t crtc; 854562236bSHarry Wentland }; 864562236bSHarry Wentland 874562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 884562236bSHarry Wentland { 894562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 904562236bSHarry Wentland }, 914562236bSHarry Wentland { 924562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 934562236bSHarry Wentland }, 944562236bSHarry Wentland { 954562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 964562236bSHarry Wentland }, 974562236bSHarry Wentland { 984562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 994562236bSHarry Wentland } 1004562236bSHarry Wentland }; 1014562236bSHarry Wentland 1024562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 1034562236bSHarry Wentland (reg + reg_offsets[id].blnd) 1044562236bSHarry Wentland 1054562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 1064562236bSHarry Wentland (reg + reg_offsets[id].crtc) 1074562236bSHarry Wentland 1084562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 1094562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 1104562236bSHarry Wentland 1114562236bSHarry Wentland /******************************************************************************* 1124562236bSHarry Wentland * Private definitions 1134562236bSHarry Wentland ******************************************************************************/ 1144562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 1154562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 1164562236bSHarry Wentland { 1174562236bSHarry Wentland uint32_t addr; 1184562236bSHarry Wentland uint32_t value = 0; 1194562236bSHarry Wentland uint32_t chunk_int = 0; 1204562236bSHarry Wentland uint32_t chunk_mul = 0; 1214562236bSHarry Wentland 1224562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 1234562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1244562236bSHarry Wentland 1254562236bSHarry Wentland set_reg_field_value( 1264562236bSHarry Wentland value, 1274562236bSHarry Wentland 0, 1284562236bSHarry Wentland DVMM_PTE_CONTROL, 1294562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1304562236bSHarry Wentland 1314562236bSHarry Wentland set_reg_field_value( 1324562236bSHarry Wentland value, 1334562236bSHarry Wentland 1, 1344562236bSHarry Wentland DVMM_PTE_CONTROL, 1354562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1364562236bSHarry Wentland 1374562236bSHarry Wentland set_reg_field_value( 1384562236bSHarry Wentland value, 1394562236bSHarry Wentland 1, 1404562236bSHarry Wentland DVMM_PTE_CONTROL, 1414562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1424562236bSHarry Wentland 1434562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1444562236bSHarry Wentland 1454562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1464562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1474562236bSHarry Wentland 1484562236bSHarry Wentland chunk_int = get_reg_field_value( 1494562236bSHarry Wentland value, 1504562236bSHarry Wentland DVMM_PTE_REQ, 1514562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1524562236bSHarry Wentland 1534562236bSHarry Wentland chunk_mul = get_reg_field_value( 1544562236bSHarry Wentland value, 1554562236bSHarry Wentland DVMM_PTE_REQ, 1564562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1574562236bSHarry Wentland 1584562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1594562236bSHarry Wentland 1604562236bSHarry Wentland set_reg_field_value( 1614562236bSHarry Wentland value, 1624562236bSHarry Wentland 255, 1634562236bSHarry Wentland DVMM_PTE_REQ, 1644562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1654562236bSHarry Wentland 1664562236bSHarry Wentland set_reg_field_value( 1674562236bSHarry Wentland value, 1684562236bSHarry Wentland 4, 1694562236bSHarry Wentland DVMM_PTE_REQ, 1704562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1714562236bSHarry Wentland 1724562236bSHarry Wentland set_reg_field_value( 1734562236bSHarry Wentland value, 1744562236bSHarry Wentland 4, 1754562236bSHarry Wentland DVMM_PTE_REQ, 1764562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1774562236bSHarry Wentland 1784562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1794562236bSHarry Wentland } 1804562236bSHarry Wentland } 1814562236bSHarry Wentland /**************************************************************************/ 1824562236bSHarry Wentland 1834562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1844562236bSHarry Wentland struct dc_context *ctx, 1854562236bSHarry Wentland bool clock_gating) 1864562236bSHarry Wentland { 1874562236bSHarry Wentland /*TODO*/ 1884562236bSHarry Wentland } 1894562236bSHarry Wentland 1904562236bSHarry Wentland static bool dce110_enable_display_power_gating( 191fb3466a4SBhawanpreet Lakha struct dc *dc, 1924562236bSHarry Wentland uint8_t controller_id, 1934562236bSHarry Wentland struct dc_bios *dcb, 1944562236bSHarry Wentland enum pipe_gating_control power_gating) 1954562236bSHarry Wentland { 1964562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 1974562236bSHarry Wentland enum bp_pipe_control_action cntl; 1984562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 1994562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 2004562236bSHarry Wentland 2014562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 2024562236bSHarry Wentland return true; 2034562236bSHarry Wentland 2044562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 2054562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 2064562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 2074562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 2084562236bSHarry Wentland else 2094562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 2104562236bSHarry Wentland 2114562236bSHarry Wentland if (controller_id == underlay_idx) 2124562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 2134562236bSHarry Wentland 2144562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 2154562236bSHarry Wentland 2164562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 2174562236bSHarry Wentland dcb, controller_id + 1, cntl); 2184562236bSHarry Wentland 2194562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 2204562236bSHarry Wentland * by default when command table is called 2214562236bSHarry Wentland * 2224562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 2234562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2244562236bSHarry Wentland * than 3. 2254562236bSHarry Wentland */ 2264562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2274562236bSHarry Wentland dm_write_reg(ctx, 2284562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2294562236bSHarry Wentland 0); 2304562236bSHarry Wentland } 2314562236bSHarry Wentland 2324562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2334562236bSHarry Wentland dce110_init_pte(ctx); 2344562236bSHarry Wentland 2354562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2364562236bSHarry Wentland return true; 2374562236bSHarry Wentland else 2384562236bSHarry Wentland return false; 2394562236bSHarry Wentland } 2404562236bSHarry Wentland 2414562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2423be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2434562236bSHarry Wentland { 2444562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2454562236bSHarry Wentland 2463be5262eSHarry Wentland switch (plane_state->format) { 2474562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2488693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2494562236bSHarry Wentland prescale_params->scale = 0x2020; 2504562236bSHarry Wentland break; 2514562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2524562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2534562236bSHarry Wentland prescale_params->scale = 0x2008; 2544562236bSHarry Wentland break; 2554562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2564562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2574562236bSHarry Wentland prescale_params->scale = 0x2000; 2584562236bSHarry Wentland break; 2594562236bSHarry Wentland default: 2604562236bSHarry Wentland ASSERT(false); 261d7194cf6SAric Cyr break; 2624562236bSHarry Wentland } 2634562236bSHarry Wentland } 2644562236bSHarry Wentland 265a6114e85SHarry Wentland static bool 266a6114e85SHarry Wentland dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, 2673be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2684562236bSHarry Wentland { 26986a66c4eSHarry Wentland struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2707b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 27190e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 27290e508baSAnthony Koo bool result = true; 27390e508baSAnthony Koo 27490e508baSAnthony Koo if (ipp == NULL) 27590e508baSAnthony Koo return false; 27690e508baSAnthony Koo 2773be5262eSHarry Wentland if (plane_state->in_transfer_func) 2783be5262eSHarry Wentland tf = plane_state->in_transfer_func; 27990e508baSAnthony Koo 2803be5262eSHarry Wentland build_prescale_params(&prescale_params, plane_state); 28190e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 28290e508baSAnthony Koo 28384ffa801SLeo (Sunpeng) Li if (plane_state->gamma_correction && 28484ffa801SLeo (Sunpeng) Li !plane_state->gamma_correction->is_identity && 28584ffa801SLeo (Sunpeng) Li dce_use_lut(plane_state->format)) 2863be5262eSHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 287d7194cf6SAric Cyr 28890e508baSAnthony Koo if (tf == NULL) { 28990e508baSAnthony Koo /* Default case if no input transfer function specified */ 290a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 2917b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 2927b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 29390e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 294a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 29590e508baSAnthony Koo break; 29690e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 297a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 29890e508baSAnthony Koo break; 29990e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 300a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 30190e508baSAnthony Koo break; 30290e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 30390e508baSAnthony Koo default: 30490e508baSAnthony Koo result = false; 305d7194cf6SAric Cyr break; 30690e508baSAnthony Koo } 3077b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 30870063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 30990e508baSAnthony Koo } else { 31090e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 31190e508baSAnthony Koo result = false; 31290e508baSAnthony Koo } 31390e508baSAnthony Koo 31490e508baSAnthony Koo return result; 31590e508baSAnthony Koo } 31690e508baSAnthony Koo 317bd1be8e8SHarry Wentland static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 318fcd2f4bfSAmy Zhang struct curve_points *arr_points, 319fcd2f4bfSAmy Zhang uint32_t hw_points_num) 320fcd2f4bfSAmy Zhang { 321fcd2f4bfSAmy Zhang struct custom_float_format fmt; 322fcd2f4bfSAmy Zhang 323fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 324fcd2f4bfSAmy Zhang 325fcd2f4bfSAmy Zhang uint32_t i = 0; 326fcd2f4bfSAmy Zhang 327fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 328fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 329fcd2f4bfSAmy Zhang fmt.sign = true; 330fcd2f4bfSAmy Zhang 331bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 332fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 333fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 334fcd2f4bfSAmy Zhang return false; 335fcd2f4bfSAmy Zhang } 336fcd2f4bfSAmy Zhang 337bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 338fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 339fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 340fcd2f4bfSAmy Zhang return false; 341fcd2f4bfSAmy Zhang } 342fcd2f4bfSAmy Zhang 343bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 344fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 345fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 346fcd2f4bfSAmy Zhang return false; 347fcd2f4bfSAmy Zhang } 348fcd2f4bfSAmy Zhang 349fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 350fcd2f4bfSAmy Zhang fmt.sign = false; 351fcd2f4bfSAmy Zhang 352bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 353fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 354fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 355fcd2f4bfSAmy Zhang return false; 356fcd2f4bfSAmy Zhang } 357fcd2f4bfSAmy Zhang 358bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 359fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 360fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 361fcd2f4bfSAmy Zhang return false; 362fcd2f4bfSAmy Zhang } 363fcd2f4bfSAmy Zhang 3644d06ccd0SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 3654d06ccd0SHarry Wentland &arr_points[1].custom_float_slope)) { 366fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 367fcd2f4bfSAmy Zhang return false; 368fcd2f4bfSAmy Zhang } 369fcd2f4bfSAmy Zhang 370fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 371fcd2f4bfSAmy Zhang fmt.sign = true; 372fcd2f4bfSAmy Zhang 373fcd2f4bfSAmy Zhang while (i != hw_points_num) { 374bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->red, &fmt, 375fcd2f4bfSAmy Zhang &rgb->red_reg)) { 376fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 377fcd2f4bfSAmy Zhang return false; 378fcd2f4bfSAmy Zhang } 379fcd2f4bfSAmy Zhang 380bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->green, &fmt, 381fcd2f4bfSAmy Zhang &rgb->green_reg)) { 382fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 383fcd2f4bfSAmy Zhang return false; 384fcd2f4bfSAmy Zhang } 385fcd2f4bfSAmy Zhang 386bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->blue, &fmt, 387fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 388fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 389fcd2f4bfSAmy Zhang return false; 390fcd2f4bfSAmy Zhang } 391fcd2f4bfSAmy Zhang 392bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 393fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 394fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 395fcd2f4bfSAmy Zhang return false; 396fcd2f4bfSAmy Zhang } 397fcd2f4bfSAmy Zhang 398bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 399fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 400fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 401fcd2f4bfSAmy Zhang return false; 402fcd2f4bfSAmy Zhang } 403fcd2f4bfSAmy Zhang 404bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 405fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 406fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 407fcd2f4bfSAmy Zhang return false; 408fcd2f4bfSAmy Zhang } 409fcd2f4bfSAmy Zhang 410fcd2f4bfSAmy Zhang ++rgb; 411fcd2f4bfSAmy Zhang ++i; 412fcd2f4bfSAmy Zhang } 413fcd2f4bfSAmy Zhang 414fcd2f4bfSAmy Zhang return true; 415fcd2f4bfSAmy Zhang } 416fcd2f4bfSAmy Zhang 41708616da5SLeo (Sunpeng) Li #define MAX_LOW_POINT 25 4188f8372c7SKrunoslav Kovac #define NUMBER_REGIONS 16 4198f8372c7SKrunoslav Kovac #define NUMBER_SW_SEGMENTS 16 4208f8372c7SKrunoslav Kovac 421b310b081SHarry Wentland static bool 422b310b081SHarry Wentland dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 423b310b081SHarry Wentland struct pwl_params *regamma_params) 424fcd2f4bfSAmy Zhang { 42523ae4f8eSAmy Zhang struct curve_points *arr_points; 42623ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 42723ae4f8eSAmy Zhang struct pwl_result_data *rgb; 42823ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 429fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 430fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 431fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 432fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 433fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 434fcd2f4bfSAmy Zhang 4358f8372c7SKrunoslav Kovac int32_t region_start, region_end; 4368f8372c7SKrunoslav Kovac uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 43723ae4f8eSAmy Zhang 438b310b081SHarry Wentland if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 43923ae4f8eSAmy Zhang return false; 44023ae4f8eSAmy Zhang 44123ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 44223ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 44323ae4f8eSAmy Zhang hw_points = 0; 444fcd2f4bfSAmy Zhang 445fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 446fcd2f4bfSAmy Zhang 447fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 448534db198SAmy Zhang /* 16 segments 449fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 450fcd2f4bfSAmy Zhang */ 45108616da5SLeo (Sunpeng) Li region_start = -11; 45208616da5SLeo (Sunpeng) Li region_end = region_start + NUMBER_REGIONS; 453fcd2f4bfSAmy Zhang 4548f8372c7SKrunoslav Kovac for (i = 0; i < NUMBER_REGIONS; i++) 4558f8372c7SKrunoslav Kovac seg_distr[i] = 4; 456534db198SAmy Zhang 457fcd2f4bfSAmy Zhang } else { 458534db198SAmy Zhang /* 10 segments 459fcd2f4bfSAmy Zhang * segment is from 2^-10 to 2^0 460fcd2f4bfSAmy Zhang */ 4618f8372c7SKrunoslav Kovac region_start = -10; 4628f8372c7SKrunoslav Kovac region_end = 0; 463534db198SAmy Zhang 4648f8372c7SKrunoslav Kovac seg_distr[0] = 4; 465534db198SAmy Zhang seg_distr[1] = 4; 466534db198SAmy Zhang seg_distr[2] = 4; 467534db198SAmy Zhang seg_distr[3] = 4; 468534db198SAmy Zhang seg_distr[4] = 4; 469534db198SAmy Zhang seg_distr[5] = 4; 470534db198SAmy Zhang seg_distr[6] = 4; 471534db198SAmy Zhang seg_distr[7] = 4; 4728f8372c7SKrunoslav Kovac seg_distr[8] = 4; 4738f8372c7SKrunoslav Kovac seg_distr[9] = 4; 474534db198SAmy Zhang seg_distr[10] = -1; 475534db198SAmy Zhang seg_distr[11] = -1; 476534db198SAmy Zhang seg_distr[12] = -1; 477534db198SAmy Zhang seg_distr[13] = -1; 478534db198SAmy Zhang seg_distr[14] = -1; 479534db198SAmy Zhang seg_distr[15] = -1; 480fcd2f4bfSAmy Zhang } 481fcd2f4bfSAmy Zhang 482534db198SAmy Zhang for (k = 0; k < 16; k++) { 483534db198SAmy Zhang if (seg_distr[k] != -1) 484534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 485534db198SAmy Zhang } 486534db198SAmy Zhang 487fcd2f4bfSAmy Zhang j = 0; 4888f8372c7SKrunoslav Kovac for (k = 0; k < (region_end - region_start); k++) { 489ec47734aSLeo (Sunpeng) Li increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 4908f8372c7SKrunoslav Kovac start_index = (region_start + k + MAX_LOW_POINT) * 4918f8372c7SKrunoslav Kovac NUMBER_SW_SEGMENTS; 4928f8372c7SKrunoslav Kovac for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 4938f8372c7SKrunoslav Kovac i += increment) { 494534db198SAmy Zhang if (j == hw_points - 1) 495fcd2f4bfSAmy Zhang break; 496fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 497fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 498fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 499fcd2f4bfSAmy Zhang j++; 500fcd2f4bfSAmy Zhang } 501534db198SAmy Zhang } 502534db198SAmy Zhang 503534db198SAmy Zhang /* last point */ 5048f8372c7SKrunoslav Kovac start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 505b310b081SHarry Wentland rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 506b310b081SHarry Wentland rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 507b310b081SHarry Wentland rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 508fcd2f4bfSAmy Zhang 509fcd2f4bfSAmy Zhang arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 5108f8372c7SKrunoslav Kovac dal_fixed31_32_from_int(region_start)); 511fcd2f4bfSAmy Zhang arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 5128f8372c7SKrunoslav Kovac dal_fixed31_32_from_int(region_end)); 513fcd2f4bfSAmy Zhang 514fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 515fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 516fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 517fcd2f4bfSAmy Zhang 518fcd2f4bfSAmy Zhang y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); 519fcd2f4bfSAmy Zhang 520fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 521b310b081SHarry Wentland arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, 522fcd2f4bfSAmy Zhang arr_points[0].x); 523fcd2f4bfSAmy Zhang 524fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 525fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 526fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 527fcd2f4bfSAmy Zhang 528fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 529fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 530fcd2f4bfSAmy Zhang */ 531fcd2f4bfSAmy Zhang y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); 532fcd2f4bfSAmy Zhang 533fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 534fcd2f4bfSAmy Zhang 535fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_zero; 536fcd2f4bfSAmy Zhang 537fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 538fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 539fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 540fcd2f4bfSAmy Zhang */ 541b310b081SHarry Wentland const struct fixed31_32 end_value = dal_fixed31_32_from_int(125); 542fcd2f4bfSAmy Zhang 543fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_div( 544fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 545fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 546fcd2f4bfSAmy Zhang } 547fcd2f4bfSAmy Zhang 548fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 549fcd2f4bfSAmy Zhang 550534db198SAmy Zhang i = 1; 551534db198SAmy Zhang for (k = 0; k < 16 && i < 16; k++) { 552534db198SAmy Zhang if (seg_distr[k] != -1) { 553b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 554534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 555b310b081SHarry Wentland regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 556fcd2f4bfSAmy Zhang } 557534db198SAmy Zhang i++; 558534db198SAmy Zhang } 559534db198SAmy Zhang 560534db198SAmy Zhang if (seg_distr[k] != -1) 561b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 562fcd2f4bfSAmy Zhang 56323ae4f8eSAmy Zhang rgb = rgb_resulted; 56423ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 565fcd2f4bfSAmy Zhang 566fcd2f4bfSAmy Zhang i = 1; 567fcd2f4bfSAmy Zhang 568fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 569fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) 570fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 571fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) 572fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 573fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) 574fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 575fcd2f4bfSAmy Zhang 576b310b081SHarry Wentland rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); 577b310b081SHarry Wentland rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); 578b310b081SHarry Wentland rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); 579fcd2f4bfSAmy Zhang 580fcd2f4bfSAmy Zhang ++rgb_plus_1; 581fcd2f4bfSAmy Zhang ++rgb; 582fcd2f4bfSAmy Zhang ++i; 583fcd2f4bfSAmy Zhang } 584fcd2f4bfSAmy Zhang 585fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 586fcd2f4bfSAmy Zhang 587fcd2f4bfSAmy Zhang return true; 588fcd2f4bfSAmy Zhang } 589fcd2f4bfSAmy Zhang 590a6114e85SHarry Wentland static bool 591a6114e85SHarry Wentland dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, 5920971c40eSHarry Wentland const struct dc_stream_state *stream) 59390e508baSAnthony Koo { 59486a66c4eSHarry Wentland struct transform *xfm = pipe_ctx->plane_res.xfm; 5954562236bSHarry Wentland 5967a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, true); 5977a09f5beSYue Hin Lau xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 5984562236bSHarry Wentland 5994fa086b9SLeo (Sunpeng) Li if (stream->out_transfer_func && 600efd52204SHarry Wentland stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 601efd52204SHarry Wentland stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 6027a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 603efd52204SHarry Wentland } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 604efd52204SHarry Wentland &xfm->regamma_params)) { 6057a09f5beSYue Hin Lau xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 6067a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 6074562236bSHarry Wentland } else { 6087a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 6094562236bSHarry Wentland } 6104562236bSHarry Wentland 6117a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, false); 6124562236bSHarry Wentland 613cc0cb445SLeon Elazar return true; 6144562236bSHarry Wentland } 6154562236bSHarry Wentland 6164562236bSHarry Wentland static enum dc_status bios_parser_crtc_source_select( 6174562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 6184562236bSHarry Wentland { 6194562236bSHarry Wentland struct dc_bios *dcb; 6204562236bSHarry Wentland /* call VBIOS table to set CRTC source for the HW 6214562236bSHarry Wentland * encoder block 6224562236bSHarry Wentland * note: video bios clears all FMT setting here. */ 6234562236bSHarry Wentland struct bp_crtc_source_select crtc_source_select = {0}; 624b73a22d3SHarry Wentland const struct dc_sink *sink = pipe_ctx->stream->sink; 6254562236bSHarry Wentland 6268e9c4c8cSHarry Wentland crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id; 627e07f541fSYongqiang Sun crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1; 6284562236bSHarry Wentland /*TODO: Need to un-hardcode color depth, dp_audio and account for 6294562236bSHarry Wentland * the case where signal and sink signal is different (translator 6304562236bSHarry Wentland * encoder)*/ 6314562236bSHarry Wentland crtc_source_select.signal = pipe_ctx->stream->signal; 6324562236bSHarry Wentland crtc_source_select.enable_dp_audio = false; 6334562236bSHarry Wentland crtc_source_select.sink_signal = pipe_ctx->stream->signal; 6341b7441b0SCharlene Liu 6351b7441b0SCharlene Liu switch (pipe_ctx->stream->timing.display_color_depth) { 6361b7441b0SCharlene Liu case COLOR_DEPTH_666: 6371b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR; 6381b7441b0SCharlene Liu break; 6391b7441b0SCharlene Liu case COLOR_DEPTH_888: 6404562236bSHarry Wentland crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6411b7441b0SCharlene Liu break; 6421b7441b0SCharlene Liu case COLOR_DEPTH_101010: 6431b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR; 6441b7441b0SCharlene Liu break; 6451b7441b0SCharlene Liu case COLOR_DEPTH_121212: 6461b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR; 6471b7441b0SCharlene Liu break; 6481b7441b0SCharlene Liu default: 6491b7441b0SCharlene Liu BREAK_TO_DEBUGGER(); 6501b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6511b7441b0SCharlene Liu break; 6521b7441b0SCharlene Liu } 6534562236bSHarry Wentland 6544562236bSHarry Wentland dcb = sink->ctx->dc_bios; 6554562236bSHarry Wentland 6564562236bSHarry Wentland if (BP_RESULT_OK != dcb->funcs->crtc_source_select( 6574562236bSHarry Wentland dcb, 6584562236bSHarry Wentland &crtc_source_select)) { 6594562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 6604562236bSHarry Wentland } 6614562236bSHarry Wentland 6624562236bSHarry Wentland return DC_OK; 6634562236bSHarry Wentland } 6644562236bSHarry Wentland 6654562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6664562236bSHarry Wentland { 66786e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 66886e2e1beSHersen Wu 6698e9c4c8cSHarry Wentland if (pipe_ctx->stream_res.stream_enc == NULL) 67086e2e1beSHersen Wu return; /* this is not root pipe */ 67186e2e1beSHersen Wu 6724562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 6738e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 6748e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 67596c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6764562236bSHarry Wentland else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6778e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 6788e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 67996c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6804562236bSHarry Wentland } 6814562236bSHarry Wentland 6824562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6834562236bSHarry Wentland { 6844562236bSHarry Wentland enum dc_lane_count lane_count = 685d0778ebfSHarry Wentland pipe_ctx->stream->sink->link->cur_link_settings.lane_count; 6864562236bSHarry Wentland 6874fa086b9SLeo (Sunpeng) Li struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 688d0778ebfSHarry Wentland struct dc_link *link = pipe_ctx->stream->sink->link; 6894562236bSHarry Wentland 690f215a57dSEric Yang 6914562236bSHarry Wentland uint32_t active_total_with_borders; 6924562236bSHarry Wentland uint32_t early_control = 0; 6936b670fa9SHarry Wentland struct timing_generator *tg = pipe_ctx->stream_res.tg; 6944562236bSHarry Wentland 695f215a57dSEric Yang /* For MST, there are multiply stream go to only one link. 696f215a57dSEric Yang * connect DIG back_end to front_end while enable_stream and 697f215a57dSEric Yang * disconnect them during disable_stream 698f215a57dSEric Yang * BY this, it is logic clean to separate stream and link */ 699f215a57dSEric Yang link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 700f215a57dSEric Yang pipe_ctx->stream_res.stream_enc->id, true); 701f215a57dSEric Yang 702f215a57dSEric Yang /* update AVI info frame (HDMI, DP)*/ 703f215a57dSEric Yang /* TODO: FPGA may change to hwss.update_info_frame */ 7044562236bSHarry Wentland dce110_update_info_frame(pipe_ctx); 705f215a57dSEric Yang 7064562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 7074562236bSHarry Wentland active_total_with_borders = 7084562236bSHarry Wentland timing->h_addressable 7094562236bSHarry Wentland + timing->h_border_left 7104562236bSHarry Wentland + timing->h_border_right; 7114562236bSHarry Wentland 7124562236bSHarry Wentland if (lane_count != 0) 7134562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 7144562236bSHarry Wentland 7154562236bSHarry Wentland if (early_control == 0) 7164562236bSHarry Wentland early_control = lane_count; 7174562236bSHarry Wentland 7184562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 7194562236bSHarry Wentland 7204562236bSHarry Wentland /* enable audio only within mode set */ 721afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 7224562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7238e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 7244562236bSHarry Wentland } 7254562236bSHarry Wentland 726f215a57dSEric Yang 727f215a57dSEric Yang 7284562236bSHarry Wentland 7294562236bSHarry Wentland } 7304562236bSHarry Wentland 7315eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 7325eefbc40SYue Hin Lau static bool is_panel_backlight_on(struct dce_hwseq *hws) 7335eefbc40SYue Hin Lau { 7345eefbc40SYue Hin Lau uint32_t value; 7355eefbc40SYue Hin Lau 7365eefbc40SYue Hin Lau REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value); 7375eefbc40SYue Hin Lau 7385eefbc40SYue Hin Lau return value; 7395eefbc40SYue Hin Lau } 7405eefbc40SYue Hin Lau 74187401969SAndrew Jiang static bool is_panel_powered_on(struct dce_hwseq *hws) 74287401969SAndrew Jiang { 743d03f3f63SEric Yang uint32_t pwr_seq_state, dig_on, dig_on_ovrd; 74487401969SAndrew Jiang 745d03f3f63SEric Yang 746d03f3f63SEric Yang REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); 747d03f3f63SEric Yang 748d03f3f63SEric Yang REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd); 749d03f3f63SEric Yang 750d03f3f63SEric Yang return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1); 75187401969SAndrew Jiang } 75287401969SAndrew Jiang 7535eefbc40SYue Hin Lau static enum bp_result link_transmitter_control( 75487401969SAndrew Jiang struct dc_bios *bios, 7555eefbc40SYue Hin Lau struct bp_transmitter_control *cntl) 7565eefbc40SYue Hin Lau { 7575eefbc40SYue Hin Lau enum bp_result result; 7585eefbc40SYue Hin Lau 75987401969SAndrew Jiang result = bios->funcs->transmitter_control(bios, cntl); 7605eefbc40SYue Hin Lau 7615eefbc40SYue Hin Lau return result; 7625eefbc40SYue Hin Lau } 7635eefbc40SYue Hin Lau 76487401969SAndrew Jiang /* 76587401969SAndrew Jiang * @brief 76687401969SAndrew Jiang * eDP only. 76787401969SAndrew Jiang */ 76887401969SAndrew Jiang void hwss_edp_wait_for_hpd_ready( 769069d418fSAndrew Jiang struct dc_link *link, 77087401969SAndrew Jiang bool power_up) 77187401969SAndrew Jiang { 772069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 773069d418fSAndrew Jiang struct graphics_object_id connector = link->link_enc->connector; 77487401969SAndrew Jiang struct gpio *hpd; 77587401969SAndrew Jiang bool edp_hpd_high = false; 77687401969SAndrew Jiang uint32_t time_elapsed = 0; 77787401969SAndrew Jiang uint32_t timeout = power_up ? 77887401969SAndrew Jiang PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 77987401969SAndrew Jiang 78087401969SAndrew Jiang if (dal_graphics_object_id_get_connector_id(connector) 78187401969SAndrew Jiang != CONNECTOR_ID_EDP) { 78287401969SAndrew Jiang BREAK_TO_DEBUGGER(); 78387401969SAndrew Jiang return; 78487401969SAndrew Jiang } 78587401969SAndrew Jiang 78687401969SAndrew Jiang if (!power_up) 78787401969SAndrew Jiang /* 78887401969SAndrew Jiang * From KV, we will not HPD low after turning off VCC - 78987401969SAndrew Jiang * instead, we will check the SW timer in power_up(). 79087401969SAndrew Jiang */ 79187401969SAndrew Jiang return; 79287401969SAndrew Jiang 79387401969SAndrew Jiang /* 79487401969SAndrew Jiang * When we power on/off the eDP panel, 79587401969SAndrew Jiang * we need to wait until SENSE bit is high/low. 79687401969SAndrew Jiang */ 79787401969SAndrew Jiang 79887401969SAndrew Jiang /* obtain HPD */ 79987401969SAndrew Jiang /* TODO what to do with this? */ 80087401969SAndrew Jiang hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 80187401969SAndrew Jiang 80287401969SAndrew Jiang if (!hpd) { 80387401969SAndrew Jiang BREAK_TO_DEBUGGER(); 80487401969SAndrew Jiang return; 80587401969SAndrew Jiang } 80687401969SAndrew Jiang 80787401969SAndrew Jiang dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 80887401969SAndrew Jiang 80987401969SAndrew Jiang /* wait until timeout or panel detected */ 81087401969SAndrew Jiang 81187401969SAndrew Jiang do { 81287401969SAndrew Jiang uint32_t detected = 0; 81387401969SAndrew Jiang 81487401969SAndrew Jiang dal_gpio_get_value(hpd, &detected); 81587401969SAndrew Jiang 81687401969SAndrew Jiang if (!(detected ^ power_up)) { 81787401969SAndrew Jiang edp_hpd_high = true; 81887401969SAndrew Jiang break; 81987401969SAndrew Jiang } 82087401969SAndrew Jiang 82187401969SAndrew Jiang msleep(HPD_CHECK_INTERVAL); 82287401969SAndrew Jiang 82387401969SAndrew Jiang time_elapsed += HPD_CHECK_INTERVAL; 82487401969SAndrew Jiang } while (time_elapsed < timeout); 82587401969SAndrew Jiang 82687401969SAndrew Jiang dal_gpio_close(hpd); 82787401969SAndrew Jiang 82887401969SAndrew Jiang dal_gpio_destroy_irq(&hpd); 82987401969SAndrew Jiang 83087401969SAndrew Jiang if (false == edp_hpd_high) { 8311296423bSBhawanpreet Lakha DC_LOG_ERROR( 83287401969SAndrew Jiang "%s: wait timed out!\n", __func__); 83387401969SAndrew Jiang } 83487401969SAndrew Jiang } 83587401969SAndrew Jiang 83687401969SAndrew Jiang void hwss_edp_power_control( 837069d418fSAndrew Jiang struct dc_link *link, 83887401969SAndrew Jiang bool power_up) 83987401969SAndrew Jiang { 840069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 84187401969SAndrew Jiang struct dce_hwseq *hwseq = ctx->dc->hwseq; 84287401969SAndrew Jiang struct bp_transmitter_control cntl = { 0 }; 84387401969SAndrew Jiang enum bp_result bp_result; 84487401969SAndrew Jiang 84587401969SAndrew Jiang 846069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 84787401969SAndrew Jiang != CONNECTOR_ID_EDP) { 84887401969SAndrew Jiang BREAK_TO_DEBUGGER(); 84987401969SAndrew Jiang return; 85087401969SAndrew Jiang } 85187401969SAndrew Jiang 85287401969SAndrew Jiang if (power_up != is_panel_powered_on(hwseq)) { 85387401969SAndrew Jiang /* Send VBIOS command to prompt eDP panel power */ 85478d5d04dSCharlene Liu if (power_up) { 85578d5d04dSCharlene Liu unsigned long long current_ts = dm_get_timestamp(ctx); 85678d5d04dSCharlene Liu unsigned long long duration_in_ms = 85778d5d04dSCharlene Liu dm_get_elapse_time_in_ns( 85878d5d04dSCharlene Liu ctx, 85978d5d04dSCharlene Liu current_ts, 86045a2d58eSHarry Wentland div64_u64(link->link_trace.time_stamp.edp_poweroff, 1000000)); 86178d5d04dSCharlene Liu unsigned long long wait_time_ms = 0; 86278d5d04dSCharlene Liu 86378d5d04dSCharlene Liu /* max 500ms from LCDVDD off to on */ 86478d5d04dSCharlene Liu if (link->link_trace.time_stamp.edp_poweroff == 0) 86578d5d04dSCharlene Liu wait_time_ms = 500; 86678d5d04dSCharlene Liu else if (duration_in_ms < 500) 86778d5d04dSCharlene Liu wait_time_ms = 500 - duration_in_ms; 86878d5d04dSCharlene Liu 86978d5d04dSCharlene Liu if (wait_time_ms) { 87078d5d04dSCharlene Liu msleep(wait_time_ms); 87178d5d04dSCharlene Liu dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 87278d5d04dSCharlene Liu __func__, wait_time_ms); 87378d5d04dSCharlene Liu } 87478d5d04dSCharlene Liu 87578d5d04dSCharlene Liu } 87687401969SAndrew Jiang 8771296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 87887401969SAndrew Jiang "%s: Panel Power action: %s\n", 87987401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 88087401969SAndrew Jiang 88187401969SAndrew Jiang cntl.action = power_up ? 88287401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_ON : 88387401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_OFF; 884069d418fSAndrew Jiang cntl.transmitter = link->link_enc->transmitter; 885069d418fSAndrew Jiang cntl.connector_obj_id = link->link_enc->connector; 88687401969SAndrew Jiang cntl.coherent = false; 88787401969SAndrew Jiang cntl.lanes_number = LANE_COUNT_FOUR; 888069d418fSAndrew Jiang cntl.hpd_sel = link->link_enc->hpd_source; 88987401969SAndrew Jiang bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 89087401969SAndrew Jiang 89178d5d04dSCharlene Liu if (!power_up) 89278d5d04dSCharlene Liu /*save driver power off time stamp*/ 89378d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 89478d5d04dSCharlene Liu else 89578d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 89678d5d04dSCharlene Liu 89787401969SAndrew Jiang if (bp_result != BP_RESULT_OK) 8981296423bSBhawanpreet Lakha DC_LOG_ERROR( 89987401969SAndrew Jiang "%s: Panel Power bp_result: %d\n", 90087401969SAndrew Jiang __func__, bp_result); 90187401969SAndrew Jiang } else { 9021296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 90387401969SAndrew Jiang "%s: Skipping Panel Power action: %s\n", 90487401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 90587401969SAndrew Jiang } 90687401969SAndrew Jiang } 9075eefbc40SYue Hin Lau 9085eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 9095eefbc40SYue Hin Lau /* 9105eefbc40SYue Hin Lau * @brief 9115eefbc40SYue Hin Lau * eDP only. Control the backlight of the eDP panel 9125eefbc40SYue Hin Lau */ 91387401969SAndrew Jiang void hwss_edp_backlight_control( 9145eefbc40SYue Hin Lau struct dc_link *link, 9155eefbc40SYue Hin Lau bool enable) 9165eefbc40SYue Hin Lau { 917069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 918069d418fSAndrew Jiang struct dce_hwseq *hws = ctx->dc->hwseq; 9195eefbc40SYue Hin Lau struct bp_transmitter_control cntl = { 0 }; 9205eefbc40SYue Hin Lau 921069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 9225eefbc40SYue Hin Lau != CONNECTOR_ID_EDP) { 9235eefbc40SYue Hin Lau BREAK_TO_DEBUGGER(); 9245eefbc40SYue Hin Lau return; 9255eefbc40SYue Hin Lau } 9265eefbc40SYue Hin Lau 9275eefbc40SYue Hin Lau if (enable && is_panel_backlight_on(hws)) { 9281296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 9295eefbc40SYue Hin Lau "%s: panel already powered up. Do nothing.\n", 9305eefbc40SYue Hin Lau __func__); 9315eefbc40SYue Hin Lau return; 9325eefbc40SYue Hin Lau } 9335eefbc40SYue Hin Lau 9345eefbc40SYue Hin Lau /* Send VBIOS command to control eDP panel backlight */ 9355eefbc40SYue Hin Lau 9361296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 9375eefbc40SYue Hin Lau "%s: backlight action: %s\n", 9385eefbc40SYue Hin Lau __func__, (enable ? "On":"Off")); 9395eefbc40SYue Hin Lau 9405eefbc40SYue Hin Lau cntl.action = enable ? 9415eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_ON : 9425eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_OFF; 94387401969SAndrew Jiang 9445eefbc40SYue Hin Lau /*cntl.engine_id = ctx->engine;*/ 9455eefbc40SYue Hin Lau cntl.transmitter = link->link_enc->transmitter; 9465eefbc40SYue Hin Lau cntl.connector_obj_id = link->link_enc->connector; 9475eefbc40SYue Hin Lau /*todo: unhardcode*/ 9485eefbc40SYue Hin Lau cntl.lanes_number = LANE_COUNT_FOUR; 9495eefbc40SYue Hin Lau cntl.hpd_sel = link->link_enc->hpd_source; 950cf1835f0SCharlene Liu cntl.signal = SIGNAL_TYPE_EDP; 9515eefbc40SYue Hin Lau 9525eefbc40SYue Hin Lau /* For eDP, the following delays might need to be considered 9535eefbc40SYue Hin Lau * after link training completed: 9545eefbc40SYue Hin Lau * idle period - min. accounts for required BS-Idle pattern, 9555eefbc40SYue Hin Lau * max. allows for source frame synchronization); 9565eefbc40SYue Hin Lau * 50 msec max. delay from valid video data from source 9575eefbc40SYue Hin Lau * to video on dislpay or backlight enable. 9585eefbc40SYue Hin Lau * 9595eefbc40SYue Hin Lau * Disable the delay for now. 9605eefbc40SYue Hin Lau * Enable it in the future if necessary. 9615eefbc40SYue Hin Lau */ 9625eefbc40SYue Hin Lau /* dc_service_sleep_in_milliseconds(50); */ 9635180d4a4SCharlene Liu /*edp 1.2*/ 9645180d4a4SCharlene Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 9655180d4a4SCharlene Liu edp_receiver_ready_T7(link); 966069d418fSAndrew Jiang link_transmitter_control(ctx->dc_bios, &cntl); 96769b9723aSCharlene Liu /*edp 1.2*/ 9685180d4a4SCharlene Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) 96969b9723aSCharlene Liu edp_receiver_ready_T9(link); 9705eefbc40SYue Hin Lau } 9715eefbc40SYue Hin Lau 9724176664bSCharlene Liu void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) 9734562236bSHarry Wentland { 9740971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 975d0778ebfSHarry Wentland struct dc_link *link = stream->sink->link; 9764176664bSCharlene Liu struct dc *dc = pipe_ctx->stream->ctx->dc; 9774562236bSHarry Wentland 9782b7c97d6SCharlene Liu if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 9792b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 9802b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc); 9812b7c97d6SCharlene Liu 9822b7c97d6SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 9832b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 9842b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc); 9852b7c97d6SCharlene Liu 9862b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 9872b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc, true); 988afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio) { 9897c357e61SCharlene Liu if (option != KEEP_ACQUIRED_RESOURCE || 9907c357e61SCharlene Liu !dc->debug.az_endpoint_mute_only) { 9917c357e61SCharlene Liu /*only disalbe az_endpoint if power down or free*/ 992afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 9937c357e61SCharlene Liu } 9944562236bSHarry Wentland 9954562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 9968e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 9978e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 9984562236bSHarry Wentland else 9998e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 10008e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 10014176664bSCharlene Liu /*don't free audio if it is from retrain or internal disable stream*/ 10024176664bSCharlene Liu if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) { 10034176664bSCharlene Liu /*we have to dynamic arbitrate the audio endpoints*/ 10044176664bSCharlene Liu pipe_ctx->stream_res.audio = NULL; 10054176664bSCharlene Liu /*we free the resource, need reset is_audio_acquired*/ 10064176664bSCharlene Liu update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false); 10074176664bSCharlene Liu } 10084562236bSHarry Wentland 10094562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 10104562236bSHarry Wentland * add audio mode list change flag */ 10114562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 10124562236bSHarry Wentland * stream->stream_engine_id); 10134562236bSHarry Wentland */ 10144562236bSHarry Wentland } 10154562236bSHarry Wentland 1016904623eeSYongqiang Sun 10174562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 10184562236bSHarry Wentland link->link_enc, 10198e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->id, 10204562236bSHarry Wentland false); 10214562236bSHarry Wentland 10224562236bSHarry Wentland } 10234562236bSHarry Wentland 10244562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 10254562236bSHarry Wentland struct dc_link_settings *link_settings) 10264562236bSHarry Wentland { 10274562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 102841b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 102941b49742SCharlene Liu struct dc_link *link = stream->sink->link; 10304562236bSHarry Wentland 10314562236bSHarry Wentland /* only 3 items below are used by unblank */ 10326235b23cSTony Cheng params.pixel_clk_khz = 10334fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.pix_clk_khz; 10344562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 103541b49742SCharlene Liu 103641b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10378e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 103841b49742SCharlene Liu 103914d6f644SYongqiang Sun if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 104041b49742SCharlene Liu link->dc->hwss.edp_backlight_control(link, true); 10415282cbe3SYongqiang Sun stream->bl_pwm_level = EDP_BACKLIGHT_RAMP_DISABLE_LEVEL; 104214d6f644SYongqiang Sun } 104341b49742SCharlene Liu } 104441b49742SCharlene Liu void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 104541b49742SCharlene Liu { 104641b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 104741b49742SCharlene Liu struct dc_link *link = stream->sink->link; 104841b49742SCharlene Liu 104941b49742SCharlene Liu if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 105041b49742SCharlene Liu link->dc->hwss.edp_backlight_control(link, false); 105141b49742SCharlene Liu 105241b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 105341b49742SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 10544562236bSHarry Wentland } 10554562236bSHarry Wentland 105615e17335SCharlene Liu 105715e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 105815e17335SCharlene Liu { 10598e9c4c8cSHarry Wentland if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 10608e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 106115e17335SCharlene Liu } 106215e17335SCharlene Liu 10634562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 10644562236bSHarry Wentland { 10654562236bSHarry Wentland switch (crtc_id) { 10664562236bSHarry Wentland case CONTROLLER_ID_D0: 10674562236bSHarry Wentland return DTO_SOURCE_ID0; 10684562236bSHarry Wentland case CONTROLLER_ID_D1: 10694562236bSHarry Wentland return DTO_SOURCE_ID1; 10704562236bSHarry Wentland case CONTROLLER_ID_D2: 10714562236bSHarry Wentland return DTO_SOURCE_ID2; 10724562236bSHarry Wentland case CONTROLLER_ID_D3: 10734562236bSHarry Wentland return DTO_SOURCE_ID3; 10744562236bSHarry Wentland case CONTROLLER_ID_D4: 10754562236bSHarry Wentland return DTO_SOURCE_ID4; 10764562236bSHarry Wentland case CONTROLLER_ID_D5: 10774562236bSHarry Wentland return DTO_SOURCE_ID5; 10784562236bSHarry Wentland default: 10794562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 10804562236bSHarry Wentland } 10814562236bSHarry Wentland } 10824562236bSHarry Wentland 10834562236bSHarry Wentland static void build_audio_output( 1084ab8db3e1SAndrey Grodzovsky struct dc_state *state, 10854562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 10864562236bSHarry Wentland struct audio_output *audio_output) 10874562236bSHarry Wentland { 10880971c40eSHarry Wentland const struct dc_stream_state *stream = pipe_ctx->stream; 10898e9c4c8cSHarry Wentland audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 10904562236bSHarry Wentland 10914562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 10924562236bSHarry Wentland 10934562236bSHarry Wentland /* audio_crtc_info */ 10944562236bSHarry Wentland 10954562236bSHarry Wentland audio_output->crtc_info.h_total = 10964fa086b9SLeo (Sunpeng) Li stream->timing.h_total; 10974562236bSHarry Wentland 10984562236bSHarry Wentland /* 10994562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 11004562236bSHarry Wentland * need to specify actual active signal portion 11014562236bSHarry Wentland */ 11024562236bSHarry Wentland audio_output->crtc_info.h_active = 11034fa086b9SLeo (Sunpeng) Li stream->timing.h_addressable 11044fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_left 11054fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_right; 11064562236bSHarry Wentland 11074562236bSHarry Wentland audio_output->crtc_info.v_active = 11084fa086b9SLeo (Sunpeng) Li stream->timing.v_addressable 11094fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_top 11104fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_bottom; 11114562236bSHarry Wentland 11124562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 11134562236bSHarry Wentland 11144562236bSHarry Wentland audio_output->crtc_info.interlaced = 11154fa086b9SLeo (Sunpeng) Li stream->timing.flags.INTERLACE; 11164562236bSHarry Wentland 11174562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 11184fa086b9SLeo (Sunpeng) Li (stream->timing.pix_clk_khz*1000)/ 11194fa086b9SLeo (Sunpeng) Li (stream->timing.h_total*stream->timing.v_total); 11204562236bSHarry Wentland 11214562236bSHarry Wentland audio_output->crtc_info.color_depth = 11224fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth; 11234562236bSHarry Wentland 11244562236bSHarry Wentland audio_output->crtc_info.requested_pixel_clock = 112510688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; 11264562236bSHarry Wentland 11274562236bSHarry Wentland audio_output->crtc_info.calculated_pixel_clock = 112810688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; 11294562236bSHarry Wentland 113087b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 113187b58768SCharlene Liu if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && 113287b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock == 11334fa086b9SLeo (Sunpeng) Li stream->timing.pix_clk_khz) { 113410688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 113587b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock = 113687b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock/2; 113787b58768SCharlene Liu audio_output->crtc_info.calculated_pixel_clock = 113810688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2; 113987b58768SCharlene Liu 114087b58768SCharlene Liu } 114187b58768SCharlene Liu } 114287b58768SCharlene Liu 11434562236bSHarry Wentland if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 11444562236bSHarry Wentland pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 11454562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 1146ab8db3e1SAndrey Grodzovsky state->dis_clk->funcs->get_dp_ref_clk_frequency( 1147ab8db3e1SAndrey Grodzovsky state->dis_clk); 11484562236bSHarry Wentland } 11494562236bSHarry Wentland 11504562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 11514562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 11524562236bSHarry Wentland 11534562236bSHarry Wentland audio_output->pll_info.dto_source = 11544562236bSHarry Wentland translate_to_dto_source( 1155e07f541fSYongqiang Sun pipe_ctx->stream_res.tg->inst + 1); 11564562236bSHarry Wentland 11574562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 11584562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 11594562236bSHarry Wentland 11604562236bSHarry Wentland audio_output->pll_info.ss_percentage = 11614562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 11624562236bSHarry Wentland } 11634562236bSHarry Wentland 11644562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 11654562236bSHarry Wentland struct tg_color *color) 11664562236bSHarry Wentland { 11672a54bd6eSJerry (Fangzhi) Zuo uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; 11684562236bSHarry Wentland 11696702a9acSHarry Wentland switch (pipe_ctx->plane_res.scl_data.format) { 11704562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 11714562236bSHarry Wentland /* set boarder color to red */ 11724562236bSHarry Wentland color->color_r_cr = color_value; 11734562236bSHarry Wentland break; 11744562236bSHarry Wentland 11754562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 11764562236bSHarry Wentland /* set boarder color to blue */ 11774562236bSHarry Wentland color->color_b_cb = color_value; 11784562236bSHarry Wentland break; 117987449a90SAnthony Koo case PIXEL_FORMAT_420BPP8: 11804562236bSHarry Wentland /* set boarder color to green */ 11814562236bSHarry Wentland color->color_g_y = color_value; 11824562236bSHarry Wentland break; 118387449a90SAnthony Koo case PIXEL_FORMAT_420BPP10: 118487449a90SAnthony Koo /* set boarder color to yellow */ 118587449a90SAnthony Koo color->color_g_y = color_value; 118687449a90SAnthony Koo color->color_r_cr = color_value; 118787449a90SAnthony Koo break; 11884562236bSHarry Wentland case PIXEL_FORMAT_FP16: 11894562236bSHarry Wentland /* set boarder color to white */ 11904562236bSHarry Wentland color->color_r_cr = color_value; 11914562236bSHarry Wentland color->color_b_cb = color_value; 11924562236bSHarry Wentland color->color_g_y = color_value; 11934562236bSHarry Wentland break; 11944562236bSHarry Wentland default: 11954562236bSHarry Wentland break; 11964562236bSHarry Wentland } 11974562236bSHarry Wentland } 11984562236bSHarry Wentland 1199fb3466a4SBhawanpreet Lakha static void program_scaler(const struct dc *dc, 12004562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 12014562236bSHarry Wentland { 12024562236bSHarry Wentland struct tg_color color = {0}; 12034562236bSHarry Wentland 1204ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1205ff5ef992SAlex Deucher /* TOFPGA */ 120686a66c4eSHarry Wentland if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1207ff5ef992SAlex Deucher return; 1208ff5ef992SAlex Deucher #endif 1209ff5ef992SAlex Deucher 1210fb3466a4SBhawanpreet Lakha if (dc->debug.surface_visual_confirm) 12114562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 12124562236bSHarry Wentland else 12134562236bSHarry Wentland color_space_to_black_color(dc, 12144fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space, 12154562236bSHarry Wentland &color); 12164562236bSHarry Wentland 121786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 121886a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, 12196702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.depth, 12204562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 12214562236bSHarry Wentland 12226b670fa9SHarry Wentland if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) 12236b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 12246b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12254562236bSHarry Wentland &color); 12264562236bSHarry Wentland 122786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 12286702a9acSHarry Wentland &pipe_ctx->plane_res.scl_data); 12294562236bSHarry Wentland } 12304562236bSHarry Wentland 12314b5e7d62SHersen Wu static enum dc_status dce110_prog_pixclk_crtc_otg( 12324562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1233608ac7bbSJerry Zuo struct dc_state *context, 1234fb3466a4SBhawanpreet Lakha struct dc *dc) 12354562236bSHarry Wentland { 12360971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1237608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 12384562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 12394562236bSHarry Wentland struct tg_color black_color = {0}; 12404562236bSHarry Wentland 12414562236bSHarry Wentland if (!pipe_ctx_old->stream) { 12424562236bSHarry Wentland 12434562236bSHarry Wentland /* program blank color */ 12444562236bSHarry Wentland color_space_to_black_color(dc, 12454fa086b9SLeo (Sunpeng) Li stream->output_color_space, &black_color); 12466b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank_color( 12476b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12484562236bSHarry Wentland &black_color); 12494b5e7d62SHersen Wu 12504562236bSHarry Wentland /* 12514562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 12524562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 12534562236bSHarry Wentland */ 12546b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 12554562236bSHarry Wentland 12564562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 12574562236bSHarry Wentland pipe_ctx->clock_source, 125810688217SHarry Wentland &pipe_ctx->stream_res.pix_clk_params, 12594562236bSHarry Wentland &pipe_ctx->pll_settings)) { 12604562236bSHarry Wentland BREAK_TO_DEBUGGER(); 12614562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 12624562236bSHarry Wentland } 12634562236bSHarry Wentland 12646b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->program_timing( 12656b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12664fa086b9SLeo (Sunpeng) Li &stream->timing, 12674562236bSHarry Wentland true); 126894267b3dSSylvia Tsai 12696b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 12706b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 127194267b3dSSylvia Tsai 0x182); 12724562236bSHarry Wentland } 12734562236bSHarry Wentland 12744562236bSHarry Wentland if (!pipe_ctx_old->stream) { 12756b670fa9SHarry Wentland if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 12766b670fa9SHarry Wentland pipe_ctx->stream_res.tg)) { 12774562236bSHarry Wentland BREAK_TO_DEBUGGER(); 12784562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 12794562236bSHarry Wentland } 12804562236bSHarry Wentland } 12814562236bSHarry Wentland 128294267b3dSSylvia Tsai 128394267b3dSSylvia Tsai 12844562236bSHarry Wentland return DC_OK; 12854562236bSHarry Wentland } 12864562236bSHarry Wentland 12874562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 12884562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1289608ac7bbSJerry Zuo struct dc_state *context, 1290fb3466a4SBhawanpreet Lakha struct dc *dc) 12914562236bSHarry Wentland { 12920971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1293608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 12944562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 12954562236bSHarry Wentland 12964562236bSHarry Wentland /* */ 12974562236bSHarry Wentland dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); 12984562236bSHarry Wentland 1299f0c4d997SCorbin McElhanney /* FPGA does not program backend */ 1300f0c4d997SCorbin McElhanney if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 1301a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1302a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 13034562236bSHarry Wentland COLOR_SPACE_YCBCR601, 13044fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth, 13054562236bSHarry Wentland pipe_ctx->stream->signal); 13064562236bSHarry Wentland 1307a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1308a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 13094562236bSHarry Wentland &stream->bit_depth_params, 13104562236bSHarry Wentland &stream->clamping); 13114562236bSHarry Wentland return DC_OK; 1312181a888fSCharlene Liu } 13134562236bSHarry Wentland /* TODO: move to stream encoder */ 13144562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 13154562236bSHarry Wentland if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { 13164562236bSHarry Wentland BREAK_TO_DEBUGGER(); 13174562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 13184562236bSHarry Wentland } 1319f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1320f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp, 1321f0c4d997SCorbin McElhanney COLOR_SPACE_YCBCR601, 1322f0c4d997SCorbin McElhanney stream->timing.display_color_depth, 1323f0c4d997SCorbin McElhanney pipe_ctx->stream->signal); 13244562236bSHarry Wentland 13254562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 13264562236bSHarry Wentland stream->sink->link->link_enc->funcs->setup( 13274562236bSHarry Wentland stream->sink->link->link_enc, 13284562236bSHarry Wentland pipe_ctx->stream->signal); 13294562236bSHarry Wentland 1330ab3c1798SVitaly Prosyak if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 13318e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync( 13328e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 13336b670fa9SHarry Wentland pipe_ctx->stream_res.tg->inst, 13344fa086b9SLeo (Sunpeng) Li stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); 1335ab3c1798SVitaly Prosyak 1336ab3c1798SVitaly Prosyak 1337a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1338a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 1339181a888fSCharlene Liu &stream->bit_depth_params, 1340181a888fSCharlene Liu &stream->clamping); 1341603767f9STony Cheng 13424562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 13438e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute( 13448e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 13454fa086b9SLeo (Sunpeng) Li &stream->timing, 13464fa086b9SLeo (Sunpeng) Li stream->output_color_space); 13474562236bSHarry Wentland 13484562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 13498e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute( 13508e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 13514fa086b9SLeo (Sunpeng) Li &stream->timing, 13524562236bSHarry Wentland stream->phy_pix_clk, 1353afaacef4SHarry Wentland pipe_ctx->stream_res.audio != NULL); 13544562236bSHarry Wentland 13554562236bSHarry Wentland if (dc_is_dvi_signal(pipe_ctx->stream->signal)) 13568e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute( 13578e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 13584fa086b9SLeo (Sunpeng) Li &stream->timing, 13594562236bSHarry Wentland (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? 13604562236bSHarry Wentland true : false); 13614562236bSHarry Wentland 136215e17335SCharlene Liu resource_build_info_frame(pipe_ctx); 13633639fa68SZeyu Fan dce110_update_info_frame(pipe_ctx); 1364f0362823SYongqiang Sun if (!pipe_ctx_old->stream) 1365ab8db3e1SAndrey Grodzovsky core_link_enable_stream(context, pipe_ctx); 13664562236bSHarry Wentland 13676702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 13684562236bSHarry Wentland 136994267b3dSSylvia Tsai pipe_ctx->stream->sink->link->psr_enabled = false; 137094267b3dSSylvia Tsai 13714562236bSHarry Wentland return DC_OK; 13724562236bSHarry Wentland } 13734562236bSHarry Wentland 13744562236bSHarry Wentland /******************************************************************************/ 13754562236bSHarry Wentland 1376fb3466a4SBhawanpreet Lakha static void power_down_encoders(struct dc *dc) 13774562236bSHarry Wentland { 13784562236bSHarry Wentland int i; 1379a0c38ebaSCharlene Liu enum connector_id connector_id; 138068d77dd8SAndrew Jiang enum signal_type signal = SIGNAL_TYPE_NONE; 1381b9b171ffSHersen Wu 1382b9b171ffSHersen Wu /* do not know BIOS back-front mapping, simply blank all. It will not 1383b9b171ffSHersen Wu * hurt for non-DP 1384b9b171ffSHersen Wu */ 1385b9b171ffSHersen Wu for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1386b9b171ffSHersen Wu dc->res_pool->stream_enc[i]->funcs->dp_blank( 1387b9b171ffSHersen Wu dc->res_pool->stream_enc[i]); 1388b9b171ffSHersen Wu } 1389b9b171ffSHersen Wu 13904562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 1391a0c38ebaSCharlene Liu connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id); 1392a0c38ebaSCharlene Liu if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || 1393a0c38ebaSCharlene Liu (connector_id == CONNECTOR_ID_EDP)) { 1394a0c38ebaSCharlene Liu 1395a0c38ebaSCharlene Liu if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) 1396a0c38ebaSCharlene Liu dp_receiver_power_ctrl(dc->links[i], false); 1397904623eeSYongqiang Sun if (connector_id == CONNECTOR_ID_EDP) 139868d77dd8SAndrew Jiang signal = SIGNAL_TYPE_EDP; 1399a0c38ebaSCharlene Liu } 1400a0c38ebaSCharlene Liu 14014562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 1402069d418fSAndrew Jiang dc->links[i]->link_enc, signal); 14034562236bSHarry Wentland } 14044562236bSHarry Wentland } 14054562236bSHarry Wentland 1406fb3466a4SBhawanpreet Lakha static void power_down_controllers(struct dc *dc) 14074562236bSHarry Wentland { 14084562236bSHarry Wentland int i; 14094562236bSHarry Wentland 14104562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 14114562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 14124562236bSHarry Wentland dc->res_pool->timing_generators[i]); 14134562236bSHarry Wentland } 14144562236bSHarry Wentland } 14154562236bSHarry Wentland 1416fb3466a4SBhawanpreet Lakha static void power_down_clock_sources(struct dc *dc) 14174562236bSHarry Wentland { 14184562236bSHarry Wentland int i; 14194562236bSHarry Wentland 14204562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 14214562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 14224562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 14234562236bSHarry Wentland 14244562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 14254562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 14264562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 14274562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 14284562236bSHarry Wentland } 14294562236bSHarry Wentland } 14304562236bSHarry Wentland 1431fb3466a4SBhawanpreet Lakha static void power_down_all_hw_blocks(struct dc *dc) 14324562236bSHarry Wentland { 14334562236bSHarry Wentland power_down_encoders(dc); 14344562236bSHarry Wentland 14354562236bSHarry Wentland power_down_controllers(dc); 14364562236bSHarry Wentland 14374562236bSHarry Wentland power_down_clock_sources(dc); 14381663ae1cSBhawanpreet Lakha 14393eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 14402f3bfb27SRoman Li if (dc->fbc_compressor) 14411663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 14421663ae1cSBhawanpreet Lakha #endif 14434562236bSHarry Wentland } 14444562236bSHarry Wentland 14454562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 1446fb3466a4SBhawanpreet Lakha struct dc *dc) 14474562236bSHarry Wentland { 14484562236bSHarry Wentland int i; 14494562236bSHarry Wentland struct timing_generator *tg; 14504562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 14514562236bSHarry Wentland 14524562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 14534562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 14544562236bSHarry Wentland 14550a87425aSTony Cheng if (tg->funcs->disable_vga) 14564562236bSHarry Wentland tg->funcs->disable_vga(tg); 14574562236bSHarry Wentland 14584562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 14594562236bSHarry Wentland * powergating. */ 14604562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 14614562236bSHarry Wentland true); 14624562236bSHarry Wentland 1463e6c258cbSYongqiang Sun dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 14647f914a62SYongqiang Sun dc->hwss.disable_plane(dc, 1465e6c258cbSYongqiang Sun &dc->current_state->res_ctx.pipe_ctx[i]); 14664562236bSHarry Wentland } 14674562236bSHarry Wentland } 14684562236bSHarry Wentland 1469cf1835f0SCharlene Liu static struct dc_link *get_link_for_edp_not_in_use( 147025292028SYongqiang Sun struct dc *dc, 147125292028SYongqiang Sun struct dc_state *context) 147225292028SYongqiang Sun { 147325292028SYongqiang Sun int i; 147425292028SYongqiang Sun struct dc_link *link = NULL; 147525292028SYongqiang Sun 147625292028SYongqiang Sun /* check if eDP panel is suppose to be set mode, if yes, no need to disable */ 147725292028SYongqiang Sun for (i = 0; i < context->stream_count; i++) { 147825292028SYongqiang Sun if (context->streams[i]->signal == SIGNAL_TYPE_EDP) 147925292028SYongqiang Sun return NULL; 148025292028SYongqiang Sun } 148125292028SYongqiang Sun 148225292028SYongqiang Sun /* check if there is an eDP panel not in use */ 148325292028SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 148425292028SYongqiang Sun if (dc->links[i]->local_sink && 148525292028SYongqiang Sun dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 148625292028SYongqiang Sun link = dc->links[i]; 148725292028SYongqiang Sun break; 148825292028SYongqiang Sun } 148925292028SYongqiang Sun } 149025292028SYongqiang Sun 149125292028SYongqiang Sun return link; 149225292028SYongqiang Sun } 149325292028SYongqiang Sun 14944562236bSHarry Wentland /** 14954562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 14964562236bSHarry Wentland * 1. Power down all DC HW blocks 14974562236bSHarry Wentland * 2. Disable VGA engine on all controllers 14984562236bSHarry Wentland * 3. Enable power gating for controller 14994562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 15004562236bSHarry Wentland */ 150125292028SYongqiang Sun void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 15024562236bSHarry Wentland { 1503c5fc7f59SCharlene Liu struct dc_bios *dcb = dc->ctx->dc_bios; 15044562236bSHarry Wentland 15054cac1e6dSYongqiang Sun /* vbios already light up eDP, so we can leverage vbios and skip eDP 15064cac1e6dSYongqiang Sun * programming 15074cac1e6dSYongqiang Sun */ 15084cac1e6dSYongqiang Sun bool can_eDP_fast_boot_optimize = 15094cac1e6dSYongqiang Sun (dcb->funcs->get_vga_enabled_displays(dc->ctx->dc_bios) == ATOM_DISPLAY_LCD1_ACTIVE); 15104cac1e6dSYongqiang Sun 15114cac1e6dSYongqiang Sun /* if OS doesn't light up eDP and eDP link is available, we want to disable */ 15124cac1e6dSYongqiang Sun struct dc_link *edp_link_to_turnoff = NULL; 15134cac1e6dSYongqiang Sun 15144cac1e6dSYongqiang Sun if (can_eDP_fast_boot_optimize) { 15154cac1e6dSYongqiang Sun edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context); 15164cac1e6dSYongqiang Sun 15174cac1e6dSYongqiang Sun if (!edp_link_to_turnoff) 15184cac1e6dSYongqiang Sun dc->apply_edp_fast_boot_optimization = true; 15194cac1e6dSYongqiang Sun } 15204cac1e6dSYongqiang Sun 15214cac1e6dSYongqiang Sun if (!dc->apply_edp_fast_boot_optimization) { 15224cac1e6dSYongqiang Sun if (edp_link_to_turnoff) { 15234cac1e6dSYongqiang Sun /*turn off backlight before DP_blank and encoder powered down*/ 15244cac1e6dSYongqiang Sun dc->hwss.edp_backlight_control(edp_link_to_turnoff, false); 1525c5fc7f59SCharlene Liu } 1526c5fc7f59SCharlene Liu /*resume from S3, no vbios posting, no need to power down again*/ 152725292028SYongqiang Sun power_down_all_hw_blocks(dc); 15284562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 1529cf1835f0SCharlene Liu if (edp_link_to_turnoff) 1530cf1835f0SCharlene Liu dc->hwss.edp_power_control(edp_link_to_turnoff, false); 1531c5fc7f59SCharlene Liu } 15324562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 15334562236bSHarry Wentland } 15344562236bSHarry Wentland 15354562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 15364562236bSHarry Wentland struct bw_fixed blackout_duration, 15370971c40eSHarry Wentland const struct dc_stream_state *stream) 15384562236bSHarry Wentland { 15394562236bSHarry Wentland uint32_t total_dest_line_time_ns; 15404562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 15414562236bSHarry Wentland 15424562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 15434562236bSHarry Wentland 15444562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 15454fa086b9SLeo (Sunpeng) Li stream->timing.h_total / 15464fa086b9SLeo (Sunpeng) Li stream->timing.pix_clk_khz + 15474562236bSHarry Wentland pstate_blackout_duration_ns; 15484562236bSHarry Wentland 15494562236bSHarry Wentland return total_dest_line_time_ns; 15504562236bSHarry Wentland } 15514562236bSHarry Wentland 1552f774b339SEric Yang static void dce110_set_displaymarks( 1553fb3466a4SBhawanpreet Lakha const struct dc *dc, 1554608ac7bbSJerry Zuo struct dc_state *context) 15554562236bSHarry Wentland { 15564562236bSHarry Wentland uint8_t i, num_pipes; 15574562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 15584562236bSHarry Wentland 15594562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 15604562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15614562236bSHarry Wentland uint32_t total_dest_line_time_ns; 15624562236bSHarry Wentland 15634562236bSHarry Wentland if (pipe_ctx->stream == NULL) 15644562236bSHarry Wentland continue; 15654562236bSHarry Wentland 15664562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 156777a4ea53SBhawanpreet Lakha dc->bw_vbios->blackout_duration, pipe_ctx->stream); 156886a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 156986a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 15709037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 15719037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 15723722c794SMikita Lipski context->bw.dce.stutter_entry_wm_ns[num_pipes], 15739037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 15744562236bSHarry Wentland total_dest_line_time_ns); 15754562236bSHarry Wentland if (i == underlay_idx) { 15764562236bSHarry Wentland num_pipes++; 157786a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 157886a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 15799037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 15809037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 15819037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 15824562236bSHarry Wentland total_dest_line_time_ns); 15834562236bSHarry Wentland } 15844562236bSHarry Wentland num_pipes++; 15854562236bSHarry Wentland } 15864562236bSHarry Wentland } 15874562236bSHarry Wentland 1588a2b8659dSTony Cheng static void set_safe_displaymarks( 1589a2b8659dSTony Cheng struct resource_context *res_ctx, 1590a2b8659dSTony Cheng const struct resource_pool *pool) 15914562236bSHarry Wentland { 15924562236bSHarry Wentland int i; 1593a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 15949037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 15954562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 15969037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 15974562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 15983722c794SMikita Lipski struct dce_watermarks min_marks = { 0, 0, 0, 0}; 15994562236bSHarry Wentland 16004562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 16018feabd03SYue Hin Lau if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 16024562236bSHarry Wentland continue; 16034562236bSHarry Wentland 160486a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 160586a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 16064562236bSHarry Wentland nbp_marks, 16074562236bSHarry Wentland max_marks, 16083722c794SMikita Lipski min_marks, 16094562236bSHarry Wentland max_marks, 16104562236bSHarry Wentland MAX_WATERMARK); 16118feabd03SYue Hin Lau 16124562236bSHarry Wentland if (i == underlay_idx) 161386a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 161486a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 16154562236bSHarry Wentland nbp_marks, 16164562236bSHarry Wentland max_marks, 16174562236bSHarry Wentland max_marks, 16184562236bSHarry Wentland MAX_WATERMARK); 16198feabd03SYue Hin Lau 16204562236bSHarry Wentland } 16214562236bSHarry Wentland } 16224562236bSHarry Wentland 16234562236bSHarry Wentland /******************************************************************************* 16244562236bSHarry Wentland * Public functions 16254562236bSHarry Wentland ******************************************************************************/ 16264562236bSHarry Wentland 16274562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 16284562236bSHarry Wentland int num_pipes, int vmin, int vmax) 16294562236bSHarry Wentland { 16304562236bSHarry Wentland int i = 0; 16314562236bSHarry Wentland struct drr_params params = {0}; 16324562236bSHarry Wentland 16334562236bSHarry Wentland params.vertical_total_max = vmax; 16344562236bSHarry Wentland params.vertical_total_min = vmin; 16354562236bSHarry Wentland 16364562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 16374562236bSHarry Wentland * some GSL stuff 16384562236bSHarry Wentland */ 16394562236bSHarry Wentland 16404562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 16416b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms); 16424562236bSHarry Wentland } 16434562236bSHarry Wentland } 16444562236bSHarry Wentland 164572ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 164672ada5f7SEric Cook int num_pipes, 164772ada5f7SEric Cook struct crtc_position *position) 164872ada5f7SEric Cook { 164972ada5f7SEric Cook int i = 0; 165072ada5f7SEric Cook 165172ada5f7SEric Cook /* TODO: handle pipes > 1 165272ada5f7SEric Cook */ 165372ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 16546b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 165572ada5f7SEric Cook } 165672ada5f7SEric Cook 16574562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 165894267b3dSSylvia Tsai int num_pipes, const struct dc_static_screen_events *events) 16594562236bSHarry Wentland { 16604562236bSHarry Wentland unsigned int i; 166194267b3dSSylvia Tsai unsigned int value = 0; 166294267b3dSSylvia Tsai 166394267b3dSSylvia Tsai if (events->overlay_update) 166494267b3dSSylvia Tsai value |= 0x100; 166594267b3dSSylvia Tsai if (events->surface_update) 166694267b3dSSylvia Tsai value |= 0x80; 166794267b3dSSylvia Tsai if (events->cursor_update) 166894267b3dSSylvia Tsai value |= 0x2; 1669ed8462acSCharlene Liu if (events->force_trigger) 1670ed8462acSCharlene Liu value |= 0x1; 16714562236bSHarry Wentland 16723eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 1673c3aa1d67SBhawanpreet Lakha value |= 0x84; 1674c3aa1d67SBhawanpreet Lakha #endif 1675c3aa1d67SBhawanpreet Lakha 16764562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 16776b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs-> 16786b670fa9SHarry Wentland set_static_screen_control(pipe_ctx[i]->stream_res.tg, value); 16794562236bSHarry Wentland } 16804562236bSHarry Wentland 16814562236bSHarry Wentland /* unit: in_khz before mode set, get pixel clock from context. ASIC register 16824562236bSHarry Wentland * may not be programmed yet. 16834562236bSHarry Wentland * TODO: after mode set, pre_mode_set = false, 16844562236bSHarry Wentland * may read PLL register to get pixel clock 16854562236bSHarry Wentland */ 16864562236bSHarry Wentland static uint32_t get_max_pixel_clock_for_all_paths( 1687fb3466a4SBhawanpreet Lakha struct dc *dc, 1688608ac7bbSJerry Zuo struct dc_state *context, 16894562236bSHarry Wentland bool pre_mode_set) 16904562236bSHarry Wentland { 16914562236bSHarry Wentland uint32_t max_pix_clk = 0; 16924562236bSHarry Wentland int i; 16934562236bSHarry Wentland 16944562236bSHarry Wentland if (!pre_mode_set) { 16954562236bSHarry Wentland /* TODO: read ASIC register to get pixel clock */ 16964562236bSHarry Wentland ASSERT(0); 16974562236bSHarry Wentland } 16984562236bSHarry Wentland 16994562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 17004562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 17014562236bSHarry Wentland 17024562236bSHarry Wentland if (pipe_ctx->stream == NULL) 17034562236bSHarry Wentland continue; 17044562236bSHarry Wentland 17054562236bSHarry Wentland /* do not check under lay */ 17064562236bSHarry Wentland if (pipe_ctx->top_pipe) 17074562236bSHarry Wentland continue; 17084562236bSHarry Wentland 170910688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk) 17104562236bSHarry Wentland max_pix_clk = 171110688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; 17124562236bSHarry Wentland } 17134562236bSHarry Wentland 17144562236bSHarry Wentland if (max_pix_clk == 0) 17154562236bSHarry Wentland ASSERT(0); 17164562236bSHarry Wentland 17174562236bSHarry Wentland return max_pix_clk; 17184562236bSHarry Wentland } 17194562236bSHarry Wentland 1720f6baff4dSHarry Wentland /* 1721f6baff4dSHarry Wentland * Find clock state based on clock requested. if clock value is 0, simply 17224562236bSHarry Wentland * set clock state as requested without finding clock state by clock value 17234562236bSHarry Wentland */ 1724f6baff4dSHarry Wentland 17254562236bSHarry Wentland static void apply_min_clocks( 1726fb3466a4SBhawanpreet Lakha struct dc *dc, 1727608ac7bbSJerry Zuo struct dc_state *context, 1728e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state *clocks_state, 17294562236bSHarry Wentland bool pre_mode_set) 17304562236bSHarry Wentland { 17314562236bSHarry Wentland struct state_dependent_clocks req_clocks = {0}; 17324562236bSHarry Wentland 17334562236bSHarry Wentland if (!pre_mode_set) { 17344562236bSHarry Wentland /* set clock_state without verification */ 1735ab8db3e1SAndrey Grodzovsky if (context->dis_clk->funcs->set_min_clocks_state) { 1736ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->set_min_clocks_state( 1737ab8db3e1SAndrey Grodzovsky context->dis_clk, *clocks_state); 17384562236bSHarry Wentland return; 17395d6d185fSDmytro Laktyushkin } 17404562236bSHarry Wentland 17412c8ad2d5SAlex Deucher /* TODO: This is incorrect. Figure out how to fix. */ 1742ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1743ab8db3e1SAndrey Grodzovsky context->dis_clk, 17442c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1745ab8db3e1SAndrey Grodzovsky context->dis_clk->cur_clocks_value.dispclk_in_khz, 17462c8ad2d5SAlex Deucher pre_mode_set, 17472c8ad2d5SAlex Deucher false); 17482c8ad2d5SAlex Deucher 1749ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1750ab8db3e1SAndrey Grodzovsky context->dis_clk, 17512c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 1752ab8db3e1SAndrey Grodzovsky context->dis_clk->cur_clocks_value.max_pixelclk_in_khz, 17532c8ad2d5SAlex Deucher pre_mode_set, 17542c8ad2d5SAlex Deucher false); 17552c8ad2d5SAlex Deucher 1756ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1757ab8db3e1SAndrey Grodzovsky context->dis_clk, 17582c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 1759ab8db3e1SAndrey Grodzovsky context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, 17602c8ad2d5SAlex Deucher pre_mode_set, 17612c8ad2d5SAlex Deucher false); 17622c8ad2d5SAlex Deucher return; 17634562236bSHarry Wentland } 17644562236bSHarry Wentland 17654562236bSHarry Wentland /* get the required state based on state dependent clocks: 17664562236bSHarry Wentland * display clock and pixel clock 17674562236bSHarry Wentland */ 17689037d802SDmytro Laktyushkin req_clocks.display_clk_khz = context->bw.dce.dispclk_khz; 17694562236bSHarry Wentland 17704562236bSHarry Wentland req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( 17714562236bSHarry Wentland dc, context, true); 17724562236bSHarry Wentland 1773ab8db3e1SAndrey Grodzovsky if (context->dis_clk->funcs->get_required_clocks_state) { 1774ab8db3e1SAndrey Grodzovsky *clocks_state = context->dis_clk->funcs->get_required_clocks_state( 1775ab8db3e1SAndrey Grodzovsky context->dis_clk, &req_clocks); 1776ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->set_min_clocks_state( 1777ab8db3e1SAndrey Grodzovsky context->dis_clk, *clocks_state); 17784562236bSHarry Wentland } else { 1779ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1780ab8db3e1SAndrey Grodzovsky context->dis_clk, 17812c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 17822c8ad2d5SAlex Deucher req_clocks.display_clk_khz, 17832c8ad2d5SAlex Deucher pre_mode_set, 17842c8ad2d5SAlex Deucher false); 17852c8ad2d5SAlex Deucher 1786ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1787ab8db3e1SAndrey Grodzovsky context->dis_clk, 17882c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 17892c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 17902c8ad2d5SAlex Deucher pre_mode_set, 17912c8ad2d5SAlex Deucher false); 17922c8ad2d5SAlex Deucher 1793ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1794ab8db3e1SAndrey Grodzovsky context->dis_clk, 17952c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 17962c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 17972c8ad2d5SAlex Deucher pre_mode_set, 17982c8ad2d5SAlex Deucher false); 17994562236bSHarry Wentland } 18004562236bSHarry Wentland } 18014562236bSHarry Wentland 18023eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 1803690b5e39SRoman Li 1804690b5e39SRoman Li /* 1805690b5e39SRoman Li * Check if FBC can be enabled 1806690b5e39SRoman Li */ 18079c6569deSHarry Wentland static bool should_enable_fbc(struct dc *dc, 18083bc4aaa9SRoman Li struct dc_state *context, 18093bc4aaa9SRoman Li uint32_t *pipe_idx) 1810690b5e39SRoman Li { 18113bc4aaa9SRoman Li uint32_t i; 18123bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = NULL; 18133bc4aaa9SRoman Li struct resource_context *res_ctx = &context->res_ctx; 18143bc4aaa9SRoman Li 1815690b5e39SRoman Li 1816690b5e39SRoman Li ASSERT(dc->fbc_compressor); 1817690b5e39SRoman Li 1818690b5e39SRoman Li /* FBC memory should be allocated */ 1819690b5e39SRoman Li if (!dc->ctx->fbc_gpu_addr) 18209c6569deSHarry Wentland return false; 1821690b5e39SRoman Li 1822690b5e39SRoman Li /* Only supports single display */ 1823690b5e39SRoman Li if (context->stream_count != 1) 18249c6569deSHarry Wentland return false; 1825690b5e39SRoman Li 18263bc4aaa9SRoman Li for (i = 0; i < dc->res_pool->pipe_count; i++) { 18273bc4aaa9SRoman Li if (res_ctx->pipe_ctx[i].stream) { 18283bc4aaa9SRoman Li pipe_ctx = &res_ctx->pipe_ctx[i]; 18293bc4aaa9SRoman Li *pipe_idx = i; 18303bc4aaa9SRoman Li break; 18313bc4aaa9SRoman Li } 18323bc4aaa9SRoman Li } 18333bc4aaa9SRoman Li 18347a840773SRoman Li /* Pipe context should be found */ 18357a840773SRoman Li ASSERT(pipe_ctx); 18367a840773SRoman Li 1837690b5e39SRoman Li /* Only supports eDP */ 1838690b5e39SRoman Li if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP) 18399c6569deSHarry Wentland return false; 1840690b5e39SRoman Li 1841690b5e39SRoman Li /* PSR should not be enabled */ 1842690b5e39SRoman Li if (pipe_ctx->stream->sink->link->psr_enabled) 18439c6569deSHarry Wentland return false; 1844690b5e39SRoman Li 184593984bbcSShirish S /* Nothing to compress */ 184693984bbcSShirish S if (!pipe_ctx->plane_state) 18479c6569deSHarry Wentland return false; 184893984bbcSShirish S 184905230fa9SRoman Li /* Only for non-linear tiling */ 185005230fa9SRoman Li if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 18519c6569deSHarry Wentland return false; 185205230fa9SRoman Li 18539c6569deSHarry Wentland return true; 1854690b5e39SRoman Li } 1855690b5e39SRoman Li 1856690b5e39SRoman Li /* 1857690b5e39SRoman Li * Enable FBC 1858690b5e39SRoman Li */ 18599c6569deSHarry Wentland static void enable_fbc(struct dc *dc, 1860608ac7bbSJerry Zuo struct dc_state *context) 1861690b5e39SRoman Li { 18623bc4aaa9SRoman Li uint32_t pipe_idx = 0; 18633bc4aaa9SRoman Li 18643bc4aaa9SRoman Li if (should_enable_fbc(dc, context, &pipe_idx)) { 1865690b5e39SRoman Li /* Program GRPH COMPRESSED ADDRESS and PITCH */ 1866690b5e39SRoman Li struct compr_addr_and_pitch_params params = {0, 0, 0}; 1867690b5e39SRoman Li struct compressor *compr = dc->fbc_compressor; 18683bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 18693bc4aaa9SRoman Li 1870690b5e39SRoman Li 18719c6569deSHarry Wentland params.source_view_width = pipe_ctx->stream->timing.h_addressable; 18729c6569deSHarry Wentland params.source_view_height = pipe_ctx->stream->timing.v_addressable; 1873690b5e39SRoman Li 1874690b5e39SRoman Li compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 1875690b5e39SRoman Li 1876690b5e39SRoman Li compr->funcs->surface_address_and_pitch(compr, ¶ms); 1877690b5e39SRoman Li compr->funcs->set_fbc_invalidation_triggers(compr, 1); 1878690b5e39SRoman Li 1879690b5e39SRoman Li compr->funcs->enable_fbc(compr, ¶ms); 1880690b5e39SRoman Li } 1881690b5e39SRoman Li } 1882690b5e39SRoman Li #endif 1883690b5e39SRoman Li 188454e8695eSDmytro Laktyushkin static void dce110_reset_hw_ctx_wrap( 1885fb3466a4SBhawanpreet Lakha struct dc *dc, 1886608ac7bbSJerry Zuo struct dc_state *context) 18874562236bSHarry Wentland { 18884562236bSHarry Wentland int i; 18894562236bSHarry Wentland 18904562236bSHarry Wentland /* Reset old context */ 18914562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 1892a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 18934562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 1894608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 18954562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 18964562236bSHarry Wentland 18974562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 18984562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 18994562236bSHarry Wentland * PHY when not already disabled. 19004562236bSHarry Wentland */ 19014562236bSHarry Wentland 19024562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 19034562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 19044562236bSHarry Wentland continue; 19054562236bSHarry Wentland 19064562236bSHarry Wentland if (!pipe_ctx->stream || 190754e8695eSDmytro Laktyushkin pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 190821e67d4dSHarry Wentland struct clock_source *old_clk = pipe_ctx_old->clock_source; 190921e67d4dSHarry Wentland 1910827f11e9SLeo (Sunpeng) Li /* Disable if new stream is null. O/w, if stream is 1911827f11e9SLeo (Sunpeng) Li * disabled already, no need to disable again. 1912827f11e9SLeo (Sunpeng) Li */ 1913827f11e9SLeo (Sunpeng) Li if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) 19144176664bSCharlene Liu core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); 1915d050f8edSHersen Wu 19166b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 19176b670fa9SHarry Wentland if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 191854e8695eSDmytro Laktyushkin dm_error("DC: failed to blank crtc!\n"); 191954e8695eSDmytro Laktyushkin BREAK_TO_DEBUGGER(); 192054e8695eSDmytro Laktyushkin } 19216b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 192286a66c4eSHarry Wentland pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 1923608ac7bbSJerry Zuo pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 192454e8695eSDmytro Laktyushkin 192521e67d4dSHarry Wentland if (old_clk) 192621e67d4dSHarry Wentland old_clk->funcs->cs_power_down(old_clk); 192721e67d4dSHarry Wentland 19287f914a62SYongqiang Sun dc->hwss.disable_plane(dc, pipe_ctx_old); 192954e8695eSDmytro Laktyushkin 193054e8695eSDmytro Laktyushkin pipe_ctx_old->stream = NULL; 193154e8695eSDmytro Laktyushkin } 19324562236bSHarry Wentland } 19334562236bSHarry Wentland } 19344562236bSHarry Wentland 1935cf437593SDmytro Laktyushkin 19364562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 1937fb3466a4SBhawanpreet Lakha struct dc *dc, 1938608ac7bbSJerry Zuo struct dc_state *context) 19394562236bSHarry Wentland { 19404562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 19414562236bSHarry Wentland enum dc_status status; 19424562236bSHarry Wentland int i; 1943e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID; 19444562236bSHarry Wentland 19454562236bSHarry Wentland /* Reset old context */ 19464562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 19474562236bSHarry Wentland dc->hwss.reset_hw_ctx_wrap(dc, context); 19484562236bSHarry Wentland 19494562236bSHarry Wentland /* Skip applying if no targets */ 1950ab2541b6SAric Cyr if (context->stream_count <= 0) 19514562236bSHarry Wentland return DC_OK; 19524562236bSHarry Wentland 19534562236bSHarry Wentland /* Apply new context */ 19544562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 19554562236bSHarry Wentland 19564562236bSHarry Wentland /* below is for real asic only */ 1957a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 19584562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 1959608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 19604562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 19614562236bSHarry Wentland 19624562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 19634562236bSHarry Wentland continue; 19644562236bSHarry Wentland 19654562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 19664562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 19674562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 19684562236bSHarry Wentland pipe_ctx->clock_source, i); 19694562236bSHarry Wentland continue; 19704562236bSHarry Wentland } 19714562236bSHarry Wentland 19724562236bSHarry Wentland dc->hwss.enable_display_power_gating( 19734562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 19744562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 19754562236bSHarry Wentland } 19764562236bSHarry Wentland 1977a2b8659dSTony Cheng set_safe_displaymarks(&context->res_ctx, dc->res_pool); 19781663ae1cSBhawanpreet Lakha 19793eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 19802f3bfb27SRoman Li if (dc->fbc_compressor) 19811663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 19821663ae1cSBhawanpreet Lakha #endif 19834562236bSHarry Wentland /*TODO: when pplib works*/ 19844562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, true); 19854562236bSHarry Wentland 1986ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 19873639fa68SZeyu Fan if (dc->ctx->dce_version >= DCN_VERSION_1_0) { 19889037d802SDmytro Laktyushkin if (context->bw.dcn.calc_clk.fclk_khz 1989608ac7bbSJerry Zuo > dc->current_state->bw.dcn.cur_clk.fclk_khz) { 1990ff5ef992SAlex Deucher struct dm_pp_clock_for_voltage_req clock; 1991ff5ef992SAlex Deucher 1992ff5ef992SAlex Deucher clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; 19939037d802SDmytro Laktyushkin clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; 1994ff5ef992SAlex Deucher dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); 1995608ac7bbSJerry Zuo dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; 1996c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; 1997ff5ef992SAlex Deucher } 19989037d802SDmytro Laktyushkin if (context->bw.dcn.calc_clk.dcfclk_khz 1999608ac7bbSJerry Zuo > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { 2000ff5ef992SAlex Deucher struct dm_pp_clock_for_voltage_req clock; 2001ff5ef992SAlex Deucher 2002ff5ef992SAlex Deucher clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; 20039037d802SDmytro Laktyushkin clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; 2004ff5ef992SAlex Deucher dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); 2005608ac7bbSJerry Zuo dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; 2006c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; 2007ff5ef992SAlex Deucher } 2008c66a54dcSDmytro Laktyushkin if (context->bw.dcn.calc_clk.dispclk_khz 2009608ac7bbSJerry Zuo > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { 2010c66a54dcSDmytro Laktyushkin dc->res_pool->display_clock->funcs->set_clock( 2011c66a54dcSDmytro Laktyushkin dc->res_pool->display_clock, 2012c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz); 2013608ac7bbSJerry Zuo dc->current_state->bw.dcn.cur_clk.dispclk_khz = 2014c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz; 2015c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.dispclk_khz = 2016c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz; 2017c66a54dcSDmytro Laktyushkin } 2018c66a54dcSDmytro Laktyushkin } else 2019ff5ef992SAlex Deucher #endif 20209037d802SDmytro Laktyushkin if (context->bw.dce.dispclk_khz 2021608ac7bbSJerry Zuo > dc->current_state->bw.dce.dispclk_khz) { 2022a2b8659dSTony Cheng dc->res_pool->display_clock->funcs->set_clock( 2023a2b8659dSTony Cheng dc->res_pool->display_clock, 20249037d802SDmytro Laktyushkin context->bw.dce.dispclk_khz * 115 / 100); 20251ce71fcdSCharlene Liu } 2026ab8812a3SHersen Wu /* program audio wall clock. use HDMI as clock source if HDMI 2027ab8812a3SHersen Wu * audio active. Otherwise, use DP as clock source 2028ab8812a3SHersen Wu * first, loop to find any HDMI audio, if not, loop find DP audio 2029ab8812a3SHersen Wu */ 20304562236bSHarry Wentland /* Setup audio rate clock source */ 20314562236bSHarry Wentland /* Issue: 20324562236bSHarry Wentland * Audio lag happened on DP monitor when unplug a HDMI monitor 20334562236bSHarry Wentland * 20344562236bSHarry Wentland * Cause: 20354562236bSHarry Wentland * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 20364562236bSHarry Wentland * is set to either dto0 or dto1, audio should work fine. 20374562236bSHarry Wentland * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 20384562236bSHarry Wentland * set to dto0 will cause audio lag. 20394562236bSHarry Wentland * 20404562236bSHarry Wentland * Solution: 20414562236bSHarry Wentland * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 20424562236bSHarry Wentland * find first available pipe with audio, setup audio wall DTO per topology 20434562236bSHarry Wentland * instead of per pipe. 20444562236bSHarry Wentland */ 2045a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2046ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2047ab8812a3SHersen Wu 2048ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2049ab8812a3SHersen Wu continue; 2050ab8812a3SHersen Wu 2051ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 2052ab8812a3SHersen Wu continue; 2053ab8812a3SHersen Wu 2054ab8812a3SHersen Wu if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 2055ab8812a3SHersen Wu continue; 2056ab8812a3SHersen Wu 2057afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 2058ab8812a3SHersen Wu struct audio_output audio_output; 2059ab8812a3SHersen Wu 2060ab8db3e1SAndrey Grodzovsky build_audio_output(context, pipe_ctx, &audio_output); 2061ab8812a3SHersen Wu 2062afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2063afaacef4SHarry Wentland pipe_ctx->stream_res.audio, 2064ab8812a3SHersen Wu pipe_ctx->stream->signal, 2065ab8812a3SHersen Wu &audio_output.crtc_info, 2066ab8812a3SHersen Wu &audio_output.pll_info); 2067ab8812a3SHersen Wu break; 2068ab8812a3SHersen Wu } 2069ab8812a3SHersen Wu } 2070ab8812a3SHersen Wu 2071ab8812a3SHersen Wu /* no HDMI audio is found, try DP audio */ 2072a2b8659dSTony Cheng if (i == dc->res_pool->pipe_count) { 2073a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2074ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2075ab8812a3SHersen Wu 2076ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2077ab8812a3SHersen Wu continue; 2078ab8812a3SHersen Wu 2079ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 2080ab8812a3SHersen Wu continue; 2081ab8812a3SHersen Wu 2082ab8812a3SHersen Wu if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 2083ab8812a3SHersen Wu continue; 2084ab8812a3SHersen Wu 2085afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 2086ab8812a3SHersen Wu struct audio_output audio_output; 2087ab8812a3SHersen Wu 2088ab8db3e1SAndrey Grodzovsky build_audio_output(context, pipe_ctx, &audio_output); 2089ab8812a3SHersen Wu 2090afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2091afaacef4SHarry Wentland pipe_ctx->stream_res.audio, 2092ab8812a3SHersen Wu pipe_ctx->stream->signal, 2093ab8812a3SHersen Wu &audio_output.crtc_info, 2094ab8812a3SHersen Wu &audio_output.pll_info); 2095ab8812a3SHersen Wu break; 2096ab8812a3SHersen Wu } 2097ab8812a3SHersen Wu } 2098ab8812a3SHersen Wu } 2099ab8812a3SHersen Wu 2100a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2101ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 2102608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 2103ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2104ab8812a3SHersen Wu 2105ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2106ab8812a3SHersen Wu continue; 2107ab8812a3SHersen Wu 2108ab8812a3SHersen Wu if (pipe_ctx->stream == pipe_ctx_old->stream) 2109ab8812a3SHersen Wu continue; 2110ab8812a3SHersen Wu 21115b92d9d4SHarry Wentland if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2112313bf4ffSYongqiang Sun continue; 2113313bf4ffSYongqiang Sun 2114ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 2115ab8812a3SHersen Wu continue; 2116ab8812a3SHersen Wu 2117afaacef4SHarry Wentland if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) { 2118ab8812a3SHersen Wu 21194562236bSHarry Wentland struct audio_output audio_output; 21204562236bSHarry Wentland 2121ab8db3e1SAndrey Grodzovsky build_audio_output(context, pipe_ctx, &audio_output); 21224562236bSHarry Wentland 21234562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 21248e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 21258e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 2126afaacef4SHarry Wentland pipe_ctx->stream_res.audio->inst, 21274fa086b9SLeo (Sunpeng) Li &pipe_ctx->stream->audio_info); 21284562236bSHarry Wentland else 21298e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 21308e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 2131afaacef4SHarry Wentland pipe_ctx->stream_res.audio->inst, 21324fa086b9SLeo (Sunpeng) Li &pipe_ctx->stream->audio_info, 21334562236bSHarry Wentland &audio_output.crtc_info); 21344562236bSHarry Wentland 2135afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->az_configure( 2136afaacef4SHarry Wentland pipe_ctx->stream_res.audio, 21374562236bSHarry Wentland pipe_ctx->stream->signal, 21384562236bSHarry Wentland &audio_output.crtc_info, 21394fa086b9SLeo (Sunpeng) Li &pipe_ctx->stream->audio_info); 21404562236bSHarry Wentland } 21414562236bSHarry Wentland 21424562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 21434562236bSHarry Wentland pipe_ctx, 21444562236bSHarry Wentland context, 21454562236bSHarry Wentland dc); 21464562236bSHarry Wentland 21474562236bSHarry Wentland if (DC_OK != status) 21484562236bSHarry Wentland return status; 21494562236bSHarry Wentland } 21504562236bSHarry Wentland 21514562236bSHarry Wentland /* to save power */ 21524562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, false); 21534562236bSHarry Wentland 21544562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, false); 21554562236bSHarry Wentland 21563eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 2157690b5e39SRoman Li if (dc->fbc_compressor) 2158690b5e39SRoman Li enable_fbc(dc, context); 2159690b5e39SRoman Li 2160690b5e39SRoman Li #endif 2161cf437593SDmytro Laktyushkin 21624562236bSHarry Wentland return DC_OK; 21634562236bSHarry Wentland } 21644562236bSHarry Wentland 21654562236bSHarry Wentland /******************************************************************************* 21664562236bSHarry Wentland * Front End programming 21674562236bSHarry Wentland ******************************************************************************/ 21684562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 21694562236bSHarry Wentland { 21704562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 21714562236bSHarry Wentland 21724562236bSHarry Wentland default_adjust.force_hw_default = false; 217334996173SHarry Wentland default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 217434996173SHarry Wentland default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 21754562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 21766702a9acSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 21774562236bSHarry Wentland 21784562236bSHarry Wentland /* display color depth */ 21794562236bSHarry Wentland default_adjust.color_depth = 21804fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.display_color_depth; 21814562236bSHarry Wentland 21824562236bSHarry Wentland /* Lb color depth */ 21836702a9acSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 21844562236bSHarry Wentland 218586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 218686a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, &default_adjust); 21874562236bSHarry Wentland } 21884562236bSHarry Wentland 2189b06b7680SLeon Elazar 2190b06b7680SLeon Elazar /******************************************************************************* 2191b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 2192b06b7680SLeon Elazar * Blender + CRTC 2193b06b7680SLeon Elazar * 2194b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 2195b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 2196b06b7680SLeon Elazar * 2197b06b7680SLeon Elazar * |----------------------------------------------- | 2198b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 2199b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 2200b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 2201b06b7680SLeon Elazar * |------------------------------------------------| 2202b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 2203b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 2204b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 2205b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 2206b06b7680SLeon Elazar * -------------------------------------------------| 2207b06b7680SLeon Elazar * 2208b06b7680SLeon Elazar ******************************************************************************/ 2209fb3466a4SBhawanpreet Lakha static void program_surface_visibility(const struct dc *dc, 22104562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 22114562236bSHarry Wentland { 22124562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2213b06b7680SLeon Elazar bool blank_target = false; 22144562236bSHarry Wentland 22154562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 2216b06b7680SLeon Elazar 2217b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 2218b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2219b06b7680SLeon Elazar 22203be5262eSHarry Wentland if (pipe_ctx->bottom_pipe->plane_state->visible) { 22213be5262eSHarry Wentland if (pipe_ctx->plane_state->visible) 22224562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 22234562236bSHarry Wentland else 22244562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 2225b06b7680SLeon Elazar 22263be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2227b06b7680SLeon Elazar blank_target = true; 2228b06b7680SLeon Elazar 22293be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2230b06b7680SLeon Elazar blank_target = true; 2231b06b7680SLeon Elazar 2232e07f541fSYongqiang Sun dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 22336b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2234b06b7680SLeon Elazar 22354562236bSHarry Wentland } 22364562236bSHarry Wentland 22371bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 22381bf56e62SZeyu Fan { 2239146a9f63SKrunoslav Kovac int i = 0; 22401bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 22411bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 22421bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 22431bf56e62SZeyu Fan 22441bf56e62SZeyu Fan 22454fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 22461bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2247146a9f63SKrunoslav Kovac 2248146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2249146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2250146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 22511bf56e62SZeyu Fan } 22521bf56e62SZeyu Fan 225386a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 22541bf56e62SZeyu Fan } 22551bf56e62SZeyu Fan 22564562236bSHarry Wentland /** 22574562236bSHarry Wentland * TODO REMOVE, USE UPDATE INSTEAD 22584562236bSHarry Wentland */ 22594562236bSHarry Wentland static void set_plane_config( 2260fb3466a4SBhawanpreet Lakha const struct dc *dc, 22614562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 22624562236bSHarry Wentland struct resource_context *res_ctx) 22634562236bSHarry Wentland { 226486a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 22653be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 22664562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 22674562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 22684562236bSHarry Wentland unsigned int i; 22694562236bSHarry Wentland 22704562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 22714562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 22724562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 22734562236bSHarry Wentland 2274e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 22754562236bSHarry Wentland 22764562236bSHarry Wentland set_default_colors(pipe_ctx); 227756ef6ed9SAnthony Koo if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 22784562236bSHarry Wentland tbl_entry.color_space = 22794fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 22804562236bSHarry Wentland 22814562236bSHarry Wentland for (i = 0; i < 12; i++) 22824562236bSHarry Wentland tbl_entry.regval[i] = 22834fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 22844562236bSHarry Wentland 228586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 228686a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 22874562236bSHarry Wentland } 22884562236bSHarry Wentland 22894fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 22904562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2291146a9f63SKrunoslav Kovac 2292146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2293146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2294146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 22954562236bSHarry Wentland } 22964562236bSHarry Wentland 229786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 22984562236bSHarry Wentland 22996702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 23004562236bSHarry Wentland program_scaler(dc, pipe_ctx); 23014562236bSHarry Wentland 2302b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 23034562236bSHarry Wentland 23044562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 23054562236bSHarry Wentland mi, 23063be5262eSHarry Wentland plane_state->format, 23073be5262eSHarry Wentland &plane_state->tiling_info, 23083be5262eSHarry Wentland &plane_state->plane_size, 23093be5262eSHarry Wentland plane_state->rotation, 23104562236bSHarry Wentland NULL, 23114b28b76bSDmytro Laktyushkin false); 23124b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 23133be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 23144562236bSHarry Wentland 2315fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 23164562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 231786a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 23183be5262eSHarry Wentland plane_state->format, 23193be5262eSHarry Wentland &plane_state->tiling_info, 23203be5262eSHarry Wentland plane_state->rotation); 23214562236bSHarry Wentland } 23224562236bSHarry Wentland 2323fb3466a4SBhawanpreet Lakha static void update_plane_addr(const struct dc *dc, 23244562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 23254562236bSHarry Wentland { 23263be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 23274562236bSHarry Wentland 23283be5262eSHarry Wentland if (plane_state == NULL) 23294562236bSHarry Wentland return; 23304562236bSHarry Wentland 233186a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 233286a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 23333be5262eSHarry Wentland &plane_state->address, 23343be5262eSHarry Wentland plane_state->flip_immediate); 23354562236bSHarry Wentland 23363be5262eSHarry Wentland plane_state->status.requested_address = plane_state->address; 23374562236bSHarry Wentland } 23384562236bSHarry Wentland 2339f774b339SEric Yang static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 23404562236bSHarry Wentland { 23413be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 23424562236bSHarry Wentland 23433be5262eSHarry Wentland if (plane_state == NULL) 23444562236bSHarry Wentland return; 23454562236bSHarry Wentland 23463be5262eSHarry Wentland plane_state->status.is_flip_pending = 234786a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 234886a66c4eSHarry Wentland pipe_ctx->plane_res.mi); 23494562236bSHarry Wentland 23503be5262eSHarry Wentland if (plane_state->status.is_flip_pending && !plane_state->visible) 235186a66c4eSHarry Wentland pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 23524562236bSHarry Wentland 235386a66c4eSHarry Wentland plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 235486a66c4eSHarry Wentland if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 23556b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 23563be5262eSHarry Wentland plane_state->status.is_right_eye =\ 23576b670fa9SHarry Wentland !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 23587f5c22d1SVitaly Prosyak } 23594562236bSHarry Wentland } 23604562236bSHarry Wentland 2361fb3466a4SBhawanpreet Lakha void dce110_power_down(struct dc *dc) 23624562236bSHarry Wentland { 23634562236bSHarry Wentland power_down_all_hw_blocks(dc); 23644562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 23654562236bSHarry Wentland } 23664562236bSHarry Wentland 23674562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 23684562236bSHarry Wentland struct dc_context *dc_ctx, 23694562236bSHarry Wentland struct timing_generator *tg) 23704562236bSHarry Wentland { 23714562236bSHarry Wentland bool rc = false; 23724562236bSHarry Wentland 23734562236bSHarry Wentland /* To avoid endless loop we wait at most 23744562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 23754562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 23764562236bSHarry Wentland uint32_t i; 23774562236bSHarry Wentland 23784562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 23794562236bSHarry Wentland 23804562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 23814562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 23824562236bSHarry Wentland break; 23834562236bSHarry Wentland } 23844562236bSHarry Wentland 23854562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 23864562236bSHarry Wentland rc = true; 23874562236bSHarry Wentland /* usually occurs at i=1 */ 23884562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 23894562236bSHarry Wentland i); 23904562236bSHarry Wentland break; 23914562236bSHarry Wentland } 23924562236bSHarry Wentland 23934562236bSHarry Wentland /* Wait for one frame. */ 23944562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 23954562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 23964562236bSHarry Wentland } 23974562236bSHarry Wentland 23984562236bSHarry Wentland if (false == rc) 23994562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 24004562236bSHarry Wentland 24014562236bSHarry Wentland return rc; 24024562236bSHarry Wentland } 24034562236bSHarry Wentland 24044562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 24054562236bSHarry Wentland static void dce110_enable_timing_synchronization( 2406fb3466a4SBhawanpreet Lakha struct dc *dc, 24074562236bSHarry Wentland int group_index, 24084562236bSHarry Wentland int group_size, 24094562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 24104562236bSHarry Wentland { 24114562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 24124562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 24134562236bSHarry Wentland int i; 24144562236bSHarry Wentland 24154562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 24164562236bSHarry Wentland 24174562236bSHarry Wentland /* Designate a single TG in the group as a master. 24184562236bSHarry Wentland * Since HW doesn't care which one, we always assign 24194562236bSHarry Wentland * the 1st one in the group. */ 24204562236bSHarry Wentland gsl_params.gsl_group = 0; 24216b670fa9SHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 24224562236bSHarry Wentland 24234562236bSHarry Wentland for (i = 0; i < group_size; i++) 24246b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 24256b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg, &gsl_params); 24264562236bSHarry Wentland 24274562236bSHarry Wentland /* Reset slave controllers on master VSync */ 24284562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 24294562236bSHarry Wentland 24304562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 24316b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2432fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2433fa2123dbSMikita Lipski gsl_params.gsl_group); 24344562236bSHarry Wentland 24354562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 24364562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 24376b670fa9SHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2438fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2439fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg); 24404562236bSHarry Wentland } 24414562236bSHarry Wentland 24424562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 24434562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 24444562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 24454562236bSHarry Wentland for (i = 0; i < group_size; i++) 24466b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 24474562236bSHarry Wentland 24484562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 24494562236bSHarry Wentland } 24504562236bSHarry Wentland 2451fa2123dbSMikita Lipski static void dce110_enable_per_frame_crtc_position_reset( 2452fa2123dbSMikita Lipski struct dc *dc, 2453fa2123dbSMikita Lipski int group_size, 2454fa2123dbSMikita Lipski struct pipe_ctx *grouped_pipes[]) 2455fa2123dbSMikita Lipski { 2456fa2123dbSMikita Lipski struct dc_context *dc_ctx = dc->ctx; 2457fa2123dbSMikita Lipski struct dcp_gsl_params gsl_params = { 0 }; 2458fa2123dbSMikita Lipski int i; 2459fa2123dbSMikita Lipski 2460fa2123dbSMikita Lipski gsl_params.gsl_group = 0; 2461fa2123dbSMikita Lipski gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst; 2462fa2123dbSMikita Lipski 2463fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2464fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2465fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, &gsl_params); 2466fa2123dbSMikita Lipski 2467fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2468fa2123dbSMikita Lipski 2469fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2470fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2471fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2472fa2123dbSMikita Lipski gsl_params.gsl_master, 2473fa2123dbSMikita Lipski &grouped_pipes[i]->stream->triggered_crtc_reset); 2474fa2123dbSMikita Lipski 2475fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2476fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2477fa2123dbSMikita Lipski wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2478fa2123dbSMikita Lipski 2479fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2480fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2481fa2123dbSMikita Lipski 2482fa2123dbSMikita Lipski } 2483fa2123dbSMikita Lipski 2484fb3466a4SBhawanpreet Lakha static void init_hw(struct dc *dc) 24854562236bSHarry Wentland { 24864562236bSHarry Wentland int i; 24874562236bSHarry Wentland struct dc_bios *bp; 24884562236bSHarry Wentland struct transform *xfm; 24895e7773a2SAnthony Koo struct abm *abm; 24904562236bSHarry Wentland 24914562236bSHarry Wentland bp = dc->ctx->dc_bios; 24924562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 24934562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 24944562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 24954562236bSHarry Wentland 24964562236bSHarry Wentland dc->hwss.enable_display_power_gating( 24974562236bSHarry Wentland dc, i, bp, 24984562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 24994562236bSHarry Wentland dc->hwss.enable_display_power_gating( 25004562236bSHarry Wentland dc, i, bp, 25014562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 25024562236bSHarry Wentland dc->hwss.enable_display_pipe_clock_gating( 25034562236bSHarry Wentland dc->ctx, 25044562236bSHarry Wentland true); 25054562236bSHarry Wentland } 25064562236bSHarry Wentland 2507e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 25084562236bSHarry Wentland /***************************************/ 25094562236bSHarry Wentland 25104562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 25114562236bSHarry Wentland /****************************************/ 25124562236bSHarry Wentland /* Power up AND update implementation according to the 25134562236bSHarry Wentland * required signal (which may be different from the 25144562236bSHarry Wentland * default signal on connector). */ 2515d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 2516069d418fSAndrew Jiang 2517069d418fSAndrew Jiang if (link->link_enc->connector.id == CONNECTOR_ID_EDP) 2518069d418fSAndrew Jiang dc->hwss.edp_power_control(link, true); 2519069d418fSAndrew Jiang 25204562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 25214562236bSHarry Wentland } 25224562236bSHarry Wentland 25234562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 25244562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 25254562236bSHarry Wentland 25264562236bSHarry Wentland tg->funcs->disable_vga(tg); 25274562236bSHarry Wentland 25284562236bSHarry Wentland /* Blank controller using driver code instead of 25294562236bSHarry Wentland * command table. */ 25304562236bSHarry Wentland tg->funcs->set_blank(tg, true); 25314b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 25324562236bSHarry Wentland } 25334562236bSHarry Wentland 25344562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 25354562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 25364562236bSHarry Wentland audio->funcs->hw_init(audio); 25374562236bSHarry Wentland } 25385e7773a2SAnthony Koo 25395e7773a2SAnthony Koo abm = dc->res_pool->abm; 25406728b30cSAnthony Koo if (abm != NULL) { 25416728b30cSAnthony Koo abm->funcs->init_backlight(abm); 25425e7773a2SAnthony Koo abm->funcs->abm_init(abm); 25434562236bSHarry Wentland } 25443eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 25452f3bfb27SRoman Li if (dc->fbc_compressor) 25461663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 25471663ae1cSBhawanpreet Lakha #endif 2548690b5e39SRoman Li 25496728b30cSAnthony Koo } 25504562236bSHarry Wentland 255128f72454SJordan Lazare void dce110_fill_display_configs( 2552608ac7bbSJerry Zuo const struct dc_state *context, 2553cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg) 25544562236bSHarry Wentland { 2555cf437593SDmytro Laktyushkin int j; 2556cf437593SDmytro Laktyushkin int num_cfgs = 0; 2557cf437593SDmytro Laktyushkin 2558cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 2559cf437593SDmytro Laktyushkin int k; 2560cf437593SDmytro Laktyushkin 25610971c40eSHarry Wentland const struct dc_stream_state *stream = context->streams[j]; 2562cf437593SDmytro Laktyushkin struct dm_pp_single_disp_config *cfg = 2563cf437593SDmytro Laktyushkin &pp_display_cfg->disp_configs[num_cfgs]; 2564cf437593SDmytro Laktyushkin const struct pipe_ctx *pipe_ctx = NULL; 2565cf437593SDmytro Laktyushkin 2566cf437593SDmytro Laktyushkin for (k = 0; k < MAX_PIPES; k++) 2567cf437593SDmytro Laktyushkin if (stream == context->res_ctx.pipe_ctx[k].stream) { 2568cf437593SDmytro Laktyushkin pipe_ctx = &context->res_ctx.pipe_ctx[k]; 2569cf437593SDmytro Laktyushkin break; 25704562236bSHarry Wentland } 25714562236bSHarry Wentland 2572cf437593SDmytro Laktyushkin ASSERT(pipe_ctx != NULL); 2573cf437593SDmytro Laktyushkin 2574631aaa0aSHersen Wu /* only notify active stream */ 2575631aaa0aSHersen Wu if (stream->dpms_off) 2576631aaa0aSHersen Wu continue; 2577631aaa0aSHersen Wu 2578cf437593SDmytro Laktyushkin num_cfgs++; 2579cf437593SDmytro Laktyushkin cfg->signal = pipe_ctx->stream->signal; 2580e07f541fSYongqiang Sun cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; 25814fa086b9SLeo (Sunpeng) Li cfg->src_height = stream->src.height; 25824fa086b9SLeo (Sunpeng) Li cfg->src_width = stream->src.width; 2583cf437593SDmytro Laktyushkin cfg->ddi_channel_mapping = 2584cf437593SDmytro Laktyushkin stream->sink->link->ddi_channel_mapping.raw; 2585cf437593SDmytro Laktyushkin cfg->transmitter = 2586cf437593SDmytro Laktyushkin stream->sink->link->link_enc->transmitter; 2587cf437593SDmytro Laktyushkin cfg->link_settings.lane_count = 2588d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.lane_count; 2589cf437593SDmytro Laktyushkin cfg->link_settings.link_rate = 2590d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.link_rate; 2591cf437593SDmytro Laktyushkin cfg->link_settings.link_spread = 2592d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.link_spread; 2593cf437593SDmytro Laktyushkin cfg->sym_clock = stream->phy_pix_clk; 2594cf437593SDmytro Laktyushkin /* Round v_refresh*/ 25954fa086b9SLeo (Sunpeng) Li cfg->v_refresh = stream->timing.pix_clk_khz * 1000; 25964fa086b9SLeo (Sunpeng) Li cfg->v_refresh /= stream->timing.h_total; 25974fa086b9SLeo (Sunpeng) Li cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) 25984fa086b9SLeo (Sunpeng) Li / stream->timing.v_total; 2599cf437593SDmytro Laktyushkin } 2600cf437593SDmytro Laktyushkin 2601cf437593SDmytro Laktyushkin pp_display_cfg->display_count = num_cfgs; 2602cf437593SDmytro Laktyushkin } 2603cf437593SDmytro Laktyushkin 2604608ac7bbSJerry Zuo uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) 2605cf437593SDmytro Laktyushkin { 2606cf437593SDmytro Laktyushkin uint8_t j; 2607cf437593SDmytro Laktyushkin uint32_t min_vertical_blank_time = -1; 2608cf437593SDmytro Laktyushkin 2609cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 26100971c40eSHarry Wentland struct dc_stream_state *stream = context->streams[j]; 2611cf437593SDmytro Laktyushkin uint32_t vertical_blank_in_pixels = 0; 2612cf437593SDmytro Laktyushkin uint32_t vertical_blank_time = 0; 2613cf437593SDmytro Laktyushkin 2614cf437593SDmytro Laktyushkin vertical_blank_in_pixels = stream->timing.h_total * 2615cf437593SDmytro Laktyushkin (stream->timing.v_total 2616cf437593SDmytro Laktyushkin - stream->timing.v_addressable); 2617cf437593SDmytro Laktyushkin 2618cf437593SDmytro Laktyushkin vertical_blank_time = vertical_blank_in_pixels 2619cf437593SDmytro Laktyushkin * 1000 / stream->timing.pix_clk_khz; 2620cf437593SDmytro Laktyushkin 2621cf437593SDmytro Laktyushkin if (min_vertical_blank_time > vertical_blank_time) 2622cf437593SDmytro Laktyushkin min_vertical_blank_time = vertical_blank_time; 2623cf437593SDmytro Laktyushkin } 2624cf437593SDmytro Laktyushkin 2625cf437593SDmytro Laktyushkin return min_vertical_blank_time; 2626cf437593SDmytro Laktyushkin } 2627cf437593SDmytro Laktyushkin 2628cf437593SDmytro Laktyushkin static int determine_sclk_from_bounding_box( 2629fb3466a4SBhawanpreet Lakha const struct dc *dc, 2630cf437593SDmytro Laktyushkin int required_sclk) 26314562236bSHarry Wentland { 26324562236bSHarry Wentland int i; 26334562236bSHarry Wentland 2634cf437593SDmytro Laktyushkin /* 2635cf437593SDmytro Laktyushkin * Some asics do not give us sclk levels, so we just report the actual 2636cf437593SDmytro Laktyushkin * required sclk 2637cf437593SDmytro Laktyushkin */ 2638cf437593SDmytro Laktyushkin if (dc->sclk_lvls.num_levels == 0) 2639cf437593SDmytro Laktyushkin return required_sclk; 26404562236bSHarry Wentland 2641cf437593SDmytro Laktyushkin for (i = 0; i < dc->sclk_lvls.num_levels; i++) { 2642cf437593SDmytro Laktyushkin if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) 2643cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[i]; 2644cf437593SDmytro Laktyushkin } 2645cf437593SDmytro Laktyushkin /* 2646cf437593SDmytro Laktyushkin * even maximum level could not satisfy requirement, this 2647cf437593SDmytro Laktyushkin * is unexpected at this stage, should have been caught at 2648cf437593SDmytro Laktyushkin * validation time 2649cf437593SDmytro Laktyushkin */ 2650cf437593SDmytro Laktyushkin ASSERT(0); 2651cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; 26524562236bSHarry Wentland } 26534562236bSHarry Wentland 2654cf437593SDmytro Laktyushkin static void pplib_apply_display_requirements( 2655fb3466a4SBhawanpreet Lakha struct dc *dc, 2656608ac7bbSJerry Zuo struct dc_state *context) 2657cf437593SDmytro Laktyushkin { 2658cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 2659cf437593SDmytro Laktyushkin 2660cf437593SDmytro Laktyushkin pp_display_cfg->all_displays_in_sync = 26619037d802SDmytro Laktyushkin context->bw.dce.all_displays_in_sync; 2662cf437593SDmytro Laktyushkin pp_display_cfg->nb_pstate_switch_disable = 26639037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_enable == false; 2664cf437593SDmytro Laktyushkin pp_display_cfg->cpu_cc6_disable = 26659037d802SDmytro Laktyushkin context->bw.dce.cpuc_state_change_enable == false; 2666cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_disable = 26679037d802SDmytro Laktyushkin context->bw.dce.cpup_state_change_enable == false; 2668cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_separation_time = 26699037d802SDmytro Laktyushkin context->bw.dce.blackout_recovery_time_us; 2670cf437593SDmytro Laktyushkin 26719037d802SDmytro Laktyushkin pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz 2672cf437593SDmytro Laktyushkin / MEMORY_TYPE_MULTIPLIER; 2673cf437593SDmytro Laktyushkin 2674cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( 2675cf437593SDmytro Laktyushkin dc, 26769037d802SDmytro Laktyushkin context->bw.dce.sclk_khz); 2677cf437593SDmytro Laktyushkin 2678cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_deep_sleep_khz 26799037d802SDmytro Laktyushkin = context->bw.dce.sclk_deep_sleep_khz; 2680cf437593SDmytro Laktyushkin 2681cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_us = 268228f72454SJordan Lazare dce110_get_min_vblank_time_us(context); 2683cf437593SDmytro Laktyushkin /* TODO: dce11.2*/ 2684cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; 2685cf437593SDmytro Laktyushkin 26869037d802SDmytro Laktyushkin pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz; 2687cf437593SDmytro Laktyushkin 268828f72454SJordan Lazare dce110_fill_display_configs(context, pp_display_cfg); 2689cf437593SDmytro Laktyushkin 2690cf437593SDmytro Laktyushkin /* TODO: is this still applicable?*/ 2691cf437593SDmytro Laktyushkin if (pp_display_cfg->display_count == 1) { 2692cf437593SDmytro Laktyushkin const struct dc_crtc_timing *timing = 26934fa086b9SLeo (Sunpeng) Li &context->streams[0]->timing; 2694cf437593SDmytro Laktyushkin 2695cf437593SDmytro Laktyushkin pp_display_cfg->crtc_index = 2696cf437593SDmytro Laktyushkin pp_display_cfg->disp_configs[0].pipe_idx; 2697cf437593SDmytro Laktyushkin pp_display_cfg->line_time_in_us = timing->h_total * 1000 2698cf437593SDmytro Laktyushkin / timing->pix_clk_khz; 2699cf437593SDmytro Laktyushkin } 2700cf437593SDmytro Laktyushkin 2701cf437593SDmytro Laktyushkin if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( 2702cf437593SDmytro Laktyushkin struct dm_pp_display_configuration)) != 0) 2703cf437593SDmytro Laktyushkin dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); 2704cf437593SDmytro Laktyushkin 2705cf437593SDmytro Laktyushkin dc->prev_display_config = *pp_display_cfg; 2706cf437593SDmytro Laktyushkin } 2707cf437593SDmytro Laktyushkin 2708cf437593SDmytro Laktyushkin static void dce110_set_bandwidth( 2709fb3466a4SBhawanpreet Lakha struct dc *dc, 2710608ac7bbSJerry Zuo struct dc_state *context, 2711cf437593SDmytro Laktyushkin bool decrease_allowed) 2712cf437593SDmytro Laktyushkin { 27132180e7ccSDmytro Laktyushkin dce110_set_displaymarks(dc, context); 2714cf437593SDmytro Laktyushkin 2715608ac7bbSJerry Zuo if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { 2716a2b8659dSTony Cheng dc->res_pool->display_clock->funcs->set_clock( 2717a2b8659dSTony Cheng dc->res_pool->display_clock, 27189037d802SDmytro Laktyushkin context->bw.dce.dispclk_khz * 115 / 100); 2719608ac7bbSJerry Zuo dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; 2720cf437593SDmytro Laktyushkin } 2721cf437593SDmytro Laktyushkin 2722cf437593SDmytro Laktyushkin pplib_apply_display_requirements(dc, context); 27234562236bSHarry Wentland } 27244562236bSHarry Wentland 27254562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 2726fb3466a4SBhawanpreet Lakha struct dc *dc, struct pipe_ctx *pipe_ctx) 27274562236bSHarry Wentland { 272886a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 27294562236bSHarry Wentland struct pipe_ctx *old_pipe = NULL; 27303be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 27314562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 27324562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 27334562236bSHarry Wentland unsigned int i; 27345d4b05ddSBhawanpreet Lakha DC_LOGGER_INIT(); 27354562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 27364562236bSHarry Wentland 2737608ac7bbSJerry Zuo if (dc->current_state) 2738608ac7bbSJerry Zuo old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 27394562236bSHarry Wentland 27404562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 27414562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 27424562236bSHarry Wentland 2743e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 27444562236bSHarry Wentland 27454562236bSHarry Wentland set_default_colors(pipe_ctx); 27464fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 27474562236bSHarry Wentland == true) { 27484562236bSHarry Wentland tbl_entry.color_space = 27494fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 27504562236bSHarry Wentland 27514562236bSHarry Wentland for (i = 0; i < 12; i++) 27524562236bSHarry Wentland tbl_entry.regval[i] = 27534fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 27544562236bSHarry Wentland 275586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 275686a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 27574562236bSHarry Wentland } 27584562236bSHarry Wentland 27594fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 27604562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2761146a9f63SKrunoslav Kovac 2762146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2763146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2764146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 27654562236bSHarry Wentland } 27664562236bSHarry Wentland 276786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 27684562236bSHarry Wentland 27696702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2770c1473558SAndrey Grodzovsky 27714562236bSHarry Wentland program_scaler(dc, pipe_ctx); 27724562236bSHarry Wentland 27733eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 2774e008b0bcSRoman Li if (dc->fbc_compressor && old_pipe->stream) { 2775e008b0bcSRoman Li if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 2776e008b0bcSRoman Li dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2777e008b0bcSRoman Li else 2778e008b0bcSRoman Li enable_fbc(dc, dc->current_state); 2779e008b0bcSRoman Li } 2780e008b0bcSRoman Li #endif 2781e008b0bcSRoman Li 27824562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 27834562236bSHarry Wentland mi, 27843be5262eSHarry Wentland plane_state->format, 27853be5262eSHarry Wentland &plane_state->tiling_info, 27863be5262eSHarry Wentland &plane_state->plane_size, 27873be5262eSHarry Wentland plane_state->rotation, 2788624d7c47SYongqiang Sun NULL, 27894b28b76bSDmytro Laktyushkin false); 27904b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 27913be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 27924562236bSHarry Wentland 2793fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 27944562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 279586a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 27963be5262eSHarry Wentland plane_state->format, 27973be5262eSHarry Wentland &plane_state->tiling_info, 27983be5262eSHarry Wentland plane_state->rotation); 27994562236bSHarry Wentland 2800067c878aSYongqiang Sun /* Moved programming gamma from dc to hwss */ 2801405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update || 2802405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2803405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.gamma_change) 2804a6114e85SHarry Wentland dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); 2805405c50a0SAndrew Jiang 2806405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update) 2807a6114e85SHarry Wentland dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); 2808067c878aSYongqiang Sun 28091296423bSBhawanpreet Lakha DC_LOG_SURFACE( 28103032deb5SBhawanpreet Lakha "Pipe:%d %p: addr hi:0x%x, " 28114562236bSHarry Wentland "addr low:0x%x, " 28124562236bSHarry Wentland "src: %d, %d, %d," 28134562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 28144562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 28154562236bSHarry Wentland pipe_ctx->pipe_idx, 28163032deb5SBhawanpreet Lakha (void *) pipe_ctx->plane_state, 28173be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.high_part, 28183be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.low_part, 28193be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.x, 28203be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.y, 28213be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.width, 28223be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.height, 28233be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.x, 28243be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.y, 28253be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.width, 28263be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.height, 28273be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.x, 28283be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.y, 28293be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.width, 28303be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.height); 28314562236bSHarry Wentland 28321296423bSBhawanpreet Lakha DC_LOG_SURFACE( 28334562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 28344562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 28354562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 28364562236bSHarry Wentland pipe_ctx->pipe_idx, 28376702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.width, 28386702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.height, 28396702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.x, 28406702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.y, 28416702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.width, 28426702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.height, 28436702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.x, 28446702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.y); 28454562236bSHarry Wentland } 28464562236bSHarry Wentland 28474562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 2848fb3466a4SBhawanpreet Lakha struct dc *dc, 28493e9ad616SEric Yang const struct dc_stream_state *stream, 28503e9ad616SEric Yang int num_planes, 2851608ac7bbSJerry Zuo struct dc_state *context) 28524562236bSHarry Wentland { 28532194e3aeSRoman Li int i; 28544562236bSHarry Wentland 28553e9ad616SEric Yang if (num_planes == 0) 28564562236bSHarry Wentland return; 28574562236bSHarry Wentland 28583e9ad616SEric Yang for (i = 0; i < dc->res_pool->pipe_count; i++) { 28593dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 28603dc780ecSYongqiang Sun struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 28613dc780ecSYongqiang Sun 28622194e3aeSRoman Li if (stream == pipe_ctx->stream) { 28633dc780ecSYongqiang Sun if (!pipe_ctx->top_pipe && 28643dc780ecSYongqiang Sun (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) 28653dc780ecSYongqiang Sun dc->hwss.pipe_control_lock(dc, pipe_ctx, true); 28663e9ad616SEric Yang } 28673e9ad616SEric Yang } 28683e9ad616SEric Yang 2869a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 28704562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 28714562236bSHarry Wentland 2872a2607aefSHarry Wentland if (pipe_ctx->stream != stream) 28734562236bSHarry Wentland continue; 28744562236bSHarry Wentland 28753b21b6d2SJerry Zuo /* Need to allocate mem before program front end for Fiji */ 28763b21b6d2SJerry Zuo pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 28773b21b6d2SJerry Zuo pipe_ctx->plane_res.mi, 28783b21b6d2SJerry Zuo pipe_ctx->stream->timing.h_total, 28793b21b6d2SJerry Zuo pipe_ctx->stream->timing.v_total, 28803b21b6d2SJerry Zuo pipe_ctx->stream->timing.pix_clk_khz, 28813b21b6d2SJerry Zuo context->stream_count); 28823b21b6d2SJerry Zuo 28834562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 28844f804817SYongqiang Sun 28854f804817SYongqiang Sun dc->hwss.update_plane_addr(dc, pipe_ctx); 28864f804817SYongqiang Sun 2887b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 28884562236bSHarry Wentland 28894562236bSHarry Wentland } 28903dc780ecSYongqiang Sun 28913dc780ecSYongqiang Sun for (i = 0; i < dc->res_pool->pipe_count; i++) { 28923dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 28933dc780ecSYongqiang Sun struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 28943dc780ecSYongqiang Sun 28953dc780ecSYongqiang Sun if ((stream == pipe_ctx->stream) && 28963dc780ecSYongqiang Sun (!pipe_ctx->top_pipe) && 28973dc780ecSYongqiang Sun (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) 28983dc780ecSYongqiang Sun dc->hwss.pipe_control_lock(dc, pipe_ctx, false); 28993dc780ecSYongqiang Sun } 29004562236bSHarry Wentland } 29014562236bSHarry Wentland 2902e6c258cbSYongqiang Sun static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 29034562236bSHarry Wentland { 2904bc373a89SRoman Li int fe_idx = pipe_ctx->plane_res.mi ? 2905bc373a89SRoman Li pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2906e6c258cbSYongqiang Sun 29077950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2908608ac7bbSJerry Zuo if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 29094562236bSHarry Wentland return; 29104562236bSHarry Wentland 29114562236bSHarry Wentland dc->hwss.enable_display_power_gating( 2912cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2913cfe4645eSDmytro Laktyushkin 2914cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2915cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 29164562236bSHarry Wentland } 29174562236bSHarry Wentland 29186be425f3SEric Yang static void dce110_wait_for_mpcc_disconnect( 2919fb3466a4SBhawanpreet Lakha struct dc *dc, 29206be425f3SEric Yang struct resource_pool *res_pool, 29216be425f3SEric Yang struct pipe_ctx *pipe_ctx) 2922b6762f0cSEric Yang { 2923b6762f0cSEric Yang /* do nothing*/ 2924b6762f0cSEric Yang } 2925b6762f0cSEric Yang 2926bdf9a1a0SYue Hin Lau static void program_csc_matrix(struct pipe_ctx *pipe_ctx, 2927bdf9a1a0SYue Hin Lau enum dc_color_space colorspace, 2928bdf9a1a0SYue Hin Lau uint16_t *matrix) 2929bdf9a1a0SYue Hin Lau { 2930bdf9a1a0SYue Hin Lau int i; 2931bdf9a1a0SYue Hin Lau struct out_csc_color_matrix tbl_entry; 2932bdf9a1a0SYue Hin Lau 2933bdf9a1a0SYue Hin Lau if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 2934bdf9a1a0SYue Hin Lau == true) { 2935bdf9a1a0SYue Hin Lau enum dc_color_space color_space = 2936bdf9a1a0SYue Hin Lau pipe_ctx->stream->output_color_space; 2937bdf9a1a0SYue Hin Lau 2938bdf9a1a0SYue Hin Lau //uint16_t matrix[12]; 2939bdf9a1a0SYue Hin Lau for (i = 0; i < 12; i++) 2940bdf9a1a0SYue Hin Lau tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 2941bdf9a1a0SYue Hin Lau 2942bdf9a1a0SYue Hin Lau tbl_entry.color_space = color_space; 2943bdf9a1a0SYue Hin Lau //tbl_entry.regval = matrix; 294486a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry); 2945bdf9a1a0SYue Hin Lau } 2946bdf9a1a0SYue Hin Lau } 2947bdf9a1a0SYue Hin Lau 294833fd17d9SEric Yang void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 294933fd17d9SEric Yang { 295033fd17d9SEric Yang struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 295133fd17d9SEric Yang struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 295233fd17d9SEric Yang struct mem_input *mi = pipe_ctx->plane_res.mi; 295333fd17d9SEric Yang struct dc_cursor_mi_param param = { 295433fd17d9SEric Yang .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz, 295533fd17d9SEric Yang .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz, 295633fd17d9SEric Yang .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x, 295733fd17d9SEric Yang .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width, 295833fd17d9SEric Yang .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz 295933fd17d9SEric Yang }; 296033fd17d9SEric Yang 296133fd17d9SEric Yang if (pipe_ctx->plane_state->address.type 296233fd17d9SEric Yang == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 296333fd17d9SEric Yang pos_cpy.enable = false; 296433fd17d9SEric Yang 296533fd17d9SEric Yang if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 296633fd17d9SEric Yang pos_cpy.enable = false; 296733fd17d9SEric Yang 2968dc75dd70SRoman Li if (ipp->funcs->ipp_cursor_set_position) 296933fd17d9SEric Yang ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2970dc75dd70SRoman Li if (mi->funcs->set_cursor_position) 297133fd17d9SEric Yang mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 297233fd17d9SEric Yang } 297333fd17d9SEric Yang 297433fd17d9SEric Yang void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 297533fd17d9SEric Yang { 297633fd17d9SEric Yang struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 297733fd17d9SEric Yang 2978d1aaad05SHarry Wentland if (pipe_ctx->plane_res.ipp && 2979d1aaad05SHarry Wentland pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 298033fd17d9SEric Yang pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 298133fd17d9SEric Yang pipe_ctx->plane_res.ipp, attributes); 298233fd17d9SEric Yang 2983d1aaad05SHarry Wentland if (pipe_ctx->plane_res.mi && 2984d1aaad05SHarry Wentland pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 298533fd17d9SEric Yang pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 298633fd17d9SEric Yang pipe_ctx->plane_res.mi, attributes); 298733fd17d9SEric Yang 2988d1aaad05SHarry Wentland if (pipe_ctx->plane_res.xfm && 2989d1aaad05SHarry Wentland pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 299033fd17d9SEric Yang pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 299133fd17d9SEric Yang pipe_ctx->plane_res.xfm, attributes); 299233fd17d9SEric Yang } 299333fd17d9SEric Yang 29946bf52028SHersen Wu static void ready_shared_resources(struct dc *dc, struct dc_state *context) {} 299541f97c07SHersen Wu 299641f97c07SHersen Wu static void optimize_shared_resources(struct dc *dc) {} 299741f97c07SHersen Wu 29984562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 29991bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 3000bdf9a1a0SYue Hin Lau .program_csc_matrix = program_csc_matrix, 30014562236bSHarry Wentland .init_hw = init_hw, 30024562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 30034562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 30044562236bSHarry Wentland .set_plane_config = set_plane_config, 30054562236bSHarry Wentland .update_plane_addr = update_plane_addr, 30064562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 3007d7194cf6SAric Cyr .set_input_transfer_func = dce110_set_input_transfer_func, 300890e508baSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 30094562236bSHarry Wentland .power_down = dce110_power_down, 30104562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 30114562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 3012fa2123dbSMikita Lipski .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 30134562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 30144562236bSHarry Wentland .enable_stream = dce110_enable_stream, 30154562236bSHarry Wentland .disable_stream = dce110_disable_stream, 30164562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 301741b49742SCharlene Liu .blank_stream = dce110_blank_stream, 30184562236bSHarry Wentland .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 30194562236bSHarry Wentland .enable_display_power_gating = dce110_enable_display_power_gating, 30207f914a62SYongqiang Sun .disable_plane = dce110_power_down_fe, 30214562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 30224562236bSHarry Wentland .set_bandwidth = dce110_set_bandwidth, 30234562236bSHarry Wentland .set_drr = set_drr, 302472ada5f7SEric Cook .get_position = get_position, 30254562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 302654e8695eSDmytro Laktyushkin .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 30274b5e7d62SHersen Wu .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, 302815e17335SCharlene Liu .setup_stereo = NULL, 302915e17335SCharlene Liu .set_avmute = dce110_set_avmute, 303041f97c07SHersen Wu .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 303141f97c07SHersen Wu .ready_shared_resources = ready_shared_resources, 303241f97c07SHersen Wu .optimize_shared_resources = optimize_shared_resources, 3033631aaa0aSHersen Wu .pplib_apply_display_requirements = pplib_apply_display_requirements, 303487401969SAndrew Jiang .edp_backlight_control = hwss_edp_backlight_control, 303587401969SAndrew Jiang .edp_power_control = hwss_edp_power_control, 3036904623eeSYongqiang Sun .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, 303733fd17d9SEric Yang .set_cursor_position = dce110_set_cursor_position, 303833fd17d9SEric Yang .set_cursor_attribute = dce110_set_cursor_attribute 30394562236bSHarry Wentland }; 30404562236bSHarry Wentland 3041c13b408bSDave Airlie void dce110_hw_sequencer_construct(struct dc *dc) 30424562236bSHarry Wentland { 30434562236bSHarry Wentland dc->hwss = dce110_funcs; 30444562236bSHarry Wentland } 30454562236bSHarry Wentland 3046